EX128-PTQ64PP [ETC]
eX Family FPGAs; 的eX系列FPGA
| 型号： | EX128-PTQ64PP |
| 厂家： | 
ETC |
| 描述： | eX Family FPGAs |
| 文件： | 总36页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
v3.0
eX Family FPGAs
Leading Edge Performance
• 240 MHz System Performance
• Individual Output Slew Rate Control
• 2.5V, 3.3V, and 5.0V Mixed Voltage Operation with 5.0V
Input Tolerance and 5.0V Drive Strength
• Software Design Support with Actel Designer Series and
Libero Tools
• 3.9ns Clock-to-Out (Pad-to-Pad)
• 350 MHz Internal Performance
Specifications
• Up to 100% Resource Utilization with 100% Pin Locking
• Deterministic Timing
• 3,000 to 12,000 Available System Gates
• As Many as 512 Maximum Flip-Flops (Using CC Macros)
• 0.22µ CMOS Process Technology
• Unique In-System Diagnostic and Verification Capability
with Silicon Explorer II
• Up to 132 User-Programmable I/O Pins
• Boundary Scan Testing in Compliance with IEEE Standard
1149.1 (JTAG)
Features
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
• High-Performance, Low-Power Antifuse FPGA
• LP/Sleep Mode for Additional Power Savings
• Advanced Small-footprint Packages
• Hot-Swap Compliant I/Os
General Description
The eX family of FPGAs is a low-cost solution for low-power,
high-performance designs. The inherent low power
attributes of the antifuse technology, coupled with an
additional low static power mode, make these devices ideal
for power-sensitive applications. Fabricated with an
advanced 0.22µ CMOS antifuse technology, these devices
achieve high performance with no power penalty.
• Single-Chip Solution
• Nonvolatile
• Live on power up
• Power-Up/Down Friendly (No Sequencing Required for
Supply Voltages)
• Configurable Weak-Resistor Pull-Up or Pull-Down for
Tristated Outputs during Power Up
eX Product Profile
Device
eX64
eX128
eX256
Capacity
System Gates
Typical Gates
3,000
2,000
6,000
4,000
12,000
8,000
Register Cells (Dedicated Flip-Flops)
Combinatorial Cells
64
128
84
128
256
256
512
Maximum User I/Os
100
132
Speed Grades
–F, Std, –P
C, I
–F, Std, –P
C, I
–F, Std, –P
C, I
Temperature Grades
Package (by pin count)
TQFP
CSP
64, 100
49, 128
64, 100
49, 128
100
128, 180
December 2001
1
© 2001 Actel Corporation
eX Family FPGAs
Ordering Information
eX128
–P
TQ
100
Application (Temperature Range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
PP = Pre-production
Package Lead Count
Package Type
TQ = Thin (1.4mm) Quad Flat Pack
CS = Chip-Scale Package (0.8mm pitch)
Speed Grade
Blank = Standard Speed
–P = Approximately 30% Faster than Standard
–F = Approximately 40% Slower than Standard
Part Number
eX64
=
64 Dedicated Flip-Flops (3,000 System Gates)
eX128 = 128 Dedicated Flip-Flops (6,000 System Gates)
eX256 = 256 Dedicated Flip-Flops (12,000 System Gates)
Product Plan
Speed Grade
Application
–F
Std
–P
C
I†
eX64 Device
64-Pin Thin Quad Flat Pack (TQFP)
100-Pin Thin Quad Flat Pack (TQFP)
49-Pin Chip Scale Package (CSP)
128-Pin Chip Scale Package (CSP)
eX128 Device
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
64-Pin Thin Quad Flat Pack (TQFP)
100-Pin Thin Quad Flat Pack (TQFP)
49-Pin Chip Scale Package (CSP)
128-Pin Chip Scale Package (CSP)
eX256 Device
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
100-Pin Thin Quad Flat Pack (TQFP)
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
128-Pin Chip Scale Package (CSP)
180-Pin Chip Scale Package (CSP)
Contact your Actel sales representative for product availability.
Speed Grade: –P = Approx. 30% faster than Standard
–F = Approx. 40% slower than Standard
Availability: ✔ = Available
Applications:
C = Commercial
I
= Industrial
† Only Std Speed Grade
Plastic Device Resources
User I/Os (including clock buffers)
TQFP 64-Pin TQFP 100-Pin CSP 49-Pin CSP 128-Pin
84
Device
CSP 180-Pin
eX64
41
46
—
56
70
81
36
36
—
—
—
eX128
eX256
100
100
132
Package Definitions: TQFP = Thin Quad Flat Pack, CSP = Chip Scale Package
2
v3.0
eX Family FPGAs
eX Family Architecture
The eX family architecture uses a “sea-of-modules”
structure where the entire floor of the device is covered
with a grid of logic modules with virtually no chip area lost
to interconnect elements or routing. Interconnection
among these logic modules is achieved using Actel’s
The C-cell implements a range of combinatorial functions
up to 5 inputs (Figure 2). Inclusion of the DB input and its
associated inverter function dramatically increases the
number of combinatorial functions that can be
implemented in a single module from 800 options in
previous architectures to more than 4,000 in the eX
architecture.
patented
metal-to-metal
programmable
antifuse
interconnect elements. Actel’s eX family provides two types
of logic modules, the register cell (R-cell) and the
combinatorial cell (C-cell).
Module Organization
Actel has arranged all C-cell and R-cell logic modules into
horizontal banks called Clusters. The eX devices contain
one type of Cluster, which contains two C-cells and one
R-cell.
The R-cell contains a flip-flop featuring asynchronous clear,
asynchronous preset, and clock enable (using the S0 and S1
lines) control signals (Figure 1). The R-cell registers
feature programmable clock polarity selectable on a
register-by-register basis. This provides additional flexibility
while allowing mapping of synthesized functions into the eX
FPGA. The clock source for the R-cell can be chosen from
either the hard-wired clock or the routed clock.
To increase design efficiency and device performance, Actel
has further organized these modules into SuperClusters
(Figure 3 on page 4). The eX devices contain one type of
SuperClusters, which are two-wide groupings of one type of
clusters.
Routed
Data Input
S0
S1
PSET
DirectConnect
Input
D
Q
Y
HCLK
CLKA,
CLKB,
CLR
Internal Logic
CKS
CKP
Figure 1 • R-Cell
D0
D1
Y
D2
D3
Sa
Sb
DB
B1
A1
A0 B0
Figure 2 • C-Cell
v3.0
3
eX Family FPGAs
Routing Resources
FastConnect enables horizontal routing between any two
logic modules within a given SuperCluster and vertical
routing with the SuperCluster immediately below it. Only
one programmable connection is used in a FastConnect
path, delivering maximum pin-to-pin propagation of 0.3 ns
(–P speed grade).
Clusters and SuperClusters can be connected through the
use of two innovative local routing resources called
FastConnect and DirectConnect, which enable extremely
fast and predictable interconnection of modules within
Clusters and SuperClusters (Figure 4). This routing
architecture also dramatically reduces the number of
antifuses required to complete a circuit, ensuring the
highest possible performance.
In addition to DirectConnect and FastConnect, the
architecture makes use of two globally oriented routing
resources known as segmented routing and high-drive
routing. Actel’s segmented routing structure provides a
variety of track lengths for extremely fast routing between
SuperClusters. The exact combination of track lengths and
antifuses within each path is chosen by the 100 percent
automatic place-and-route software to minimize signal
propagation delays.
DirectConnect is a horizontal routing resource that provides
connections from a C-cell to its neighboring R-cell in a given
SuperCluster. DirectConnect uses a hard-wired signal path
requiring no programmable interconnection to achieve its
fast signal propagation time of less than 0.1 ns (–P speed
grade).
R-Cell
C-Cell
D0
D1
Routed
Data Input
S1
S0
PSET
Y
D2
DirectConnect
Input
D3
D
Q
Y
Sa
Sb
HCLK
CLKA,
CLKB,
Internal Logic
CLR
DB
CKS
CKP
A0 B0
A1 B1
Cluster 1
Cluster 1
Type 1 SuperCluster
Figure 3 • Cluster Organization
DirectConnect
• No antifuses
Type 1 SuperClusters
• 0.1 ns routing delay
FastConnect
• One antifuse
• 0.3 ns routing delay
Routing Segments
• Typically 2 antifuses
• Max. 5 antifuses
Figure 4 • DirectConnect and FastConnect for Type 1 SuperClusters
4
v3.0
eX Family FPGAs
Clock Resources
platform upon which to integrate the functionality
previously contained in CPLDs. In addition, designs that
previously would have required a gate array to meet
performance goals can now be integrated into an eX device
with dramatic improvements in cost and time to market.
Using timing-driven place-and-route tools, designers can
achieve highly deterministic device performance.
Actel’s high-drive routing structure provides three clock
networks. The first clock, called HCLK, is hardwired from
the HCLK buffer to the clock select MUX in each R-Cell.
HCLK cannot be connected to combinational logic. This
provides a fast propagation path for the clock signal,
enabling the 3.9ns clock-to-out (pad-to-pad) performance of
the eX devices. The hard-wired clock is tuned to provide a
clock skew of less than 0.1ns worst case.
I/O Modules
Each I/O on an eX device can be configured as an input, an
output, a tristate output, or a bidirectional pin. Even without
the inclusion of dedicated I/O registers, these I/Os, in
combination with array registers, can achieve clock-to-out
(pad-to-pad) timing as fast as 3.9ns. I/O cells that have
embedded latches and flip-flops require instantiation in HDL
code; this is a design complication not encountered in eX
FPGAs. Fast pin-to-pin timing ensures that the device will
have little trouble interfacing with any other device in the
system, which in turn enables parallel design of system
components and reduces overall design time. See Table 1 for
more information.
The remaining two clocks (CLKA, CLKB) are global clocks
that can be sourced from external pins or from internal
logic signals within the eX device. CLKA and CLKB may be
connected to sequential cells or to combinational logic. If
CLKA or CLKB is sourced from internal logic signals then
the external clock pin cannot be used for any other input
and must be tied low or high. Figure 5 describes the clock
circuit used for the constant load HCLK. Figure 6 describes
the CLKA and CLKB circuit used in eX devices.
Table 1 • I/O Features
Constant Load
Clock Network
Function
Description
HCLKBUF
Input Buffer
Threshold
Selection
•
TTL/3.3V LVTTL
Figure 5 • eX HCLK Clock Pad
Flexible
Output
Driver
•
•
•
2.5V LVCMOS 2
3.3V LVTTL
Clock Network
5.0V TTL/CMOS
Output
Buffer
“Hot-Swap” Capability
From Internal Logic
•
I/O on an unpowered device does not
sink current
CLKBUF
CLKBUFI
CLKINT
CLKINTI
•
Can be used for “cold sparing”
Selectable on an individual I/O basis
Individually selectable low-slew option
Power Up
Individually selectable pull ups and pull
downs during power up (default is to power
up in tristate)
Figure 6 • eX Routed Clock Buffer
Other Architectural Features
Enables deterministic power up of device
VCCA and VCCI can be powered in any order
Technology
Actel’s eX family is implemented on a high-voltage twin-well
CMOS process using 0.22µ design rules. The metal-to-metal
antifuse is made up of a combination of amorphous silicon
and dielectric material with barrier metals and has an “on”
state resistance of 25Ω with a capacitance of 1.0 fF for low
signal impedance.
Hot Swapping
eX I/Os are configured to be hot swappable. During power
up/down (or partial up/down), all I/Os are tristated. VCCA
and VCCI do not have to be stable during power up/down,
and they do not require a specific power-up or power-down
sequence in order to avoid damage to the eX devices. After
the eX device is plugged into an electrically active system,
the device will not degrade the reliability of or cause
damage to the host system. The device’s output pins are
driven to a high impedance state until normal chip
Performance
The combination of architectural features described above
enables eX devices to operate with internal clock
frequencies exceeding 350 MHz for very fast execution of
complex logic functions. Thus, the eX family is an optimal
v3.0
5
eX Family FPGAs
operating conditions are reached. Please see the Actel SX-A
and RT54SX-S Devices in Hot-Swap and Cold-Sparing
Applications application note for more information on hot
swapping.
in conjunction with the program fuse. The functionality of
each pin is described in Table 3. In the dedicated test mode,
TCK, TDI, and TDO are dedicated pins and cannot be used
as regular I/Os. In flexible mode, TMS should be set HIGH
through a pull-up resistor of 10kΩ. TMS can be pulled LOW
to initiate the test sequence.
Power Requirements
The eX family supports mixed voltage operation and is
designed to tolerate 5.0V inputs in each case (Table 2).
Power consumption is extremely low due to the very short
distances signals, which are required to travel to complete a
circuit. Power requirements are further reduced because of
the small number of low-resistance antifuses in the path.
The antifuse architecture does not require active circuitry
to hold a charge (as do SRAM or EPROM), making it the
lowest-power architecture FPGA available today. Also, when
the device is in low power mode, the clock pins must not
float. They must be driven either HIGH or LOW. We
recommend that signals driving the clock pins be fixed at
HIGH or LOW rather than toggle to achieve maximum power
efficiency.
Table 3 • Boundary Scan Pin Functionality
Program Fuse Blown
(Dedicated Test Mode)
Program Fuse Not Blown
(Flexible Mode)
TCK, TDI, TDO are
dedicated BST pins
TCK, TDI, TDO are flexible
and may be used as I/Os
No need for pull-up resistor Use a pull-up resistor of
for TMS
10kΩ on TMS
Configuring Diagnostic Pins
The JTAG and Probe pins (TDI, TCK, TMS, TDO, PRA, and
PRB) are placed in the desired mode by selecting the
appropriate check boxes in the “Variation” dialog window.
This dialog window is accessible through the Design Setup
Wizard under the Tools menu in Actel's Designer software.
Table 2 • Supply Voltages
Maximum Maximum
TRST Pin
Input
Output
Drive
When the “Reserve JTAG Reset” box is checked, the TRST
pin will become a Boundary Scan Reset pin. In this mode,
the TRST pin will function as an asynchronous, active-low
input to initialize or reset the BST circuit. An internal
pull-up resistor will be automatically enabled on the TRST
pin.
VCCA
VCCI Tolerance
2.5V
2.5V
2.5V
2.5V
3.3V
5.0V
5.0V
5.0V
5.0V
2.5V
3.3V
5.0V
eX64
eX128
eX256
Low Power Mode
The TRST pin will function as a user I/O when the “Reserve
JTAG Reset” box is not checked. The internal pull-up
resistor will be disabled in this mode.
The new Actel eX family has been designed with a Low
Power Mode. This feature, activated with a special LP pin, is
particularly useful for battery-operated systems where
battery life is a primary concern. In this mode, the core of
the device is turned off and the device consumes minimal
power with low standby current. In addition, all input
buffers are turned off, and all outputs and bidirectional
buffers are tristated when the device enters this mode.
Since the core of the device is turned off, the states of the
registers are lost. The device must be re-initialized when
normal operating mode is achieved.
Dedicated Test Mode
When the “Reserve JTAG” box is checked, the eX device is
placed in Dedicated Test mode, which configures the TDI,
TCK, and TDO pins for BST or in-circuit verification with
Silicon Explorer II. An internal pull-up resistor is
automatically enabled on both the TMS and TDI pins. In
Dedicated Test Mode, TCK, TDI, and TDO are dedicated test
pins and become unavailable for pin assignment in the Pin
Editor. The TMS pin will function as specified in the IEEE
1149.1 (JTAG) Specification.
2.5V LP/Sleep Mode Specifications
Typical Conditions, VCCA, VCCI = 2.5V, TJ = 25° C
Flexible Mode
Product
Low Power Standby Current
Units
When the “Reserve JTAG” box is not selected (default
setting in Designer software), eX is placed in Flexible mode,
which allows the TDI, TCK, and TDO pins to function as user
I/Os or BST pins. In this mode the internal pull-up resistors
on the TMS and TDI pins are disabled. An external 10kΩ
pull-up resistor to VCCI is required on the TMS pin.
eX64
100
111
134
µA
µA
µA
eX128
eX256
Boundary Scan Testing (BST)
The TDI, TCK, and TDO pins are transformed from user I/Os
into BST pins when a rising edge on TCK is detected while
TMS is at logical low. Once the BST pins are in test mode
they will remain in BST mode until the internal BST state
All eX devices are IEEE 1149.1 compliant. eX devices offer
superior diagnostic and testing capabilities by providing
Boundary Scan Testing (BST) and probing capabilities.
These functions are controlled through the special test pins
6
v3.0
eX Family FPGAs
machine reaches the “logic reset” state. At this point the
BST pins will be released and will function as regular I/O
pins. The “logic reset” state is reached five TCK cycles after
the TMS pin is set to logical HIGH.
verification and logic analysis tool that can sample data at
100 MHz (asynchronous) or 66 MHz (synchronous). Silicon
Explorer II attaches to a PC’s standard COM port, turning
the PC into a fully functional 18-channel logic analyzer.
Silicon Explorer II allows designers to complete the design
verification process at their desks and reduces verification
time from several hours per cycle to only a few seconds.
The Program fuse determines whether the device is in
Dedicated Test or Flexible mode. The default (fuse not
programmed) is Flexible mode.
eX Probe Circuit Control Pins
Development Tool Support
The Silicon Explorer II tool uses the boundary scan ports
(TDI, TCK, TMS and TDO) to select the desired nets for
verification. The selected internal nets are assigned to the
PRA/PRB pins for observation. Figure 7 illustrates the
interconnection between Silicon Explorer II and the FPGA
to perform in-circuit verification. The TRST pin is equipped
with an internal pull-up resistor. To remove the boundary
scan state machine from the reset state during probing, it is
recommended that the TRST pin be left floating.
The eX devices are fully supported by Actel’s line of FPGA
development tools, including the Actel Designer Series suite
and Libero, the FPGA design tool suite. Designer Series,
Actel’s suite of FPGA development tools for PCs and
Workstations, includes the ACTgen Macro Builder, timing
driven place-and-route, timing analysis tools, and fuse file
generation. Libero is a design management environment
that integrates the needed design tools, streamlines the
design flow, manages all design and log files, and passes
necessary design data between tools. Libero includes
Synplify, ViewDraw, Actel’s Designer Series, ModelSim HDL
Simulator, WaveFormer Lite, and Actel Silicon Explorer.
Design Considerations
For prototyping, the TDI, TCK, TDO, PRA, and PRB pins
should not be used as input or bidirectional ports. Because
these pins are active during probing, critical signals input
through these pins are not available while probing. In
addition, the Security Fuse should not be programmed
because doing so disables the probe circuitry.
In addition, the eX devices contain internal probe circuitry
that provides built-in access to the output of every C-cell,
R-cell, and routed clock in the design, enabling 100-percent
real-time observation and analysis of a device's internal
logic nodes without design iteration. The probe circuitry is
accessed by Silicon Explorer II, an easy-to-use integrated
eX FPGA
TDI
TCK
TMS
Serial Connection
Silicon Explorer II
TDO
PRA
PRB
Figure 7 • Probe Setup
v3.0
7
eX Family FPGAs
Recommended Operating Conditions
Parameter Commercial Industrial
2.5V/3.3V/5.0V Operating Conditions
Absolute Maximum Ratings1
Units
Temperature
Symbol
Parameter
Limits
Units
0 to +70
2.3-2.7
–40 to +85
2.3-2.7
°C
Range1
VCCI
VCCA
VI
DC Supply Voltage
DC Supply Voltage
Input Voltage
–0.3 to +6.0
–0.3 to +3.0
V
V
2.5V Power Supply
Range (VCCA, VCCI
V
V
V
)
–0.5 to +5.5
V
3.3V Power Supply
3.0-3.6
3.0-3.6
Range (VCCI
)
VO
Output Voltage
–0.5 to +VCCI + 0.5
–65 to +150
V
5.0V Power Supply
TSTG
Note:
Storage Temperature
°C
4.75-5.25
4.5-5.5
Range (VCCI
)
Note:
1. Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. Exposure
to absolute maximum rated conditions for extended periods
may affect device reliability. Devices should not be operated
outside the Recommended Operating Conditions.
1. Ambient temperature (TA).
Typical eX Standby Current at 25°C
VCCA= 2.5V
VCCI = 2.5V
VCCA = 2.5V
VCCI = 3.3V
Product
eX64
397µA
696µA
698µA
497µA
795µA
796µA
eX128
eX256
2.5V Electrical Specifications
Commercial
Industrial
Symbol
Parameter
Min.
Max.
Min.
Max.
Units
VDD = MIN, VI = VIH or VIL
VDD = MIN, VI = VIH or VIL
(IOH = -100µA) 2.1
2.1
2.0
1.7
V
V
VOH
(IOH = -1 mA)
(IOH = -2 mA)
(IOL= 100µA)
(IOL= 1mA)
2.0
1.7
V
DD = MIN, VI = VIH or VIL
VDD = MIN, VI = VIH or VIL
DD = MIN, VI = VIH or VIL
V
0.2
0.4
0.7
0.7
0.2
0.4
0.7
0.7
V
VOL
V
V
VDD = MIN,VI = VIH or VIL
(IOL= 2 mA)
V
VIL
VIH
IOZ
Input Low Voltage, VOUT ≤ VVOL(max)
Input High Voltage, VOUT ≥ VVOH(min)
-0.3
-0.3
V
1.7 VDD + 0.3 1.7 VDD + 0.3
V
3-State Output Leakage Current, VOUT = VCCI or GND
Input Transition Time tR, tF
I/O Capacitance
–10
10
10
10
1.0
–10
10
10
10
3.0
µA
ns
pF
mA
1,2
tR, tF
CIO
3,4
ICC
Standby Current
IV Curve5 Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.
Notes:
1. tR is the transition time from 0.7 V to 1.7V.
2. tF is the transition time from 1.7V to 0.7V.
3. ICC max Commercial –F = 5.0mA
4. ICC=ICCI + ICCA
8
v3.0
eX Family FPGAs
3.3V Electrical Specifications
Commercial
Industrial
Symbol Parameter
Min.
Max.
Min.
Max. Units
VDD = MIN, VI = VIH or VIL
VOH
(IOH = -1mA) 0.9 VCCI
0.9 VCCI
2.4
V
V
VDD = MIN, VI = VIH or VIL
(IOH = -8mA)
(IOL= 1mA)
(IOL= 12mA)
2.4
VDD = MIN, VI = VIH or VIL
VOL
0.1 VCCI
0.4
0.1 VCCI
0.4
V
V
VDD = MIN, VI = VIH or VIL
VIL
Input Low Voltage
0.8
0.8
V
VIH
Input High Voltage
2.0
–10
–10
2.0
–10
–10
V
IIL/ IIH
IOZ
Input Leakage Current, VIN = VCCI or GND
3-State Output Leakage Current, VOUT = VCCI or GND
Input Transition Time tR, tF
I/O Capacitance
10
10
10
10
1.5
10
10
10
10
10
µA
µA
ns
pF
mA
1,2
tR, tF
CIO
3,4
ICC
Standby Current
IV Curve5 Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html.
Notes:
1. tR is the transition time from 0.8 V to 2.0V.
2. tF is the transition time from 2.0V to 0.8V.
3. ICC max Commercial –F=5.0mA
4.
ICC=ICCI + ICCA
5.0V Electrical Specifications
Commercial
Industrial
Symbol Parameter
Min.
Max.
Min.
Max. Units
VDD = MIN, VI = VIH or VIL
VOH
(IOH = -1mA) 0.9 VCCI
0.9 VCCI
2.4
V
V
VDD = MIN, VI = VIH or VIL
(IOH = -8mA)
(IOL= 1mA)
(IOL= 12mA)
2.4
VDD = MIN, VI = VIH or VIL
VOL
0.1 VCCI
0.4
0.1 VCCI
0.4
V
V
VDD = MIN, VI = VIH or VIL
VIL
Input Low Voltage
0.8
0.8
V
VIH
Input High Voltage
2.0
–10
–10
2.0
–10
–10
V
IIL/ IIH
Input Leakage Current, VIN = VCCI or GND
3-State Output Leakage Current, VOUT = VCCI or GND
Input Transition Time tR, tF
I/O Capacitance
10
10
10
10
15
10
10
10
10
20
µA
µA
ns
pF
mA
IOZ
1,2
tR, tF
CIO
3,4
ICC
Standby Current
IV Curve5 Can be derived from the IBIS model at www.actel.com/custsup/models/ibis.html
Notes:
1. tR is the transition time from 0.8 V to 2.0V.
2. tF is the transition time from 2.0V to 0.8V.
3. ICC max Commercial –F=20mA
4. ICC=ICCI + ICCA
v3.0
9
eX Family FPGAs
eX Dynamic Power Consumption – High Frequency
300
250
200
150
100
50
eX64
eX128
eX256
0
50
100
150
200
Frequency (MHz)
Notes:
1. Device filled with 16-bit counters.
2. VCCA, VCCI = 2.7V, device tested at room temperature.
eX Dynamic Power Consumption – Low Frequency
80
70
60
50
40
30
20
10
0
eX64
eX128
eX256
0
10
20
30
40
50
Frequency (MHz)
Notes:
1. Device filled with 16-bit counters.
2. VCCA, VCCI = 2.7V, device tested at room temperature.
10
v3.0
eX Family FPGAs
Total Dynamic Power (mW)
180
160
140
120
100
80
32-bit Decoder
8 x 8-bit Counters
SDRAM Controller
60
40
20
0
0
25
50
75
100
125
150
175
200
Frequency (MHz)
System Power at 5%, 10%, and 15% Duty Cycle
12,000
10,000
8,000
6,000
4,000
2,000
0
5% DC
10% DC
15% DC
0
10
20
30
40
50
60
Frequency (MHz)
v3.0
11
eX Family FPGAs
Junction Temperature (TJ)
The temperature variable in the Designer Series software
refers to the junction temperature, not the ambient
temperature. This is an important distinction because the
heat generated from dynamic power consumption is usually
hotter than the ambient temperature. Equation 1, shown
below, can be used to calculate junction temperature.
θ
= Junction to ambient of package. θ numbers are
ja ja
located in the Package Thermal Characteristics section
below.
Package Thermal Characteristics
The device junction to case thermal characteristic is θjc,
and the junction to ambient air characteristic is θja. The
thermal characteristics for θja are shown with two different
air flow rates.
Junction Temperature = ∆T + Ta
(1)
Where:
Ta = Ambient Temperature
The maximum junction temperature is 150°C.
∆T = Temperature gradient between junction (silicon) and
ambient
A sample calculation of the absolute maximum power
dissipation allowed for a TQFP 100-pin package at
commercial temperature and still air is as follows:
∆T = θ * P
ja
P = Power
Max. junction temp. (°C) – Max. ambient temp. (°C) 150°C – 70°C
--------------------------------------------------------------------------------------------------------------------------------- ----------------------------------
= 2.1W
Maximum Power Allowed =
=
θja(°C/W)
37.5°C/W
θja
Still Air
θja
300 ft/min
Package Type
Pin Count
θjc
Units
Thin Quad Flat Pack (TQFP)
Thin Quad Flat Pack (TQFP)
Chip Scale Package (CSP)
Chip Scale Package (CSP)
Chip Scale Package (CSP)
64
100
49
14
12
3
51.2
37.5
71.3
54.1
57.8
35
30
°C/W
°C/W
°C/W
°C/W
°C/W
56.0
47.8
51
128
180
3
3
12
v3.0
eX Family FPGAs
eX Timing Model*
Input Delays
Internal Delays
Predicted
Routing
Delays
Output Delays
Combinatorial
Cell
t
t
= 0.3 ns
= 0.4 ns
I/O Module
I/O Module
IRD1
IRD2
t
= 0.7 ns
INYH
t
= 2.6 ns
DHL
t
= 0.7 ns
PD
t
t
t
= 0.3 ns
RD1
= 0.7 ns
RD4
= 1.2 ns
RD8
I/O Module
Register
Cell
t
= 1.9 ns
ENZL
D
Q
t
t
t
RD1
= 0.5 ns
= 0.3 ns
SUD
HD
= 0.0 ns
t
= 2.6 ns
DHL
Routed
Clock
t
= 1.3 ns
RCKH
t
= 0.6 ns
(100% Load)
RCO
I/O Module
Register
Cell
I/O Module
t
= 0.7 ns
t
= 1.9 ns
INYH
ENZL
t
= 0.3 ns
= 0.5ns
IRD1
D
Q
t
t
t
RD1
= 0.3 ns
SUD
= 0.0 ns
HD
t
= 2.6 ns
DHL
Hard-Wired
Clock
t
t
RCO
= 1.1 ns
= 0.6 ns
HCKH
*Values shown for eX128–P, worst-case commercial conditions (5.0V, 35pF Pad Load).
Hard-Wired Clock
Routed Clock
External Setup = tINYH + tIRD1 + tSUD – tHCKH
External Setup = tINYH + tIRD2 + tSUD – tRCKH
= 0.7 + 0.4 + 0.5 – 1.3= 0.3 ns
= 0.7 + 0.3 + 0.5 – 1.1 = 0.4 ns
Clock-to-Out (Pad-to-Pad), typical
= tHCKH + tRCO + tRD1 + tDHL
Clock-to-Out (Pad-to-Pad), typical
= tRCKH + tRCO + tRD1 + tDHL
= 1.1 + 0.6 + 0.3 + 2.6 = 4.6 ns
= 1.3+ 0.6 + 0.3 + 2.6 = 4.8 ns
v3.0
13
eX Family FPGAs
Output Buffer Delays
E
D
To AC test loads (shown below)
PAD
TRIBUFF
VCC
VCC
VCC
In
GND
50%
VOH
En
Out
GND
10%
50%
En
GND
90%
50%
50%
VCC
50%
VOH
50%
1.5V
1.5V
VOL
Out
VOL
Out
GND
1.5V
1.5V
tDLH
tDHL
tENZL
tENLZ
tENZH
tENHZ
AC Test Loads
Load 3
Load 2
Load 1
(Used to measure
propagation delay)
(Used to measure disable delays)
(Used to measure enable delays)
VCC
VCC
GND
GND
To the output
under test
35 pF
R to VCC for tPLZ
R to GND for tPHZ
R = 1 kΩ
R to VCC for tPZL
R to GND for tPZH
R = 1 kΩ
To the output
under test
To the output
under test
5 pF
35 pF
Input Buffer Delays
C-Cell Delays
S
A
B
Y
Y
PAD
INBUF
VCC
GND
S, A or B
50% 50%
VCC
3V
In
0V
50%
1.5V
VCC
1.5V
50%
Out
50%
GND
tPD
tPD
Out
GND
50%
VCC
50%
Out
GND
tPD
50%
tPD
14
v3.0
eX Family FPGAs
Cell Timing Characteristics
Flip-Flops
D
Q
PRESET
CLR
CLK
(Positive edge triggered)
tHD
D
tSUD
CLK
tHP
tHPWH
tRPWH
,
tHPWL
,
tRPWL
tRCO
Q
tCLR
tPRESET
CLR
tWASYN
PRESET
Long Tracks
Timing Characteristics
Some nets in the design use long tracks. Long tracks are
special routing resources that span multiple rows, columns,
or modules. Long tracks employ three to five antifuse
connections. This increases capacitance and resistance,
resulting in longer net delays for macros connected to long
tracks. Typically, no more than six percent of nets in a fully
utilized device require long tracks. Long tracks contribute
approximately 4 ns to 8.4 ns delay. This additional delay is
represented statistically in higher fanout routing delays.
Timing characteristics for eX devices fall into three
categories: family-dependent, device-dependent, and
design-dependent. The input and output buffer
characteristics are common to all eX family members.
Internal routing delays are device-dependent. Design
dependency means actual delays are not determined until
after placement and routing of the user’s design are
complete. Delay values may then be determined by using
the Timer utility or performing simulation with post-layout
delays.
Timing Derating
eX devices are manufactured with a CMOS process.
Therefore, device performance varies according to
temperature, voltage, and process changes. Minimum
timing parameters reflect maximum operating voltage,
minimum operating temperature, and best-case processing.
Maximum timing parameters reflect minimum operating
voltage, maximum operating temperature, and worst-case
processing.
Critical Nets and Typical Nets
Propagation delays are expressed only for typical nets,
which are used for initial design performance evaluation.
Critical net delays can then be applied to the most timing
critical paths. Critical nets are determined by net property
assignment prior to placement and routing. Up to
six percent of the nets in a design may be designated as
critical.
Temperature and Voltage Derating Factors
(Normalized to Worst-Case Commercial, TJ = 70°C, VCCA = 2.3V)
Junction Temperature (TJ)
VCCA
2.3
–55
0.75
0.70
0.66
–40
0.79
0.74
0.69
0
25
70
85
125
1.16
1.08
1.02
0.88
0.82
0.79
0.89
0.83
0.79
1.00
0.93
0.88
1.04
0.97
0.92
2.5
2.7
v3.0
15
eX Family FPGAs
eX Family Timing Characteristics
(Worst-Case Commercial Conditions, VCCA = 2.3V, TJ = 70°C)
‘–P’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Units
C-Cell Propagation Delays1
tPD
Internal Array Module
0.7
1.0
1.4
ns
Predicted Routing Delays2
tDC
FO=1 Routing Delay, DirectConnect
0.1
0.3
0.3
0.4
0.5
0.7
1.2
1.7
0.1
0.5
0.5
0.6
0.8
1.0
1.7
2.5
0.2
0.7
0.7
0.8
1.1
1.3
2.4
3.5
ns
ns
ns
ns
ns
ns
ns
ns
tFC
FO=1 Routing Delay, FastConnect
FO=1 Routing Delay
tRD1
tRD2
FO=2 Routing Delay
tRD3
FO=3 Routing Delay
tRD4
FO=4 Routing Delay
tRD8
FO=8 Routing Delay
tRD12
R-Cell Timing
FO=12 Routing Delay
tRCO
Sequential Clock-to-Q
0.6
0.6
0.7
0.9
0.8
0.9
1.3
1.2
1.3
ns
ns
ns
ns
ns
ns
ns
ns
tCLR
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
Flip-Flop Data Input Set-Up
Flip-Flop Data Input Hold
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Hold Time
tPRESET
tSUD
0.5
0.0
1.3
0.3
0.3
0.7
0.0
1.9
0.5
0.5
1.0
0.0
2.6
0.7
0.7
tHD
tWASYN
tRECASYN
tHASYN
2.5V Input Module Propagation Delays
tINYH
tINYL
Input Data Pad-to-Y HIGH
Input Data Pad-to-Y LOW
0.6
0.8
0.9
1.1
1.3
1.5
ns
ns
3.3V Input Module Propagation Delays
tINYH
tINYL
Input Data Pad-to-Y HIGH
Input Data Pad-to-Y LOW
0.7
0.9
1.0
1.3
1.4
1.8
ns
ns
5.0V Input Module Propagation Delays
tINYH
tINYL
Input Data Pad-to-Y HIGH
Input Data Pad-to-Y LOW
0.7
0.9
1.0
1.3
1.4
1.8
ns
ns
Input Module Predicted Routing Delays2
tIRD1
tIRD2
tIRD3
tIRD4
tIRD8
tIRD12
Notes:
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
FO=12 Routing Delay
0.3
0.4
0.5
0.7
1.2
1.7
0.4
0.6
0.8
1.0
1.7
2.5
0.5
0.8
1.1
1.3
2.4
3.5
ns
ns
ns
ns
ns
ns
1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance.
16
v3.0
eX Family FPGAs
eX Family Timing Characteristics (Continued)
(Worst-Case Commercial Conditions VCCA = 2.3V, VCCI = 4.75V, TJ = 70°C)
‘–P’ Speed
Min. Max.
‘Std’ Speed
‘–F’ Speed
Min. Max.
Parameter
Description
Min.
Max.
Units
Dedicated (Hard-Wired) Array Clock Networks
tHCKH
tHCKL
Input LOW to HIGH
(Pad to R-Cell Input)
1.1
1.1
1.6
1.6
2.3
2.3
ns
Input HIGH to LOW
(Pad to R-Cell Input)
ns
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
1.4
1.4
2.0
2.0
2.8
2.8
ns
<0.1
357
<0.1
250
<0.1
178
ns
Minimum Period
2.8
4.0
5.6
ns
fHMAX
Maximum Frequency
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) MAX.
1.1
1.0
1.2
1.2
1.3
1.3
1.6
1.4
1.7
1.7
1.9
1.9
2.2
2.0
2.4
2.4
2.6
2.6
ns
ns
ns
ns
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) MAX.
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) MAX.
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) MAX.
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) MAX.
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) MAX.
ns
ns
ns
ns
ns
ns
tRPWH
tRPWL
Min. Pulse Width HIGH
1.5
1.5
2.1
2.1
3.0
3.0
Min. Pulse Width LOW
1
1
1
tRCKSW
tRCKSW
tRCKSW
Note:
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
0.2
0.1
0.1
0.3
0.2
0.1
0.4
0.3
0.2
1. Clock skew improves as the clock network becomes more heavily loaded.
v3.0
17
eX Family FPGAs
eX Family Timing Characteristics (Continued)
(Worst-Case Commercial Conditions VCCA = 2.3V, VCCI = 2.3V or 3.0V, TJ = 70°C)
‘–P’ Speed ‘Std’ Speed ‘–F’ Speed
Min. Max. Min. Max.
Parameter
Description
Min.
Max.
Units
Dedicated (Hard-Wired) Array Clock Networks
tHCKH
tHCKL
Input LOW to HIGH
(Pad to R-Cell Input)
1.1
1.1
1.6
1.6
2.3
2.3
ns
Input HIGH to LOW
(Pad to R-Cell Input)
ns
ns
tHPWH
tHPWL
tHCKSW
tHP
Minimum Pulse Width HIGH
Minimum Pulse Width LOW
Maximum Skew
1.4
1.4
2.0
2.0
2.8
2.8
ns
<0.1
357
<0.1
250
<0.1
178
ns
Minimum Period
2.8
4.0
5.6
ns
fHMAX
Maximum Frequency
MHz
Routed Array Clock Networks
tRCKH
tRCKL
tRCKH
tRCKL
tRCKH
tRCKL
Input LOW to HIGH (Light Load)
(Pad to R-Cell Input) MAX.
1.0
1.0
1.2
1.2
1.4
1.4
1.4
1.4
1.7
1.7
2.0
2.0
2.0
2.0
2.4
2.4
2.8
2.8
ns
ns
ns
ns
ns
Input HIGH to LOW (Light Load)
(Pad to R-Cell Input) MAX.
Input LOW to HIGH (50% Load)
(Pad to R-Cell Input) MAX.
Input HIGH to LOW (50% Load)
(Pad to R-Cell Input) MAX.
Input LOW to HIGH (100% Load)
(Pad to R-Cell Input) MAX.
Input HIGH to LOW (100% Load)
(Pad to R-Cell Input) MAX.
ns
ns
ns
ns
ns
ns
tRPWH
tRPWL
Min. Pulse Width HIGH
1.4
1.4
2.0
2.0
2.8
2.8
Min. Pulse Width LOW
1
1
1
tRCKSW
tRCKSW
tRCKSW
Note:
Maximum Skew (Light Load)
Maximum Skew (50% Load)
Maximum Skew (100% Load)
0.2
0.2
0.1
0.3
0.2
0.1
0.4
0.3
0.2
1. Clock skew improves as the clock network becomes more heavily loaded.
18
v3.0
eX Family FPGAs
eX Family Timing Characteristics (Continued)
(Worst-Case Commercial Conditions VCCA = 2.3V, TJ = 70°C)
‘–P’ Speed
‘Std’ Speed
‘–F’ Speed
Min. Max.
Parameter
Description
Min.
Max.
Min.
Max.
Units
2.5V LVTTL Output Module Timing1 (VCCI = 2.3V)
tDLH
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Data-to-Pad HIGH to LOW—Low Slew
Enable-to-Pad, Z to L
3.3
3.5
4.7
5.0
6.6
7.0
ns
ns
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
dTLH
11.6
2.5
16.6
3.6
23.2
5.1
ns
ns
Enable-to-Pad Z to L—Low Slew
Enable-to-Pad, Z to H
11.8
3.4
16.9
4.9
23.7
6.9
ns
ns
Enable-to-Pad, L to Z
2.1
3.0
4.2
ns
Enable-to-Pad, H to Z
2.4
5.67
0.046
0.022
7.94
0.066
0.05
ns
Delta Delay vs. Load LOW to HIGH
Delta Delay vs. Load HIGH to LOW
0.034
0.016
ns/pF
ns/pF
dTHL
Delta Delay vs. Load HIGH to LOW—Low
Slew
dTHLS
0.05
0.072
0.1
ns/pF
3.3V LVTTL Output Module Timing1 (VCCI = 3.0V)
tDLH
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Data-to-Pad HIGH to LOW—Low Slew
Enable-to-Pad, Z to L
2.8
2.7
4.0
3.9
5.6
5.4
ns
ns
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
tENHZ
dTLH
9.7
13.9
3.2
19.5
4.4
ns
2.2
ns
Enable-to-Pad Z to L—Low Slew
Enable-to-Pad, Z to H
9.7
13.9
4.0
19.6
5.6
ns
2.8
ns
Enable-to-Pad, L to Z
2.8
4.0
5.6
ns
Enable-to-Pad, H to Z
2.6
3.8
5.3
ns
Delta Delay vs. Load LOW to HIGH
Delta Delay vs. Load HIGH to LOW
0.02
0.016
0.03
0.022
0.046
0.05
ns/pF
ns/pF
dTHL
Delta Delay vs. Load HIGH to LOW—Low
Slew
dTHLS
0.05
0.072
0.1
ns/pF
5.0V TTL Output Module Timing1 (VCCI = 4.75V)
tDLH
Data-to-Pad LOW to HIGH
Data-to-Pad HIGH to LOW
Data-to-Pad HIGH to LOW—Low Slew
Enable-to-Pad, Z to L
2.0
2.6
6.8
1.9
6.8
2.1
3.3
2.9
3.7
9.7
2.7
9.8
3.0
4.8
4.0
5.2
ns
ns
ns
ns
ns
ns
ns
tDHL
tDHLS
tENZL
tENZLS
tENZH
tENLZ
Note:
13.6
3.8
Enable-to-Pad Z to L—Low Slew
Enable-to-Pad, Z to H
13.7
4.1
Enable-to-Pad, L to Z
6.6
1. Delays based on 35 pF loading.
v3.0
19
eX Family FPGAs
Pin Description
CLKA/B
Clock A and B
TCK, I/O
Test Clock
These pins are clock inputs for clock distribution networks.
Input levels are compatible with standard TTL or LVTTL
specifications. The clock input is buffered prior to clocking
the R-cells. If not used, this pin must be set LOW or HIGH on
the board. It must not be left floating.
Test clock input for diagnostic probe and device
programming. In flexible mode, TCK becomes active when
the TMS pin is set LOW (refer to Table 3 on page 6). This pin
functions as an I/O when the boundary scan state machine
reaches the “logic reset” state.
GND
Ground
TDI, I/O
Test Data Input
LOW supply voltage.
Serial input for boundary scan testing and diagnostic probe.
In flexible mode, TDI is active when the TMS pin is set LOW
(refer to Table 3 on page 6). This pin functions as an I/O
when the boundary scan state machine reaches the “logic
reset” state.
HCLK
Dedicated (Hard-wired)
Array Clock
This pin is the clock input for sequential modules. Input
levels are compatible with standard TTL or LVTTL
specifications. This input is directly wired to each R-cell and
offers clock speeds independent of the number of R-cells
being driven. If not used, this pin must be set LOW or HIGH
on the board. It must not be left floating.
TDO, I/O
Test Data Output
Serial output for boundary scan testing. In flexible mode,
TDO is active when the TMS pin is set LOW (refer to Table 3
on page 6). This pin functions as an I/O when the boundary
scan state machine reaches the "logic reset" state. When
Silicon Explorer is being used, TDO will act as an output
when the "checksum" command is run. It will return to user
IO when "checksum" is complete.
I/O
Input/Output
The I/O pin functions as an input, output, tristate, or
bidirectional buffer. Based on certain configurations, input
and output levels are compatible with standard TTL or
LVTTL specifications. Unused I/O pins are automatically
tristated by the Designer Series software.
TMS
Test Mode Select
The TMS pin controls the use of the IEEE 1149.1 Boundary
Scan pins (TCK, TDI, TDO, TRST). In flexible mode when
the TMS pin is set LOW, the TCK, TDI, and TDO pins are
boundary scan pins (refer to Table 3 on page 6). Once the
boundary scan pins are in test mode, they will remain in that
mode until the internal boundary scan state machine
reaches the “logic reset” state. At this point, the boundary
scan pins will be released and will function as regular I/O
pins. The “logic reset” state is reached 5 TCK cycles after
the TMS pin is set HIGH. In dedicated test mode, TMS
functions as specified in the IEEE 1149.1 specifications.
LP
Low Power Pin
Controls the low power mode of the eX devices. The device
is placed in the low power mode by connecting the LP pin
to logic high. In low power mode, all I/Os are tristated, all
input buffers are turned OFF, and the core of the devices is
turned OFF. To exit the low power mode, the LP pin must
be set LOW. The device enters the low power mode 800ns
after the LP pin is driven to a logic HIGH. It will resume
normal operation in 200µs after the LP pin is driven to a
logic low. The logic high level on the LP pin must never
exceed the VSV voltage. Refer to the VSV pin description.
TRST, I/O
Boundary Scan Reset Pin
Once it is configured as the JTAG Reset pin, the TRST pin
functions as an active-low input to asynchronously initialize
or reset the boundary scan circuit. The TRST pin is equipped
with an internal pull-up resistor. This pin functions as an I/O
when the “Reserve JTAG Reset Pin” is not selected in
Designer.
NC
No Connection
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
PRA, I/O
PRB, I/O
Probe A/B
VCCI
Supply Voltage
The Probe pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the other probe pin to
allow real-time diagnostic output of any signal path within
the device. The Probe pin can be used as a user-defined I/O
when verification has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality.
Supply voltage for I/Os. See Table 2 on page 6.
VCCA
Supply Voltage
Supply voltage for Array. See Table 2 on page 6.
VSV
Programming Voltage
Supply voltage used for device programming. This pin can be
tied to VCCA or VCCI but cannot exceed 3.6V. If the security
fuse is programmed, the VSV limit is extended to 6.0V.
20
v3.0
eX Family FPGAs
Package Pin Assignments
64-Pin TQFP (Top View)
64
1
64-Pin
TQFP
v3.0
21
eX Family FPGAs
64-Pin TQFP
eX64
Function
eX128
Function
eX64
Function
eX128
Function
Pin Number
Pin Number
1
GND
TDI, I/O
I/O
GND
TDI, I/O
I/O
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
GND
I/O
GND
I/O
2
3
I/O
I/O
1
1
4
TMS
GND
VCCI
I/O
TMS
GND
VCCI
I/O
VSV
VSV
5
VCCI
I/O
VCCI
I/O
6
7
I/O
I/O
8
I/O
I/O
NC
I/O
9
NC
I/O
NC
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
I/O
I/O
I/O
TRST, I/O
I/O
TRST, I/O
I/O
I/O
I/O
VCCA
GND/LP1
GND
I/O
VCCA
GND/ LP1
GND
I/O
NC
I/O
GND
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
PRB, I/O
VCCA
GND
I/O
PRB, I/O
VCCA
GND
I/O
I/O
I/O
CLKA
CLKB
VCCA
GND
PRA, I/O
I/O
CLKA
CLKB
VCCA
GND
PRA, I/O
I/O
HCLK
I/O
HCLK
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
TDO, I/O
TCK, I/O
TCK, I/O
1. Please read the VSV and LP pin descriptions for restrictions on their use.
22
v3.0
eX Family FPGAs
Package Pin Assignments (Continued)
100-Pin TQFP (Top View)
100
1
100-Pin
TQFP
v3.0
23
eX Family FPGAs
100-TQFP
eX64
eX128
eX256
eX64
eX128
eX256
Pin Number
Function
Function
Function
Pin Number
Function
Function
Function
1
GND
TDI, I/O
NC
GND
TDI, I/O
NC
GND
TDI, I/O
I/O
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
GND
NC
NC
NC
I/O
GND
NC
NC
NC
I/O
GND
I/O
2
3
I/O
4
NC
NC
I/O
I/O
5
NC
NC
I/O
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
1
1
1
7
TMS
VCCI
GND
NC
TMS
VCCI
GND
I/O
TMS
VCCI
GND
I/O
VSV
VSV
VSV
8
VCCI
NC
VCCI
I/O
VCCI
I/O
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
TRST, I/O
NC
TRST, I/O
I/O
TRST, I/O
I/O
I/O
I/O
I/O
VCCA
GND/LP1
GND
I/O
VCCA
GND/LP1
GND
I/O
VCCA
GND/LP1
GND
I/O
I/O
I/O
I/O
NC
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
NC
NC
I/O
NC
NC
I/O
NC
NC
I/O
NC
NC
I/O
I/O
I/O
I/O
NC
NC
I/O
I/O
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
PRB, I/O
VCCA
GND
NC
PRB, I/O
VCCA
GND
NC
PRB, I/O
VCCA
GND
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CLKA
CLKB
NC
CLKA
CLKB
NC
CLKA
CLKB
NC
I/O
I/O
I/O
HCLK
I/O
HCLK
I/O
HCLK
I/O
VCCA
GND
PRA, I/O
I/O
VCCA
GND
PRA, I/O
I/O
VCCA
GND
PRA, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
NC
TDO, I/O
I/O
TDO, I/O
I/O
I/O
I/O
I/O
TCK, I/O
TCK, I/O
TCK, I/O
1. Please read the VSV and LP pin descriptions for restrictions on their use.
24
v3.0
eX Family FPGAs
Package Pin Assignments (Continued)
49-Pin CSP (Top View)
A1 Ball Pad Corner
1
2
3
5
6
7
4
A
B
C
D
E
F
G
49-Pin CSP
eX64
Function
eX128
Function
eX64
Function
eX128
Function
Pin Number
Pin Number
1
1
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
C1
C2
C3
C4
C5
C6
C7
D1
D2
D3
D4
I/O
I/O
I/O
I/O
D5
D6
D7
E1
E2
E3
E4
E5
E6
E7
F1
F2
F3
F4
F5
F6
F7
G1
G2
G3
G4
G5
G6
G7
VSV
VSV
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
VCCA
I/O
TRST, I/O
VCCI
GND
I/O
TRST, I/O
VCCI
GND
I/O
I/O
I/O
TCK, I/O
I/O
TCK, I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
VCCI
I/O
PRA, I/O
CLKA
I/O
PRA, I/O
CLKA
I/O
I/O
I/O
I/O
I/O
GND/LP1
GND/LP1
I/O
I/O
I/O
I/O
HCLK
I/O
HCLK
I/O
TDI, I/O
VCCI
GND
CLKB
VCCA
I/O
TDI, I/O
VCCI
GND
CLKB
VCCA
I/O
TDO, I/O
I/O
TDO, I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
VCCA
I/O
PRB, I/O
VCCA
I/O
I/O
I/O
TMS
GND
GND
TMS
GND
GND
I/O
I/O
1. Please read the VSV and LP pin descriptions for restrictions on their use.
v3.0
25
eX Family FPGAs
Package Pin Assignments (Continued)
128-Pin CSP (Top View)
A1 Ball Pad Corner
2
3
4
5
6
8
12
1
7
9
10 11
A
B
C
D
E
F
G
H
J
K
L
M
26
v3.0
eX Family FPGAs
128-CSP
eX64
eX128
eX256
eX64
eX128
eX256
Pin Number
Function
Function
Function
Pin Number
Function
Function
Function
A1
A2
I/O
TCK, I/O
VCCI
I/O
I/O
TCK, I/O
VCCI
I/O
I/O
TCK, I/O
VCCI
I/O
D4
D5
I/O
I/O
I/O
I/O
I/O
I/O
A3
D6
GND
I/O
GND
I/O
GND
I/O
A4
D7
A5
I/O
I/O
I/O
D8
GND
I/O
GND
I/O
GND
I/O
A6
VCCA
I/O
VCCA
I/O
VCCA
I/O
D9
A7
D10
D11
D12
E1
I/O
I/O
I/O
A8
I/O
I/O
I/O
I/O
I/O
I/O
A9
VCCI
I/O
VCCI
I/O
VCCI
I/O
VCCI
NC
VCCI
I/O
VCCI
I/O
A10
A11
A12
B1
I/O
I/O
I/O
E2
VCCI
I/O
VCCI
I/O
VCCI
I/O
I/O
I/O
I/O
E3
TMS
I/O
TMS
I/O
TMS
I/O
E4
GND
GND
I/O
GND
GND
I/O
GND
GND
I/O
B2
E9
B3
I/O
I/O
I/O
E10
E11
E12
F1
B4
I/O
I/O
I/O
GND/LP1
VCCA
NC
GND/LP1
VCCA
I/O
GND/LP1
VCCA
I/O
B5
I/O
I/O
I/O
B6
PRA, I/O
CLKB
I/O
PRA, I/O
CLKB
I/O
PRA, I/O
CLKB
I/O
B7
F2
NC
I/O
I/O
B8
F3
NC
I/O
I/O
B9
I/O
I/O
I/O
F4
I/O
I/O
I/O
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
I/O
I/O
I/O
F9
GND
NC
GND
I/O
GND
I/O
GND
I/O
GND
I/O
GND
I/O
F10
F11
F12
G1
G2
G3
G4
G9
G10
G11
G12
H1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI, I/O
I/O
TDI, I/O
I/O
TDI, I/O
I/O
NC
I/O
I/O
TRST, I/O
I/O
TRST, I/O
I/O
TRST, I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
NC
GND
GND
I/O
GND
GND
I/O
CLKA
I/O
CLKA
I/O
CLKA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
GND
I/O
GND
I/O
GND
I/O
NC
I/O
I/O
H2
I/O
I/O
I/O
H3
VCCI
GND
I/O
VCCI
GND
I/O
VCCI
GND
I/O
NC
I/O
I/O
H4
I/O
I/O
I/O
H9
I/O
I/O
I/O
H10
VCCI
VCCI
VCCI
v3.0
27
eX Family FPGAs
128-CSP
eX64
eX128
eX256
eX64
eX128
eX256
Pin Number
Function
Function
Function
Pin Number
Function
Function
Function
1
1
1
H11
H12
J1
VSV
VSV
VSV
K12
L1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
GND
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
GND
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
NC
NC
I/O
NC
I/O
VSV1
I/O
L2
I/O
J2
I/O
I/O
L3
NC
I/O
J3
VCCI
I/O
VCCI
I/O
VCCI
I/O
L4
J4
L5
I/O
J5
I/O
I/O
I/O
L6
I/O
J6
I/O
I/O
I/O
L7
I/O
J7
GND
I/O
GND
I/O
GND
I/O
L8
I/O
J8
L9
I/O
J9
GND
I/O
GND
I/O
GND
I/O
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
I/O
J10
J11
J12
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
NC
VCCI
GND
I/O
I/O
I/O
I/O
NC
I/O
I/O
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRB, I/O
HCLK
I/O
PRB, I/O
HCLK
I/O
PRB, I/O
HCLK
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDO, I/O
TDO, I/O
TDO, I/O
I/O
1. Please read the VSV and LP pin descriptions for restrictions on their use.
28
v3.0
eX Family FPGAs
Package Pin Assignments (Continued)
180-Pin CSP (Top View)
A1 Ball Pad Corner
12
1
2
3
4
5
6
7
9
10
14
13
8
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
v3.0
29
eX Family FPGAs
180-Pin CSP
eX256
eX256
eX256
eX256
Pin Number
Function
Pin Number
Function
Pin Number
Function
Pin Number
Function
A1
A2
I/O
I/O
D6
D7
I/O
CLKA
I/O
H5
H10
H11
H12
H13
H14
J1
GND
GND
I/O
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
N1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCI
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCA
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
NC
NC
NC
NC
NC
NC
NC
NC
GND
I/O
I/O
A3
GND
NC
D8
A4
D9
I/O
I/O
A5
NC
D10
D11
D12
D13
D14
E1
I/O
I/O
A6
NC
I/O
I/O
A7
NC
I/O
I/O
A8
NC
I/O
J2
GND
I/O
A9
NC
I/O
J3
A10
A11
A12
A13
A14
B1
NC
I/O
J4
VCCI
GND
I/O
NC
E2
I/O
J5
I/O
E3
I/O
J10
J11
J12
J13
J14
K1
I/O
E4
I/O
VCCI
N2
1
I/O
E5
I/O
VSV
N3
I/O
E6
I/O
I/O
I/O
I/O
N4
B2
I/O
E7
GND
I/O
N5
B3
TCK, I/O
VCCI
I/O
E8
N6
1
B4
E9
GND
I/O
K2
VSV
N7
B5
E10
E11
E12
E13
E14
F1
K3
I/O
VCCI
I/O
N8
B6
I/O
I/O
K4
N9
B7
VCCA
I/O
I/O
K5
N10
N11
N12
N13
N14
P1
B8
VCCI
I/O
K6
I/O
B9
I/O
K7
I/O
B10
B11
B12
B13
B14
C1
VCCI
I/O
I/O
K8
GND
I/O
F2
I/O
K9
I/O
F3
VCCI
I/O
K10
K11
K12
K13
K14
L1
GND
I/O
I/O
F4
P2
I/O
F5
GND
GND
I/O
GND/LP1
VCCA
I/O
I/O
P3
I/O
F10
F11
F12
F13
F14
G1
I/O
P4
C2
TMS
I/O
I/O
P5
C3
I/O
P6
C4
I/O
L2
I/O
P7
C5
I/O
L3
I/O
P8
C6
I/O
VCCA
I/O
L4
I/O
P9
C7
PRA, I/O
CLKB
I/O
G2
L5
I/O
P10
P11
P12
P13
P14
C8
G3
I/O
L6
I/O
C9
G4
I/O
L7
PRB, I/O
HCLK
I/O
C10
C11
C12
C13
C14
D1
I/O
G5
I/O
L8
I/O
G10
G11
G12
G13
G14
H1
GND
I/O
L9
GND
I/O
L10
L11
L12
L13
L14
M1
M2
M3
I/O
I/O
I/O
I/O
I/O
TDO, I/O
I/O
I/O
VCCA
I/O
D2
I/O
I/O
D3
TDI, I/O
I/O
H2
I/O
I/O
D4
H3
TRST, I/O
I/O
I/O
D5
I/O
H4
I/O
1. Please read the VSV and LP pin descriptions for restrictions on their use.
30
v3.0
eX Family FPGAs
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous version Changes in current version (v3.0)
Page
The “Recommended Operating Conditions” on page 8 has been changed.
The “3.3V Electrical Specifications” on page 9 has been updated.
page 8
page 9
page 9
page 11
page 11
page 13
page 5
The “5.0V Electrical Specifications” on page 9 has been updated.
v2.0.1
The “Total Dynamic Power (mW)” on page 11 is new.
The System Power at 5%, 10%, and 15% Duty Cycle is new.
The “eX Timing Model*” on page 13 has been updated.
The I/O Features table, Table 1 on page 5, was updated.
The table, “2.5V LP/Sleep Mode Specifications Typical Conditions, VCCA, VCCI =
2.5V, TJ = 25° C” on page 6, was updated.
page 6
“Typical eX Standby Current at 25°C” on page 8 is a new table.
page 8
The table in the section, “Package Thermal Characteristics” on page 12 has been
updated for the 49-Pin CSP.
page 11
page 12
pages 15-18
page 18
The “eX Timing Model*” on page 13 has been updated.
Advanced v0.4
The timing numbers found in, “eX Family Timing Characteristics” on page 16 have
been updated.
The VSV pin has been added to the “Pin Description” on page 20.
Please see the following pin tables for the VSV pin and an important footnote
including the pin: “64-Pin TQFP” on page 22,“100-TQFP” on page 24,“49-Pin CSP”
on page 25,“128-CSP” on page 27, and “180-Pin CSP” on page 30.
pages- 21, 23, 24,
26, 27, 29
The figure, “100-Pin TQFP (Top View)” on page 23 has been updated.
page 22
page 1
In the Product Profile table, the Maximum User I/Os for eX64 was changed to 84.
Advanced v0.3
In the Product Profile table, the Maximum User I/Os for eX128 was changed to 100. page 1
The Mechanical Drawings section has been removed from the data sheet. The
mechanical drawings are now contained in a separate document, “Package
Characteristics and Mechanical Drawings,” available on the Actel web site.
A new section describing Clock Resources has been added.
A new table describing I/O Features has been added.
page 5
page 6
page 21
The Pin Description section has been updated and clarified.
The original Electrical Specifications table was separated into two tables (2.5V and
Page 8 and 9
3.3/5.0V). In both tables, several different currents are specified for VOH and VOL
.
Advanced v0.2
A new table listing 2.5V low power specifications and associated power graphs were
added.
page 9
Pin functions for eX256 TQ100 have been added to the 100-TQFP table.
page 25
page 26
A CS49 pin drawing and pin assignment table including eX64 and eX128 pin
functions have been added.
A CS128 pin drawing and pin assignment table including eX64, eX128, and eX256
pin functions have been added.
pages 26-27
pages 27, 31
A CS180 pin drawing and pin assignment table for eX256 pin functions have been
added.
The following table note was added to the eX Timing Characteristics table for
clarification: Clock skew improves as the clock network becomes more heavily
loaded.
Advanced v.1
pages 14-15
v3.0
31
eX Family FPGAs
Data Sheet Categories
In order to provide the latest information to designers, some data sheets are published before data has been fully
characterized. Product Briefs are modified versions of data sheets. Data sheets are marked as “Advanced,” “Preliminary,” and
“Web-only.” The definition of these categories are as follows:
Product Brief
The product brief is a modified version of an Advanced data sheet containing general product information. This brief
summarizes specific device and family information for non-release products.
Advanced
The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This
information can be used as estimates, but not for production.
Preliminary
The data sheet contains information based on simulation and/or initial characterization. The information is believed to be
correct, but changes are possible.
Unmarked (production)
The data sheet contains information that is considered to be final.
Web-only Versions
Web-only versions have three numbers in the version number (example: v2.0.1). A web-only version means Actel is posting
the data sheet so customers have the latest information, but we are not printing the version because some information is
going to change shortly after posting.
32
v3.0
eX Family FPGAs
v3.0
33
eX Family FPGAs
34
v3.0
eX Family FPGAs
v3.0
35
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Europe Ltd.
Actel Corporation
955 East Arques Avenue
Sunnyvale, California 94086
USA
Actel Asia-Pacific
Maxfli Court, Riverside Way
Camberley, Surrey GU15 3YL
United Kingdom
EXOS Ebisu Bldg. 4F
1-24-14 Ebisu Shibuya-ku
Tokyo 150 Japan
Tel: +44 (0)1276 401450
Fax: +44 (0)1276 401490
Tel: (408) 739-1010
Fax: (408) 739-1540
Tel: +81 03-3445-7671
Fax: +81 03-3445-7668
5172154-4/12.01
相关型号：
EX128-PTQ64X79
Field Programmable Gate Array, 256 CLBs, 6000 Gates, 357MHz, 384-Cell, CMOS, PQFP64, 0.50 MM PITCH, PLASTIC, TQFP-64
ACTEL
EX128-TQ100AX79
Field Programmable Gate Array, 6000 Gates, 250MHz, 384-Cell, CMOS, PQFP100, 1.40 MM PITCH, TQFP-100
ACTEL
EX128-TQ100X79
Field Programmable Gate Array, 256 CLBs, 6000 Gates, 250MHz, 384-Cell, CMOS, PQFP100, 0.50 MM PITCH, PLASTIC, TQFP-100
ACTEL
©2020 ICPDF网 联系我们和版权申明