FAN5242QSC [ETC]
;
ETC 
www.fairchildsemi.com
FAN5242
Voltage Regulator for IMVP-II Notebook Processors
Features
Description
• Powers Intel IMVP-II CPU core
• 0.600V to 1.750V output voltage range
The FAN5242 provꢂdes the power, control and protectꢂon ꢁor
the CPU ꢂn Intel IMVP-II notebook PC applꢂcatꢂons. The IC
ꢂntegrates a PWM controller as well as monꢂtorꢂng and
protectꢂon cꢂrcuꢂtry ꢂnto a sꢂngle 24 lead QSOP package.
It provꢂdes hꢂgh eꢁficꢂency PWM at maxꢂmum load and
hysteretꢂc conversꢂon at mꢂnꢂmum load, and generates Intel
specꢂfied load lꢂnes ꢂn both Perꢁormance and Battery Mode.
•
1ꢀ reꢁerence precꢂsꢂon over temperature
• Dynamꢂc VID code change supported
• 5V to 24V ꢂnput voltage range
• Specꢂal controls ꢁor Battery Mode and Deeper Sleep
Mode
• Meets IMVP-II Load Lꢂnes
• Hꢂgh eꢁficꢂency at all load currents
• Actꢂve Droop provꢂdes correct load lꢂnes
• True dꢂꢁꢁerentꢂal remote voltage sense
• Current sense uses MOSFETs
• Power Good, Over-current, OV, UVLO
• Space-savꢂng QSOP24
The FAN5242 ꢂncludes an Intel specꢂfied 5-ꢂnput DAC that
adjusts the core PWM output voltage ꢁrom 600mV to
1.750V ꢂn 25mV steps. The DAC settꢂng may be changed
durꢂng operatꢂon, transꢂtꢂon occurrꢂng ꢂn <100µsec. A
precꢂsꢂon reꢁerence, true dꢂꢁꢁerentꢂal remote sense, and a
proprꢂetary archꢂtecture wꢂth actꢂve droop provꢂde excellent
statꢂc and dynamꢂc core voltage regulatꢂon. The FAN5242
ꢂncludes over-voltage, and over-current protectꢂon, and an
enable. It ꢂs avaꢂlable ꢂn a QSOP 24.
Applications
• Notebook CPUs
• Internet applꢂances
Typical Application
Vin = 5–24V
13
1
18
19
20
21
5
VCORE
7
+
6
23
22
16
17
24
15
FAN5242
12
11
10
9
DPSLP
3
4
PGOOD
EN
DPRSLPVR
14
2
SS
GMUXSEL
8
+5Vin
REV. 1.0.1 1/24/02
FAN5242
PRODUCT SPECIFICATIONS
Pin Assignments
1
24
23
22
21
20
19
18
AGND
VCC
PVCC
LDRV
PGND
ISNS
SW
2
3
PWRGD
ENBL
FPWM
SLP
4
5
6
HDRV
BOOT
VCORE
VCORE
ILIM
7
FREQ
VID4
8
17
16
15
14
13
9
VID3
10
11
12
VID2
VID1
SS
VID0
VBATT
Pin Description
Pin
Number Pin Name
Pin Function Description
1
2
3
4
AGND
Analog Ground. Return path for low power analog circuitry. This pin should be
connected to a low impedance system ground plane to minimize ground loops.
VCC
VCC. Internal IC supply. Connect to system 5V supply, and decouple with a 0.1µF
ceramic capacitor.
PWRGD
ENABLE
Power Good Flag. An open collector output that will be logic LOW if the output voltage
is not within 10ꢀ of the nominal output voltage setpoint.
Output Enable. A logic LOW on this pin will disable the output. An internal current source
allows for open collector control.
5
6
7
FPWM
SLP
Forced PWM. A logic HIGH on this pin forces the converter to remain in PWM mode.
Sleep Input. A resistor to ground on this pin overrides the VID settings.
FREQ
Frequency Set. Grounding this pin sets the switching frequency to 300KHz. Attaching it
to VCC sets the frequency to 600KHz.
8-12
VID0-4
Voltage Identification Code Inputs. These open collector/TTL compatible inputs will
program the output voltage over the range specified in Table 2. Pull-ups are internal to
the controller.
13
14
15
VBATT
SS
Battery Voltage Input. Connect to the main power source.
Soft Start.
ILIM
Current Limit. A resistor from this pin to ground sets the over current trip level.
16-17 VCORE,
VCORE
Voltage Feedback. Connect these pins to the desired regulation point at the processor
for true differential feedback.
18
19
BOOT
HDRV
Bootstrap. Input supply for high-side MOSFET.
High Side FET Driver. Connect this pin to the gate of an N-channel MOSFET. The trace
from this pin to the MOSFET gate should be <0.5".
20
21
22
23
24
SW
High side driver source and low side driver drain switching node. Gate drive return
for high side MOSFET, and negative input for low-side MOSFET current sense.
ISNS
PGND
LDRV
PVCC
Current Sense. Connect this pin to the SW node through a resistor to sense output
current.
Power Ground. Return pin for high currents flowing in low-side MOSFET. Connect
directly to low-side MOSFET source.
Low Side FET Driver. Connect this pin to the gate of an N-channel MOSFET for
synchronous operation. The trace from this pin to the MOSFET gate should be <0.5".
Power VCC. Provides power to drive low-side MOSFET.
2
REV. 1.0.1 1/24/02
PRODUCT SPECIFICATIONS
FAN5242
Absolute Maximum Ratings
Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life
impaired. Functional operation under these conditions is not implied.
Parameter
Min.
Typ.
Max.
6.5
Units
VCC Supply Voltage:
VBATT
V
V
27
BOOT, SW, HDRV Pins
BOOT to SW
33
V
6.5
V
All Other Pins
–0.3
–10
–65
VCC+0.3
150
V
Junction Temperature (TJ )
Storage Temperature
Lead Soldering Temperature, 10 seconds
°C
°C
°C
150
300
Recommended Operating Conditions
Parameter
Conditions
Min.
4.75
5
Typ.
Max. Units
Supply Voltage VCC
Supply Voltage VBATT
Ambient Temperature (TA )
5
5.25
24
V
V
–10
85
°C
Electrical Specifications
(VCC = 5V, VBATT = 5V–24V, and TA = recommended operating ambient temperature range using circuit of Figure
1 unless otherwise noted.)
Parameter
Conditions
Min.
Typ.
Max.
Units
Power Supplies
VCC Current
Operating, CL = 10pF
Shut-down (ENABLE=0)
Operating
2.7
6
3.2
30
mA
µA
µA
µA
V
VBATT Current
UVLO Threshold
12
20
Shut-down (ENABLE=0)
Rising VCC
1
4.3
4.1
4.65
4.35
4.75
4.45
Falling
V
Regulator / Control Functions
Output voltage
per Table 1. Output Voltage VID
0.6
–1
–2
1.75
1
V
% VID
% VID
dB
Initial Accuracy
Static Load Regulation
Error Amplifier Gain
2
86
2.7
1
Error Amplifier GBW
Error Amplifier Slew Rate
ILIM Voltage
MHz
V/µS
V
RILIM = 30KΩ
0.89
1.9
1.6
72
0.91
2.0
3.2
78
Over-voltage Threshold
Over-voltage Protection delay
Under-voltage Shutdown
Under-voltage Delay
ENABLE, input threshold
1.95
75
V
µS
Disabled during VID code change
% VID
µS
1.2
1.6
1.2
Logic LOW
Logic HIGH
V
2
V
REV. 1.0.1 1/24/02
3
FAN5242
PRODUCT SPECIFICATIONS
Electrical Specifications(Continued)
(VCC = 5V, VBATT = 5V–24V, and TA = recommended operating ambient temperature range using circuit of Figure
1 unless otherwise noted.)
Parameter
Conditions
Min.
Typ.
Max.
Units
Output Drivers
HDRV Output Resistance
Sourcing
Sinking
3.8
1.6
3.8
0.8
5
3
Ω
Ω
Ω
Ω
LDRV Output Resistance
Sourcing
Sinking
5
1.5
Oscillator
Frequency
FREQ = HIGH
FREQ = LOW
VBATT = 16V
255
510
300
600
2
345
690
KHz
KHz
V
Ramp Amplitude, pk–pk
Ramp Offset
0.5
125
V
Ramp Gain
Ramp amplitude
-------------------------------------------
VIN
mV/V
Reference, DAC and Soft-Start
VID input threshold
Logic LOW
1.21
V
V
Logic HIGH
1.62
VID pull-up current
to internal 2.5V reference
12
µA
%
DAC output accuracy
–1
20
1
Soft Start current (ISS
)
at start-up, VSS.< 0.5
26
500
10
32
µA
µA
µA
V
at start-up, 1.75 > VSS.> 0.5
350
9.5
1.71
650
10.5
1.78
SLP Current Source
SLP to VID mode threshold
PWRGD
1.75
VCORE Upper Threshold
VCORE Lower Threshold
123
77
127
81
% VID
% VID
% VID
V
Falling Edge
Rising Edge
IPWRGD = 4mA
VPULLUP = 5V
87
94
PWRGD Output Low
Leakage Current
0.5
1
µA
4
REV. 1.0.1 1/24/02
PRODUCT SPECIFICATIONS
FAN5242
Table 1. Output Voltage Programming Codes
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VOUT to CPU
0.600
0.625
0.650
0.675
0.700
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.050
1.100
1.150
1.200
1.250
1.300
1.350
1.400
1.450
1.500
1.550
1.600
1.650
1.700
1.750
1 - Logic High or open, 0 = Logic Low
REV. 1.0.1 1/24/02
5
FAN5242
PRODUCT SPECIFICATIONS
Application Circuit
Vin = 5–24V
+5Vin
+
C1-2
C3
D1
C4
13
1
18
19
20
21
L1
Q4
R5
Q5
5
Processor @ 17.6A
+
7
Q6
C5-7
R7
6
23
22
16
17
24
15
12
11
10
9
+5Vin
R1
R2
U1
FAN5242
Q7
R8
Q2
R4
DPSLP
R3
Q1
PGOOD
3
4
+3.3V
EN
R6
DPRSLPVR
14
2
Q3
R9
Q8
C8
8
+5Vin
C9
GMUXSEL
Figure 1. FAN5242 IMVP-II Application Circuit
Table 2. FAN5242 Application Bill of Materials
Reference Manufacturer, Part # Quantity
Description
Comments
C1-2
AVX
2
68µF, 25V Tantalum
TPSV686*025#0150
C3, C9
C4, C8
C5-7
Any
Any
Panasonic
2
2
3
1µF Ceramic
220nF, Ceramic
270µF, Polymer
EEFUE0D271R
R1, R6
R2
R3
R4
R5
R7
R8
R9
D1
Any
Any
Any
Any
Any
Any
Any
Any
2
1
1
1
1
1
1
1
1
10KΩ
117.3KΩ, 1%
698Ω, 1%
2.74KΩ, 1%
5.62KΩ, 1%
10Ω, 1%
1.69KΩ, 1%
TBD KΩ, 1%
0.5A, 20V Schottky
Fairchild
MBRD0520
L1
Coiltronics
DR127-1R0
Fairchild
FDV301N
Fairchild
FDS6690A
Fairchild
FDS6680S
1
4
1
2
1
1
1.0µH, 16A Inductor
N MOSFET
R < 2.5mΩ
Q1-3, Q8
Q4
SOT-23
30V N MOSFET
R = 17mΩ
Q5-6
Q7
30V N MOSFET w/ Schottky R = 17mΩ
Fairchild
FDV302P
Fairchild
P MOSFET
SOT-23
U1
CPU Controller
FAN5242
6
REV. 1.0.1 1/24/02
PRODUCT SPECIFICATIONS
FAN5242
Selectꢂon oꢁ a current-lꢂmꢂt resꢂstor must ꢂnclude the toler-
Applications Information
ance oꢁ the current-lꢂmꢂt trꢂp poꢂnt, the MOSFET RDS,on
tolerance and temperature coeꢁficꢂent, and the rꢂpple current,
ꢂn addꢂtꢂon to the maxꢂmum output current.
Overview
The FAN5242 ꢂs a hꢂgh eꢁficꢂency and hꢂgh precꢂsꢂon DC/DC
controller ꢁor IMVP-II powered notebooks and other
portable applꢂcatꢂons. It provꢂdes the voltage necessary ꢁor
portable applꢂcatꢂons’ processor core. The core voltage ꢂs
programmed wꢂth a 5-bꢂt VID. Utꢂlꢂzatꢂon oꢁ both ꢂnput and
output voltage ꢁeedback, and summꢂng-mode compensatꢂon,
allows ꢁor ꢁast loop response over a wꢂde range oꢁ ꢂnput and
output varꢂatꢂons. Thꢂs scheme has a superꢂor range oꢁ output
current operatꢂon and ꢂs ꢁree oꢁ the lꢂght load ꢂnstabꢂlꢂtꢂes
typꢂcal oꢁ current mode. The IC desꢂgn allows ꢁor a mꢂnꢂ-
mum sꢂze desꢂgn oꢁ magnetꢂcs and dꢂscrete transꢂstors ꢁor
mꢂnꢂmum cost and space at maxꢂmum perꢁormance. Actꢂve
droop on the CPU output also mꢂnꢂmꢂzes the number oꢁ out-
put capacꢂtors requꢂred. Also ꢂncluded are a number oꢁ addꢂ-
tꢂonal ꢁeatures to make desꢂgn straꢂghtꢁorward, ꢂncludꢂng a
pꢂn to set the core voltage durꢂng Deep Sleep and Deeper
Sleep.
Example: Maxꢂmum DC output current ꢂs 18A, and the
ꢂnductor ꢂs 1.0µH at thꢂs current. The MOSFETs have a
cumulatꢂve RDS,on = 8.5mΩ at VGS = 4.5V, and wꢂll be
runnꢂng at 100°C, at whꢂch ꢂts resꢂstance ꢂs 30ꢀ hꢂgher than
at 25°C.
Peak current ꢂs DC output current plus peak rꢂpple current:
TVo
4µsec × 1.25V
I
= IDC + ---------- = 18A + ----------------------------------- = 21A
pk
2L
2 × 1µH
where T ꢂs the maxꢂmum perꢂod, VO ꢂs output voltage, and L
ꢂs the ꢂnductance. The voltage across the MOSFET at thꢂs
current ꢂs
V = Ipk × RDS,on × TC = 21A × 8.5mΩ × 1.3
Power Architecture
= 230mV
The power output oꢁ the FAN5242 ꢂs generated ꢁrom the
unregulated ꢂnput voltage usꢂng synchronous buck convert-
ers. Both the hꢂgh-sꢂde and the low-sꢂde MOSFET are
N-channels to maxꢂmꢂze eꢁficꢂency.
The current source drꢂvꢂng the external resꢂstor ꢂs 100µA
mꢂnꢂmum, so we must use
V
I
230mV
100µA
R ≥ --- = ------------------ = 2.39kΩ
The power output has a pꢂn ꢁor settꢂng output overcurrent;
two pꢂns ꢁor remote voltage-sense ꢁeedback; a pꢂn that gener-
ates a soꢁtstart; and an enable pꢂn that can be used to shut-
down the converter.
Softstart Timing
Soꢁtstart oꢁ the converter ꢂs accomplꢂshed by attachꢂng a
capacꢂtor to the SS pꢂn.
Loop Description
The control loop oꢁ the FAN5242 uses summꢂng-mode con-
trol, and requꢂres no external compensatꢂon. The control loop
measures the current dꢂꢁꢁerentꢂally across ꢂts low-sꢂde MOS-
FET, subtractꢂng ꢂt ꢁrom the ground voltage, and subtracts
the sum ꢁrom the reꢁerence voltage. In addꢂtꢂon, ꢂt uses volt-
age ꢁeed-ꢁorward to guarantee loop rejectꢂon oꢁ ꢂnput voltage
varꢂatꢂon: the ramp amplꢂtude ꢂs varꢂed as a ꢁunctꢂon oꢁ the
ꢂnput voltage.
Example: To get approxꢂmately a 1msec soꢁtstart, select a
It
C = --- = ------------------------------------ = 1 0 n F
1V
10µA × 1msec
V
capacꢂtor.
Light Load Mode
Compensatꢂon oꢁ the control loop amounts to merely select-
ꢂng suꢂtable output capacꢂtors. Most selectꢂons oꢁ common
Tantalum capacꢂtors wꢂll result ꢂn a stable loop wꢂth adequate
phase margꢂn, as wꢂll Oscons or Polycaps.
Because the converter ꢂs a synchronous buck, ꢂt can operate
ꢂn two quadrants, whꢂch means that the rꢂpple current ꢂs a
constant ꢂndependent oꢁ the load current. At lꢂght loads, thꢂs
rꢂpple current translates ꢂnto poor eꢁficꢂency, sꢂnce ꢂt causes
cꢂrculatꢂng current losses ꢂn the MOSFETs. To optꢂmꢂze the
eꢁficꢂency at lꢂght loads, then, the FAN5242 swꢂtches ꢁrom
normal operatꢂon to a specꢂal lꢂght load when the current ꢂs
low. Lꢂght load occurs when the on-state draꢂn-source volt-
age ꢂs less than about 17mV.
Current Limit
The converter senses the voltage across the low-sꢂde N-chan-
nel MOSFET (ꢁrom the SW pꢂn to ground) and compares ꢂt
to the voltage across a resꢂstor ꢁrom SW to the ISNS pꢂns; ꢂt
can also use a dꢂscrete resꢂstor ꢂn serꢂes wꢂth the low-sꢂde
MOSFET ꢁor precꢂsꢂon. Iꢁ the voltage drop exceeds the set-
poꢂnt, the soꢁtstart capacꢂtor ꢂs dꢂscharged, ꢁorcꢂng the con-
verter to re-soꢁtstart.
In lꢂght load mode, the FAN5242 swꢂtches ꢁrom PWM (pulse
wꢂdth modulatꢂon) to PFM (pulse ꢁrequency modulatꢂon),
whꢂch reduces the gate drꢂve current. It also turns oꢁꢁ the low
sꢂde drꢂve completely, whꢂch ꢁurther saves on gate current; ꢂn
REV. 1.0.1 1/24/02
7
FAN5242
PRODUCT SPECIFICATIONS
thꢂs mode, the converter operates non-synchronously, usꢂng
the output schottky. The swꢂtch to thꢂs mode oꢁ operatꢂon can
be avoꢂded by pullꢂng the FPWM pꢂn to VCC.
The ISNS pꢂn can be quꢂte sensꢂtꢂve to stray capacꢂtance, and
so ꢂt ꢂs ꢂmportant to use a low capacꢂtance swꢂtch ꢁor the
resꢂstor to ground, such as the Faꢂrchꢂld FDV301N shown ꢂn
the Fꢂgure.
Setting the Switching Frequency
Overvoltage Protection
Connectꢂng the FREQ pꢂn to ground sets the swꢂtchꢂng ꢁre-
quency to 300KHz. Connectꢂng the FREQ pꢂn to VCC sets
the swꢂtchꢂng ꢁrequency to 600KHz.
When the output voltage oꢁ the converter exceeds approxꢂ-
mately 120ꢀ oꢁ nomꢂnal, ꢂt enters ꢂnto over-voltage protec-
tꢂon, wꢂth the goal oꢁ protectꢂng the load ꢁrom damage. In
over-voltage protectꢂon, the hꢂgh-sꢂde MOSFET ꢂs turned oꢁꢁ
and the low-sꢂde MOSFET ꢂs turned on, crowbarrꢂng the out-
put. Once over-voltage protectꢂon ꢂs trꢂggered, ꢂt remaꢂns on
untꢂl power ꢂs recycled.
Setting the Voltage with SLP
Deep Sleep and Deeper Sleep voltages can be set wꢂth the
SLP pꢂn. When the SLP pꢂn ꢂs open, the output voltage oꢁ the
converter ꢂs set by the VID pꢂns. When the SLP pꢂn has a
resꢂstor to ground, the output voltage oꢁ the converter wꢂll be
equal to 10µA ✕ R. Thus, the DEEPSLEEP voltage oꢁ
1.173V can be obtaꢂned by turnꢂng on a swꢂtch wꢂth a
117.3KΩ resꢂstor to ground, and the DEEPERSLEEP
voltage oꢁ 700mV can be obtaꢂned by turnꢂng on a swꢂtch
wꢂth a 698Ω resꢂstor to ground.
Power good
Power good ꢂs asserted when the output ꢂs wꢂthꢂn ꢂts specꢂ-
fied tolerance.
ENABLE
The ENBL pꢂn does the on/oꢁꢁ control. Pullꢂng thꢂs pꢂn low
turns oꢁꢁ the converter.
Setting the Load Line with ISNS
The load lꢂne can be set wꢂth a resꢂstor between the swꢂtchꢂng
node oꢁ the power MOSFETs and the ISNS pꢂn, and ꢁurther
adjusted wꢂth a resꢂstor ꢁrom the ISNS pꢂn to ground. The
schematꢂc oꢁ Fꢂgure 3 shows how to obtaꢂn the nomꢂnal Per-
ꢁormance Mode load lꢂne oꢁ 4mV/A, and how to use a swꢂtch
connected to the GMUXSEL sꢂgnal to obtaꢂn the Battery
Mode load lꢂne oꢁ 3mV/A.
Thermal shutdown
Iꢁ the dꢂe temperature oꢁ the FAN5242 exceeds saꢁe lꢂmꢂts,
the IC shuts ꢂtselꢁ oꢁꢁ.
UVLO
Iꢁ the ꢂnput voltages ꢁalls below the UVLO threshold, the
FAN5242 turns ꢂtselꢁ oꢁꢁ.
8
REV. 1.0.1 1/24/02
PRODUCT SPECIFICATIONS
FAN5242
Mechanical Dimensions
24 Lead QSOP
Notes:
Inches
Min. Max.
0.0532 0.0668
Millimeters
Symbol
Notes
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
Min.
Max.
2. "D" and "E" do not include mold flash. Mold flash or
protrusions shall not exceed .006 inch (0.15mm).
A
1.35
0.1
1.75
0.25
1.57
0.30
0.25
8.74
3.99
A1
A2
b
0.0040
0.054
0.008
0.0098
0.062
0.012
3. "L" is the length of terminal for soldering to a substrate.
4. Terminal numbers are shown for reference only.
5. "b" and "c" dimensions include solder finish thickness.
6. Symbol "N" is the maximum number of terminals.
1.37
0.20
0.19
8.55
3.81
5
5
c
0.0075 0.0098
D
E
0.337
0.150
0.344
0.157
2, 4
2
e
0.025 BSC
0.635 BSC
H
L
0.228
0.016
0.244
0.050
5.79
0.40
6.20
1.27
3
6
N
α
24
24
0°
8°
0°
8°
ccc
—
.004
—
0.10
D
E
H
C
A1
A
A2
α
SEATING
PLANE
– C –
L
B
LEAD COPLANARITY
ccc C
e
REV. 1.0.1 1/24/02
9
FAN5242
PRODUCT SPECIFICATIONS
Ordering Information
Part Number
FAN5242QSC
FAN5242QSCX
Temperature Range
0°C to 85°C
Package
QSOP-24
QSOP-24
Packing
Rails
0°C to 85°C
Tape and Reel
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
1/24/02 0.0m 001
Stock#DS30005242
2001 Fairchild Semiconductor Corporation
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