FMMT560A_技术文档

PRELIMINARY

August 1999

FM24C256

256 KBit 2-Wire Bus Interface

Serial EEPROM with Write Protect

General Description

Features

The FM24C256/C256L/C256LZ devices are 256 Kbits CMOS

nonvolatile electrically erasable memory. These devices offer the

designer different low voltage and low power options. They

conform to all requirements in the Extended I²C™ 2-wire protocol.

Furthermore, they are designed to minimize device pin count and

simplify PC board layout requirements.

I Extended Operating Voltages

— C256: 4.5V - 5.5V

— C256L: 2.7V - 5.5V

— C256LZ: 2.7V - 5.5V

I Low Power CMOS

— 1mA active current typical

— C256/C256L: 10µA standby current typical

— C256LZ: less than 1µA standby current

I 2-wire I²C serial interface

The entire memory array can be disabled (Write Protection) by

connecting the WP pin to V_CC

.

Functional address lines allow up to eight devices on the same

bus, for up to a total of 2 Mbit address space.

I 64 byte page write mode

I Max write cycle time of 6ms byte/page

I 40 years data retention

The I²C communication protocol uses CLOCK (SCL) and DATA

I/O (SDA) lines to synchronously clock data between the master

(forexampleamicroprocessor)andtheslaveEEPROMdevice(s).

I Endurance: 100,000 data changes

I Hardware write protect for entire array

I Schmitt trigger inputs for noise suppression

I Electrostatic discharge protection > 4000V

I 8-pin DIP and 8-pin SO (150 mil) packages

Fairchild EEPROMs are designed and tested for applications

requiring high endurance, high reliability, and low power con-

sumption.

Block Diagram

WRITE

LOCKOUT

V

CC

H.V. GENERATION

TIMING &CONTROL

WP

START CYCLE

START

STOP

SDA

LOGIC

CONTROL

LOGIC

SLAVE ADDRESS

REGISTER &

COMPARATOR

2

E

PROM

ARRAY

XDEC

SCL

LOAD

INC

A2

A1

A0

WORD

ADDRESS

COUNTER

R/W

YDEC

CK

D

OUT

DATA REGISTER

D

IN

DS800023-1

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FM24C256 rev. A.2

Connection Diagram

Dual-In-Line Package (N)

and 8-Pin SO Package (M8)

A0

A1

A2

1

2

3

4

8

7

6

5

V

CC

WP

FM24C256

FM24C256L

FM24C256LZ

SCL

SDA

V

SS

DS800023-2

Top View

See Package Number N08E and M08A

Pin Names

A0, A1, A2

V_SS

Device Address Input

Ground

SDA

Data I/O

SCL

Clock Input

WP

Write Protect

Power Supply

V_CC

Ordering Information

FM

24

C

XX

F

LZ

E

XX

Letter Description

Package

N

M8

8-pin DIP

8-pin SO8

Temp. Range

None

0 to 70°C

V

E

-40 to +125°C

-40 to +85°C

Voltage Operating Range

Blank

L

4.5V to 5.5V

2.7V to 5.5V

LZ

2.7V to 5.5V and

<1µA Standby Current

SCL Clock Frequency

Density

Blank

F

100KHz

400KHz

256

C

256K with write protect

CMOS

Interface

24

IIC - 2 Wire

FM

Fairchild Non-Volatile

Memory

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FM24C256 rev. A.2

Absolute Maximum Ratings

Operating Conditions

Ambient Storage Temperature

–65°C to +150°C

Ambient Operating Temperature

FM24C256

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltages

with Respect to Ground

FM24C256E

FM24C256V

6.5V to –0.3V

Lead Temperature

Positive Power Supply

FM24C256

(Soldering, 10 seconds)

+300°C

4.5V to 5.5V

2.7V to 5.5V

FM24C256L

FM24C256LZ

ESD Rating

4000V min.

Standard V_CC(4.5V to 5.5V) DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Limits

Typ

Units

Min

Max

I_CCA

Active Power Supply Current

f_SCL= 100 kHz

f_SCL= 400 kHz

0.5

1.0

mA

I_SB

I_LI

Standby Current

V_IN= GND or V_CC

V_IN= GND to V_CC

V_OUT= GND to V_CC

10

0.1

50

µA

V

Input Leakage Current

Output Leakage Current

Input Low Voltage

1

I_LO

V_IL

V_IH

V_OL

–0.3

V_CCx 0.3

V_CC+ 0.5

0.4

Input High Voltage

Output Low Voltage

V_CCx 0.7

V

I_OL= 2.1 mA

V

Low V_CC(2.7V to 5.5V) DC Electrical Characteristics

Symbol

Parameter

Test Conditions

Limits

Typ

Units

mA

Min

Max

I_CCA

Active Power Supply Current

f_SCL= 100 kHz

0.5

1.0

f_SCL= 400 kHz

I_SB

(Note 1)

Standby Current for L

Standby Current for LZ

V_IN= GND or V_CC= 4.5V - 5.5V

V_IN= GND or V_CC= 2.7V - 4.5V

V_IN= GND or V_CC= 4.5V - 5.5V

V_IN= GND or V_CC= 2.7V - 4.5V

10

1

10

0.1

50

10

50

1

µA

I_LI

I_LO

Input Leakage Current

Output Leakage Current

Input Low Voltage

V_IN= GND to V_CC

0.1

1

µA

V

V_OUT= GND to V_CC

V_IL

V_IH

V_OL

–0.3

V_CCx 0.3

V_CC+ 0.5

0.4

Input High Voltage

V_CCx 0.7

V

Output Low Voltage

I_OL= 2.1 mA

V

Capacitance T_A= +25°C, f = 1.0 MHz, V_CC= 5V

Symbol

C_I/O

Test

Conditions

V_I/O= 0V

Max Units

Input/Output Capacitance (SDA)

Input Capacitance (A0, A1, A2, SCL)

8

6

pF

C_IN

V_IN= 0V

Note 1: Typical values are for T = 25°C and nominal supply voltage (5V).

A

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FM24C256 rev. A.2

AC Conditions of Test

Input Pulse Levels

V_CCx 0.1 to V_CCx 0.9

10 ns

Input Rise and Fall Times

Input & Output Timing Levels V_CCx 0.5

Output Load

1 TTL Gate and C_L= 100 pF

Read and Write Cycle Limits (Standard and Low V_CCRange - 2.7V-5.5V)

Symbol

Parameter

100 kHz

Max

400 kHz

Max

Units

kHz

Min

f_SCL

T_I

SCL Clock Frequency

100

3.5

400

Noise Suppression Time Constant at

SCL, SDA Inputs (Minimum V_IN

Pulse width)

50

ns

t_AA

SCL Low to SDA Data Out Valid

0.3

4.7

0.3

1.3

1.2

µs

t_BUF

Time the Bus Must Be Free before

a New Transmission Can Start

t_HD:STA

t_LOW

Start Condition Hold Time

Clock Low Period

4.0

4.7

4.0

4.7

0.6

1.5

0.6

µs

t_HIGH

Clock High Period

t_SU:STA

Start Condition Setup Time

(for a Repeated Start Condition)

t_HD:DAT

t_SU:DAT

t_R

Data in Hold Time

0

µs

ns

µs

ns

µs

ns

ms

Data in Setup Time

250

100

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Condition Setup Time

Data Out Hold Time

1

0.3

t_F

300

t_SU:STO

t_DH

4.7

0.6

100

t_WR

(Note 2)

Write Cycle Time - FM24C256

- FM24C256L, FM24C256LZ

6

Note 2: The write cycle time (t_WR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the

FM24C256 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address

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FM24C256 rev. A.2

Bus Timing

t

R

F

t

HIGH

t

LOW

SCL

t

SU:STO

t

SU:DAT

SU:STA

HD:DAT

t

HD:STA

SDA

IN

t

BUF

t

AA

t

DH

SDA

OUT

Note 3: SCL = Serial Clock Data

DS800023-3

SDA = Serial Data I/O

BACKGROUND INFORMATION (I²C Bus)

SERIAL DATA (SDA)

As mentioned, the I²C bus allows synchronous bidirectional com-

munication between Transmitter/Receiver using the SCL (clock)

and SDA (Data I/O) lines. All communication must be started with a

valid START condition, concluded with a STOP condition and

acknowledgedbytheReceiverwithanACKNOWLEDGEcondition.

SDA is a bidirectional pin used to transfer data to and from the

device. It is an open drain output and may be wire-ORed with any

number of open drain or open collector outputs.

Device Address Inputs (A0, A1, A2)

In addition, since the I²C bus is designed to support other devices

such as RAM, EPROM, etc., the device type identifier string, or

control byte, must follow the START condition. For EEPROMs, the

first 4-bit of the control byte is 1010 binary for READ and WRITE

operations. This is then followed by the device selection bits A2, A1

and A0, and acts as the three most significant bits of the word

address.The final bit in the control byte determines the type of

operation performed (READ/WRITE). A "1" signifies a READ while

a"0"signifiesaWRITE.Thecontrolbyteisthenfollowedbytwobytes

that define the word address, which is then followed by the data byte.

The EEPROMs on the I²C bus may be configured in any manner

required, providing the total memory addressed does not exceed

512Kbits(64Kbytes). EEPROMmemoryaddressingiscontrolled

by hardware configuring the A2, A1, and A0 pins (Device Address

pins) with pull-up or pull-down resistors. ALL UNUSED PINS

MUST BE GROUNDED (tied to V_SS).

Device address pins A0, A1, and A2 are connected to V_CCor V_SS

to configure the EEPROM address for multiple device configura-

tion. A total of eight different devices can be attached to the same

SDA bus.

Write Protection (WP)

If WP is tied to V_CC, program WRITE operations onto the entire

array of the memory will not be executed. READ operations are

always available.

If WP is tied to V_SS, normal memory operation is enabled for

READ/WRITE over the entire 256K bit memory array.

Thisfeatureallowstheusertoassigntheentirearrayofthememory

as ROM, which can be protected against accidental programming

writes. When WRITE is disabled, slave address and word address

will be acknowledged but data will not be acknowledged.

Addressing an EEPROM memory location involves sending a

command string with the following information:

Device Operation

The FM24C256xxx supports a bidirectional bus oriented protocol.

The protocol defines any device that sends data onto the bus as a

transmitter and the receiving devices as the receiver. The device

controlling the transfer is the master and the device that is con-

trolledistheslave.Themasterwillalwaysinitiatedatatransfersand

provide the clock for both transmit and receive operations. There-

fore, the FM24C256xxx is considered a slave in all applications.

[DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK AD-

DRESS]-[BYTE ADDRESS]

Pin Description

SERIAL CLOCK (SCL)

Definitions

CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during SCL LOW.

SDA state changes during SCL HIGH and are reserved for

indication of start and stop conditions. Refer to Figures 1 and 2.

Word

Page

8 bits (byte) of data

64 sequential addresses (one byte each) that

may be programmed during a "Page Write"

programming cycle.

START CONDITION

All commands are preceded by the start condition, which is a

HIGH to LOW transition of SDA when SCL is HIGH. The

FM24C256xxx continuously monitors the SDA and SCL lines for

the start condition and will not respond to any command until this

condition has been met.

Master

Any I²C device CONTROLLING the transfer of

data (such as a microcontroller).

Slave

Device being controlled (EEPROMS are

always considered Slaves).

Transmitter

Receiver

Device currently SENDING data on the bus

(may be either a Master or Slave).

STOP CONDITION

All communications are terminated by a stop condition, which is a

LOW to HIGH transition of SDA when SCL is HIGH. The stop

condition is also used by the FM24C256xxx to place the device in

the standby power mode.

Device currently receiving data on the bus

(Master or Slave).

The SCL input is used to clock all data into and out of the device.

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FM24C256 rev. A.2

both the device and a WRITE operation have been selected, the

FM24C256xxx will respond with an acknowledge after the receipt

of each subsequent eight bit word.

Write Cycle Timing

ACKNOWLEDGE

ACK (acknowledge) is a software convention used to indicate

successful data transfers. The transmitting device, either master or

slave,willreleasethebusaftertransmittingeightbits.Duringtheninth

clock cycle the receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data. Refer to Figure 3.

In the READ mode the FM24C256xxx slave will transmit eight bits

of data, release the SDA line and monitor the line for an acknowl-

edge. If an acknowledge is detected and no stop condition is

generated by the master, the slave will continue to transmit data.

If an acknowledge is not detected, the slave will terminate further

data transmissions and await the stop condition to return to the

standby power mode.

The FM24C256xxx device will always respond with an acknowl-

edge after recognition of a start condition and its slave address. If

Write Cycle Timing:

SCL

SDA

8th BIT

WORD n

ACK

t

WR

STOP

CONDITION

START

CONDITION

DS800023-4

Data Validity (Figure 1)

SCL

SDA

DATA

CHANGE

DATA STABLE

DS800023-5

Definition of Start and Stop (Figure 2)

SCL

SDA

START CONDITION

STOP CONDITION

DS800023-6

Acknowledge Response from Receiver (Figure 3)

SCL FROM

MASTER

1

8

9

Data Output

from Transmitter

Data Output

from Receiver

START

ACKNOWLEDGE

DS800023-7

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FM24C256 rev. A.2

transfer by generating a stop condition, at which time the

FM24C256xxx begins the internal write cycle to the nonvolatile

memory. While the internal write cycle is in progress, the device's

inputsaredisabledandthedevicewillnotrespondtoanyrequests

from the master. Refer to Figure 5 for the address, acknowledge

and data transfer sequence.

DEVICE ADDRESSING

Following a start condition the master must output the address of

the slave it is accessing. The most significant four bits of the slave

address are those of the device type identifier. This is fixed as

1010 for all different FM24C256xxx devices.

The next three bits identify the device address. Address from 000

to 111 are acceptable thus allowing up to eight devices to be

connected to the I²C bus.

PAGE WRITE

The FM24C256xxx is capable of 64 byte page write operation. It

is initiated in the same manner as the byte write operation; but

instead of termination the write cycle after the first data word is

transfered, themastercantransmitupto63morewords. Afterthe

receipt of each word, the device responds with an acknowledge.

The last bit of the slave address defines whether a write or read

condition is requested by the master. A "1" indicates that a READ

operation is to be executed and a "0" initiates the WRITE mode.

A simple review: After the FM24C256xxx recognizes the start

condition, the device interfaced to the I²C bus waits for a slave

address to be transmitted over the SDA line. If the transmitted

slave address matches an address of one of the devices, the

designated slave pulls the line LOW with an acknowledge signal

and awaits further transmissions.

After the receipt of each word, the internal address counter

increments to the next address and the next SDA data is ac-

cepted. If the master should transmit more than 64 words prior to

generating the stop condition, the address counter will "roll over"

and the previous written data will be overwritten. As with the byte

write operation, all inputs are disabled until completion of the

internal write cycle. Refer to Figure 6 for the address, acknowl-

edge and data transfer sequence.

Write Operations

BYTE WRITE

For a WRITE operation, two additional address fields are required

afterthecontrolbyteacknowledge.Thesearethewordaddresses

and are comprised of fifteen bits to provide access to any one of

the 32K words. The first byte indicates the high-order byte of the

wordaddress. Onlythesevenleastsignicantbitscanbechanged,

themostsignificantbitispre-assignedthevalue"0". Followingthe

acknowledgement from the first word address, the next byte

indicates the low-order byte of the word address. Upon receipt of

the word address, the FM24C256xxx responds with another

acknowledge and waits for the next eight bits of data, again,

responding with an acknowledge. The master then terminates the

Acknowledge Polling

Once the stop condition is isssued to indicate the end of the host's

write operation, the FM24C256xxx initiates the internal write

cycle. ACK polling can be initiated immediately. This involves

issuingthestartconditionfollowedbytheslaveaddressforawrite

operation. If the FM24C256xxx is still busy with the write opera-

tion, noACKwillbereturned. Ifthedevicehascompletedthewrite

operation, an ACK will be returned and the host can then proceed

with the next read or write operation.

Byte Write (Figure 5)

S

SLAVE

ADDRESS

WORD

ADDRESS (1)

WORD

ADDRESS (0)

DATA

T

A

R

T

O

P

Bus Activity:

Master

1

0

1 0

0

SDA Line

A

C

K

A

C

K

A

C

K

A

C

K

Bus Activity

DS800023-8

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FM24C256 rev. A.2

withtheR/Wbitsetto"1", themastermustfirstperforma"dummy"

write operation. The master issues a start condition, a slave

address, and then the word address to be read. After the word

address acknowledge, the master immediately reissues the start

conditionandtheslaveaddresswiththeR/Wbitsetto"1". Thiswill

be followed by an acknowledge from the FM24C256xxx and then

by theeightbit word. The master willnotacknowledge the transfer

but does generate the stop condition, and therefore the

FM24C256xxx discontinues transmission. Refer to Figure 8 for

the address, acknowledge, and data transfer sequence.

Write Protection

Programming of the memory array will not take place if the WP pin

is connected to V_CC. The device will accept control and word

addresses; but if the memory accessed is write protected by the

WPpin, theFM24C256xxxwillnotgenerateanacknowledgeafter

the first byte of data has been received, and thus the program

cycle will not be started when the stop condition is asserted.

Read Operation

Read operations are initiated in the same manner as write

operations,withtheexceptionthattheR/Wbitoftheslaveaddress

is set to "1". There are three basic read operations: current

address read, random read and sequential read.

SEQUENTIAL READ

Sequential reads can be initiated as either a current address read

or random access read. The first word is transmitted in the same

manner as the other read modes; however, the master now

responds with an acknowledge, indicating it requires additional

data. The FM24C256xxx continues to output data for each ac-

knowledge received. The read operation is terminated by the

master not responding with an acknowledge or by generating a

stop condition.

CURRENT ADDRESS READ

Internally the FM24C256xxx contains an address counter that

maintains the address of the last word accessed, incremented by

one. Therefore, if the last access (either a read or write) was to

address n, the next read operation would access data from

address n+1. Upon receipt of the slave address with R/W set to

"1," the FM24C256xxx issues an acknowledge and transmits the

eight bit word. The master will not acknowledge the transfer but

does generate a stop condition, and therefore discontinues trans-

mission. Refer to Figure 7 for the sequence of address, acknowl-

edge and data transfer.

The data output is sequential, with the data from address n,

followedbythedatan+1. Theaddresscounterforreadoperations

increments all word address bits, allowing the entire memory

contents to be serially read during one operation. After the entire

memory has been read, the counter "rolls over" and the

FM24C256xxx continues to output data for each acknowledge

received. Refer to Figure 9 for the address, acknowledge, and

data transfer sequence.

RANDOM READ

Random read operations allow the master to access any memory

location in a random manner. Prior to issuing the slave address

Page Write (Figure 6)

S

SLAVE

ADDRESS

WORD

ADDRESS (1)

WORD

ADDRESS (0)

DATA n

DATA n+31

T

A

R

T

O

P

Bus Activity:

Master

1

0

1 0

0

SDA Line

A

C

K

A

C

K

A

C

K

A

C

K

Bus Activity

DS800023-9

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FM24C256 rev. A.2

Current Address Read (Figure 7)

S

T

A

R

T

S

T

O

P

SLAVE ADDRESS

1 0 1 0

DATA

A

C

K

NO

DS800023-10

A

C

K

Random Read (Figure 8)

S

T

A

S

T

A

R

T

S

T

O

P

SLAVE

WORD

ADDRESS (1)

WORD

ADDRESS (0)

SLAVE

ADDRESS

Bus Activity:

R

DATA n

ADDRESS

Master

T

1

0

1 0

0

1 0 1 0

1 0

SDA Line

A

C

K

A

C

K

A

C

K

A

C

K

NO

A

C

K

Bus Activity

DS800023-11

Sequential Read (Figure 9)

S

T

A

R

T

S

T

O

P

SLAVE

ADDRESS

DATA n

DATA n + 1

DATA n + x

Bus Activity:

Master

1

0 1 0

SDA Line

A

C

K

A

C

K

A

C

K

A

C

K

NO

A

C

Bus Activity

K

DS800023-12

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FM24C256 rev. A.2

Physical Dimensions inches (millimeters) unless otherwise noted

0.189 - 0.197

(4.800 - 5.004)

8

7

6

3

5

4

0.228 - 0.244

(5.791 - 6.198)

1

2

Lead #1

IDENT

0.150 - 0.157

(3.810 - 3.988)

0.053 - 0.069

(1.346 - 1.753)

0.010 - 0.020

(0.254 - 0.508)

0.004 - 0.010

(0.102 - 0.254)

x 45°

8° Max, Typ.

All leads

Seating

Plane

0.04

0.0075 - 0.0098

(0.190 - 0.249)

Typ. All Leads

(0.102)

All lead tips

0.014

(0.356)

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

0.050

(1.270)

Typ

0.014 - 0.020

(0.356 - 0.508)

Typ.

Molded Small Out-Line Package (M8)

Order Number FM24C256xxxM8 or FM24C256xxxEM8

Package Number M08A

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FM24C256 rev. A.2

Physical Dimensions inches (millimeters) unless otherwise noted

0.373 - 0.400

(9.474 - 10.16)

0.090

(2.286)

8

7

0.032 0.005

(0.813 0.127)

RAD

8

7

6

5

4

0.092

(2.337)

DIA

0.250 - 0.005

(6.35 0.127)

Pin #1

IDENT

+

Pin #1 IDENT

1

Option 1

1

2

3

Option 2

0.280

MIN

0.040

(1.016)

Typ.

(7.112)

0.030

0.145 - 0.200

(3.683 - 5.080)

0.039

(0.991)

MAX

(0.762)

0.300 - 0.320

(7.62 - 8.128)

20° 1°

0.130 0.005

(3.302 0.127)

0.125 - 0.140

95° 5°

0.009 - 0.015

(3.175 - 3.556)

0.065

(1.651)

0.125

(3.175)

DIA

0.020

90° 4°

Typ

(0.508)

Min

(0.229 - 0.381)

0.018 0.003

(0.457 0.076)

NOM

+0.040

-0.015

0.325

0.100 0.010

+1.016

-0.381

8.255

(2.540 0.254)

0.045 0.015

(1.143 0.381)

0.060

(1.524)

0.050

(1.270)

Molded Dual-In-Line Package (N)

Order Number FM24C256xxxN or FM24C256xxxEN

Package Number N08E

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a)areintendedforsurgicalimplantintothebody,or(b)support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-

pected to cause the failure of the life support device or system,

or to affect its safety or effectiveness.

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Japan Ltd.

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+44 (0) 1793-856856

+33 (0) 1-6930-3696

+39 (0) 2-249111-1

2-18-6, Yushima, Bunkyo-ku

Tokyo, 113-0034 Japan

Tel: 81-3-3818-8840

Fax: 81-3-3818-8841

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

11

www.fairchildsemi.com

FM24C256 rev. A.2

December 1999

FM93C06

256-Bit Serial CMOS EEPROM

(MICROWIRE™ Bus Interface)

General Description

Features

The FM93C06 device is 256 bits of CMOS non-volatile electrically

erasable memory organized as 16x16 bit array. They are fabri-

cated using Fairchild Semiconductor's floating-gate CMOS pro-

cess for high reliability, high endurance and low power consump-

tion. These memory devices are available in an 8-pin SOIC or 8-

pin TSSOP package for small space considerations.

I Device status during programming mode

I Typical active current of 200µA

10µA standby current typical

1µA standby current typical (L)

0.1µA standby current typical (LZ)

I No erase required before write

I Reliable CMOS floating gate technology

I 2.7V to 5.5V operation in all modes

I MICROWIRE compatible serial l/O

I Self-timed programming cycle

I 40 years data retention

FM93C06 is compatible with MICROWIRE serial interface, which

offers simple interface to standard microcontrollers and micropro-

cessors. There are 7 instructions which control this device: Read,

WriteEnable, Erase, EraseAll, Write, WriteAll, andWriteDisable.

The ready/busy status is available on the DO pin to indicate the

completion of a programming cycle.

I Endurance: 1,000,000 data changes

I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP

I Schmitt Trigger inputs and V_CClockout to prevent data

corruption

Block Diagram

V_CC

CS

SK

INSTRUCTION

DECODER

CONTROL LOGIC,

AND CLOCK

GENERATORS

INSTRUCTION

REGISTER

DI

HIGH VOLTAGE

GENERATOR

AND

ADDRESS

REGISTER

PROGRAM

TIMER

V_PP

DECODER

1 OF 16

EEPROM ARRAY

16

READ/WRITE AMPS

16

V_SS

DATA IN/OUT REGISTER

16 BITS

DO

DATA OUT BUFFER

DS800024-1

1

FM93C06

www.fairchildsemi.com

Connection Diagrams

Dual-In-Line Package (N),

8-Pin SO (M8) and 8-Pin TSSOP (MT8)

1

2

3

4

8

7

6

5

CS

SK

DI

V_CC

NC

DO

GND

DS800024-2

Top View

See Package Number

N08E, M08A and MTC08

Pin Names

CS

Chip Select

SK

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

DI

DO

GND

V_CC

Power Supply

Ordering Information

FM

93

C

XX LZ

E

XX

Letter Description

Package

N

8-Pin DIP

M8

MT8

8-Pin SO8

8-Pin TSSOP

Temp. Range

None

0 to 70°C

V

E

-40 to +125°C

-40 to +85°C

Voltage Operating Range

Blank

L

4.5V to 5.5V

2.7V to 5.5V

LZ

2.7V to 5.5V and

<1µA Standby Current

Density

06

256 bit

C

CMOS

CS

Data protect and sequential

read

Interface

93

MICROWIRE

FM

Fairchild Non-Volatile

Memory

2

www.fairchildsemi.com

FM93C06

Absolute Maximum Ratings (Note 1)

Operating Range

Ambient Storage Temperature

–65°C to +150°C

Ambient Operating Temperature

FM93C06

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltage

with Respect to Ground

+6.5V to -0.3V

FM93C06E

FM93C06V

Lead Temperature (Soldering, 10 sec.)

ESD Rating

+300°C

Power Supply (V_CC

)

4.5V to 5.5V

2000V

DC and AC Electrical Characteristics 4.5V ≤ V_CC≤ 5.5V

Symbol

Parameter

Part Number

Conditions

Min.

Max.

Units

I_CCA

I_CCS

Operating Current

Standby Current

CS = V_IH, SK = 1MHz

CS = V_IL

1

50

1

mA

µA

I_IL

I_OL

Input Leakage

Output Leakage

V_IN= 0V to V_CC

(Note 2)

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.1

2

0.8

V_CC+1

V

V_OL1

V_OH1

Output Low Voltage

Output High Voltage

I_OL= 2.1mA

I_OH= -400 µA

0.4

0.2

1

V

2.4

V_OL2

V_OH2

Output Low Voltage

Output High Voltage

I_OL= 10 µA

I_OH= -10 µA

V

V_CC-0.2

0

f_SK

SK Clock Frequency

SK High Time

(Note 3)

MHz

ns

t_SKH

FM93C06

FM93C06E/V

250

300

t_SKL

t_SKS

SK Low Time

250

50

ns

SK Setup Time

SK must be at V_ILfor

t_SKSbefore CS goes

high

t_CS

Minimum CS

Low Time

(Note 4)

250

ns

t_CSS

t_DH

CS Setup Time

DO Hold Time

DI Setup Time

50

70

ns

t_DIS

FM93C06

FM93C06E/V

100

200

t_CSH

t_DIH

t_PD

CS Hold Time

0

ns

ms

DI Hold Time

20

Output Delay

500

100

10

t_SV

CS to Status Valid

CS to DO in Hi-Z

Write Cycle Time

t_DF

CS = V_IL

t_WP

3

www.fairchildsemi.com

FM93C06

Absolute Maximum Ratings (Note 1)

Operating Range

Ambient Operating Temperature

Ambient Storage Temperature

–65°C to +150°C

FM93C06L/LZ

FM93C06LE/LZE

FM93C06LV/LZV

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltage

with Respect to Ground

+6.5V to -0.3V

Lead Temperature (Soldering, 10 sec.)

ESD Rating

+300°C

Power Supply (V_CC

)

2.7V to 5.5V

2000V

DC and AC Electrical Characteristics V_CC= 2.7V to 5.5V unless otherwise specified

Symbol

Parameter

Part Number

Conditions

Min.

Max.

Units

I_CCA

I_CCS

Operating Current

CS = V_IH, SK = 250KHz

CS = V_IL

1

mA

Standby Current

L

LZ

10

1

µA

I_IL

I_OL

Input Leakage

Output Leakage

V_IN= 0V to V_CC

(Note 2)

1

µA

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.1

0.8 V_CC

0.15 V_CC

V_CC+1

V

V_OL

V_OH

Output Low Voltage

Output High Voltage

I_OL= 10 µA

I_OH= -10 µA

0.1 V_CC

V

0.9 V_CC

f_SK

SK Clock Frequency

SK High Time

(Note 3)

0

1

250

KHz

µs

t_SKH

t_SKL

t_SKS

SK Low Time

1

µs

SK Setup Time

SK must be at V_ILfor

t_SKSbefore CS goes

high

0.2

µs

t_CS

Minimum CS

Low Time

(Note 4)

1

µs

t_CSS

t_DH

CS Setup Time

DO Hold Time

DI Setup Time

CS Hold Time

DI Hold Time

0.2

70

0.4

0

µs

ns

µs

ns

µs

ms

t_DIS

t_CSH

t_DIH

t_PD

0.4

Output Delay

2

1

t_SV

CS to Status Valid

CS to DO in Hi-Z

Write Cycle Time

t_DF

CS = V_IL

0.4

15

t_WP

Note 1: Stressabovethoselistedunder“AbsoluteMaximumRatings”maycausepermanentdamage

to the device. This is a stress rating only and functional operation of the device at these or any other

conditionsabovethoseindicatedintheoperationalsectionsofthespecificationisnotimplied. Exposure

to absolute maximum rating conditions for extended periods may affect device reliability.

Capacitance T_A= 25°C, f = 1 MHz (Note 5)

Note 2: Typical leakage values are in the 20nA range.

Symbol

C_OUT

Test

Typ Max Units

Note 3: TheshortestallowableSKclockperiod=1/f_SK(asshownunderthef_SKparameter). Maximum

SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated

in the datasheet. Within this SK period, both t_SKHand t_SKLlimits must be observed. Therefore, it is not

allowable to set 1/f_SK= t_SKHminimum+ t_SKLminimumfor shorter SK cycle time operation.

Output Capacitance

Input Capacitance

5

pF

C_IN

Note 4: CS (Chip Select) must be brought low (to V_IL) for an interval of t_CSin order to reset all internal

device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode

diagram on the following page.)

Note 5: This parameter is periodically sampled and not 100% tested.

AC Test Conditions

V_CCRange

V_IL/V_IH

Input Levels

.03V/1.8V

V_IL/V_IH

Timing Level

V_OL/V_OH

Timing Level

0.8V/1.5V

I_OL/I_OH

2.7V ≤ V_CC≤ 5.5V

(Extended Voltage Levels)

1.0V

10µA

4.5V ≤ V_CC≤ 5.5V

0.4V/2.4V

1.0V/2.0V

0.4V/2.4V

2.1mA/-0.4mA

(TTL Levels)

Output Load: 1 TTL Gate (C_L= 100 pF)

4

www.fairchildsemi.com

FM93C06

Write (WRITE):

Functional Description

TheWRITEinstructionisfollowedbytheaddressand16bitsofdata

to be written into the specified address. After the last bit of data is

put in the data-in (DI) pin, CS must be brought low before the next

rising edge of the SK clock. This falling edge of the CS initiates the

self-timed programming cycle. The D0 pin indicates the READY/

The FM93C06device has7 instructionsas describedbelow. Note

that the MSB of any instruction is a “1” and is viewed as a start bit

in the interface sequence. The next 8 bits carry the op code and

the 6-bit address for register selection.

Read (READ):

BUSYstatusofthechipifCSisbroughthighafteraminimumoft

.

CS

D0 = logical 1 indicates that the register at the address specified in

theinstructionhasbeenwrittenwiththedatapatternspecifiedinthe

instruction and the part is ready for another instruction.

The READ instruction outputs serial data on the D0 pin. After a

READ instruction is received, the instruction and address are

decoded, followed by data transfer from the selected memory

register into a 16-bit serial-out shift register. A dummy bit (logical

0)precedesthe16-bitdataoutputstring. Outputdatachangesare

initiated by a low to high transition of the SK clock.

Erase All (ERAL):

The ERAL instruction will simultaneously program all registers in

thememoryarrayandseteachbittothelogical“1”state.TheErase

All cycle is identical to the ERASE cycle except for the different op-

code. As in the ERASE mode, the DO pin indicates the READY/

BUSY status of the chip if CS is brought high after the t_CSinterval.

Write Enable (WEN):

When V_CCis applied to the part, it 'powers-up' in the Write Disable

(WDS) state. Therefore, all programming modes must be pre-

ceded by a Write Enable (WEN) instruction. Once a Write Enable

instructionisexecuted,programmingremainsenableduntilaWrite

Disable (WDS) instruction is executed or V_CCis removed from the

part.

Write All (WRALL):

The WRALL instruction will simultaneously program all registers

with the data pattern specified in the instruction. As in the WRITE

mode, the DO pin indicates the READY/BUSY status of the chip

Erase (ERASE):

if CS is brought high after the t interval.

CS

The ERASE instruction will program all bits in the specified

register to the logical “1” state. CS is brought low following the

loading of the last address bit. This falling edge of the CS pin

initiates the self-timed programming cycle.

Write Disable (WDS):

To protect against accidental data disturb, the WDS instruction

disables all programming modes and should follow all program-

ming operations. Execution of a READ instruction is independent

of both the WEN and WDS instructions.

The DO pin indicates the READY/BUSY status of the chip if CS is

broughthighafteraminimumtimeoft_CS. DO=logical“0”indicates

that the register, at the address specified in the instruction, has

been erased, and the part is ready for another instruction.

Note: The Fairchild CMOS EEPROMs do not require an "ERASE" or "ERASE ALL"

operationpriortothe"WRITE"and"WRITEALL"instructions. The"ERASE"and"ERASE

ALL"instructionsareincludedtomaintaincompatibilitywithearliertechnologyEEPROMs.

Instruction Set for the FM93C06

Instruction

READ

SB

1

Op. Code

Address

00 A3 A2 A1 A0

11xxxx

Data

Comments

Reads data stored in memory, at specified address.

Write enable must precede all programming modes.

Erase selected register.

10

00

11

01

00

WEN

1

ERASE

WRITE

ERAL

1

00 A3 A2 A1 A0

1

00 A3 A2 A1 A0 D15-D0

10xxxx

Writes selected register.

1

Erases all registers.

WRALL

WDS

1

01xxxx

00xxxx

D15-D0

Writes all registers.

1

Disables all programming instructions.

Note:

Address bits A5 and A4 should be set to '0' for READ, ERASE and WRITE instructions.

x = Don't care

5

www.fairchildsemi.com

FM93C06

Timing Diagrams

Synchronous Data Timing

V

IH

CS

SK

V

t

IL

CSS

t

CSH

SKH

SKL

t

SKS

V

IH

V

IL

t

DIH

DIS

V

IH

DI

V

IL

t

PD

t

DF

t

DH

V

OH

DO (READ)

V

OL

t

SV

t

DF

DH

V

OH

DO (PROGRAM)

STATUS VALID

V

DS800024-4

OL

READ

CS

SK

DI

t

CS

. . .

1

0

A3

A0

. . .

DO

0

D15

D0

DS800024-5

WEN

CS

SK

DI

t

CS

. . .

1

0

1

X

DS800024-6

WDS

CS

SK

DI

t_CS

. . .

1

0

X

DS800024-7

6

www.fairchildsemi.com

FM93C06

Timing Diagrams (Continued)

WRITE

CS

SK

t

CS

. . .

1

0

1

0

A3

A0

D15

D0

DI

DO

BUSY

READY

t

WP

DS800024-8

WRALL

CS

SK

DI

t

CS

. . .

1

0

1

DON'T CARE (4 BITS) D15

D0

DO

BUSY

READY

t

WP

DS800024-9

ERASE

t

CS

SK

STANDBY

. . .

DI

1

0

A3

A0

HI-Z

DO

BUSY

READY

t

WP

DS800024-10

ERAL

t

CS

STANDBY

SK

DI

1

0

1

0

DON'T CARE BITS (4 BITS)

HI-Z

DO

BUSY

READY

t

WP

DS800024-11

7

www.fairchildsemi.com

FM93C06

Physical Dimensions inches (millimeters) unless otherwise noted

0.189 - 0.197

(4.800 - 5.004)

8

7

6

5

0.228 - 0.244

(5.791 - 6.198)

1

2

3

4

Lead #1

IDENT

0.150 - 0.157

(3.810 - 3.988)

0.053 - 0.069

(1.346 - 1.753)

0.010 - 0.020

(0.254 - 0.508)

0.004 - 0.010

(0.102 - 0.254)

x 45°

8° Max, Typ.

All leads

Seating

Plane

0.04

0.0075 - 0.0098

(0.190 - 0.249)

Typ. All Leads

(0.102)

All lead tips

0.014

(0.356)

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

0.050

(1.270)

Typ

0.014 - 0.020

(0.356 - 0.508)

Typ.

Molded Small Out-Line Package (M8)

Package Number M08A

0.114 - 0.122

(2.90 - 3.10)

8

5

(7.72) Typ

(4.16) Typ

0.169 - 0.177

(4.30 - 4.50)

0.246 - 0.256

(6.25 - 6.5)

(1.78) Typ

(0.42) Typ

0.123 - 0.128

(3.13 - 3.30)

(0.65) Typ

Land pattern recommendation

1

4

Pin #1 IDENT

0.0433

Max

(1.1)

0.0035 - 0.0079

See detail A

0.002 - 0.006

(0.05 - 0.15)

0.0256 (0.65)

Typ.

Gage

plane

0.0075 - 0.0098

(0.19 - 0.30)

0°-8°

DETAIL A

Typ. Scale: 40X

0.0075 - 0.0098

(0.19 - 0.25)

0.020 - 0.028

(0.50 - 0.70)

Seating

plane

8-Pin Molded TSSOP, JEDEC (MT8)

Package Number MTC08

8

www.fairchildsemi.com

FM93C06

Physical Dimensions inches (millimeters) unless otherwise noted

0.373 - 0.400

(9.474 - 10.16)

0.090

(2.286)

8

7

0.032 0.005

(0.813 0.127)

RAD

8

7

6

3

5

4

0.092

(2.337)

Min

0.250 - 0.005

(6.35 0.127)

Pin #1 IDENT

+

Pin #1 IDENT

1

Option 1

1

2

Option 2

0.280

(7.112)

DIA

0.040

(1.016)

Typ.

0.030

0.145 - 0.200

(3.683 - 5.080)

0.039

(0.991)

Max.

(0.762)

0.300 - 0.320

(7.62 - 8.128)

20° 1°

0.130 0.005

(3.302 0.127)

0.125 - 0.140

95° 5°

(3.175 - 3.556)

0.065

(1.651)

0.125

(3.175)

DIA

0.020

90° 4°

Typ

0.009 - 0.015

(0.229 - 0.381)

(0.508)

Min

0.018 0.003

(0.457 0.076)

+0.040

-0.015

NOM

0.325

0.100 0.010

+1.016

-0.381

8.255

(2.540 0.254)

0.045 0.015

(1.143 0.381)

0.060

(1.524)

0.050

(1.270)

Molded Dual-In-Line Package (N)

Package Number N08E

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a)areintendedforsurgicalimplantintothebody,or(b)support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-

pected to cause the failure of the life support device or system,

or to affect its safety or effectiveness.

Fairchild Semiconductor

Americas

Fairchild Semiconductor

Europe

Fairchild Semiconductor

Hong Kong

Fairchild Semiconductor

Japan Ltd.

Customer Response Center

Tel. 1-888-522-5372

Fax:

Tel:

+44 (0) 1793-856858

8/F, Room 808, Empire Centre

68 Mody Road, Tsimshatsui East

Kowloon. Hong Kong

Tel; +852-2722-8338

Fax: +852-2722-8383

4F, Natsume Bldg.

Deutsch

English

Français

Italiano

+49 (0) 8141-6102-0

+44 (0) 1793-856856

+33 (0) 1-6930-3696

+39 (0) 2-249111-1

2-18-6, Yushima, Bunkyo-ku

Tokyo, 113-0034 Japan

Tel: 81-3-3818-8840

Fax: 81-3-3818-8841

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

9

www.fairchildsemi.com

FM93C06

December 1999

FM93C46

1K-Bit Serial CMOS EEPROM

(MICROWIRE™ Bus Interface)

General Description

Features

The FM93C46 device is 1024 bits of CMOS non-volatile electri-

cally erasable memory organized as 64x16 bit array. They are

fabricated using Fairchild Semiconductor's floating-gate CMOS

process for high reliability, high endurance and low power con-

sumption. These memory devices are available in an 8-pin SOIC

or 8-pin TSSOP package for small space considerations.

I Device status during programming mode

I Typical active current of 200µA

10µA standby current typical

1µA standby current typical (L)

0.1µA standby current typical (LZ)

I No erase required before write

I Reliable CMOS floating gate technology

I 2.7V to 5.5V operation in all modes

I MICROWIRE compatible serial l/O

I Self-timed programming cycle

I 40 years data retention

FM93C46 is compatible with MICROWIRE serial interface, which

offers simple interface to standard microcontrollers and micropro-

cessors. There are 7 instructions which control this device: Read,

WriteEnable, Erase, EraseAll, Write, WriteAll, andWriteDisable.

The ready/busy status is available on the DO pin to indicate the

completion of a programming cycle.

I Endurance: 1,000,000 data changes

I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP

I Schmitt Trigger inputs and V_CClockout to prevent data

corruption

Block Diagram

V_CC

CS

SK

INSTRUCTION

DECODER

CONTROL LOGIC,

AND CLOCK

GENERATORS

INSTRUCTION

REGISTER

DI

HIGH VOLTAGE

GENERATOR

AND

ADDRESS

REGISTER

PROGRAM

TIMER

V_PP

DECODER

1 OF 64

EEPROM ARRAY

READ/WRITE AMPS

V_SS

DATA IN/OUT REGISTER

16 BITS

DO

DATA OUT BUFFER

DS800025-1

1

FM93C46

www.fairchildsemi.com

Connection Diagrams

Dual-In-Line Package (N),

8-Pin SO (M8) and 8-Pin TSSOP (MT8)

Rotated Die (93C46T)

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

CS

SK

DI

NC

V_CC

NC

GND

DO

DI

V

CC

NC

CS

DO

GND

SK

DS800025-2

DS800025-12

Top View

See Package Number N08E, M08A and MTC08

Pin Names

CS

Chip Select

SK

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

DI

DO

GND

V_CC

Power Supply

Ordering Information

FM

93

C

XX

T

LZ

E

XX

Letter Description

Package

N

8-Pin DIP

M8

MT8

8-Pin SO8

8-Pin TSSOP

Temp. Range

None

0 to 70°C

V

E

-40 to +125°C

-40 to +85°C

Voltage Operating Range

Blank

L

4.5V to 5.5V

2.7V to 5.5V

LZ

2.7V to 5.5V and

<1µA Standby Current

Blank

T

Normal Pin Out

Rotated Die Pin Out

Density

46

1K

C

CMOS

CS

Data protect and sequential

read

Interface

93

MICROWIRE

FM

Fairchild Non-Volatile

Memory

2

www.fairchildsemi.com

FM93C46

Absolute Maximum Ratings (Note 1)

Operating Range

Ambient Storage Temperature

–65°C to +150°C

Ambient Operating Temperature

FM93C46

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltage

with Respect to Ground

+6.5V to -0.3V

FM93C46E

FM93C46V

Lead Temperature (Soldering, 10 sec.)

ESD Rating

+300°C

Power Supply (V_CC

)

4.5V to 5.5V

2000V

Standard V_CC(4.5V to 5.5V) DC and AC Electrical Characteristics

Symbol

Parameter

Part Number

Conditions

Min.

Max.

Units

I_CCA

I_CCS

Operating Current

Standby Current

CS = V_IH, SK = 1MHz

CS = V_IL

1

50

1

mA

µA

I_IL

I_OL

Input Leakage

Output Leakage

V_IN= 0V to V_CC

(Note 2)

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.1

2

0.8

V_CC+1

V

V_OL1

V_OH1

Output Low Voltage

Output High Voltage

I_OL= 2.1mA

I_OH= -400 µA

0.4

0.2

1

V

2.4

V_OL2

V_OH2

Output Low Voltage

Output High Voltage

I_OL= 10 µA

I_OH= -10 µA

V

V_CC-0.2

0

f_SK

SK Clock Frequency

SK High Time

(Note 3)

MHz

ns

t_SKH

FM93C46

FM93C46E/V

250

300

t_SKL

t_SKS

SK Low Time

250

50

ns

SK Setup Time

SK must be at V_ILfor

t_SKSbefore CS goes

high

t_CS

Minimum CS

Low Time

(Note 4)

250

ns

t_CSS

t_DH

CS Setup Time

DO Hold Time

DI Setup Time

50

70

ns

t_DIS

FM93C46

FM93C46E/V

100

200

t_CSH

t_DIH

t_PD

CS Hold Time

0

ns

ms

DI Hold Time

20

Output Delay

500

100

10

t_SV

CS to Status Valid

CS to DO in Hi-Z

Write Cycle Time

t_DF

CS = V_IL

t_WP

3

www.fairchildsemi.com

FM93C46

Absolute Maximum Ratings (Note 1)

Operating Range

Ambient Storage Temperature

–65°C to +150°C

Ambient Operating Temperature

FM93C46L/LZ

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltage

with Respect to Ground

+6.5V to -0.3V

FM93C46LE/LZE

FM93C46LV/LZV

Lead Temperature (Soldering, 10 sec.)

ESD Rating

+300°C

Power Supply (V_CC

)

2.7V to 4.5V

2000V

DC and AC Electrical Characteristics V_CC= 2.7V to 4.5V unless otherwise specified

Symbol

Parameter

Part Number

Conditions

Min.

Max.

Units

I_CCA

I_CCS

Operating Current

CS = V_IH, SK = 250KHz

CS = V_IL

1

mA

Standby Current

L

LZ

10

1

µA

I_IL

I_OL

Input Leakage

Output Leakage

V_IN= 0V to V_CC

(Note 2)

1

µA

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.1

0.8 V_CC

0.15 V_CC

V_CC+1

V

V_OL

V_OH

Output Low Voltage

Output High Voltage

I_OL= 10 µA

I_OH= -10 µA

0.1 V_CC

V

0.9 V_CC

f_SK

SK Clock Frequency

SK High Time

(Note 3)

0

1

250

KHz

µs

t_SKH

t_SKL

t_SKS

SK Low Time

1

µs

SK Setup Time

SK must be at V_ILfor

t_SKSbefore CS goes

high

0.2

µs

t_CS

Minimum CS

Low Time

(Note 4)

1

µs

t_CSS

t_DH

CS Setup Time

DO Hold Time

DI Setup Time

CS Hold Time

DI Hold Time

0.2

70

0.4

0

µs

ns

µs

ns

µs

ms

t_DIS

t_CSH

t_DIH

t_PD

0.4

Output Delay

2

1

t_SV

CS to Status Valid

CS to DO in Hi-Z

Write Cycle Time

t_DF

CS = V_IL

0.4

15

t_WP

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or any

other conditions above those indicated in the operational sections of the specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Capacitance T_A= 25°C, f = 1 MHz (Note 5)

Note 2: Typical leakage values are in the 20nA range.

Symbol

C_OUT

Test

Typ Max Units

Note 3: The shortest allowable SK clock period = 1/f_SK(as shown under the f_SKparameter).

Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC

parametersstatedinthedatasheet.WithinthisSKperiod,botht_SKHandt_SKLlimitsmustbeobserved.

Therefore,itisnotallowabletoset1/f_SK=t_SKHminimum+t_SKLminimumforshorterSKcycletimeoperation.

Output Capacitance

Input Capacitance

5

pF

C_IN

Note 4: CS (Chip Select) must be brought low (to V_IL) for an interval of t_CSin order to reset all

internaldeviceregisters(devicereset)priortobeginninganotheropcodecycle. (Thisisshowninthe

opcode diagram on the following page.)

Note 5: This parameter is periodically sampled and not 100% tested.

AC Test Conditions

V_CCRange

V_IL/V_IH

Input Levels

.03V/1.8V

V_IL/V_IH

Timing Level

V_OL/V_OH

Timing Level

0.8V/1.5V

I_OL/I_OH

2.7V ≤ V_CC≤ 5.5V

(Extended Voltage Levels)

1.0V

10µA

4.5V ≤ V_CC≤ 5.5V

0.4V/2.4V

1.0V/2.0V

0.4V/2.4V

2.1mA/-0.4mA

(TTL Levels)

Output Load: 1 TTL Gate (C_L= 100 pF)

4

www.fairchildsemi.com

FM93C46

Write (WRITE):

Functional Description

TheWRITEinstructionisfollowedbytheaddressand16bitsofdata

to be written into the specified address. After the last bit of data is

put in the data-in (DI) pin, CS must be brought low before the next

rising edge of the SK clock. This falling edge of the CS initiates the

self-timed programming cycle. The D0 pin indicates the READY/

The FM93C46device has7 instructionsas describedbelow. Note

that the MSB of any instruction is a “1” and is viewed as a start bit

in the interface sequence. The next 8 bits carry the op code and

the 6-bit address for register selection.

Read (READ):

BUSYstatusofthechipifCSisbroughthighafteraminimumoft

.

CS

D0 = logical 1 indicates that the register at the address specified in

theinstructionhasbeenwrittenwiththedatapatternspecifiedinthe

instruction and the part is ready for another instruction.

The READ instruction outputs serial data on the D0 pin. After a

READ instruction is received, the instruction and address are

decoded, followed by data transfer from the selected memory

register into a 16-bit serial-out shift register. A dummy bit (logical

0)precedesthe16-bitdataoutputstring. Outputdatachangesare

initiated by a low to high transition of the SK clock.

Erase All (ERAL):

The ERAL instruction will simultaneously program all registers in

thememoryarrayandseteachbittothelogical“1”state.TheErase

All cycle is identical to the ERASE cycle except for the different op-

code. As in the ERASE mode, the DO pin indicates the READY/

BUSY status of the chip if CS is brought high after the t_CSinterval.

Write Enable (WEN):

When V_CCis applied to the part, it 'powers-up' in the Write Disable

(WDS) state. Therefore, all programming modes must be pre-

ceded by a Write Enable (WEN) instruction. Once a Write Enable

instructionisexecuted,programmingremainsenableduntilaWrite

Disable (WDS) instruction is executed or V_CCis removed from the

part.

Write All (WRALL):

The WRALL instruction will simultaneously program all registers

with the data pattern specified in the instruction. As in the WRITE

mode, the DO pin indicates the READY/BUSY status of the chip

Erase (ERASE):

if CS is brought high after the t interval.

CS

The ERASE instruction will program all bits in the specified

register to the logical “1” state. CS is brought low following the

loading of the last address bit. This falling edge of the CS pin

initiates the self-timed programming cycle.

Write Disable (WDS):

To protect against accidental data disturb, the WDS instruction

disables all programming modes and should follow all program-

ming operations. Execution of a READ instruction is independent

of both the WEN and WDS instructions.

The DO pin indicates the READY/BUSY status of the chip if CS is

broughthighafteraminimumtimeoft_CS. DO=logical“0”indicates

that the register, at the address specified in the instruction, has

been erased, and the part is ready for another instruction.

Note: The Fairchild CMOS EEPROMs do not require an "ERASE" or "ERASE ALL"

operationpriortothe"WRITE"and"WRITEALL"instructions. The"ERASE"and"ERASE

ALL"instructionsareincludedtomaintaincompatibilitywithearliertechnologyEEPROMs.

Instruction Set for the FM93C46

Instruction

READ

SB

1

Op. Code

Address

A5-A0

Data

Comments

Reads data stored in memory, at specified address.

Write enable must precede all programming modes.

Erase selected register.

10

00

11

01

00

WEN

1

11xxxx

A5-A0

ERASE

WRITE

ERAL

1

A5-A0

D15-D0

Writes selected register.

1

10xxxx

01xxxx

00xxxx

Erases all registers.

WRALL

WDS

1

Writes all registers.

1

Disables all programming instructions.

x = Don't care.

5

www.fairchildsemi.com

FM93C46

Timing Diagrams

Synchronous Data Timing

V

IH

CS

V

t

IL

CSS

t

CSH

SKH

SKL

t

SKS

V

IH

SK

V

IL

t

DIH

DIS

V

IH

DI

V

IL

t

PD

t

DF

t

DH

V

OH

DO (READ)

V

OL

t

SV

t

DF

DH

V

OH

DO (PROGRAM)

STATUS VALID

V

OL

DS800025-4

READ

CS

SK

DI

t

CS

. . .

1

0

A5

A0

. . .

DO

0

D15

D0

DS800025-5

WEN

CS

SK

DI

t

CS

. . .

1

0

1

X

DS800025-6

WDS

CS

SK

DI

t_CS

. . .

1

0

X

DS800025-7

6

www.fairchildsemi.com

FM93C46

Timing Diagrams (Continued)

W^WR^RI^IT^TEE

CS

SK

t

CS

. . .

1

0

1

A5

A0

D15

D0

DI

DO

BUSY

READY

t

WP

DS800025-8

WRALL

CS

SK

DI

t

CS

. . .

1

0

1

DON'T CARE (4 BITS) D15

D0

DO

BUSY

READY

t

WP

DS800025-9

ERASE

t

CS

SK

STANDBY

. . .

DI

1

A5

A4

A3

A0

HI-Z

DO

BUSY

READY

t

WP

DS800025-10

ERAL

t

CS

STANDBY

SK

DI

1

0

1

0

DON'T CARE BITS (4 BITS)

HI-Z

DO

BUSY

READY

t

WP

DS800025-11

7

www.fairchildsemi.com

FM93C46

Physical Dimensions inches (millimeters) unless otherwise noted

0.189 - 0.197

(4.800 - 5.004)

8

7

6

5

0.228 - 0.244

(5.791 - 6.198)

1

2

3

4

Lead #1

IDENT

0.150 - 0.157

(3.810 - 3.988)

0.053 - 0.069

(1.346 - 1.753)

0.010 - 0.020

(0.254 - 0.508)

0.004 - 0.010

(0.102 - 0.254)

x 45°

8° Max, Typ.

All leads

Seating

Plane

0.04

0.0075 - 0.0098

(0.190 - 0.249)

Typ. All Leads

(0.102)

All lead tips

0.014

(0.356)

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

0.050

(1.270)

Typ

0.014 - 0.020

(0.356 - 0.508)

Typ.

Molded Small Out-Line Package (M8)

Package Number M08A

0.114 - 0.122

(2.90 - 3.10)

8

5

(7.72) Typ

(4.16) Typ

0.169 - 0.177

(4.30 - 4.50)

0.246 - 0.256

(6.25 - 6.5)

(1.78) Typ

(0.42) Typ

0.123 - 0.128

(3.13 - 3.30)

(0.65) Typ

Land pattern recommendation

1

4

Pin #1 IDENT

0.0433

Max

(1.1)

0.0035 - 0.0079

See detail A

0.002 - 0.006

(0.05 - 0.15)

0.0256 (0.65)

Typ.

Gage

plane

0.0075 - 0.0098

(0.19 - 0.30)

0°-8°

DETAIL A

Typ. Scale: 40X

0.0075 - 0.0098

(0.19 - 0.25)

0.020 - 0.028

(0.50 - 0.70)

Seating

plane

8-Pin Molded TSSOP, JEDEC (MT8)

Package Number MTC08

8

www.fairchildsemi.com

FM93C46

Physical Dimensions inches (millimeters) unless otherwise noted

0.373 - 0.400

(9.474 - 10.16)

0.090

(2.286)

8

7

0.032 0.005

(0.813 0.127)

RAD

8

7

6

5

4

0.092

(2.337)

DIA

0.250 - 0.005

(6.35 0.127)

Pin #1

IDENT

+

Pin #1 IDENT

1

Option 1

1

2

3

Option 2

0.280

MIN

0.040

(1.016)

Typ.

(7.112)

0.030

0.145 - 0.200

(3.683 - 5.080)

0.039

(0.991)

MAX

(0.762)

0.300 - 0.320

(7.62 - 8.128)

20° 1°

0.130 0.005

(3.302 0.127)

0.125 - 0.140

95° 5°

(3.175 - 3.556)

0.065

(1.651)

0.125

(3.175)

DIA

0.020

90° 4°

Typ

0.009 - 0.015

(0.229 - 0.381)

(0.508)

Min

0.018 0.003

(0.457 0.076)

NOM

+0.040

-0.015

0.325

0.100 0.010

+1.016

-0.381

8.255

(2.540 0.254)

0.045 0.015

(1.143 0.381)

0.060

(1.524)

0.050

(1.270)

Molded Dual-In-Line Package (N)

Package Number N08E

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a)areintendedforsurgicalimplantintothebody,or(b)support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-

pected to cause the failure of the life support device or system,

or to affect its safety or effectiveness.

Fairchild Semiconductor

Americas

Fairchild Semiconductor

Europe

Fairchild Semiconductor

Hong Kong

Fairchild Semiconductor

Japan Ltd.

Customer Response Center

Tel. 1-888-522-5372

Fax:

Tel:

+44 (0) 1793-856858

8/F, Room 808, Empire Centre

68 Mody Road, Tsimshatsui East

Kowloon. Hong Kong

Tel; +852-2722-8338

Fax: +852-2722-8383

4F, Natsume Bldg.

Deutsch

English

Français

Italiano

+49 (0) 8141-6102-0

+44 (0) 1793-856856

+33 (0) 1-6930-3696

+39 (0) 2-249111-1

2-18-6, Yushima, Bunkyo-ku

Tokyo, 113-0034 Japan

Tel: 81-3-3818-8840

Fax: 81-3-3818-8841

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

9

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FM93C46

January 2000

FM93C46A

1K-Bit Serial CMOS EEPROM

(MICROWIRE™ Synchronous Bus)

General Description

Features

The FM93C46A is 1024 bits of CMOS nonvolatile EEPROM

(Electrically Erasable Programmable Read Only Memory) with

MICROWIRE serial interface. FM93C46A can be configured for

either 64 x 16 bit or 128 x 8 bit array using an organization (ORG)

inputpin.ThisdeviceisfabricatedusingFairchildSemiconductor's

floating gate CMOS process for high reliability, high endurance

and low power consumption. This device is available in 8-pin DIP,

SO and TSSOP packages.

I 2.7V to 5.5V operation in all modes

I Typical active current 200µA

10 µA standby current typical

1 µA standby current typical (L)

0.1 µA standby current typical (LZ)

I Self-timed programming cycle

I Device status indication during programming mode

I No erase required before write

The MICROWIRE serial interface offered by this EEPROM en-

ables simple interface to a wide variety of microcontrollers and

microprocessors. There are 7 instructions that operate the

FM93C46A: Read, Erase/Write Enable, Erase, Write, Erase/

Write Disable, Write All and Erase All.

I Reliable CMOS floating gate technology

I MICROWIRE compatible serial I/O

I 40 years data retention

I Endurance: 1,000,000 data changes

I Packages available: 8-pin TSSOP, 8-pin SO, 8-pin DIP

I Schmitt Trigger inputs and V_CClockout to prevent data

corruption

Block Diagram

CS

V

CC

Instruction

Decoder

SK

Control Logic,

And Clock

Generators

Instruction

Register

DI

High Voltage

Generator

And

Address

Register

ORG

Program

Timer

V

PP

EEPROM Array

1024 Bits

(64x16) or (128x8)

Decoder

1 of 64

(or 128)

Read/Write Amps

Data In/Out Register

16 (or 8) Bits

GND

Data Out Buffer

DO

DS800028-1

1

FM93C46A Rev. A

www.fairchildsemi.com

Connection Diagrams

Dual-In-Line Package (N),

8-Pin SO Package (M8)

Rotated Die

(93C46AT)

and 8-Pin TSSOP Package (MT8)

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

NC

CS

SK

DI

ORG

V

CC

V

NC

CC

CS

SS

FM93C46A

DO

DI

ORG

SK

DO

V

SS

DS800028-2

Top View

See Package Number N08E, M08A and MTC08

Pin Names

CS

SK

Chip Select

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

DI

DO

V_SS

ORG

NC

V_CC

Memory Organizational Select

No Connect

Positive Power Supply

Ordering Information

FM 93 XX

C

A

T

LZ

E

XX

Letter Description

Package

N

8-Pin DIP

M8

MT8

8-Pin SO8

8-Pin TSSOP

Temp. Range

None

0 to 70°C

V

E

-40 to +125°C

-40 to +85°C

Voltage Operating Range

Blank

L

4.5V to 5.5V

2.7V to 5.5V

LZ

2.7V to 5.5V and

<1µA Standby Current

Blank

T

Normal Pin Out

Rotated Die Pin Out

A

x8 or x16 Configuration

1K

Density

46

C

CMOS

CS

Data protect and sequential

read

Interface

93

MICROWIRE

FM

Fairchild Non-Volatile

Memory

2

www.fairchildsemi.com

FM93C46A Rev. A

Absolute Maximum Ratings (Note 1)

Ambient Storage Temperature

-65°C to +150°C

Operating Range

Ambient Operating Temperature

FM93C46A

All Input or Output Voltages:

with Respect to Ground

V_CC+1 to -0.3V

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

FM93C46AE

FM93C46AV

Lead Temperature

(Soldering, 10 Seconds)

+300°C

Power Supply (V_CC

)

4.5V to 5.5V

EDS Rating

2000V

Standard V_CC(4.5V to 5.5V) DC and AC Electrical Characteristics

Symbol

I_CCA

Parameter

Operating Current

Standby Current

Input Leakage

Part Number

Conditions

CS = V_IH,SK=1 MHz

Min

Max

Units

mA

1

50

1

I_CCS

CS = 0V, ORG = V_CCor NC

V_IN= 0V to V_CC(Note 2)

µA

I_IL

-1

µA

I_ILO

Input Leakage

ORG Pin

ORG tied to V_CC

ORG tied to V_SS(Note 3)

-1

-2.5

1

2.5

µA

I_OL

V_IL

Output Leakage

V_IN= 0V to V_CC

-1

-0.1

2

1

0.8

µA

V

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Output Low Voltage

Output High Voltage

SK Clock Frequency

SK High Time

V_IH

V_CC+1

0.4

V

V_OL1

V_OH1

V_OL2

V_OH2

f_SK

I_OL= 2.1 mA

I_OH= -400 µA

I_OL= 10 µA

I_OL= -10 µA

(Note 4)

V

2.4

V

0.2

1

V

V_CC- 0.2

0

V

MHz

ns

t_SKH

FM93C46A

FM93C46AE/V

250

300

t_SKL

t_SKS

SK Low Time

250

50

ns

SK Setup Time

SK must be at V_ILfor

t_SKSbefore CS goes

high

t_CS

t_CSS

t_DH

Minimum CS

(Note 5)

250

50

ns

CS Setup Time

DO Hold Time

DI Setup Time

70

t_DIS

FM93C46A

FM93C46AE/V

100

200

t_CSH

t_DIH

t_PD

CS Hold Time

0

ns

ms

DI Hold Time

20

Output Delay

500

100

10

t_SV

CS to Status Valid

CS to DO in Hi-Z

Write Cycle Time

t_DF

CS = V_IL

t_WP

3

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FM93C46A Rev. A

Absolute Maximum Ratings (Note 1)

Operating Range

Ambient Operating Temperature

Ambient Storage Temperature

–65°C to +150°C

FM93C46AL/LZ

FM93C46ALE/LZE

FM93C46A LV/LZV

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltage

with Respect to Ground

+6.5V to -0.3V

Lead Temperature (Soldering, 10 sec.)

ESD Rating

+300°C

Power Supply (V_CC

)

2.7V to 5.5V

2000V

DC and AC Electrical Characteristics V_CC= 2.7V to 5.5V unless otherwise specified

Symbol

Parameter

Part Number

Conditions

Min.

Max.

Units

I_CCA

I_CCS

Operating Current

CS = V_IH, SK = 250KHz

CS = V_IL

1

mA

Standby Current

L

LZ

10

1

µA

I_IL

Input Leakage

V_IN= 0V to V_CC(Note 2)

1

µA

I_ILO

Input Leakage

ORG Pin

ORG tied to V_CC

ORG tied to V_SS(Note 3)

-1

-2.5

1

2.5

I_OL

Output Leakage

V_IN= 0V to V_CC

1

µA

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.1

0.8 V_CC

0.15 V_CC

V_CC+1

V

V_OL

V_OH

Output Low Voltage

Output High Voltage

I_OL= 10 µA

I_OH= -10 µA

0.1 V_CC

V

0.9 V_CC

f_SK

SK Clock Frequency

SK High Time

(Note 4)

0

1

250

KHz

µs

t_SKH

t_SKL

t_SKS

SK Low Time

1

µs

SK Setup Time

SK must be at V_ILfor

t_SKSbefore CS goes high

0.2

µs

t_CS

Minimum CS

Low Time

(Note 5)

1

µs

t_CSS

t_DH

CS Setup Time

DO Hold Time

DI Setup Time

CS Hold Time

DI Hold Time

0.2

70

0.4

0

µs

ns

µs

ns

µs

ms

t_DIS

t_CSH

t_DIH

t_PD

0.4

Output Delay

2

1

t_SV

CS to Status Valid

CS to DO in Hi-Z

Write Cycle Time

t_DF

CS = V_IL

0.4

15

t_WP

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or any

other conditions above those indicated in the operational sections of the specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Capacitance T_A= 25°C, f = 1 MHz

Symbol

Test

Typ Max Units

Note 2: Typical leakage values are in the 20 nA range.

Note 3: The ORG pin may draw > 1 µA when in the x8 mode ude to an internal pull-up transistor.

C_OUT

C_IN

Output Capacitance

Input Capacitance

5

pF

Note 4: The shortest allowable SK clock period = 1/f_SK(as shown under the f_SKf_SKparameter).

Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC

parameters stated in the datasheet. Within this SK period, both t_SKHand t_SKLlimits must be observed.

Therefore, it is not allowable to set 1/f_SK= t_SKHminimum+ t_SKLminimumfor shorter SK cycle time operation.

Note 5: CS (Chip Select) must be brought low (to V_IL) for an interval of t_CSin order to reset all

internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in

the opcode diagrams in the following pages.)

AC Test Conditions

V_CCRange

V_IL/V_IH

Input Levels

.03V/1.8V

V_IL/V_IH

Timing Level

V_OL/V_OH

Timing Level

0.8V/1.5V

I_OL/I_OH

2.7V ≤ V_CC≤ 5.5V

(Extended Voltage Levels)

1.0V

10µA

4.5V ≤ V_CC≤ 5.5V

0.4V/2.4V

1.0V/2.0V

0.4V/2.4V

2.1mA/-0.4mA

(TTL Levels)

Output Load: 1 TTL Gate (C_L= 100 pF)

4

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FM93C46A Rev. A

Serial Clock (SK):

MICROWIRE I/O Pin Description

This pin is the clock input (rising edge active) for clocking in all

opcodesanddataontheDIpinandclockingoutalldataontheDO

pin.However,thispinhasnoeffectontheasynchronousprogram-

ming cycle (see the CS pin section) as the BUSY/READY status

is a function of the CS pin only.

Chip Select (CS):

This pin enables and disables the MICROWIRE device and

performs 3 general functions:

1. When in the low state, the MICROWIRE device is disabled

and the output tri-stated (high impedance). If this pin is

brought high (rising edge active), all internal registers are

reset and the device is enabled, allowing MICROWIRE

communication via DI/DO pins. To restate, the CS pin must

be held high during all device communication and opcode

functions. If the CS pin is brought low, all functions will be

disabled and reset when CS is brought high again. The

exception to this is when a programming cycle is initiated

(see 2 and 3). Again, all activity on the CS, DI and DO pins

is ignored until CS is brought high.

Data-In (DI):

All serial communication into the device is performed using this

input pin (rising edge active). In order to avoid false Start Bits, or

related issues, it is advised to keep the DI pin in the low state

unless actually clocking in data bits (Start Bit, Opcode, Address or

incoming data bits to be programmed). Please note that the first

'1' clocked into the device (after CS is brought high) is seen as a

Start Bit and the beginning of a serial command string, so caution

must be observed when bringing CS high.

2. After entering all required opcode and address data, bringing

CS low initiates the (asynchronous) programming cycle.

Data-Out (DO):

All serial communication out of the device, Read Data ( during

normal reads) as well as READY/BUSY status indication ( during

programming ) are performed using this output pin. Note that,

during READ operations, the EEPROM device starts to drive the

DO output pin "active" after the last address bit (A0) is clocked in.

Hence in applications where 3-wire configuration is required (

whereDIandDOpinsaretiedtogether)cautionmustbeobserved

for correct operation. Please refer AN-758 for further information.

3. When programming is in progress, the Data-Out pin will

display the programming status as either BUSY (DO low) or

READY (DO high) when CS is brought high. (Again, the

output will be tri-stated when CS is low.) To restate, during

programming, the CS pin may be brought high and low any

number of times to view the programming status without

affect the programming operation. Once programming is

completed (Output in READY state), the output is 'cleared'

(returned to normal tri-state condition) by clocking in a Start

Bit. After the Start Bit is clocked in, the output will return to a

tri-stated condition. When clocked in, this Start Bit can be the

first bit in a command string, or CS can be brought low again

to reset all internal circuits.

Organization (ORG):

This pin controls the device architecture (8-bit data word vs. 16-bit

data word). If the ORG pin is brought to V_CC, the device is

configured with a 16-bit data word and if the ORG pin is brought

to V_SS(Ground), the device is configured with an 8-bit data word.

If the ORG pin is left floating, the device will default to a 16-bit data

word.

Instruction Set for the FM93C46A

ORG

Memory

Logic

Configuration

# of Address Bits

0

1

128 x 8

64 x 16

7 Bits

6 Bits

5

www.fairchildsemi.com

FM93C46A Rev. A

64 by 16-Bit Organization (FM93C46A when ORG = V_CCor NC)

Instruction

SB

OP-Code

2 Bits

Address

6 Bits

Data

16 Bits

Comments

READ

EWEN

EWDS

ERASE

WRITE

ERAL

1

10

00

11

01

00

A5–A0

11XXXX

00XXXX

A5–A0

Read data stored in selected registers.

Enables programming modes.

Disables all programming modes.

Erases selected register.

A5–A0

D15–D0

Writes data pattern D15–D0 into selected register.

Erases all registers.

10XXXX

01XXXX

WRAL

Writes data pattern D15–D0 into all registers.

X = Don't care.

128 by 8-Bit Organization (FM93C46A when ORG = GND)

Instruction

SB

OP-Code

2 Bits

Address

7 Bits

Data

8 Bits

Comments

READ

EWEN

EWDS

ERASE

WRITE

ERAL

1

10

00

11

01

00

A6–A0

11XXXXX

00XXXXX

A6–A0

Read data stored in selected registers.

Enables programming modes.

Disables all programming modes.

Erases selected register.

A6–A0

D7–D0

Writes data pattern D7–D0 into selected register.

Erases all registers.

10XXXXX

01XXXXX

WRAL

Writes data pattern D7–D0 into all registers.

X = Don't care.

Functional Description

Programming:

Read (READ):

1. Programming is initiated by clocking in the Start Bit, Opcode

bits, Address bits and the 8/16 data bits (refer to the ORG

pin section).

The READ instruction outputs serial data on the DO pin. After a

READ instruction is received, the instruction and address are

decoded, followed by data transfer from the selected memory

register into a serial-out shift register. A dummy bit (logical 0)

precedes the serial data output string. Output data changes are

initiated by a low to high transition of SK after the last address bit

(A0) is clocked in.

2. Programming is started by bringing the CS pin low. Once the

programming cycle is started, it cannot be stopped. (Bringing

V_CClow will stop any programming, but will also result in

data corruption.)

3. The status of the programming cycle (BUSY or READY) is

observed by bringing the CS pin high and observing the

output state. If the output is LOW, the device is still program-

ming (BUSY). If the output is HIGH, the programming cycle

has been completed and the device is ready for the next

operation. Note that the output will be tri-stated each time

CS is brought low and the READY/BUSY status will be

shown each time CS is brought high.

Erase/Write Enable (EWEN):

When V_CCis applied to the part, it “powers up” in the Erase/Write

Disable (EWDS) state. Therefore, all programming modes must

be preceded by an Erase/Write Enable (EWEN) instruction. Once

an Erase/Write Enable instruction is executed, programming

remains enabled until an Erase/Write Disable (EWDS) instruction

is executed or V_CCis removed from the part.

4. After programming, the READY state (output HIGH) can be

reset and the output tri-stated by clocking in a single Start

Bit. This Start Bit can be the first bit in a command string, or

CS can be brought low again to reset all internal circuits. In

any case, clocking in a '1' bit will tri-state the output.

6

www.fairchildsemi.com

FM93C46A Rev. A

Write (WRITE):

Functional Description (Continued)

The WRITE instruction is followed by 16 bits of data (or 8 bits of

data when using the FM93C46A in the x8 organization) to be

written into the specified address. Please refer to the Program-

ming section for details.

Erase/Write Disable (EWDS):

To protect against accidental data overwrites, the Erase/Write

Disable (EWDS) instruction disables all programming modes and

should follow all programming operations. Execution of a READ

instruction is independent of both the EVEN and EWDS instruc-

tions.

Erase All (ERAL):

The ERAL instruction will simultaneously program all registers in

the memory array to the logical “1” state.

Erase (ERASE):

Write All (WRAL):

The ERASE instruction will program all bits in the specified

register to the logical “1” state. Please refer to the Programming

section for details.

The WRAL instruction will simultaneously program all registers

with the data pattern specified in the instruction.

Timing Diagrams for the FM93C46A

Synchronous Data Timing

V

IH

CS

SK

V

t

IL

CSS

t

CSH

SKH

SKL

t

SKS

V

IH

V

IL

t

DIH

DIS

V

IH

DI

V

IL

t

PD

t

DF

t

DH

V

OH

DO (READ)

V

OL

t

SV

t

DF

DH

V

OH

DO (PROGRAM)

STATUS VALID

V

OL

DS800028-4

7

www.fairchildsemi.com

FM93C46A Rev. A

Timing Diagrams for the FM93C46A (Continued)

Key for Timing Diagrams

Organization of Address and Data Fields for FM93C46A

ORG Pin

V_CCor NC

V_SS

Organization

64 x 16

A_N

A5

A6

D_N

D15

D7

128 x 8

READ

CS

SK

DI

t_CS

. . .

1

0

AN

A₀

. . .

DO

0

D_N

D₀

DS800028-5

EWEN

DO = HI-Z

t_CS

CS

SK

DI

. . .

X

1

0

1

ORG = V , 4 X'S

CC

DS800028-6

ORG = V , 5 X'S

SS

EWDS

DO = HI-Z

t_CS

CS

SK

DI

. . .

X

1

0

ORG = V , 4 X'S

CC

DS800028-7

ORG = V , 5 X'S

SS

ERASE

t_CS

CS

SK

Standby

DI

. . .

A_N

1

A₀

HI-Z

Busy

Ready

DO

DS800028-8

t_WP

8

www.fairchildsemi.com

FM93C46A Rev. A

Timing Diagrams for the FM93C46A (Continued)

WRITE

t_CS

CS

SK

. . .

1

0

1

A_N

A₀D_N

D₀

DI

Busy

t_WP

Ready

DO

DS800028-9

ERAL

t_CS

CS

STANDBY

SK

DI

. . .

1

0

1

0

X

ORG = V_CC, 4 X's

ORG = V_SS, 5 X's

READY

DO

BUSY

READY STATUS SIGNAL RESETS

TO HI-Z AFTER CLOCKING IN

ONE SK CYCLE WITH DI = 1

t_WP

DS800028-10

WRAL

t_CS

CS

STANDBY

SK

DI

. . .

D₀

1

0

1

X

D_N

ORG = V_CC, 4 X's

ORG = V_SS, 5 X's

READY

DO

BUSY

READY STATUS SIGNAL RESETS

TO HI-Z AFTER CLOCKING IN

ONE SK CYCLE WITH DI = 1

t_WP

DS800028-11

9

www.fairchildsemi.com

FM93C46A Rev. A

Physical Dimensions inches (millimeters) unless otherwise noted

0.189 - 0.197

(4.800 - 5.004)

8

7

6

5

0.228 - 0.244

(5.791 - 6.198)

1

2

3

4

Lead #1

IDENT

0.150 - 0.157

(3.810 - 3.988)

0.053 - 0.069

(1.346 - 1.753)

0.010 - 0.020

(0.254 - 0.508)

0.004 - 0.010

(0.102 - 0.254)

x 45°

8° Max, Typ.

All leads

Seating

Plane

0.04

0.0075 - 0.0098

(0.190 - 0.249)

Typ. All Leads

(0.102)

All lead tips

0.014

(0.356)

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

0.050

(1.270)

Typ

0.014 - 0.020

(0.356 - 0.508)

Typ.

Molded Small Outline Package (M8)

Package Number M08A

10

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FM93C46A Rev. A

Physical Dimensions inches (millimeters) unless otherwise noted

0.114 - 0.122

(2.90 - 3.10)

8

5

(7.72) Typ

(4.16) Typ

0.169 - 0.177

(4.30 - 4.50)

0.246 - 0.256

(6.25 - 6.5)

(1.78) Typ

(0.42) Typ

0.123 - 0.128

(3.13 - 3.30)

(0.65) Typ

Land pattern recommendation

1

4

Pin #1 IDENT

0.0433

Max

(1.1)

0.0035 - 0.0079

See detail A

0.002 - 0.006

(0.05 - 0.15)

0.0256 (0.65)

Typ.

Gage

plane

0.0075 - 0.0098

(0.19 - 0.30)

0°-8°

DETAIL A

Typ. Scale: 40X

0.0075 - 0.0098

(0.19 - 0.25)

0.020 - 0.028

(0.50 - 0.70)

Seating

plane

8-Pin Molded TSSOP, JEDEC (MT8)

Package Number MTC08

11

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FM93C46A Rev. A

Physical Dimensions inches (millimeters) unless otherwise noted

0.373 - 0.400

(9.474 - 10.16)

0.090

(2.286)

8

7

0.032 0.005

(0.813 0.127)

RAD

8

7

6

5

4

0.092

(2.337)

DIA

0.250 - 0.005

(6.35 0.127)

Pin #1

IDENT

+

Pin #1 IDENT

1

Option 1

1

2

3

Option 2

0.280

MIN

0.040

(1.016)

Typ.

(7.112)

0.030

0.145 - 0.200

(3.683 - 5.080)

0.039

(0.991)

MAX

(0.762)

0.300 - 0.320

(7.62 - 8.128)

20° 1°

0.130 0.005

(3.302 0.127)

0.125 - 0.140

95° 5°

(3.175 - 3.556)

0.065

(1.651)

0.125

(3.175)

DIA

0.020

90° 4°

Typ

0.009 - 0.015

(0.229 - 0.381)

(0.508)

Min

0.018 0.003

(0.457 0.076)

NOM

+0.040

-0.015

0.325

0.100 0.010

+1.016

-0.381

8.255

(2.540 0.254)

0.045 0.015

(1.143 0.381)

0.060

(1.524)

0.050

(1.270)

Molded Dual-In-Line Package (N)

Package Number N08E

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a)areintendedforsurgicalimplantintothebody,or(b)support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-

pected to cause the failure of the life support device or system,

or to affect its safety or effectiveness.

Fairchild Semiconductor

Americas

Fairchild Semiconductor

Europe

Fairchild Semiconductor

Hong Kong

Fairchild Semiconductor

Japan Ltd.

Customer Response Center

Tel. 1-888-522-5372

Fax:

Tel:

+44 (0) 1793-856858

8/F, Room 808, Empire Centre

68 Mody Road, Tsimshatsui East

Kowloon. Hong Kong

Tel; +852-2722-8338

Fax: +852-2722-8383

4F, Natsume Bldg.

Deutsch

English

Français

Italiano

+49 (0) 8141-6102-0

+44 (0) 1793-856856

+33 (0) 1-6930-3696

+39 (0) 2-249111-1

2-18-6, Yushima, Bunkyo-ku

Tokyo, 113-0034 Japan

Tel: 81-3-3818-8840

Fax: 81-3-3818-8841

12

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FM93C46A Rev. A

December 1999

FM93C56

2K-Bit Serial CMOS EEPROM

(MICROWIRE™ Bus Interface)

General Description

Features

The FM93C56 device is 2048 bits of CMOS non-volatile electri-

cally erasable memory organized as 128x16 bit array. They are

fabricated using Fairchild Semiconductor's floating-gate CMOS

process for high reliability, high endurance and low power con-

sumption. These memory devices are available in an 8-pin SOIC

or 8-pin TSSOP package for small space considerations.

I Device status during programming mode

I Typical active current of 200µA

10µA standby current typical

1µA standby current typical (L)

0.1µA standby current typical (LZ)

I No erase required before write

I Reliable CMOS floating gate technology

I 2.7V to 5.5V operation in all modes

I MICROWIRE compatible serial l/O

I Self-timed programming cycle

I 40 years data retention

FM93C56 is compatible with MICROWIRE serial interface, which

offers simple interface to standard microcontrollers and micropro-

cessors. There are 7 instructions which control this device: Read,

WriteEnable, Erase, EraseAll, Write, WriteAll, andWriteDisable.

The ready/busy status is available on the DO pin to indicate the

completion of a programming cycle.

I Endurance: 1,000,000 data changes

I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP

I Schmitt Trigger inputs and V_CClockout to prevent data

corruption

Block Diagram

V_CC

CS

SK

INSTRUCTION

DECODER

CONTROL LOGIC,

AND CLOCK

GENERATORS

INSTRUCTION

REGISTER

DI

HIGH VOLTAGE

GENERATOR

AND

ADDRESS

REGISTER

PROGRAM

TIMER

V_PP

DECODER

1 OF 128

EEPROM ARRAY

16

READ/WRITE AMPS

16

V_SS

DATA IN/OUT REGISTER

16 BITS

DO

DATA OUT BUFFER

DS800026-1

1

FM93C56

www.fairchildsemi.com

Connection Diagrams

Dual-In-Line Package (N),

8-Pin SO (M8) and 8-Pin TSSOP (MT8)

Rotated Die (93C56T)

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

CS

SK

DI

NC

V_CC

NC

GND

DO

DI

V

CC

NC

CS

DO

GND

SK

DS800026-2

DS800026-12

Top View

See Package Number

N08E, M08A and MTC08

Pin Names

CS

Chip Select

SK

Serial Data Clock

Serial Data Input

DI

DO

GND

V_CC

Serial Data Output

Ground

Power Supply

Ordering Information

FM

93

C

XX

T

LZ

E

XX

Letter Description

Package

N

8-Pin DIP

M8

MT8

8-Pin SO8

8-Pin TSSOP

Temp. Range

None

0 to 70°C

V

E

-40 to +125°C

-40 to +85°C

Voltage Operating Range

Blank

L

4.5V to 5.5V

2.7V to 5.5V

LZ

2.7V to 5.5V and

<1µA Standby Current

Blank

T

Normal Pin Out

Rotated Die Pin Out

Density

56

2K

C

CMOS

CS

Data protect and sequential

read

Interface

93

MICROWIRE

FM

Fairchild Non-Volatile

Memory

2

www.fairchildsemi.com

FM93C56

Absolute Maximum Ratings (Note 1)

Operating Range

Ambient Storage Temperature

–65°C to +150°C

Ambient Operating Temperature

FM93C56

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltage

with Respect to Ground

+6.5V to -0.3V

FM93C56E

FM93C56V

Lead Temperature (Soldering, 10 sec.)

ESD Rating

+300°C

Power Supply (V_CC

)

4.5V to 5.5V

2000V

DC and AC Electrical Characteristics 4.5V ≤ V_CC≤ 5.5V

Symbol

Parameter

Part Number

Conditions

Min.

Max.

Units

I_CCA

I_CCS

Operating Current

Standby Current

CS = V_IH, SK = 1MHz

CS = V_IL

1

50

1

mA

µA

I_IL

I_OL

Input Leakage

Output Leakage

V_IN= 0V to V_CC

(Note 2)

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.1

2

0.8

V_CC+1

V

V_OL1

V_OH1

Output Low Voltage

Output High Voltage

I_OL= 2.1mA

I_OH= -400 µA

0.4

0.2

1

V

2.4

V_OL2

V_OH2

Output Low Voltage

Output High Voltage

I_OL= 10 µA

I_OH= -10 µA

V

V_CC-0.2

0

f_SK

SK Clock Frequency

SK High Time

(Note 3)

MHz

ns

t_SKH

FM93C56

FM93C56E/V

250

300

t_SKL

t_SKS

SK Low Time

250

50

ns

SK Setup Time

SK must be at V_ILfor

t_SKSbefore CS goes

high

t_CS

Minimum CS

Low Time

(Note 4)

250

ns

t_CSS

t_DH

CS Setup Time

DO Hold Time

DI Setup Time

50

70

ns

t_DIS

FM93C56

FM93C56E/V

100

200

t_CSH

t_DIH

t_PD

CS Hold Time

0

ns

ms

DI Hold Time

20

Output Delay

500

100

10

t_SV

CS to Status Valid

CS to DO in Hi-Z

Write Cycle Time

t_DF

CS = V_IL

t_WP

3

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FM93C56

Absolute Maximum Ratings (Note 1)

Operating Range

Ambient Storage Temperature

–65°C to +150°C

Ambient Operating Temperature

FM93C56L/LZ

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltage

with Respect to Ground

+6.5V to -0.3V

FM93C56LE/LZE

FM93C56LV/LZV

Lead Temperature (Soldering, 10 sec.)

ESD Rating

+300°C

Power Supply (V_CC

)

2.7V to 5.5V

2000V

DC and AC Electrical Characteristics V_CC= 2.7V to 5.5V unless otherwise specified

Symbol

Parameter

Part Number

Conditions

Min.

Max.

Units

I_CCA

I_CCS

Operating Current

CS = V_IH, SK = 250KHz

CS = V_IL

1

mA

Standby Current

L

LZ

10

1

µA

I_IL

I_OL

Input Leakage

Output Leakage

V_IN= 0V to V_CC

(Note 2)

1

µA

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.1

0.8 V_CC

0.15 V_CC

V_CC+1

V

V_OL

V_OH

Output Low Voltage

Output High Voltage

I_OL= 10 µA

I_OH= -10 µA

0.1 V_CC

V

0.9 V_CC

f_SK

SK Clock Frequency

SK High Time

(Note 3)

0

1

250

KHz

µs

t_SKH

t_SKL

t_SKS

SK Low Time

1

µs

SK Setup Time

SK must be at V_ILfor

t_SKSbefore CS goes

high

0.2

µs

t_CS

Minimum CS

Low Time

(Note 4)

1

µs

t_CSS

t_DH

CS Setup Time

DO Hold Time

DI Setup Time

CS Hold Time

DI Hold Time

0.2

70

0.4

0

µs

ns

µs

ns

µs

ms

t_DIS

t_CSH

t_DIH

t_PD

0.4

Output Delay

2

1

t_SV

CS to Status Valid

CS to DO in Hi-Z

Write Cycle Time

t_DF

CS = V_IL

0.4

15

t_WP

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or any

other conditions above those indicated in the operational sections of the specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Capacitance T_A= 25°C, f = 1 MHz (Note 5)

Symbol

Test

Typ Max Units

Note 2: Typical leakage values are in the 20nA range.

Note 3: The shortest allowable SK clock period = 1/f_SK(as shown under the f_SKparameter).

Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC

parametersstatedinthedatasheet.WithinthisSKperiod,botht_SKHandt_SKLlimitsmustbeobserved.

Therefore,itisnotallowabletoset1/f_SK=t_SKHminimum+t_SKLminimumforshorterSKcycletimeoperation.

C_OUT

C_IN

Output Capacitance

Input Capacitance

5

pF

Note 4: CS (Chip Select) must be brought low (to V_IL) for an interval of t_CSin order to reset all

internaldeviceregisters(devicereset)priortobeginninganotheropcodecycle. (Thisisshowninthe

opcode diagram on the following page.)

Note 5: This parameter is periodically sampled and not 100% tested.

AC Test Conditions

V_CCRange

V_IL/V_IH

Input Levels

.03V/1.8V

V_IL/V_IH

Timing Level

V_OL/V_OH

Timing Level

0.8V/1.5V

I_OL/I_OH

2.7V ≤ V_CC≤ 5.5V

(Extended Voltage Levels)

1.0V

10µA

4.5V ≤ V_CC≤ 5.5V

0.4V/2.4V

1.0V/2.0V

0.4V/2.4V

2.1mA/-0.4mA

(TTL Levels)

Output Load: 1 TTL Gate (C_L= 100 pF)

4

www.fairchildsemi.com

FM93C56

Write (WRITE):

Functional Description

TheWRITEinstructionisfollowedbytheaddressand16bitsofdata

to be written into the specified address. After the last bit of data is

put in the data-in (DI) pin, CS must be brought low before the next

rising edge of the SK clock. This falling edge of the CS initiates the

self-timed programming cycle. The D0 pin indicates the READY/

The FM93C56device has7 instructionsas describedbelow. Note

that the MSB of any instruction is a “1” and is viewed as a start bit

in the interface sequence. The next 10 bits carry the op code and

the 8-bit address for register selection.

Read (READ):

BUSYstatusofthechipifCSisbroughthighafteraminimumoft

.

CS

D0 = logical 1 indicates that the register at the address specified in

theinstructionhasbeenwrittenwiththedatapatternspecifiedinthe

instruction and the part is ready for another instruction.

The READ instruction outputs serial data on the D0 pin. After a

READ instruction is received, the instruction and address are

decoded, followed by data transfer from the selected memory

register into a 16-bit serial-out shift register. A dummy bit (logical

0)precedesthe16-bitdataoutputstring. Outputdatachangesare

initiated by a low to high transition of the SK clock.

Erase All (ERAL):

The ERAL instruction will simultaneously program all registers in

thememoryarrayandseteachbittothelogical“1”state.TheErase

All cycle is identical to the ERASE cycle except for the different op-

code. As in the ERASE mode, the DO pin indicates the READY/

BUSY status of the chip if CS is brought high after the t_CSinterval.

Write Enable (WEN):

When V_CCis applied to the part, it 'powers-up' in the Write Disable

(WDS) state. Therefore, all programming modes must be pre-

ceded by a Write Enable (WEN) instruction. Once a Write Enable

instructionisexecuted,programmingremainsenableduntilaWrite

Disable (WDS) instruction is executed or V_CCis removed from the

part.

Write All (WRALL):

The WRALL instruction will simultaneously program all registers

with the data pattern specified in the instruction. As in the WRITE

mode, the DO pin indicates the READY/BUSY status of the chip

Erase (ERASE):

if CS is brought high after the t interval.

CS

The ERASE instruction will program all bits in the specified

register to the logical “1” state. CS is brought low following the

loading of the last address bit. This falling edge of the CS pin

initiates the self-timed programming cycle.

Write Disable (WDS):

To protect against accidental data disturb, the WDS instruction

disables all programming modes and should follow all program-

ming operations. Execution of a READ instruction is independent

of both the WEN and WDS instructions.

The DO pin indicates the READY/BUSY status of the chip if CS is

broughthighafteraminimumtimeoft_CS. DO=logical“0”indicates

that the register, at the address specified in the instruction, has

been erased, and the part is ready for another instruction.

Note: The Fairchild CMOS EEPROMs do not require an "ERASE" or "ERASE ALL"

operationpriortothe"WRITE"and"WRITEALL"instructions. The"ERASE"and"ERASE

ALL"instructionsareincludedtomaintaincompatibilitywithearliertechnologyEEPROMs.

Instruction Set for the FM93C56

Instruction

READ

SB

1

Op. Code

Address

A7-A0

Data

Comments

Reads data stored in memory, at specified address.

Write enable must precede all programming modes.

Erase selected register.

10

00

11

01

00

WEN

1

11xxxxxx

A7-A0

ERASE

WRITE

ERAL

1

A7-A0

D15-D0

Writes selected register.

1

10xxxxxx

01xxxxxx

00xxxxxx

Erases all registers.

WRALL

WDS

1

Writes all registers.

1

Disables all programming instructions.

Note:

A7 is "don't care" bit, but must be included in the address string.

x = Don't care.

5

www.fairchildsemi.com

FM93C56

Timing Diagrams

Synchronous Data Timing

V

IH

CS

V

t

IL

CSS

t

CSH

SKH

SKL

t

SKS

V

IH

SK

V

IL

t

DIH

DIS

V

IH

DI

V

IL

t

PD

t

DF

t

DH

V

OH

DO (READ)

V

OL

t

SV

t

DF

DH

V

OH

DO (PROGRAM)

STATUS VALID

V

OL

DS800026-4

READ

CS

SK

DI

t

CS

. . .

1

0

A7

A0

. . .

DO

0

D15

D0

DS800026-5

WEN

CS

SK

DI

t

CS

. . .

1

0

1

X

DS800026-6

WDS

CS

SK

DI

t_CS

. . .

1

0

X

DS800026-7

6

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FM93C56

Timing Diagrams (Continued)

W^WR^RI^IT^TEE

CS

SK

t

CS

. . .

1

0

1

A7

A0

D15

D0

DI

DO

BUSY

READY

t

WP

DS800026-8

WRALL

CS

SK

DI

t

CS

. . .

1

0

1

DON'T CARE (6 BITS) D15

D0

DO

BUSY

READY

t

WP

DS800026-9

ERASE

t

CS

SK

STANDBY

. . .

DI

1

A7

A6

A5

A0

HI-Z

DO

BUSY

READY

t

WP

DS800026-10

ERAL

t

CS

STANDBY

SK

DI

1

0

1

0

DON'T CARE BITS (6 BITS)

HI-Z

DO

BUSY

READY

t

WP

DS800026-11

7

www.fairchildsemi.com

FM93C56

Physical Dimensions inches (millimeters) unless otherwise noted

0.189 - 0.197

(4.800 - 5.004)

8

7

6

5

0.228 - 0.244

(5.791 - 6.198)

1

2

3

4

Lead #1

IDENT

0.150 - 0.157

(3.810 - 3.988)

0.053 - 0.069

(1.346 - 1.753)

0.010 - 0.020

(0.254 - 0.508)

0.004 - 0.010

(0.102 - 0.254)

x 45°

8° Max, Typ.

All leads

Seating

Plane

0.04

0.0075 - 0.0098

(0.190 - 0.249)

Typ. All Leads

(0.102)

All lead tips

0.014

(0.356)

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

0.050

(1.270)

Typ

0.014 - 0.020

(0.356 - 0.508)

Typ.

Molded Small Out-Line Package (M8)

Package Number M08A

0.114 - 0.122

(2.90 - 3.10)

8

5

(7.72) Typ

(4.16) Typ

0.169 - 0.177

(4.30 - 4.50)

0.246 - 0.256

(6.25 - 6.5)

(1.78) Typ

(0.42) Typ

0.123 - 0.128

(3.13 - 3.30)

(0.65) Typ

Land pattern recommendation

1

4

Pin #1 IDENT

0.0433

Max

(1.1)

0.0035 - 0.0079

See detail A

0.002 - 0.006

(0.05 - 0.15)

0.0256 (0.65)

Typ.

Gage

plane

0.0075 - 0.0098

(0.19 - 0.30)

0°-8°

DETAIL A

Typ. Scale: 40X

0.0075 - 0.0098

(0.19 - 0.25)

0.020 - 0.028

(0.50 - 0.70)

Seating

plane

8-Pin Molded TSSOP, JEDEC (MT8)

Package Number MTC08

8

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FM93C56

Physical Dimensions inches (millimeters) unless otherwise noted

0.373 - 0.400

(9.474 - 10.16)

0.090

(2.286)

8

7

0.032 0.005

(0.813 0.127)

RAD

8

7

6

5

4

0.092

(2.337)

DIA

0.250 - 0.005

(6.35 0.127)

Pin #1

IDENT

+

Pin #1 IDENT

1

Option 1

1

2

3

Option 2

0.280

MIN

0.040

(1.016)

Typ.

(7.112)

0.030

0.145 - 0.200

(3.683 - 5.080)

0.039

(0.991)

MAX

(0.762)

0.300 - 0.320

(7.62 - 8.128)

20° 1°

0.130 0.005

(3.302 0.127)

0.125 - 0.140

95° 5°

(3.175 - 3.556)

0.065

(1.651)

0.125

(3.175)

DIA

0.020

90° 4°

Typ

0.009 - 0.015

(0.229 - 0.381)

(0.508)

Min

0.018 0.003

(0.457 0.076)

NOM

+0.040

-0.015

0.325

0.100 0.010

+1.016

-0.381

8.255

(2.540 0.254)

0.045 0.015

(1.143 0.381)

0.060

(1.524)

0.050

(1.270)

Molded Dual-In-Line Package (N)

Package Number N08E

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a)areintendedforsurgicalimplantintothebody,or(b)support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-

pected to cause the failure of the life support device or system,

or to affect its safety or effectiveness.

Fairchild Semiconductor

Americas

Fairchild Semiconductor

Europe

Fairchild Semiconductor

Hong Kong

Fairchild Semiconductor

Japan Ltd.

Customer Response Center

Tel. 1-888-522-5372

Fax:

Tel:

+44 (0) 1793-856858

8/F, Room 808, Empire Centre

68 Mody Road, Tsimshatsui East

Kowloon. Hong Kong

Tel; +852-2722-8338

Fax: +852-2722-8383

4F, Natsume Bldg.

Deutsch

English

Français

Italiano

+49 (0) 8141-6102-0

+44 (0) 1793-856856

+33 (0) 1-6930-3696

+39 (0) 2-249111-1

2-18-6, Yushima, Bunkyo-ku

Tokyo, 113-0034 Japan

Tel: 81-3-3818-8840

Fax: 81-3-3818-8841

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

9

www.fairchildsemi.com

FM93C56

January 2000

FM93C56A

2K-Bit Serial CMOS EEPROM

(MICROWIRE™ Synchronous Bus)

General Description

Features

The FM93C56A is 2048 bits of CMOS nonvolatile EEPROM (

Electrically Erasable Programmable Read Only Memory) with

MICROWIRE serial interface. FM93C56A can be configured for

either 128 x 16 bit or 256 x 8 bit array using an organization (ORG)

inputpin.ThisdeviceisfabricatedusingFairchildSemiconductor's

floating gate CMOS process for high reliability, high endurance

and low power consumption. This device is available in 8-pin DIP,

SO and TSSOP packages.

I 2.7V to 5.5V operation in all modes

I Typical active current 200µA

10 µA standby current typical

1 µA standby current typical (L)

0.1 µA standby current typical (LZ)

I Self-timed programming cycle

I Device status indication during programming mode

I No erase required before write

The MICROWIRE serial interface offered by this EEPROM en-

ables simple interface to a wide variety of microcontrollers and

microprocessors. There are 7 instructions that operate the

FM93C56A: Read, Erase/Write Enable, Erase, Write, Erase/

Write Disable, Write All and Erase All.

I Reliable CMOS floating gate technology

I MICROWIRE compatible serial I/O

I 40 years data retention

I Endurance: 1,000,000 data changes

I Packages available: 8-Pin TSSOP, 8-pin SO, 8-pin DIP

I Schmitt Trigger inputs and V_CClockout to prevent data

corruption

Block Diagram

CS

V

CC

Instruction

Decoder

SK

Control Logic,

And Clock

Generators

Instruction

Register

DI

High Voltage

Generator

And

Address

Register

ORG

Program

Timer

V

PP

EEPROM Array

2048 Bits

(128x16) or (256x8)

Decoder

1 of 128

(or 256)

Read/Write Amps

Data In/Out Register

16 (or 8) Bits

GND

Data Out Buffer

DO

DS800029-1

1

FM93C56A Rev. A

www.fairchildsemi.com

Connection Diagram

Rotated Die

(93C56AT)

Dual-In-Line Package (N)

8-Pin SO Package (M8)

and 8-Pin TSSOP Package (MT8)

1

8

NC

1

8

7

6

5

ORG

CS

SK

DI

V

CC

²FM93C56A

7

V

²FM93C56A

NC

CC

CS

SS

3

6

DO

DI

3

ORG

4

5

SK

4

DO

V

SS

DS800029-2

Top View

See Package Number N08E, M08A and MTC08

Pin Names

CS

Description

Chip Select

SK

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

DI

DO

V_SS

ORG

NC

Memory Organization Select

No Connect

V_CC

Positive Power Supply

Ordering Information

FM 93 XX

C

A

T

LZ

E

XX

Letter Description

Package

N

8-Pin DIP

M8

MT8

8-Pin SO8

8-Pin TSSOP

Temp. Range

None

0 to 70°C

V

E

-40 to +125°C

-40 to +85°C

Voltage Operating Range

Blank

L

4.5V to 5.5V

2.7V to 5.5V

LZ

2.7V to 5.5V and

<1µA Standby Current

Blank

T

Normal Pin Out

Rotated Die Pin Out

A

x8 or x16 Configuration

2K

Density

56

C

CMOS

CS

Data protect and sequential

read

Interface

93

MICROWIRE

FM

Fairchild Non-Volatile

Memory

2

www.fairchildsemi.com

FM93C56A Rev. A

Absolute Maximum Ratings (Note 1)

Operating Conditions

Ambient Storage Temperature

-65°C to +150°C

Ambient Operating Temperature

FM93C56A

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltages

with Respect to Ground

FM93C56AE

FM93C56AV

V_CC+1 to -0.3V

Lead Temperature

Power Supply (V_CC) Range

4.5V to 5.5V

(Soldering, 10 seconds)

+300°C

ESD Rating

2000V

DC and AC Electrical Characteristics 4.5V ≤ V_CC≤ 5.5V

Symbol

I_CCA

Parameter

Operating Current

Standby Current

Input Leakage

Part Number

Conditions

CS = V_IHSK = 1 MHz

Min

Max

Units

mA

1

50

1

I_CCS

CS = 0V ORG = V_CCor NC

V_IN= 0V to V_CC(Note 2)

µA

I_IL

-1

µA

I_ILO

Input Leakage

ORG Pin

ORG Tied to V_CC

ORG Tied to V_SS(Note 3)

-1

-2.5

1

2.5

µA

I_OL

V_IL

Output Leakage

V_IN= 0V to V_CC

-1

-0.1

2

1

0.8

µA

V

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Output Low Voltage

Output High Voltage

SK Clock Frequency

SK High Time

V_IH

V_CC+1

0.4

V

V_OL1

V_OH1

V_OL2

V_OH2

f_SK

I_OL= 2.1 mA

I_OH= -400 µA

I_OL= 10 µA

I_OL= -10 µA

(Note 4)

V

2.4

V

0.2

1

V

V_CC-0.2

0

V

MHz

ns

t_SKH

FM93C56A

FM93C56AE

250

300

t_SKL

t_SKS

SK Low Time

250

50

ns

SK Setup Time

SK must be at V_ILfor

t_SKSbefore CS goes

high

t_CS

Minimum CS

Low Time

(Note 5)

250

ns

t_CSS

t_DH

CS Set-Up Time

D0 Hold Time

50

70

ns

t_DIS

DI Set-Up Time

FM93C56A

FM93C56AE/V

100

200

t_CSH

t_DIH

t_PD

t_SV

CS Hold Time

0

ns

ms

DI Hold Time

20

Output Delay

500

100

10

CS to Status Valid

CS to DO in Hi-Z

Write Cycle Time

t_DF

t_WP

3

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FM93C56A Rev. A

Absolute Maximum Ratings (Note 1)

Operating Range

Ambient Operating Temperature

Ambient Storage Temperature

–65°C to +150°C

FM93C56AL/LZ

FM93C56ALE/LZE

FM93C56A LV/LZV

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltage

with Respect to Ground

+6.5V to -0.3V

Lead Temperature (Soldering, 10 sec.)

ESD Rating

+300°C

Power Supply (V_CC

)

2.7V to 5.5V

2000V

DC and AC Electrical Characteristics V_CC= 2.7V to 5.5V unless otherwise specified

Symbol

Parameter

Part Number

Conditions

Min.

Max.

Units

I_CCA

I_CCS

Operating Current

CS = V_IH, SK = 250KHz

CS = V_IL

1

mA

Standby Current

L

LZ

10

1

µA

I_IL

Input Leakage

V_IN= 0V to V_CC(Note 2)

1

µA

I_ILO

Input Leakage

ORG Pin

ORG tied to V_CC

ORG tied to V_SS(Note 3)

-1

-2.5

1

2.5

I_OL

Output Leakage

V_IN= 0V to V_CC

1

µA

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.1

0.8 V_CC

0.15 V_CC

V_CC+1

V

V_OL

V_OH

Output Low Voltage

Output High Voltage

I_OL= 10 µA

I_OH= -10 µA

0.1 V_CC

V

0.9 V_CC

f_SK

SK Clock Frequency

SK High Time

(Note 4)

0

1

250

KHz

µs

t_SKH

t_SKL

t_SKS

SK Low Time

1

µs

SK Setup Time

SK must be at V_ILfor

t_SKSbefore CS goes high

0.2

µs

t_CS

Minimum CS

Low Time

(Note 5)

1

µs

t_CSS

t_DH

CS Setup Time

DO Hold Time

DI Setup Time

CS Hold Time

DI Hold Time

0.2

70

0.4

0

µs

ns

µs

ns

µs

ms

t_DIS

t_CSH

t_DIH

t_PD

0.4

Output Delay

2

1

t_SV

CS to Status Valid

CS to DO in Hi-Z

Write Cycle Time

t_DF

CS = V_IL

0.4

15

t_WP

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or any

other conditions above those indicated in the operational sections of the specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Capacitance T_A= 25°C, f = 1 MHz

Symbol

C_OUT

Test

Typ Max Units

Note 2: Typical leakage values are in the 20 nA range.

Note 3: The ORG pin may draw > 1 µA when in the x8 mode ude to an internal pull-up transistor.

Output Capacitance

Input Capacitance

5

pF

Note 4: The shortest allowable SK clock period = 1/f_SK(as shown under the f_SKf_SKparameter).

Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC

parameters stated in the datasheet. Within this SK period, both t_SKHand t_SKLlimits must be observed.

Therefore, it is not allowable to set 1/f_SK= t_SKHminimum+ t_SKLminimumfor shorter SK cycle time operation.

C_IN

Note 5: CS (Chip Select) must be brought low (to V_IL) for an interval of t_CSin order to reset all

internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in

the opcode diagrams in the following pages.)

AC Test Conditions

V_CCRange

V_IL/V_IH

Input Levels

.03V/1.8V

V_IL/V_IH

Timing Level

V_OL/V_OH

Timing Level

0.8V/1.5V

I_OL/I_OH

2.7V ≤ V_CC≤ 5.5V

(Extended Voltage Levels)

1.0V

10µA

4.5V ≤ V_CC≤ 5.5V

0.4V/2.4V

1.0V/2.0V

0.4V/2.4V

2.1mA/-0.4mA

(TTL Levels)

Output Load: 1 TTL Gate (C_L= 100 pF)

4

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FM93C56A Rev. A

Serial Clock (SK):

MICROWIRE I/O Pin Description

This pin is the clock input (rising edge active) for clocking in all

opcodesanddataontheDIpinandclockingoutalldataontheDO

pin.However,thispinhasnoeffectontheasynchronousprogram-

ming cycle (see the CS pin section) as the BUSY/READY status

is a function of the CS pin only.

Chip Select (CS):

This pin enables and disables the MICROWIRE device and

performs 3 general functions:

1. When in the low state, the MICROWIRE device is disabled

and the output tri-stated (high impedance). If this pin is

brought high (rising edge active), all internal registers are

reset and the device is enabled, allowing MICROWIRE

communication via DI/DO pins. To restate, the CS pin must

be held high during all device communication and opcode

functions. If the CS pin is brought low, all functions will be

disabled and reset when CS is brought high again. The

exception to this is when a programming cycle is initiated

(see 2 and 3). Again, all activity on the CS, DI and DO pins

is ignored until CS is brought high.

Data-In (DI):

All serial communication into the device is performed using this

input pin (rising edge active). In order to avoid false Start Bits, or

related issues, it is advised to keep the DI pin in the low state

unless actually clocking in data bits (Start Bit, Opcode, Address or

incoming data bits to be programmed). Please note that the first

'1' clocked into the device (after CS is brought high) is seen as a

Start Bit and the beginning of a serial command string, so caution

must be observed when bringing CS high.

2. After entering all required opcode and address data, bringing

CS low initiates the (asynchronous) programming cycle.

Data-Out (DO):

All serial communication out of the device, Read Data ( during

normal reads) as well as READY/BUSY status indication ( during

programming ) are performed using this output pin. Note that,

during READ operations, the EEPROM device starts to drive the

DO output pin "active" after the last address bit (A0) is clocked in.

Hence in applications where 3-wire configuration is required (

whereDIandDOpinsaretiedtogether)cautionmustbeobserved

for correct operation. Please refer AN-758 for further information.

3. When programming is in progress, the Data-Out pin will

display the programming status as either BUSY (DO low) or

READY (DO high) when CS is brought high. (Again, the

output will be tri-stated when CS is low.) To restate, during

programming, the CS pin may be brought high and low any

number of times to view the programming status without

affect the programming operation. Once programming is

completed (Output in READY state), the output is 'cleared'

(returned to normal tri-state condition) by clocking in a Start

Bit. After the Start Bit is clocked in, the output will return to a

tri-stated condition. When clocked in, this Start Bit can be the

first bit in a command string, or CS can be brought low again

to reset all internal circuits.

Organization (ORG):

This pin controls the device architecture (8-bit data word vs. 16-bit

data word). If the ORG pin is brought to V_CC, the device is

configured wiht a 16-bit data word and if the ORG pin is brought

to V_SS(Ground), the device is configured with an 8-bit data word.

If the ORG pin is left floating, the device will default to a 16-bit data

word.

Instruction Set for the FM93C56A

ORG

Memory

Logic

Configuration

# of Address Bits

0

1

256 x 8

9 Bits

8 Bits

128 x 16

Note:

Theleading(MSB)bitisa"don'tcare,"butmustbeincludedintheaddressstring.

5

www.fairchildsemi.com

FM93C56A Rev. A

128 by 16-Bit Organization (FM93C56A when ORG = V_CCor NC)

Instruction

SB

OP-Code

2 Bits

Address

8 Bits

Data

16 Bits

Comments

READ

EWEN

EWDS

ERASE

WRITE

ERAL

1

10

00

11

01

00

A7–A0

11XXXXXX

00XXXXXX

A7–A0

Read data stored in selected registers.

Enables programming modes.

Disables all programming modes.

Erase selected register.

A7–A0

D15–D0

Writes data pattern D15–D0 into selected register.

Erases all registers.

10XXXXXX

01XXXXXX

WRAL

Writes data pattern D15–D0 into all registers.

Note: The A7 bit is a "don't care" bit, but must be entered in the Address string.

Note: X = Don't care.

256 by 8-Bit Organization (FM93C56A when ORG = GND)

Instruction

SB

OP-Code

2 Bits

Address

9 Bits

Data

8 Bits

Comments

READ

EWEN

EWDS

ERASE

WRITE

ERAL

1

10

00

11

01

00

A8–A0

11XXXXXXX

00XXXXXXX

A8–A0

Read data stored in selected registers.

Enables programming modes.

Disables all programming modes.

Erase selected register.

A8–A0

D7–D0

Writes data pattern D7–D0 into selected registers.

Erases all registers.

10XXXXXXX

01XXXXXXX

WRAL

Writes data pattern D7–D0 into all registers.

Note: The A8 bit is a "don't care" bit, but must be entered in the Address string.

Note: X = Don't care.

Read (READ)

Functional Description

The READ instruction outputs serial data on the DO pin. After a

READ instruction is received, the instruction and address are

decoded, followed by data transfer from the selected memory

register into a serial-out shift register. A dummy bit (logical 0)

precedes the serial data output string. Output data changes are

initiated by a low to high transition of SK after the last address bit

(A0) is clocked in.

Programming:

1. Programming is initiated by clocking in the Start Bit, Opcode

bits, Address bits and the 8/16 data bits (refer to the ORG

pin section).

2. Programming is started by bringing the CS pin low. Once the

programming cycle is started, it cannot be stopped. (Bringing

V

_CClow will stop any programming, but will also result in

Erase/Write Enable (EWEN)

data corruption.)

When V_CCis applied to the part, it “powers up” in the Erase/Write

Disable (EWDS) state. Therefore, all programming modes must

be preceded by an Erase/Write Enable (EWEN) instruction. Once

an Erase/Write Enable instruction is executed, programming

remains enabled until an Erase/Write Disable (EWDS) instruction

is executed or V_CCis removed from the part.

3. The status of the programming cycle (BUSY or READY) is

observed by bringing the CS pin high and observing the

output state. If the output is LOW, the device is still program-

ming (BUSY). If the output is HIGH, the programming cycle

has been completed and the device is ready for the next

operation. Note that the output will be tri-stated each time

CS is brought low and the READY/BUSY status will be

shown each time CS is brought high.

4. After programming, the READY state (output HIGH) can be

reset and the output tri-stated by clocking in a single Start

Bit. This Start Bit can be the first bit in a command string, or

CS can be brought low again to reset all internal circuits. In

any case, clocking in a '1' bit will tri-state the output.

6

www.fairchildsemi.com

FM93C56A Rev. A

Write (WRITE):

Functional Description (Continued)

The WRITE instruction is followed by 16 bits of data (or 8 bits of

data when using the FM93C56A in the x8 organization) to be

written into the specified address. Please refer to the Program-

ming section for details.

Erase/Write Disable (EWDS):

To protect against accidental data overwrites, the Erase/Write

Disable (EWDS) instruction disables all programming modes and

should follow all programming operations. Execution of a READ

instruction is independent of both the EWEN and EWDS instruc-

tions.

Erase All (ERAL):

The ERAL instruction will simultaneously program all registers in

the memory array to the logical “1” state.

Erase (ERASE):

Write All (WRAL):

The ERASE instruction will program all bits in the specified

register to the logical “1” state. Please refer to the Programming

section for details.

The WRAL instruction will simultaneously program all registers

with the data pattern specified in the instruction.

Timing Diagrams for the FM93C56A

Synchronous Data Timing

V

IH

CS

SK

V

t

IL

CSS

t

CSH

SKH

SKL

t

SKS

V

IH

V

IL

t

DIH

DIS

V

IH

DI

V

IL

t

PD

t

DF

t

DH

V

OH

DO (READ)

V

OL

t

DF

SV

DH

V

OH

DO (PROGRAM)

STATUS VALID

V

OL

DS800029-4

7

www.fairchildsemi.com

FM93C56A Rev. A

Timing Diagrams for the FM93C56A (Continued)

Key for Timing Diagrams

Organization of Address and Data Fields for FM93C56A

ORG Pin

V_CCor NC

V_SS

Organization

128 x 16

A_ND_N

A7

D15

256 x 8

A8

D7

Note:

The MSB is "don't care."

READ

CS

SK

DI

t_CS

. . .

1

0

A

N

A₀

. . .

DO

0

D_N

D₀

DS800029-5

EWEN

DO = HI-Z

t

CS

SK

DI

CS

. . .

X

1

0

1

ORG = V , 4 X'S

CC

DS800029-6

ORG = V , 5 X'S

SS

EWDS

DO = HI-Z

t

CS

SK

DI

CS

. . .

X

1

0

ORG = V , 4 X'S

CC

DS800029-7

ORG = V , 5 X'S

SS

ERASE

t_CS

CS

SK

Standby

DI

. . .

A_N

1

A₀

HI-Z

Busy

Ready

DO

DS800029-8

t_WP

8

www.fairchildsemi.com

FM93C56A Rev. A

Timing Diagrams for the FM93C56A (Continued)

WRITE

t_CS

CS

SK

. . .

1

0

1

A_N

A₀D_N

D₀

DI

Busy

t_WP

Ready

DO

DS800029-9

ERAL

t_CS

CS

STANDBY

SK

DI

. . .

1

0

1

0

X

ORG = V_CC, 4 X's

ORG = V_SS, 5 X's

READY

DO

BUSY

READY STATUS SIGNAL RESETS

TO HI-Z AFTER CLOCKING IN

ONE SK CYCLE WITH DI = 1

t_WP

DS800029-10

WRAL

t_CS

CS

SK

DI

STANDBY

. . .

D₀

1

0

1

X

D_N

ORG = V_CC, 4 X's

ORG = V_SS, 5 X's

READY

BUSY

DO

READY STATUS SIGNAL RESETS

TO HI-Z AFTER CLOCKING IN

ONE SK CYCLE WITH DI = 1

t_WP

DS800029-11

9

www.fairchildsemi.com

FM93C56A Rev. A

Physical Dimensions inches (millimeters) unless otherwise noted

0.189 - 0.197

(4.800 - 5.004)

8

7

6

5

0.228 - 0.244

(5.791 - 6.198)

1

2

3

4

Lead #1

IDENT

0.150 - 0.157

(3.810 - 3.988)

0.053 - 0.069

(1.346 - 1.753)

0.010 - 0.020

(0.254 - 0.508)

0.004 - 0.010

(0.102 - 0.254)

x 45°

8° Max, Typ.

All leads

Seating

Plane

0.04

0.0075 - 0.0098

(0.190 - 0.249)

Typ. All Leads

(0.102)

All lead tips

0.014

(0.356)

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

0.050

(1.270)

Typ

0.014 - 0.020

(0.356 - 0.508)

Typ.

Molded Small Outline Package (M8)

Package Number M08A

10

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FM93C56A Rev. A

Physical Dimensions inches (millimeters) unless otherwise noted

0.114 - 0.122

(2.90 - 3.10)

8

5

(7.72) Typ

(4.16) Typ

0.169 - 0.177

(4.30 - 4.50)

0.246 - 0.256

(6.25 - 6.5)

(1.78) Typ

(0.42) Typ

0.123 - 0.128

(3.13 - 3.30)

(0.65) Typ

Land pattern recommendation

1

4

Pin #1 IDENT

0.0433

Max

(1.1)

0.0035 - 0.0079

See detail A

0.002 - 0.006

(0.05 - 0.15)

0.0256 (0.65)

Typ.

Gage

plane

0.0075 - 0.0098

(0.19 - 0.30)

0°-8°

DETAIL A

Typ. Scale: 40X

0.0075 - 0.0098

(0.19 - 0.25)

0.020 - 0.028

(0.50 - 0.70)

Seating

plane

8-Pin Molded TSSOP, JEDEC (MT8)

Package Number MTC08

11

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FM93C56A Rev. A

Physical Dimensions inches (millimeters) unless otherwise noted

0.373 - 0.400

(9.474 - 10.16)

0.090

(2.286)

8

7

0.032 0.005

(0.813 0.127)

RAD

8

7

6

5

4

0.092

(2.337)

DIA

0.250 - 0.005

(6.35 0.127)

Pin #1

IDENT

+

Pin #1 IDENT

1

Option 1

1

2

3

Option 2

0.280

MIN

0.040

(1.016)

Typ.

(7.112)

0.030

0.145 - 0.200

(3.683 - 5.080)

0.039

(0.991)

MAX

(0.762)

0.300 - 0.320

(7.62 - 8.128)

20° 1°

0.130 0.005

(3.302 0.127)

0.125 - 0.140

95° 5°

(3.175 - 3.556)

0.065

(1.651)

0.125

(3.175)

DIA

0.020

90° 4°

Typ

0.009 - 0.015

(0.229 - 0.381)

(0.508)

Min

0.018 0.003

(0.457 0.076)

NOM

+0.040

-0.015

0.325

0.100 0.010

+1.016

-0.381

8.255

(2.540 0.254)

0.045 0.015

(1.143 0.381)

0.060

(1.524)

0.050

(1.270)

Molded Dual-In-Line Package (N)

Package Number N08E

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a)areintendedforsurgicalimplantintothebody,or(b)support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-

pected to cause the failure of the life support device or system,

or to affect its safety or effectiveness.

Fairchild Semiconductor

Americas

Fairchild Semiconductor

Europe

Fairchild Semiconductor

Hong Kong

Fairchild Semiconductor

Japan Ltd.

Customer Response Center

Tel. 1-888-522-5372

Fax:

Tel:

+44 (0) 1793-856858

8/F, Room 808, Empire Centre

68 Mody Road, Tsimshatsui East

Kowloon. Hong Kong

Tel; +852-2722-8338

Fax: +852-2722-8383

4F, Natsume Bldg.

Deutsch

English

Français

Italiano

+49 (0) 8141-6102-0

+44 (0) 1793-856856

+33 (0) 1-6930-3696

+39 (0) 2-249111-1

2-18-6, Yushima, Bunkyo-ku

Tokyo, 113-0034 Japan

Tel: 81-3-3818-8840

Fax: 81-3-3818-8841

12

www.fairchildsemi.com

FM93C56A Rev. A

December 1999

FM93C66

4K-Bit Serial CMOS EEPROM

(MICROWIRE™ Bus Interface)

General Description

Features

The FM93C66 device is 4096 bits of CMOS non-volatile electri-

cally erasable memory organized as 256x16 bit array. They are

fabricated using Fairchild Semiconductor's floating-gate CMOS

process for high reliability, high endurance and low power con-

sumption. These memory devices are available in an 8-pin SOIC

or 8-pin TSSOP package for small space considerations.

I Device status during programming mode

I Typical active current of 200µA

10µA standby current typical

1µA standby current typical (L)

0.1µA standby current typical (LZ)

I No erase required before write

I Reliable CMOS floating gate technology

I 2.7V to 5.5V operation in all modes

I MICROWIRE compatible serial l/O

I Self-timed programming cycle

I 40 years data retention

FM93C66 is compatible with MICROWIRE interface, which offers

simple interface to standard microcontrollers and microproces-

sors. There are 7 instructions which control this device: Read,

WriteEnable, Erase, EraseAll, Write, WriteAll, andWriteDisable.

The ready/busy status is available on the DO pin to indicate the

completion of a programming cycle.

I Endurance: 1,000,000 data changes

I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP

I Schmitt Trigger inputs and V_CClockout to prevent data

corruption

Block Diagram

V_CC

CS

SK

INSTRUCTION

DECODER

CONTROL LOGIC,

AND CLOCK

GENERATORS

INSTRUCTION

REGISTER

DI

HIGH VOLTAGE

GENERATOR

AND

ADDRESS

REGISTER

PROGRAM

TIMER

V_PP

DECODER

1 OF 256

EEPROM ARRAY

16

READ/WRITE AMPS

16

V_SS

DATA IN/OUT REGISTER

16 BITS

DO

DATA OUT BUFFER

DS800027-1

1

FM93C66

www.fairchildsemi.com

Connection Diagrams

Dual-In-Line Package (N),

8-Pin SO (M8) and 8-Pin TSSOP (MT8)

1

2

3

4

8

7

6

5

CS

SK

DI

V_CC

NC

DO

GND

DS800027-2

Top View

See Package Number

N08E, M08A and MTC08

Pin Names

CS

Chip Select

SK

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

DI

DO

GND

V_CC

Power Supply

Ordering Information

FM

93

C

XX LZ

E

XX

Letter Description

Package

N

8-Pin DIP

M8

MT8

8-Pin SO8

8-Pin TSSOP

Temp. Range

None

0 to 70°C

V

E

-40 to +125°C

-40 to +85°C

Voltage Operating Range

Blank

L

4.5V to 5.5V

2.7V to 5.5V

LZ

2.7V to 5.5V and

<1µA Standby Current

Density

66

C

4K

CMOS

Interface

93

FM

MICROWIRE

Fairchild Non-Volatile

Memory

2

www.fairchildsemi.com

FM93C66

Absolute Maximum Ratings (Note 1)

Operating Range

Ambient Storage Temperature

–65°C to +150°C

Ambient Operating Temperature

FM93C66

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltage

with Respect to Ground

+6.5V to -0.3V

FM93C66E

FM93C66V

Lead Temperature (Soldering, 10 sec.)

ESD Rating

+300°C

Power Supply (V_CC

)

4.5V to 5.5V

2000V

DC and AC Electrical Characteristics 4.5V ≤ V_CC≤ 5.5V

Symbol

Parameter

Part Number

Conditions

Min.

Max.

Units

I_CCA

I_CCS

Operating Current

Standby Current

CS = V_IH, SK = 1MHz

CS = V_IL

1

50

1

mA

µA

I_IL

I_OL

Input Leakage

Output Leakage

V_IN= 0V to V_CC

(Note 2)

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.1

2

0.8

V_CC+1

V

V_OL1

V_OH1

Output Low Voltage

Output High Voltage

I_OL= 2.1mA

I_OH= -400 µA

0.4

0.2

1

V

2.4

V_OL2

V_OH2

Output Low Voltage

Output High Voltage

I_OL= 10 µA

I_OH= -10 µA

V

V_CC-0.2

0

f_SK

SK Clock Frequency

SK High Time

(Note 3)

MHz

ns

t_SKH

FM93C66

FM93C66E/V

250

300

t_SKL

t_SKS

SK Low Time

250

50

ns

SK Setup Time

SK must be at V_ILfor

t_SKSbefore CS goes

high

t_CS

Minimum CS

Low Time

(Note 4)

250

ns

t_CSS

t_DH

CS Setup Time

DO Hold Time

DI Setup Time

50

70

ns

t_DIS

FM93C66

FM93C66E/V

100

200

t_CSH

t_DIH

t_PD

CS Hold Time

0

ns

ms

DI Hold Time

20

Output Delay

500

100

10

t_SV

CS to Status Valid

CS to DO in Hi-Z

Write Cycle Time

t_DF

CS = V_IL

t_WP

3

www.fairchildsemi.com

FM93C66

Absolute Maximum Ratings (Note 1)

Operating Range

Ambient Storage Temperature

–65°C to +150°C

Ambient Operating Temperature

FM93C66L/LZ

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltage

with Respect to Ground

+6.5V to -0.3V

FM93C66LE/LZE

FM93C66LV/LZV

Lead Temperature (Soldering, 10 sec.)

ESD Rating

+300°C

Power Supply (V_CC

)

2.7V to 5.5V

2000V

DC and AC Electrical Characteristics V_CC= 2.7V to 5.5V unless otherwise specified

Symbol

Parameter

Part Number

Conditions

Min.

Max.

Units

I_CCA

I_CCS

Operating Current

CS = V_IH, SK = 250KHz

CS = V_IL

1

mA

Standby Current

L

LZ

10

1

µA

I_IL

Input Leakage

V_IN= 0V to V_CC

1

µA

I_OL

Output Leakage

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.1

0.8 V_CC

0.15 V_CC

V_CC+1

V

V_OL

V_OH

Output Low Voltage

Output High Voltage

I_OL= 10 µA

I_OH= -10 µA

0.1 V_CC

V

0.9 V_CC

f_SK

SK Clock Frequency

SK High Time

(Note 3)

0

1

250

KHz

µs

t_SKH

t_SKL

t_SKS

SK Low Time

1

µs

SK Setup Time

SK must be at V_ILfor

t_SKSbefore CS goes

high

0.2

µs

t_CS

Minimum CS

Low Time

(Note 4)

1

µs

t_CSS

t_DH

CS Setup Time

DO Hold Time

DI Setup Time

CS Hold Time

DI Hold Time

0.2

70

0.4

0

µs

ns

µs

ns

µs

ms

t_DIS

t_CSH

t_DIH

t_PD

0.4

Output Delay

2

1

t_SV

CS to Status Valid

CS to DO in Hi-Z

Write Cycle Time

t_DF

CS = V_IL

0.4

15

t_WP

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or any

other conditions above those indicated in the operational sections of the specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Capacitance T_A= 25°C, f = 1 MHz (Note 5)

Symbol

Test

Typ Max Units

Note 2: Typical leakage values are in the 20nA range.

Note 3: TheshortestallowableSKclockperiod=1/f_SK(asshownunderthef_SKparameter).Maximum

SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated

in the datasheet. Within this SK period, both t_SKHand t_SKLlimits must be observed. Therefore, it is not

allowable to set 1/f_SK= t_SKHminimum+ t_SKLminimumfor shorter SK cycle time operation.

C_OUT

C_IN

Output Capacitance

Input Capacitance

5

pF

Note 4: CS (Chip Select) must be brought low (to V ) for an interval of t_CSin order to reset all internal

IL

device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode

diagram on the following page.)

Note 5: This parameter is periodically sampled and not 100% tested.

AC Test Conditions

V_CCRange

V_IL/V_IH

Input Levels

.03V/1.8V

V_IL/V_IH

Timing Level

V_OL/V_OH

Timing Level

0.8V/1.5V

I_OL/I_OH

2.7V ≤ V_CC≤ 5.5V

(Extended Voltage Levels)

1.0V

10µA

4.5V ≤ V_CC≤ 5.5V

0.4V/2.4V

1.0V/2.0V

0.4V/2.4V

2.1mA/-0.4mA

(TTL Levels)

Output Load: 1 TTL Gate (C_L= 100 pF)

4

www.fairchildsemi.com

FM93C66

Write (WRITE):

Functional Description

TheWRITEinstructionisfollowedbytheaddressand16bitsofdata

to be written into the specified address. After the last bit of data is

put in the data-in (DI) pin, CS must be brought low before the next

rising edge of the SK clock. This falling edge of the CS initiates the

self-timed programming cycle. The D0 pin indicates the READY/

The FM93C66device has7 instructionsas describedbelow. Note

that the MSB of any instruction is a “1” and is viewed as a start bit

in the interface sequence. The next 10 bits carry the op code and

the 8-bit address for register selection.

Read (READ):

BUSYstatusofthechipifCSisbroughthighafteraminimumoft

.

CS

D0 = logical 1 indicates that the register at the address specified in

theinstructionhasbeenwrittenwiththedatapatternspecifiedinthe

instruction and the part is ready for another instruction.

The READ instruction outputs serial data on the D0 pin. After a

READ instruction is received, the instruction and address are

decoded, followed by data transfer from the selected memory

register into a 16-bit serial-out shift register. A dummy bit (logical

0)precedesthe16-bitdataoutputstring. Outputdatachangesare

initiated by a low to high transition of the SK clock.

Erase All (ERAL):

The ERAL instruction will simultaneously program all registers in

thememoryarrayandseteachbittothelogical“1”state.TheErase

All cycle is identical to the ERASE cycle except for the different op-

code. As in the ERASE mode, the DO pin indicates the READY/

BUSY status of the chip if CS is brought high after the t_CSinterval.

Write Enable (WEN):

When V_CCis applied to the part, it 'powers-up' in the Write Disable

(WDS) state. Therefore, all programming modes must be pre-

ceded by a Write Enable (WEN) instruction. Once a Write Enable

instructionisexecuted,programmingremainsenableduntilaWrite

Disable (WDS) instruction is executed or V_CCis removed from the

part.

Write All (WRALL):

The WRALL instruction will simultaneously program all registers

with the data pattern specified in the instruction. As in the WRITE

mode, the DO pin indicates the READY/BUSY status of the chip

Erase (ERASE):

if CS is brought high after the t interval.

CS

The ERASE instruction will program all bits in the specified

register to the logical “1” state. CS is brought low following the

loading of the last address bit. This falling edge of the CS pin

initiates the self-timed programming cycle.

Write Disable (WDS):

To protect against accidental data disturb, the WDS instruction

disables all programming modes and should follow all program-

ming operations. Execution of a READ instruction is independent

of both the WEN and WDS instructions.

The DO pin indicates the READY/BUSY status of the chip if CS is

broughthighafteraminimumtimeoft_CS. DO=logical“0”indicates

that the register, at the address specified in the instruction, has

been erased, and the part is ready for another instruction.

Note: The Fairchild CMOS EEPROMs do not require an "ERASE" or "ERASE ALL"

operationpriortothe"WRITE"and"WRITEALL"instructions. The"ERASE"and"ERASE

ALL"instructionsareincludedtomaintaincompatibilitywithearliertechnologyEEPROMs.

Instruction Set for the FM93C66

Instruction

READ

SB

1

Op. Code

Address

A7-A0

Data

Comments

Reads data stored in memory, at specified address.

Write enable must precede all programming modes.

Erase selected register.

10

00

11

01

00

WEN

1

11xxxxxx

A7-A0

ERASE

WRITE

ERAL

1

A7-A0

D15-D0

Writes selected register.

1

10xxxxxx

01xxxxxx

00xxxxxx

Erases all registers.

WRALL

WDS

1

Writes all registers.

1

Disables all programming instructions.

X = Don't care.

5

www.fairchildsemi.com

FM93C66

Timing Diagrams

Synchronous Data Timing

V

IH

CS

SK

V

t

IL

CSS

t

CSH

SKH

SKL

t

SKS

V

IH

V

IL

t

DIH

DIS

V

IH

DI

V

IL

t

PD

t

DF

t

DH

V

OH

DO (READ)

V

OL

t

SV

t

DF

DH

V

OH

DO (PROGRAM)

STATUS VALID

V

OL

DS800027-4

READ

CS

SK

DI

t

CS

. . .

1

0

A7

A0

. . .

DO

0

D15

D0

DS800027-5

WEN

CS

SK

DI

t

CS

. . .

1

0

1

X

DS800027-6

WDS

CS

SK

DI

t_CS

. . .

1

0

X

DS800027-7

6

www.fairchildsemi.com

FM93C66

Timing Diagrams (Continued)

WRITE

CS

SK

t

CS

. . .

1

0

1

A7

A0

D15

D0

DI

DO

BUSY

READY

t

WP

DS800027-8

WRALL

CS

SK

DI

t

CS

. . .

1

0

1

DON'T CARE (6 BITS) D15

D0

DO

BUSY

READY

t

WP

DS800027-9

ERASE

t

CS

SK

STANDBY

. . .

DI

1

A7

A6

A5

A0

HI-Z

DO

BUSY

READY

t

WP

DS800027-10

ERAL

t

CS

STANDBY

SK

DI

1

0

1

0

DON'T CARE BITS (6 BITS)

HI-Z

DO

BUSY

READY

t

WP

DS800027-11

7

www.fairchildsemi.com

FM93C66

Physical Dimensions inches (millimeters) unless otherwise noted

0.189 - 0.197

(4.800 - 5.004)

8

7

6

5

0.228 - 0.244

(5.791 - 6.198)

1

2

3

4

Lead #1

IDENT

0.150 - 0.157

(3.810 - 3.988)

0.053 - 0.069

(1.346 - 1.753)

0.010 - 0.020

(0.254 - 0.508)

0.004 - 0.010

(0.102 - 0.254)

x 45°

8° Max, Typ.

All leads

Seating

Plane

0.04

0.0075 - 0.0098

(0.190 - 0.249)

Typ. All Leads

(0.102)

All lead tips

0.014

(0.356)

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

0.050

(1.270)

Typ

0.014 - 0.020

(0.356 - 0.508)

Typ.

Molded Small Out-Line Package (M8)

Package Number M08A

0.114 - 0.122

(2.90 - 3.10)

8

5

(7.72) Typ

(4.16) Typ

0.169 - 0.177

(4.30 - 4.50)

0.246 - 0.256

(6.25 - 6.5)

(1.78) Typ

(0.42) Typ

0.123 - 0.128

(3.13 - 3.30)

(0.65) Typ

Land pattern recommendation

1

4

Pin #1 IDENT

0.0433

Max

(1.1)

0.0035 - 0.0079

See detail A

0.002 - 0.006

(0.05 - 0.15)

0.0256 (0.65)

Typ.

Gage

plane

0.0075 - 0.0098

(0.19 - 0.30)

0°-8°

DETAIL A

Typ. Scale: 40X

0.0075 - 0.0098

(0.19 - 0.25)

0.020 - 0.028

(0.50 - 0.70)

Seating

plane

8-Pin Molded TSSOP, JEDEC (MT8)

Package Number MTC08

8

www.fairchildsemi.com

FM93C66

Physical Dimensions inches (millimeters) unless otherwise noted

0.373 - 0.400

(9.474 - 10.16)

0.090

(2.286)

8

7

0.032 0.005

(0.813 0.127)

RAD

8

7

6

5

4

0.092

(2.337)

DIA

0.250 - 0.005

(6.35 0.127)

Pin #1

IDENT

+

Pin #1 IDENT

1

Option 1

1

2

3

Option 2

0.280

MIN

0.040

(1.016)

Typ.

(7.112)

0.030

0.145 - 0.200

(3.683 - 5.080)

0.039

(0.991)

MAX

(0.762)

0.300 - 0.320

(7.62 - 8.128)

20° 1°

0.130 0.005

(3.302 0.127)

0.125 - 0.140

95° 5°

(3.175 - 3.556)

0.065

(1.651)

0.125

(3.175)

DIA

0.020

90° 4°

Typ

0.009 - 0.015

(0.229 - 0.381)

(0.508)

Min

0.018 0.003

(0.457 0.076)

NOM

+0.040

-0.015

0.325

0.100 0.010

+1.016

-0.381

8.255

(2.540 0.254)

0.045 0.015

(1.143 0.381)

0.060

(1.524)

0.050

(1.270)

Molded Dual-In-Line Package (N)

Package Number N08E

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a)areintendedforsurgicalimplantintothebody,or(b)support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-

pected to cause the failure of the life support device or system,

or to affect its safety or effectiveness.

Fairchild Semiconductor

Americas

Fairchild Semiconductor

Europe

Fairchild Semiconductor

Hong Kong

Fairchild Semiconductor

Japan Ltd.

Customer Response Center

Tel. 1-888-522-5372

Fax:

Tel:

+44 (0) 1793-856858

8/F, Room 808, Empire Centre

68 Mody Road, Tsimshatsui East

Kowloon. Hong Kong

Tel; +852-2722-8338

Fax: +852-2722-8383

4F, Natsume Bldg.

Deutsch

English

Français

Italiano

+49 (0) 8141-6102-0

+44 (0) 1793-856856

+33 (0) 1-6930-3696

+39 (0) 2-249111-1

2-18-6, Yushima, Bunkyo-ku

Tokyo, 113-0034 Japan

Tel: 81-3-3818-8840

Fax: 81-3-3818-8841

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

9

www.fairchildsemi.com

FM93C66

January 2000

FM93C66A

4K-Bit Serial CMOS EEPROM

(MICROWIRE™ Bus Interface)

General Description

Features

The FM93C66A is 4096 bits of CMOS nonvolatile EEPROM

(Electrically Erasable Programmable Read Only Memory) with

MICROWIRE serial interface. FM93C66A can be configured for

either 256 x 16 bit or 512 x 8 bit array using an organization (ORG)

inputpin.ThisdeviceisfabricatedusingFairchildSemiconductor's

floating gate CMOS process for high reliability, high endurance

and low power consumption. This device is available in 8-pin DIP,

SO and TSSOP packages.

I 2.7V to 5.5V operation in all modes

I Typical active current of 200µA

10µA standby current typical

1µA standby current typical (L)

0.1µA standby current typical (LZ)

I Self-timed programming cycle

I Device status indication during programming mode

I No erase required before write

The MICROWIRE serial interface offered by this EEPROM en-

ables simple interface to a wide variety of microcontrollers and

microprocessors. There are 7 instructions that operate the

FM93C66A: Read, Erase/Write Enable, Erase, Write, Erase/

Write Disable, Write All and Erase All.

I Reliable CMOS floating gate technology

I MICROWIRE compatible serial I/O

I 40 years data retention

I Endurance: 1,000,000 data changes

I Packages available: 8-pin TSSOP, 8-pin SO, 8-pin DIP

I Schmitt Trigger inputs and V_CClockout to prevent data

corruption

Block Diagram

CS

V

CC

Instruction

Decoder

SK

Control Logic,

And Clock

Generators

Instruction

Register

DI

High Voltage

Generator

And

Address

Register

ORG

Program

Timer

V

PP

EEPROM Array

2048 Bits

(256 x16) or (512 x8)

Decoder

1 of 256

(or 512)

Read/Write Amps

Data In/Out Register

16 (or 8) Bits

GND

Data Out Buffer

DO

DS800030-1

1

FM93C66A Rev. A

www.fairchildsemi.com

Connection Diagram

Dual-In-Line Package (N)

8-Pin SO Package (M8)

and 8-Pin TSSOP Package (MT8)

1

2

3

4

8

7

6

5

CS

SK

DI

V

CC

NC

FM93C66A

Top View

ORG

DO

V

SS

DS800030-2

See Package Number

N08E, M08A and MTC08

Pin Names

Description

Chip Select

CS

SK

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

DI

DO

V_SS

ORG

NC

V_CC

Memory Organization Select

No Connect

Positive Power Supply

Ordering Information

FM

93

C

XX

A

LZ

E

XX

Letter Description

Package

N

8-Pin DIP

M8

MT8

8-Pin SO8

8-Pin TSSOP

Temp. Range

None

0 to 70°C

V

E

-40 to +125°C

-40 to +85°C

Voltage Operating Range

Blank

L

4.5V to 5.5V

2.7V to 5.5V

LZ

2.7V to 5.5V and

<1µA Standby Current

A

x8 or x16 Configuration

Density

66

C

4K

CMOS

Interface

93

FM

MICROWIRE

Fairchild Non-Volatile

Memory

2

www.fairchildsemi.com

FM93C66A Rev. A

Absolute Maximum Ratings (Note 1)

Ambient Storage Temperature

-65°C to +150°C

Operating Conditions

Ambient Operating Temperature

FM93C66A

All Input or Output Voltages

with Respect to Ground

V_CC+1 to -0.3V

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

FM93C66AE

FM93C66AV

Lead Temperature

(Soldering, 10 seconds)

+300°C

Power Supply (V_CC) Range

4.5V to 5.5V

ESD Rating

2000V

DC and AC Electrical Characteristics 4.5V ≤ V_CC≤ 5.5V

Symbol

Parameter

Part Number

Conditions

Min

Max

Units

I_CCA

Operating Current

CS = V_IH,SK=1 MHz

1

mA

I_CCS

I_IL

Standby Current

Input Leakage

CS = 0V ORG = V_CCor NC

V_IN= 0V to V_CC(Note 2)

50

1

µA

-1

I_ILO

Input Leakage

ORG Pin

ORG Tied to V_CC

ORG Tied to V_SS

(Note 3)

-1

-2.5

1

2.5

I_OL

V_IL

Output Leakage

V_IN= 0V to V_CC

-1

-0.1

2

1

0.8

µA

V

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Output Low Voltage

Output High Voltage

SK Clock Frequency

SK High Time

V_IH

V_CC+1

0.4

V

V_OL1

V_OH1

V_OL2

V_OH2

f_SK

I_OL= 2.1 mA

I_OH= -400 µA

I_OL= 10 µA

I_OL= -10 µA

(Note 4)

V

2.4

V

0.2

1

V

V_CC- 0.2

0

V

MHz

ns

t_SKH

FM93C66A

FM93C66AE

250

300

t_SKL

t_SKS

SK Low Time

250

50

ns

SK Setup Time

SK must be at V_ILfor

t_SKSbefore CS goes

high

t_CS

Minimum CS

Low Time

(Note 5)

250

ns

t_CSS

t_DH

CS Set-Up Time

DO Hold Time

DI Set-Up Time

50

70

ns

t_DIS

FM93C66A

FM93C66AE/V

100

200

t_CSH

t_DIH

t_PD

CS Hold Time

DI Hold Time

0

ns

20

Output Delay

500

t_SV

CS to Status Valid

t_DF

CS to DO in Hi-Z

Write Cycle Time

100

10

ns

t_WP

ms

3

www.fairchildsemi.com

FM93C66A Rev. A

Absolute Maximum Ratings (Note 1)

Operating Range

Ambient Operating Temperature

Ambient Storage Temperature

–65°C to +150°C

FM93C66AL/LZ

FM93C66ALE/LZE

FM93C66ALV/LZV

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltage

with Respect to Ground

+6.5V to -0.3V

Lead Temperature (Soldering, 10 sec.)

ESD Rating

+300°C

Power Supply (V_CC

)

2.7V to 5.5V

2000V

DC and AC Electrical Characteristics V_CC= 2.7V to 5.5V unless otherwise specified

Symbol

Parameter

Part Number

Conditions

Min.

Max.

Units

I_CCA

I_CCS

Operating Current

CS = V_IH, SK = 250KHz

CS = V_IL

1

mA

Standby Current

L

LZ

10

1

µA

I_IL

Input Leakage

V_IN= 0V to V_CC(Note 2)

1

µA

I_ILO

Input Leakage

ORG Pin

ORG tied to V_CC

ORG tied to V_SS(Note 3)

-1

-2.5

1

2.5

I_OL

Output Leakage

V_IN= 0V to V_CC

1

µA

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.1

0.8 V_CC

0.15 V_CC

V_CC+1

V

V_OL

V_OH

Output Low Voltage

Output High Voltage

I_OL= 10 µA

I_OH= -10 µA

0.1 V_CC

V

0.9 V_CC

f_SK

SK Clock Frequency

SK High Time

(Note 4)

0

1

250

KHz

µs

t_SKH

t_SKL

t_SKS

SK Low Time

1

µs

SK Setup Time

SK must be at V_ILfor

t_SKSbefore CS goes high

0.2

µs

t_CS

Minimum CS

Low Time

(Note 5)

1

µs

t_CSS

t_DH

CS Setup Time

DO Hold Time

DI Setup Time

CS Hold Time

DI Hold Time

0.2

70

0.4

0

µs

ns

µs

ns

µs

ms

t_DIS

t_CSH

t_DIH

t_PD

0.4

Output Delay

2

1

t_SV

CS to Status Valid

CS to DO in Hi-Z

Write Cycle Time

t_DF

CS = V_IL

0.4

15

t_WP

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or any

other conditions above those indicated in the operational sections of the specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Capacitance T_A= 25°C, f = 1 MHz

Symbol

Test

Typ Max Units

Note 2: Typical leakage values are in the 20 nA range.

Note 3: The ORG pin may draw > 1 µA when in the x8 mode ude to an internal pull-up transistor.

C_OUT

C_IN

Output Capacitance

Input Capacitance

5

pF

Note 4: The shortest allowable SK clock period = 1/f_SK(as shown under the f_SKf_SKparameter).

Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC

parameters stated in the datasheet. Within this SK period, both t_SKHand t_SKLlimits must be observed.

Therefore, it is not allowable to set 1/f_SK= t_SKHminimum+ t_SKLminimumfor shorter SK cycle time operation.

Note 5: CS (Chip Select) must be brought low (to V_IL) for an interval of t_CSin order to reset all

internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in

the opcode diagrams in the following pages.)

AC Test Conditions

V_CCRange

V_IL/V_IH

Input Levels

.03V/1.8V

V_IL/V_IH

Timing Level

V_OL/V_OH

Timing Level

0.8V/1.5V

I_OL/I_OH

2.7V ≤ V_CC≤ 5.5V

(Extended Voltage Levels)

1.0V

10µA

4.5V ≤ V_CC≤ 5.5V

0.4V/2.4V

1.0V/2.0V

0.4V/2.4V

2.1mA/-0.4mA

(TTL Levels)

Output Load: 1 TTL Gate (C_L= 100 pF)

4

www.fairchildsemi.com

FM93C66A Rev. A

Serial Clock (SK):

MICROWIRE I/O Pin Description

This pin is the clock input (rising edge active) for clocking in all

opcodesanddataontheDIpinandclockingoutalldataontheDO

pin.However,thispinhasnoeffectontheasynchronousprogram-

ming cycle (see the CS pin section) as the READY/BUSY status

is a function of the CS pin only.

Chip Select (CS):

This pin enables and disables the MICROWIRE device and

performs 3 general functions:

1. When in the low state, the MICROWIRE device is disabled

and the output tri-stated (high impedance). If this pin is

brought high (rising edge active), all internal registers are

reset and the device is enabled, allowing MICROWIRE

communication via DI/DO pins. To restate, the CS pin must

be held high during all device communication and opcode

functions. If the CS pin is brought low, all functions will be

disabled and reset when CS is brought high again. The

exception to this is when a programming cycle is initiated

(see 2 and 3). Again, all activity on the CS, DI and DO pins

is ignored until CS is brought high.

Data-In (DI):

All serial communication into the device is performed using this

input pin (rising edge active). In order to avoid false Start Bits, or

related issues, it is advised to keep the DI pin in the low state

unless actually clocking in data bits (Start Bit, Opcode, Address or

incoming data bits to be programmed). Please note that the first

'1' clocked into the device (after CS is brought high) is seen as a

Start Bit and the beginning of a serial command string, so caution

must be observed when bringing CS high.

2. After entering all required opcode and address data, bringing

CS low initiates the (asynchronous) programming cycle.

Data-Out (DO):

All serial communication out of the device, Read Data ( during

normal reads) as well as READY/BUSY status indication ( during

programming ) are performed using this output pin. Note that,

during READ operations, the EEPROM device starts to drive the

DO output pin "active" after the last address bit (A0) is clocked in.

Hence in applications where 3-wire configuration is required (

whereDIandDOpinsaretiedtogether)cautionmustbeobserved

for correct operation. Please refer AN-758 for further information.

3. When programming is in progress, the Data-Out pin will

display the programming status as either BUSY (DO low) or

READY (DO high) when CS is brought high. (Again, the

output will be tri-stated when CS is low.) To restate, during

programming, the CS pin may be brought high and low any

number of times to view the programming status without

affect the programming operation. Once programming is

completed (Output in READY state), the output is 'cleared'

(returned to normal tri-state condition) by clocking in a Start

Bit. After the Start Bit is clocked in, the output will return to a

tri-stated condition. When clocked in, this Start Bit can be the

first bit in a command string, or CS can be brought low again

to reset all internal circuits.

Organization (ORG):

This pin controls the device architecture (8-bit data word vs. 16-bit

data word). If the ORG pin is brought to V_CC, the device is

configured with a 16-bit data word and if the ORG pin is brought

to V_SS(Ground), the device is configured with an 8-bit data word.

If the ORG pin is left floating, the device will default to a 16-bit data

word.

Instruction Set for FM93C66A

ORG

Memory

Logic

Configuration

# of Address Bits

0

1

512 x 8

9 Bits

8 Bits

256 x 16

5

www.fairchildsemi.com

FM93C66A Rev. A

256 by 16-Bit Organization (FM93C66A when ORG = V_CCor NC)

Instruction

SB

OP-Code

2 Bits

Address

8 Bits

Data

16 Bits

Comments

READ

EWEN

EWDS

ERASE

WRITE

ERAL

1

10

00

11

01

00

A7–A0

11XXXXXX

00XXXXXX

A7–A0

Read data stored in selected registers.

Enables programming modes.

Disables all programming modes.

Erase selected register.

A7–A0

D15–D0

Writes data pattern D15–D0 into selected register.

Erases all registers.

10XXXXXX

01XXXXXX

WRAL

Writes data pattern D15–D0 into all registers.

X = Don't care.

512 by 8-Bit Organization (FM93C66A when ORG = GND)

Instruction

SB

OP-Code

2 Bits

Address

9 Bits

Data

8 Bits

Comments

READ

EWEN

EWDS

ERASE

WRITE

ERAL

1

10

00

11

01

00

A8–A0

11XXXXXXX

00XXXXXXX

A8–A0

Read data stored in selected registers.

Enables programming modes.

Disables all programming modes.

Erase selected register.

A8–A0

D7–D0

Writes data pattern D7–D0 into selected register.

Erases all registers.

10XXXXXXX

01XXXXXXX

WRAL

Writes data pattern D7–D0 into all registers.

X = Don't care.

Read (READ):

Functional Description

The READ instruction outputs serial data on the DO pin. After a

READ instruction is received, the instruction and address are

decoded, followed by data transfer from the selected memory

register into a serial-out shift register. A dummy bit (logical 0)

precedes the serial data output string. Output data changes are

initiated by a low to high transition of SK after the last address bit

(A0) is clocked in.

Programming:

1. Programming is initiated by clocking in the Start Bit, Opcode

bits, Address bits and the 8/16 data bits (refer to the ORG

pin section).

2. Programming is started by bringing the CS pin low. Once the

programming cycle is started, it cannot be stopped. (Bringing

V_CClow will stop any programming, but will also result in

data corruption.)

Erase/Write Enable (EWEN):

When V_CCis applied to the part, it “powers up” in the Erase/Write

Disable (EWDS) state. Therefore, all programming modes must

be preceded by an Erase/Write Enable (EWEN) instruction. Once

an Erase/Write Enable instruction is executed, programming

remains enabled until an Erase/Write Disable (EWDS) instruction

is executed or V_CCis removed from the part.

3. The status of the programming cycle (BUSY or READY) is

observed by bringing the CS pin high and observing the

output state. If the output is LOW, the device is still program-

ming (BUSY). If the output is HIGH, the programming cycle

has been completed and the device is ready for the next

operation. Note that the output will be tri-stated each time

CS is brought low and the READY/BUSY status will be

shown each time CS is brought high.

4. After programming, the READY state (output HIGH) can be

reset and the output tri-stated by clocking in a single Start

Bit. This Start Bit can be the first bit in a command string, or

CS can be brought low again to reset all internal circuits. In

any case, clocking in a '1' bit will tri-state the output.

6

www.fairchildsemi.com

FM93C66A Rev. A

Write (WRITE):

Functional Description (Continued)

The WRITE instruction is followed by 16 bits of data (or 8 bits of

data when using the FM93C66A in the x8 organization) to be

written into the specified address. Please refer to the Program-

ming section for details.

Erase/Write Disable (EWDS):

To protect against accidental data overwrites, the Erase/Write

Disable (EWDS) instruction disables all programming modes and

should follow all programming operations. Execution of a READ

instruction is independent of both the EWEN and EWDS instruc-

tions.

Erase All (ERAL):

The ERAL instruction will simultaneously program all registers in

the memory array to the logical “1” state.

Erase (ERASE):

Write All (WRAL):

The ERASE instruction will program all bits in the specified

register to the logical “1” state. Please refer to the Programming

section for details.

The WRAL instruction will simultaneously program all registers

with the data pattern specified in the instruction.

Timing Diagrams for the FM93C66A

Synchronous Data Timing

V

IH

CS

SK

V

t

IL

CSS

t

CSH

SKH

SKL

t

SKS

V

IH

V

IL

t

DIH

DIS

V

IH

DI

V

IL

t

PD

t

DF

t

DH

V

OH

DO (READ)

V

OL

t

SV

t

DF

DH

V

OH

DO (PROGRAM)

STATUS VALID

V

OL

DS800030-4

7

www.fairchildsemi.com

FM93C66A Rev. A

Timing Diagrams for the FM93C66A (Continued)

Key for Timing Diagrams

Organization of Address and Data Fields for the FM93C66A

ORG Pin

V_CCor NC

V_SS

Organization

256 x 16

A_ND_N

A7

A8

D15

D7

512 x 8

READ

CS

SK

DI

t_CS

. . .

1

0

A

N

A₀

. . .

DO

0

D_N

D₀

DS800030-5

EWEN

DO = HI-Z

t

CS

SK

DI

CS

. . .

X

1

0

1

ORG = V , 4 X'S

CC

DS800030-6

ORG = V , 5 X'S

SS

EWDS

DO = HI-Z

t

CS

SK

DI

CS

. . .

X

1

0

ORG = V , 4 X'S

CC

DS800030-7

ORG = V , 5 X'S

SS

8

www.fairchildsemi.com

FM93C66A Rev. A

Timing Diagrams for the FM93C66A (Continued)

ERASE

t_CS

CS

SK

Standby

DI

. . .

A_N

1

A₀

HI-Z

Busy

Ready

DO

DS800030-8

t_WP

WRITE

t_CS

CS

SK

DI

. . .

1

0

1

A_N

A₀D_N

D₀

Busy

t_WP

Ready

DO

DS800030-9

ERAL

t_CS

CS

SK

DI

STANDBY

. . .

1

0

1

0

X

ORG = V_CC, 4 X's

ORG = V_SS, 5 X's

READY

DO

BUSY

DS800030-10

READY STATUS SIGNAL RESETS

TO HI-Z AFTER CLOCKING IN

ONE SK CYCLE WITH DI = 1

t_WP

WRAL

t_CS

CS

SK

STANDBY

. . .

D₀

1

0

1

X

D_N

DI

ORG = V_CC, 4 X's

ORG = V_SS, 5 X's

READY

DO

BUSY

READY STATUS SIGNAL RESETS

TO HI-Z AFTER CLOCKING IN

ONE SK CYCLE WITH DI = 1

t_WP

DS800030-11

9

www.fairchildsemi.com

FM93C66A Rev. A

Physical Dimensions inches (millimeters) unless otherwise noted

0.189 - 0.197

(4.800 - 5.004)

8

7

6

5

0.228 - 0.244

(5.791 - 6.198)

1

2

3

4

Lead #1

IDENT

0.150 - 0.157

(3.810 - 3.988)

0.053 - 0.069

(1.346 - 1.753)

0.010 - 0.020

(0.254 - 0.508)

0.004 - 0.010

(0.102 - 0.254)

x 45°

8° Max, Typ.

All leads

Seating

Plane

0.04

0.0075 - 0.0098

(0.190 - 0.249)

Typ. All Leads

(0.102)

All lead tips

0.014

(0.356)

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

0.050

(1.270)

Typ

0.014 - 0.020

(0.356 - 0.508)

Typ.

Molded Small Outline Package (M8)

Package Number M08A

10

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FM93C66A Rev. A

Physical Dimensions inches (millimeters) unless otherwise noted

0.114 - 0.122

(2.90 - 3.10)

8

5

(7.72) Typ

(4.16) Typ

0.169 - 0.177

(4.30 - 4.50)

0.246 - 0.256

(6.25 - 6.5)

(1.78) Typ

(0.42) Typ

0.123 - 0.128

(3.13 - 3.30)

(0.65) Typ

Land pattern recommendation

1

4

Pin #1 IDENT

0.0433

Max

(1.1)

0.0035 - 0.0079

See detail A

0.002 - 0.006

(0.05 - 0.15)

0.0256 (0.65)

Typ.

Gage

plane

0.0075 - 0.0098

(0.19 - 0.30)

0°-8°

DETAIL A

Typ. Scale: 40X

0.0075 - 0.0098

(0.19 - 0.25)

0.020 - 0.028

(0.50 - 0.70)

Seating

plane

8-Pin Molded TSSOP, JEDEC (MT8)

Package Number MTC08

11

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FM93C66A Rev. A

Physical Dimensions inches (millimeters) unless otherwise noted

0.373 - 0.400

(9.474 - 10.16)

0.090

(2.286)

8

7

0.032 0.005

(0.813 0.127)

RAD

8

7

6

5

4

0.092

(2.337)

DIA

0.250 - 0.005

(6.35 0.127)

Pin #1

IDENT

+

Pin #1 IDENT

1

Option 1

1

2

3

Option 2

0.280

MIN

0.040

(1.016)

Typ.

(7.112)

0.030

0.145 - 0.200

(3.683 - 5.080)

0.039

(0.991)

MAX

(0.762)

0.300 - 0.320

(7.62 - 8.128)

20° 1°

0.130 0.005

(3.302 0.127)

0.125 - 0.140

95° 5°

(3.175 - 3.556)

0.065

(1.651)

0.125

(3.175)

DIA

0.020

90° 4°

Typ

0.009 - 0.015

(0.229 - 0.381)

(0.508)

Min

0.018 0.003

(0.457 0.076)

NOM

+0.040

-0.015

0.325

0.100 0.010

+1.016

-0.381

8.255

(2.540 0.254)

0.045 0.015

(1.143 0.381)

0.060

(1.524)

0.050

(1.270)

Molded Dual-In-Line Package (N)

Package Number N08E

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a)areintendedforsurgicalimplantintothebody,or(b)support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-

pected to cause the failure of the life support device or system,

or to affect its safety or effectiveness.

Fairchild Semiconductor

Americas

Fairchild Semiconductor

Europe

Fairchild Semiconductor

Hong Kong

Fairchild Semiconductor

Japan Ltd.

Customer Response Center

Tel. 1-888-522-5372

Fax:

Tel:

+44 (0) 1793-856858

8/F, Room 808, Empire Centre

68 Mody Road, Tsimshatsui East

Kowloon. Hong Kong

Tel; +852-2722-8338

Fax: +852-2722-8383

4F, Natsume Bldg.

Deutsch

English

Français

Italiano

+49 (0) 8141-6102-0

+44 (0) 1793-856856

+33 (0) 1-6930-3696

+39 (0) 2-249111-1

2-18-6, Yushima, Bunkyo-ku

Tokyo, 113-0034 Japan

Tel: 81-3-3818-8840

Fax: 81-3-3818-8841

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

12

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FM93C66A Rev. A

January 2000

FM93C86A

16K-Bit Serial EEPROM

(MICROWIRE™ Bus Interface)

General Description

Features

The FM93C86A is 16,384 bits of CMOS nonvolatile EEPROM

(Electrically Erasable Programmable Read Only Memory) with

MICROWIRE serial interface. FM93C86A can be configured for

either 1024 x 16 bit or 2048 x 8 bit array using an organization

(ORG) input pin. This device is fabricated using Fairchild

Semiconductor's floating gate CMOS process for high reliability,

high endurance and low power consumption. This device is

available in 8-pin DIP and SO packages.

I 2.7V to 5.5V operation in all modes

I Typical active current of 200µA

10µA standby current typical

1µA standby current typical (L)

0.1µA standby current typical (LZ)

I Device status indication during programming mode

I No erase required before write

I Reliable CMOS floating gate technology

I MICROWIRE™ compatible serial I/O

I Self-timed programming cycle

The MICROWIRE serial interface offered by this EEPROM en-

ables simple interface to a wide variety of microcontrollers and

microprocessors. There are 7 instructions that operate the

FM93C86A: Read, Erase/Write Enable, Erase, Write, Erase/

Write Disable, Write All and Erase All.

I 40 years data retention

I Endurance: 1,000,000 data changes

I Packages available: 8-pin SO, 8-pin DIP

I Schmitt Trigger inputs and V_CClockout to prevent data

corruption

Block Diagram

CS

V

CC

Instruction

Decoder

SK

Control Logic,

And Clock

Generators

Instruction

Register

DI

High Voltage

Generator

And

Address

Register

ORG

Program

Timer

V

PP

EEPROM Array

16384 Bits

(1024x16) or (2048x8)

Decoder

1 of 1024

(or 2048)

Read/Write Amps

Data In/Out Register

16 (or 8) Bits

GND

Data Out Buffer

DO

DS800031-12

1

www.fairchildsemi.com

FM93C86A Rev. A

Connection Diagram

Dual-In-Line Package (N)

and 8-Pin SO Package (M8)

CS

SK

DI

1

2

3

4

8

7

6

5

V_CC

NC

NM93C86A

ORG

V_SS

DO

DS800031-14

Top View

See Package Number

N08E and M08A

Pin Names

Description

CS

SK

Chip Select

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

DI

DO

V_SS

ORG

NC

Memory Organization Select

No Connect

V_CC

Positive Power Supply

Ordering Information

FM

93

C

XX

A

LZ

E

XX

Letter Description

Package

N

M8

8-Pin DIP

8-Pin SO8

Temp. Range

None

0 to 70°C

V

E

-40 to +125°C

-40 to +85°C

Voltage Operating Range

Blank

L

4.5V to 5.5V

2.7V to 5.5V

LZ

2.7V to 5.5V and

<1µA Standby Current

A

x8 or x16 Configuration

16K

Density

86

C

CMOS

Interface

93

FM

MICROWIRE

Fairchild Non-Volatile

Memory

2

www.fairchildsemi.com

FM93C86A Rev. A

Absolute Maximum Ratings (Note 1)

Operating Range

Ambient Storage Temperature

-65°C to +150°C

Ambient Operating Temperature

FM93C86A

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltage

with Respect to Ground

FM93C86AE

FM93C86AV

V_CC+ 1 to -0.3V

Lead Temperature

Power Supply (V_CC) Range

4.5V to 5.5V

(Soldering, 10 seconds)

+300°C

ESD Rating

2000V

DC and AC Electrical Characteristics 4.5V ≤ V_CC≤ 5.5V

Symbol

Parameter

Part Number

Conditions

Min

Max

Units

I_CCA

Operating Current

CS = V_IH, SK=1 MHz

1

mA

I_CCS

I_IL

Standby Current

Input Leakage

CS = 0V ORG = V_CCor NC

V_IN= 0V to V_CC(Note 2)

50

1

µA

-1

I_ILO

Input Leakage ORG Pin

ORG tied to V_CC

ORG tied to V_SS

(Note 3)

-1

-2.5

1

2.5

µA

I_OL

V_IL

Output Leakage

V_IN= 0V to V_CC

-1

-0.1

2

1

0.8

µA

V

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Output Low Voltage

Output High Voltage

SK Clock Frequency

SK High Time

V_IH

V_CC+1

0.4

V

V_OL1

V_OH1

V_OL2

V_OH2

f_SK

I_OL= 2.1 mA

I_OH= -400 µA

I_OL= 10 µA

I_OL= -10 µA

(Note 4)

V

2.4

V

0.2

1

V

V_CC- 0.2

0

V

MHz

ns

t_SKH

FM93C86A

FM93C86AE/V

250

300

t_SKL

t_SKS

SK Low Time

250

50

ns

SK Setup Time

SK must be at V_ILfor

t_SKSbefore CS goes

high

t_CS

Minimum CS Low Time

(Note 5)

250

ns

t_CSS

t_DH

CS Set-up Time

DO Hold Time

50

70

ns

t_DIS

DI Set-up Time

FM93C86A

FM93C86AE/V

100

200

ns

t_CSH

t_DIH

t_PD

t_SV

CS Hold Time

DI Hold Time

0

ns

20

Output Delay

500

ns

CS to Status Valid

t_DF

CS to DO in Hi-Z

Write Cycle Time

100

10

ns

t_WP

ms

3

www.fairchildsemi.com

FM93C86A Rev. A

Absolute Maximum Ratings (Note 1)

Operating Range

Ambient Operating Temperature

Ambient Storage Temperature

–65°C to +150°C

FM93C86AL/LZ

FM93C86ALE/LZE

FM93C86ALV/LZV

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltage

with Respect to Ground

+6.5V to -0.3V

Lead Temperature (Soldering, 10 sec.)

ESD Rating

+300°C

Power Supply (V_CC

)

2.7V to 5.5V

2000V

DC and AC Electrical Characteristics V_CC= 2.7V to 5.5V unless otherwise specified

Symbol

Parameter

Part Number

Conditions

Min.

Max.

Units

I_CCA

I_CCS

Operating Current

CS = V_IH, SK = 250KHz

CS = V_IL

1

mA

Standby Current

L

LZ

10

1

µA

I_IL

Input Leakage

V_IN= 0V to V_CC(Note 2)

1

µA

I_ILO

Input Leakage

ORG Pin

ORG tied to V_CC

ORG tied to V_SS(Note 3)

-1

-2.5

1

2.5

I_OL

Output Leakage

V_IN= 0V to V_CC

1

µA

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.1

0.8 V_CC

0.15 V_CC

V_CC+1

V

V_OL

V_OH

Output Low Voltage

Output High Voltage

I_OL= 10 µA

I_OH= -10 µA

0.1 V_CC

V

0.9 V_CC

f_SK

SK Clock Frequency

SK High Time

(Note 4)

0

1

250

KHz

µs

t_SKH

t_SKL

t_SKS

SK Low Time

1

µs

SK Setup Time

SK must be at V_ILfor

t_SKSbefore CS goes high

0.2

µs

t_CS

Minimum CS

Low Time

(Note 5)

1

µs

t_CSS

t_DH

CS Setup Time

DO Hold Time

DI Setup Time

CS Hold Time

DI Hold Time

0.2

70

0.4

0

µs

ns

µs

ns

µs

ms

t_DIS

t_CSH

t_DIH

t_PD

0.4

Output Delay

2

1

t_SV

CS to Status Valid

CS to DO in Hi-Z

Write Cycle Time

t_DF

CS = V_IL

0.4

15

t_WP

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or any

other conditions above those indicated in the operational sections of the specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Capacitance T_A= 25°C, f = 1 MHz

Symbol

Test

Typ Max Units

Note 2: Typical leakage values are in the 20 nA range.

Note 3: The ORG pin may draw > 1 µA when in the x8 mode ude to an internal pull-up transistor.

C_OUT

C_IN

Output Capacitance

Input Capacitance

5

pF

Note 4: The shortest allowable SK clock period = 1/f_SK(as shown under the f_SKf_SKparameter).

Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC

parameters stated in the datasheet. Within this SK period, both t_SKHand t_SKLlimits must be observed.

Therefore, it is not allowable to set 1/f_SK= t_SKHminimum+ t_SKLminimumfor shorter SK cycle time operation.

Note 5: CS (Chip Select) must be brought low (to V_IL) for an interval of t_CSin order to reset all

internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in

the opcode diagrams in the following pages.)

AC Test Conditions

V_CCRange

V_IL/V_IH

Input Levels

.03V/1.8V

V_IL/V_IH

Timing Level

V_OL/V_OH

Timing Level

0.8V/1.5V

I_OL/I_OH

2.7V ≤ V_CC≤ 5.5V

(Extended Voltage Levels)

1.0V

10µA

4.5V ≤ V_CC≤ 5.5V

0.4V/2.4V

1.0V/2.0V

0.4V/2.4V

2.1mA/-0.4mA

(TTL Levels)

Output Load: 1 TTL Gate (C_L= 100 pF)

4

www.fairchildsemi.com

FM93C86A Rev. A

Serial Clock (SK):

MICROWIRE I/O Pin Description

This pin is the clock input (rising edge active) for clocking in all

opcodesanddataontheDIpinandclockingoutalldataontheDO

pin.However,thispinhasnoeffectontheasynchronousprogram-

ming cycle (see the CS pin section) as the BUSY/READY status

is a function of the CS pin only.

Chip Select (CS):

This pin enables and disables the MICROWIRE device and

performs 2 general functions:

1. When in the low state, the MICROWIRE device is disabled

and the output tri-stated (high impedance). If this pin is

brought high (rising edge active), all internal registers are

reset and the device is enabled, allowing MICROWIRE

communication via DI/DO pins. To restate, the CS pin must

be held high during all device communication and opcode

functions. If the CS pin is brought low, all functions will be

disabled and reset when CS is brought high again. The

exception to this is when a programming cycle is initiated.

Again, all activity on the CS, DI and DO pins is ignored until

CS is brought high.

Data-In (DI):

All serial communication into the device is performed using this

input pin (rising edge active). In order to avoid false Start Bits, or

related issues, it is advised to keep the DI pin in the low state

unless actually clocking in data bits (Start Bit, Opcode, Address or

incoming data bits to be programmed). Please note that the first

'1' clocked into the device (after CS is brought high) is seen as a

Start Bit and the beginning of a serial command string, so caution

must be observed when bringing CS high.

2. When programming is in progress, the Data-Out pin will

display the programming status as either BUSY (DO low) or

READY (DO high) when CS is brought high. (Again, the

output will be tri-stated when CS is low.) To restate, during

programming, the CS pin may be brought high and low any

number of times to view the programming status without

affect the programming operation. Once programming is

completed (Output in READY state), the output is 'cleared'

(returned to normal tri-state condition) by clocking in a Start

Bit. After the Start Bit is clocked in, the output will return to a

tri-stated condition. When clocked in, this Start Bit can be the

first bit in a command string, or CS can be brought low again

to reset all internal circuits.

Data-Out (DO):

All serial communication out of the device, Read Data ( during

normal reads) as well as READY/BUSY status indication ( during

programming ) are performed using this output pin. Note that,

during READ operations, the EEPROM device starts to drive the

DO output pin "active" after the last address bit (A0) is clocked in.

Hence in applications where 3-wire configuration is required (

whereDIandDOpinsaretiedtogether)cautionmustbeobserved

for correct operation. Please refer AN-758 for further information.

Organization (ORG):

This pin controls the device architecture (8-bit data word vs. 16-bit

data word). If the ORG pin is brought to V_CC, the device is

configured with a 16-bit data word and if the ORG pin is brought

to V_SS(Ground), the device is configured with an 8-bit data word.

If the ORG pin is left floating, the device will default to a 16-bit data

word.

Unlike the lower density members of the Microwire product

family (FM93C06, FM93C46, FM93C56, FM93C66)

programming is not initiated by bringing CS low but initiated

as soon as the last bit of information (address bit or data bit

depending on the instruction type) is clocked in. Refer the

section on Programming for further detail.

Instruction Set for the FM93C86A

ORG

Memory

Logic

Configuration

# of Address Bits

0

1

2048 x 8

11 Bits

10 Bits

1024 x 16

5

www.fairchildsemi.com

FM93C86A Rev. A

1024 by 16-Bit Organization (FM93C86A when ORG = V_CCor NC)

Instruction SB Op Code Address

Data

Function

2 Bits

10

10 Bits

16 Bits

READ

EWEN

EWDS

ERASE

WRITE

ERAL

1

A9–A0

Read data stored in selected registers.

Enables programming modes.

00

11XXXXXXXX

00XXXXXXXX

A9–A0

00

Disables all programming modes.

Erases selected register.

11

01

A9–A0

D15–D0

Writes data pattern D15–D0 into selected register.

Erases all registers.

00

10XXXXXXXX

01XXXXXXXX

WRAL

00

Writes data pattern D15–D0 into all registers.

X = Don't care.

2048 by 8-Bit Organization (FM93C86A when ORG = GND)

Instruction SB Op Code Address

Data

Function

2 Bits

10

11 Bits

8 Bits

READ

EWEN

EWDS

ERASE

WRITE

ERAL

1

A10–A0

Read data stored in selected registers.

Enables programming modes.

00

11XXXXXXXXX

00XXXXXXXXX

A10–A0

00

Disables all programming modes.

Erases selected register.

11

01

A10–A0

D7–D0

Writes data pattern D7–D0 into selected register.

Erases all registers.

00

10XXXXXXXXX

01XXXXXXXXX

WRAL

00

Writes data pattern D7–D0 into all registers.

X = Don't care.

BUSYstatusofthedevice.DO=logical“0”indicatesthatprogram-

ming is still in progress and no other instruction can be executed.

DO = logical “1” indicates that the device is READY for another

instruction. If CS is forced “low” the DO pin will return to the high

impedance state. After the programming cycle has been com-

pleted and DO = logical “1”, the DO pin can be reset back to the

high impedance state by clocking a logical “1” into the DI pin. (This

is also performed with the start bit on all op codes, thus clocking

an instruction has the same effect.)

Functional Description

Programming

The programming cycle is automatically started after entering the

LAST bit of the programming instruction string (unlike other

Microwire family members which use the falling edge of CS to

initiate programming). This feature, counting the number of in-

struction bits, decreases the likelihood of inadvertent program-

ming and allows the programming to be cancelled before sending

out the last bit in the string (by bringing CS low).

Read (READ)

The READ instruction outputs serial data on the DO pin. After a

READ instruction is received, the instruction and address are

decoded, followed by data transfer from the selected memory

register into a serial-out shift register. A dummy bit (logical 0)

precedes the serial data output string. Output data changes are

initiatedbyalowtohightransitionofSKclockafterthelastaddress

bit (A0) is clocked in.

Programming Instruction Last Bit in String

WRITE

WRAL

ERASE

ERAL

D0

A0

Erase/Write Enable (EWEN)

Note that, in the ERASE/ERAL instructions, the A0 bit is the last

bit in the string and clocking in that bit will initiate programming. In

order to maintain compatibility, CS may be brought low after

clocking in the last bit, but it is not necessary.

When V_CCis applied to the part, it “powers up” in the Erase/Write

Disable (EWDS) state. Therefore, all programming modes must

be preceded by an Erase/Write Enable (EWEN) instruction. Once

an Erase/Write Enable instruction is executed, programming

remains enabled until an Erase/Write Disable (EWDS) instruction

is executed or V_CCis removed from the part.

In all programming modes the READY/BUSY status of the device

can be determined by polling the DO pin. After clocking in the last

bit of the instruction sequence and with the CS held “high”, the DO

pin will exit the high impedance state and indicate the READY/

6

www.fairchildsemi.com

FM93C86A Rev. A

instruction will be aborted. The self-timed programming cycle is

initiated on the rising edge of the SK clock as the last data bit (D0)

is clocked in. At this point, CS, SK and DI become don’t care

states. No separate ERASE cycle is required before a WRITE

instruction.

Functional Description (Continued)

Erase/Write Disable (EWDS)

To protect against accidental data overwrites, the Erase/Write

Disable (EWDS) instruction disables all programming modes and

should follow all programming operations. Execution of a READ

instruction is independent of both the EWEN and EWDS instruc-

tions.

As in the ERASE instruction, after starting a WRITE cycle, the DO

pin indicates the READY/BUSY status of the chip if CS is held

“high”. DO = logical “0” indicates that programming is still in

progress. DO = logical “1” indicates that the register, at the

address specified in the instruction, has been written and that the

part is ready for another instruction.

Erase (ERASE)

The ERASE instruction will program all bits in the specified

register to the logical “1” state. The self-timed programming cycle

is initiated on the rising edge of the SK clock as the last address

bit(A0)isclockedin.AtthispointCS,SKandDIbecomedon’tcare

states. After starting an Erase cycle the DO pin indicates the

READY/BUSY status of the chip if CS is held “high”. DO = logical

“0” indicates that programming is still in progress. DO = logical “1”

indicates that the register, at the address specified in the instruc-

tion, has been erased.

Erase All (ERAL)

The ERAL instruction will simultaneously program all registers in

the memory array to the logical “1” state.

Write All (WRAL)

The WRAL instruction will simultaneously program all registers

with the data pattern specified in the instruction.

Write (WRITE)

The WRITE instruction is followed by 16 bits of data (or 8 bits of

data when using the FM93C86A in the x8 organization) to be

written into the specified address. Note that if the CS is brought

“low” before clocking in all of the data bits, then the WRITE

Timing Diagrams for the FM93C86A

Synchronous Data Timing

V

IH

CS

SK

V

t

IL

CSS

t

CSH

SKH

SKL

t

SKS

V

IH

V

IL

t

DIH

DIS

V

IH

DI

V

IL

t

PD

t

DF

t

DH

V

OH

DO (READ)

V

OL

t

SV

t

DF

DH

V

OH

DO (PROGRAM)

STATUS VALID

V

OL

DS800031-3

7

www.fairchildsemi.com

FM93C86A Rev. A

Timing Diagrams for the FM93C86A (Continued)

Key for Timing Diagrams

Organization of Address and Data Fields for the FM93C86A

ORG

V_CCor NC

V_SS

Organization

1024 x 16

A_N

A9

D_N

D15

D7

2048 x 8

A10

READ

CS

SK

DI

t

CS

. . .

1

0

AN

A

0

. . .

DO

0

D

0

N

DS800031-4

DS800031-5

DS800031-6

EWEN

DO = HI-Z

t

CS

SK

DI

. . .

X

1

0

1

ORG = V , 4 X’S

CC

ORG = V , 5 X’S

SS

EWDS

DO = HI-Z

t_CS

CS

SK

DI

. . .

X

1

0

ORG = V , 4 X’S

CC

ORG = V , 5 X’S

SS

ERASE

t_CS

CS

SK

Standby

DI

. . .

A₀

A_N

1

HI-Z

Busy

Ready

DO

t_WP

DS800031-7

8

www.fairchildsemi.com

FM93C86A Rev. A

Timing Diagrams for the FM93C86A (Continued)

WRITE

t_CS

CS

SK

. . .

1

0

1

A_N

A₀D_N

D₀

DI

Busy

Ready

DO

t_WP

DS800031-8

ERAL

t_CS

CS

STANDBY

SK

DI

. . .

1

0

1

0

X

ORG = V_CC, 4 X's

ORG = V_SS, 5 X's

READY

DO

BUSY

READY STATUS SIGNAL RESETS

TO HI-Z AFTER CLOCKING IN

ONE SK CYCLE WITH DI = 1

t_WP

DS800031-9

WRAL

t_CS

CS

SK

DI

STANDBY

. . .

D₀

1

0

1

X

D_N

ORG = V_CC, 4 X's

ORG = V_SS, 5 X's

READY

BUSY

DO

READY STATUS SIGNAL RESETS

TO HI-Z AFTER CLOCKING IN

ONE SK CYCLE WITH DI = 1

t_WP

DS800031-10

9

www.fairchildsemi.com

FM93C86A Rev. A

Physical Dimensions inches (millimeters) unless otherwise noted

0.189 - 0.197

(4.800 - 5.004)

8

7

6

5

0.228 - 0.244

(5.791 - 6.198)

1

2

3

4

Lead #1

IDENT

0.150 - 0.157

(3.810 - 3.988)

0.053 - 0.069

(1.346 - 1.753)

0.010 - 0.020

(0.254 - 0.508)

0.004 - 0.010

(0.102 - 0.254)

x 45°

8° Max, Typ.

All leads

Seating

Plane

0.04

0.0075 - 0.0098

(0.190 - 0.249)

Typ. All Leads

(0.102)

All lead tips

0.014

(0.356)

0.016 - 0.050

(0.406 - 1.270)

Typ. All Leads

0.050

(1.270)

Typ

0.014 - 0.020

(0.356 - 0.508)

Typ.

Molded Small Outline Package (M8)

Package Number M08A

10

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FM93C86A Rev. A

Physical Dimensions inches (millimeters) unless otherwise noted

0.373 - 0.400

(9.474 - 10.16)

0.090

(2.286)

8

7

0.032 0.005

(0.813 0.127)

RAD

8

7

6

5

4

0.092

(2.337)

DIA

0.250 - 0.005

(6.35 0.127)

Pin #1

IDENT

+

Pin #1 IDENT

1

Option 1

1

2

3

Option 2

0.280

MIN

0.040

(1.016)

Typ.

(7.112)

0.030

0.145 - 0.200

(3.683 - 5.080)

0.039

(0.991)

MAX

(0.762)

0.300 - 0.320

(7.62 - 8.128)

20° 1°

0.130 0.005

(3.302 0.127)

0.125 - 0.140

95° 5°

(3.175 - 3.556)

0.065

(1.651)

0.125

(3.175)

DIA

0.020

90° 4°

Typ

0.009 - 0.015

(0.229 - 0.381)

(0.508)

Min

0.018 0.003

(0.457 0.076)

NOM

+0.040

-0.015

0.325

0.100 0.010

+1.016

-0.381

8.255

(2.540 0.254)

0.045 0.015

(1.143 0.381)

0.060

(1.524)

0.050

(1.270)

Molded Dual-in-Line Package (N)

Package Number N08E

Life Support Policy

Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written

approval of the President of Fairchild Semiconductor Corporation. As used herein:

1. Life support devices or systems are devices or systems which,

(a)areintendedforsurgicalimplantintothebody,or(b)support

or sustain life, and whose failure to perform, when properly

used in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in a significant

injury to the user.

2. A critical component is any component of a life support device

or system whose failure to perform can be reasonably ex-

pected to cause the failure of the life support device or system,

or to affect its safety or effectiveness.

Fairchild Semiconductor

Americas

Fairchild Semiconductor

Europe

Fairchild Semiconductor

Hong Kong

Fairchild Semiconductor

Japan Ltd.

Customer Response Center

Tel. 1-888-522-5372

Fax:

Tel:

+44 (0) 1793-856858

8/F, Room 808, Empire Centre

68 Mody Road, Tsimshatsui East

Kowloon. Hong Kong

Tel; +852-2722-8338

Fax: +852-2722-8383

4F, Natsume Bldg.

Deutsch

English

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+49 (0) 8141-6102-0

+44 (0) 1793-856856

+33 (0) 1-6930-3696

+39 (0) 2-249111-1

2-18-6, Yushima, Bunkyo-ku

Tokyo, 113-0034 Japan

Tel: 81-3-3818-8840

Fax: 81-3-3818-8841

11

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FM93C86A Rev. A

February 2000

FM93CS06

(MICROWIRE™ Bus Interface) 256-Bit Serial EEPROM

with Data Protect and Sequential Read

General Description

Features

FM93CS06 is a 256-bit CMOS non-volatile EEPROM organized

as 16 x 16-bit array. This device features MICROWIRE interface

which is a 4-wire serial bus with chipselect (CS), clock (SK), data

input (DI) and data output (DO) signals. This interface is compat-

ible to many of standard Microcontrollers and Microprocessors.

FM93CS06 offers programmable write protection to the memory

array using a special register called Protect Register. Selected

memory locations can be protected against write by programming

this Protect Register with the address of the first memory location

to be protected (all locations greater than or equal to this first

addressarethenprotectedfromfurtherchange). Additionally, this

address can be “permanently locked” into the device, making all

future attempts to change data impossible. In addition this device

features “sequential read”, by which, entire memory can be read

in one cycle instead of multiple single byte read cycles. There are

10 instructions implemented on the FM93CS06, 5 of which are for

memory operations and the remaining 5 are for Protect Register

operations. This device is fabricated using Fairchild Semiconduc-

torfloating-gateCMOSprocessforhighreliability,highendurance

and low power consumption.

I Wide V_CC2.7V - 5.5V

I Programmable write protection

I Sequential register read

I Typical active current of 200µA

10µA standby current typical

1µA standby current typical (L)

0.1µA standby current typical (LZ)

I No Erase instruction required before Write instruction

I Self timed write cycle

I Device status during programming cycles

I 40 year data retention

I Endurance: 1,000,000 data changes

I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP

“LZ” and “L” versions of FM93CS06 offer very low standby current

makingthemsuitableforlowpowerapplications.Thisdeviceisoffered

in both SO and TSSOP packages for small space considerations.

Functional Diagram

V_CC

CS

SK

INSTRUCTION

DECODER

CONTROL LOGIC

AND CLOCK

PRE

PE

INSTRUCTION

REGISTER

DI

GENERATORS

COMPARATOR

AND

WRITE ENABLE

HIGH VOLTAGE

GENERATOR

AND

PROGRAM

TIMER

ADDRESS

REGISTER

PROTECT

REGISTER

DECODER

EEPROM ARRAY

16

READ/WRITE AMPS

16

V_SS

DATA IN/OUT REGISTER

16 BITS

DO

DATA OUT BUFFER

1

FM93CS06 Rev. A

www.fairchildsemi.com

Connection Diagram

Dual-In-Line Package (N)

8–Pin SO (M8) and 8–Pin TSSOP (MT8)

1

2

3

4

8

7

6

5

CS

SK

DI

V_CC

PRE

PE

DO

GND

Top View

Package Number

N08E, M08A and MTC08

Pin Names

CS

SK

Chip Select

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

DI

DO

GND

PE

Program Enable

Protect Register Enable

Power Supply

PRE

V_CC

Ordering Information

FM

93

CS XX LZ

E

XXX

Letter Description

Package

N

8-pin DIP

M8

MT8

8-pin SO

8-pin TSSOP

Temp. Range

None

0 to 70°C

V

E

-40 to +125°C

-40 to +85°C

Voltage Operating Range

Blank

L

4.5V to 5.5V

2.7V to 5.5V

LZ

2.7V to 5.5V and

<1µA Standby Current

Density

06

256 bits

C

CMOS

CS

Data protect and sequential

read

Interface

93

MICROWIRE

Fairchild Memory Prefix

2

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FM93CS06 Rev. A

Absolute Maximum Ratings (Note 1)

Operating Conditions

Ambient Storage Temperature

-65°C to +150°C

Ambient Operating Temperature

FM93CS06

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltages

with Respect to Ground

+6.5V to -0.3V

FM93CS06E

FM93CS06V

Lead Temperature

(Soldering, 10 sec.)

+300°C

Power Supply (V_CC

)

4.5V to 5.5V

ESD rating

2000V

DC and AC Electrical Characteristics V_CC= 4.5V to 5.5V unless otherwise specified

SymbolParameter

Conditions

Min

Max

Units

I_CCA

Operating Current

CS = V_IH, SK=1.0 MHz

1

mA

I_CCS

Standby Current

CS = V_IL

50

-1

µA

I_IL

I_OL

Input Leakage

Output Leakage

V_IN= 0V to V_CC

(Note 2)

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.1

2

0.8

V_CC+1

V

V_OL1

V_OH1

Output Low Voltage

Output High Voltage

I_OL= 2.1 mA

I_OH= -400 µA

I_OL= 10 µA

I_OH= -10 µA

(Note 3)

0.4

0.2

1

2.4

V_OL2

V_OH2

Output Low Voltage

Output High Voltage

V_CC- 0.2

f_SK

SK Clock Frequency

SK High Time

MHz

ns

t_SKH

0°C to +70°C

-40°C to +125°C

250

300

t_SKL

t_SKS

SK Low Time

250

50

ns

SK Setup Time

t_CS

Minimum CS Low Time

(Note 4)

250

ns

t_CSS

t_PRES

t_DH

CS Setup Time

PRE Setup Time

DO Hold Time

PE Setup Time

DI Setup Time

100

50

ns

70

t_PES

t_DIS

50

100

t_CSH

t_PEH

t_PREH

t_DIH

CS Hold Time

PE Hold Time

PRE Hold Time

DI Hold Time

Output Delay

0

ns

250

50

20

t_PD

500

t_SV

CS to Status Valid

ns

t_DF

CS to DO in Hi-Z

Write Cycle Time

CS = V_IL

100

10

ns

t_WP

ms

3

www.fairchildsemi.com

FM93CS06 Rev. A

Absolute Maximum Ratings (Note 1)

Operating Conditions

Ambient Storage Temperature

-65°C to +150°C

Ambient Operating Temperature

FM93CS06L/LZ

0°C to +70°C

-40°C to +85°C

-40°C to +125°C

All Input or Output Voltages

with Respect to Ground

+6.5V to -0.3V

FM93CS06LE/LZE

FM93CS06LV/LZV

Lead Temperature

(Soldering, 10 sec.)

+300°C

Power Supply (V_CC

)

2.7V to 5.5V

ESD rating

2000V

DC and AC Electrical Characteristics V_CC= 2.7V to 5.5V unless otherwise specified

SymbolParameter

Conditions

Min

Max

Units

I_CCA

Operating Current

CS = V_IH, SK=1.0 MHz

1

mA

I_CCS

Standby Current

L

CS = V_IL

10

1

µA

LZ (2.7V to 4.5V)

I_IL

I_OL

Input Leakage

Output Leakage

V_IN= 0V to V_CC

(Note 2)

1

µA

V_IL

V_IH

Input Low Voltage

Input High Voltage

-0.1

0.8V_CC

0.15V_CC

V_CC+1

V

V_OL

V_OH

Output Low Voltage

Output High Voltage

I_OL= 10µA

I_OH= -10µA

0.1V_CC

V

0.9V_CC

f_SK

SK Clock Frequency

SK High Time

(Note 3)

0

1

250

KHz

µs

t_SKH

t_SKL

t_SKS

SK Low Time

1

SK Setup Time

0.2

µs

t_CS

Minimum CS Low Time

(Note 4)

1

µs

t_CSS

t_PRES

t_DH

CS Setup Time

PRE Setup Time

DO Hold Time

PE Setup Time

DI Setup Time

0.2

50

70

50

0.4

µs

ns

µs

t_PES

t_DIS

t_CSH

t_PEH

t_PREH

t_DIH

CS Hold Time

PE Hold Time

PRE Hold Time

DI Hold Time

Output Delay

0

ns

µs

250

50

0.4

t_PD

2

1

t_SV

CS to Status Valid

µs

t_DF

CS to DO in Hi-Z

Write Cycle Time

CS = V_IL

0.4

15

µs

ms

t_WP

Note 1: Stressabovethoselistedunder“AbsoluteMaximumRatings”maycausepermanentdamage

to the device. This is a stress rating only and functional operation of the device at these or any other

conditionsabovethoseindicatedintheoperationalsectionsofthespecificationisnotimplied. Exposure

to absolute maximum rating conditions for extended periods may affect device reliability.

Capacitance T_A= 25°C, f = 1 MHz (Note 5)

Note 2: Typical leakage values are in the 20nA range.

SymbolTest

Typ Max Units

Note 3: TheshortestallowableSKclockperiod=1/f_SK(asshownunderthef_SKparameter). Maximum

SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated

in the datasheet. Within this SK period, both t_SKHand t_SKLlimits must be observed. Therefore, it is not

allowable to set 1/f_SK= t_SKHminimum+ t_SKLminimumfor shorter SK cycle time operation.

C_OUT

C_IN

Output Capacitance

Input Capacitance

5

pF

5

Note 4: CS (Chip Select) must be brought low (to V_IL) for an interval of t_CSin order to reset all internal

device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode

diagram on the following page.)

Note 5: This parameter is periodically sampled and not 100% tested.

AC Test Conditions

V_CCRange

V_IL/V_IH

Input Levels

0.3V/1.8V

V_IL/V_IH

V_OL/V_OH

Timing Level

0.8V/1.5V

I_OL/I_OH

Timing Level

2.7V ≤ V_CC≤ 5.5V

1.0V

10µA

(Extended Voltage Levels)

4.5V ≤ V_CC≤ 5.5V

0.4V/2.4V

1.0V/2.0V

0.4V/2.4V

2.1mA/-0.4mA

(TTL Levels)

Output Load: 1 TTL Gate (C_L= 100 pF)

4

www.fairchildsemi.com

FM93CS06 Rev. A

Program Enable (PE)

Pin Description

This is an active high input pin to the device and is used to enable

operations, that are write in nature, to the memory array and to the

Protect register. When this pin is held high, operations that are

“write” in nature are enabled. When this pin is held low, operations

that are “write” in nature are disabled. This pin operates in

conjunctionwithPREpin. ReferTable1forfunctionalmatrixofthis

pin for various operations.

Chip Select (CS)

ThisisanactivehighinputpintoFM93CS06EEPROM(thedevice)

and is generated by a master that is controlling the device. A high

level on this pin selects the device and a low level deselects the

device. All serial communications with the device is enabled only

when this pin is held high. However this pin cannot be permanently

tied high, as a rising edge on this signal is required to reset the

internal state-machine to accept a new cycle and a falling edge to

initiateaninternalprogrammingafterawritecycle.Allactivityonthe

SK, DI and DO pins are ignored while CS is held low.

Microwire Interface

AtypicalcommunicationontheMicrowirebusismadethroughthe

CS, SK, DI and DO signals. To facilitate various operations on the

Memory array and on the Protect Register, a set of 10 instructions

are implemented on FM93CS06. The format of each instruction is

listed in Table 1.

Serial Clock (SK)

Thisisaninputpintothedeviceandisgeneratedbythemasterthat

is controlling the device. This is a clock signal that synchronizes the

communicationbetweenamasterandthedevice. Allinputinforma-

tion(DI)tothedeviceislatchedontherisingedgeofthisclockinput,

whileoutputdata(DO)fromthedeviceisdrivenfromtherisingedge

of this clock input. This pin is gated by CS signal.

Instruction

Each of the above 10 instructions is explained under individual

instruction descriptions.

Start Bit

Serial Input (DI)

This is a 1-bit field and is the first bit that is clocked into the device

whenaMicrowirecyclestarts.Thisbithastobe“1”foravalidcycle

to begin. Any number of preceding “0” can be clocked into the

device before clocking a “1”.

This is an input pin to the device and is generated by the master

that is controlling the device. The master transfers Input informa-

tion (Start bit, Opcode bits, Array addresses and Data) serially via

this pin into the device. This Input information is latched on the

rising edge of the SCK. This pin is gated by CS signal.

Opcode

Serial Output (DO)

This is a 2-bit field and should immediately follow the start bit.

These two bits (along with PRE, PE signals and 2 MSB of address

field) select a particular instruction to be executed.

This is an output pin from the device and is used to transfer Output

data via this pin to the controlling master. Output data is serially

shifted out on this pin from the rising edge of the SCK. This pin is

active only when the device is selected.

Address Field

This is a 6-bit field and should immediately follow the Opcode bits.

In FM93CS06, only the LSB 4 bits are used for address decoding

during READ, WRITE and PRWRITE instructions. During these

instructions (READ, WRITE and PRWRITE), the MSB 2 bits are

"don't care" (can be 0 or 1). During all other instructions (with the

exception of PRREAD), the MSB 2 bits are used to decode

instruction (along with Opcode bits, PRE and PE signals).

Protect Register Enable (PRE)

This is an active high input pin to the device and is used to

distinguish operations to memory array and operations to Protect

Register. When this pin is held low, operations to the memory

array are enabled. When this pin is held high, operations to the

Protect Register are enabled. This pin operates in conjunction

with PE pin. Refer Table1 for functional matrix of this pin for

various operations.

Data Field

This is a 16-bit field and should immediately follow the Address

bits. Only the WRITE and WRALL instructions require this field.

D15 (MSB) is clocked first and D0 (LSB) is clocked last (both

during writes as well as reads).

TABLE 1. Instruction set

Instruction

READ

Start Bit

Opcode Field

Address Field

Data Field PRE Pin

PE Pin

1

10

00

01

00

10

00

11

01

00

X

1

X

0

X

1

X

0

X

1

X

1

0

X

1

X

0

A3 A2 A1 A0

0

X

1

X

1

WEN

X

WRITE

WRALL

WDS

A3 A2 A1 A0

D15-D0

0

1

X

1

X

1

X

1

X

1

PRREAD

PREN

PRCLEAR

PRWRITE

PRDS

A3 A2 A1 A0

0

5

www.fairchildsemi.com

FM93CS06 Rev. A

the part. Input information (Start bit, Opcode and Address) for this

WEN instruction should be issued as listed under Table1. The

device becomes write-enabled at the end of this cycle when the

CS signal is brought low. The PRE pin should be held low during

thiscycle.ExecutionofaREADinstructionisindependentofWEN

instruction. Refer Write Enable cycle diagram.

Functional Description

A typical Microwire cycle starts by first selecting the device

(bringing the CS signal high). Once the device is selected, a valid

Start bit (“1”) should be issued to properly recognize the cycle.

Following this, the 2-bit opcode of appropriate instruction should

be issued. After the opcode bits, the 6-bit address information

should be issued. For certain instructions, some (or all) of these

6 bits are don’t care values (can be “0” or “1”), but they should still

be issued. Following the address information, depending on the

instruction (WRITE and WRALL), 16-Bit data is issued. Other-

wise, depending on the instruction (READ and PRREAD), the

device starts to drive the output data on the DO line. Other

instructions perform certain control functions and do not deal with

data bits. The Microwire cycle ends when the CS signal is brought

low. However during certain instructions, falling edge of the CS

signal initiates an internal cycle (Programming), and the device

remains busy till the completion of the internal cycle. Each of the

10 instructions is explained in detail in the following sections.

3) Write (WRITE)

WRITE instruction allows write operation to a specified location in

the memory with a specified data. This instruction is valid only

when the following are true:

I Device is write-enabled (Refer WEN instruction)

I Address of the write location is not write-protected

I PE pin is held high during this cycle

I PRE pin should be held low during this cycle

Input information (Start bit, Opcode, Address and Data) for this

WRITE instruction should be issued as listed under Table1. After

inputtingthelastbitofdata(D0bit), CSsignalmustbebroughtlow

before the next rising edge of the SK clock. This falling edge of the

CS initiates the self-timed programming cycle. It takes t_WPtime

(Refer appropriate DC and AC Electrical Characteristics table) for

the internal programming cycle to finish. During this time, the

device remains busy and is not ready for another instruction.

Memory Instructions

Following five instructions, READ, WEN, WRITE, WRALL and

WDS are specific to operations intended for memory array. The

PRE pin should be held low during these instructions.

1) Read and Sequential Read (READ)

The status of the internal programming cycle can be polled at any

time by bringing the CS signal high again, after t_CSinterval. When

CS signal is high, the DO pin indicates the READY/BUSY status

of the chip. DO = logical 0 indicates that the programming is still

in progress. DO = logical 1 indicates that the programming is

finished and the device is ready for another instruction. It is not

required to provide the SK clock during this status polling. While

the device is busy, it is recommended that no new instruction be

issued. Refer Write cycle diagram.

READ instruction allows data to be read from a selected location

in the memory array. Input information (Start bit, Opcode and

Address) for this instruction should be issued as listed under

Table1. Upon receiving a valid input information, decoding of the

opcode and the address is made, followed by data transfer from

the selected memory location into a 16-bit serial-out shift register.

This 16-bit data is then shifted out on the DO pin. D15 bit (MSB)

is shifted out first and D0 bit (LSB) is shifted out last. A dummy-bit

(logical 0) precedes this 16-bit data output string. Output data

changes are initiated on the rising edge of the SK clock. After

reading the 16-bit data, the CS signal can be brought low to end

the Read cycle. The PRE pin should be held low during this cycle.

Refer Read cycle diagram.

It is also recommended to follow this instruction (after the device

becomes READY) with a Write Disable (WDS) instruction to

safeguarddataagainstcorruptionduetospuriousnoise,inadvert-

ent writes etc.

4) Write All (WRALL)

This device also offers “sequential memory read” operation to

allowreadingofdatafromtheadditionalmemorylocationsinstead

ofjustonelocation.Itisstartedinthesamemannerasnormalread

but the cycle is continued to read further data (instead of terminat-

ing after reading the first 16-bit data). After providing 16-bit data,

the device automatically increments the address pointer to the

next location and continues to provide the data from that location.

Any number of locations can be read out in this manner, however,

after reading out from the last location, the address pointer points

back to the first location. If the cycle is continued further, data will

be read from this first location onward. In this mode of read, the

dummy-bit is present only when the very first data is read (like

normal read cycle) and is not present on subsequent data reads.

The PRE pin should be held low during this cycle. Refer Sequen-

tial Read cycle diagram.

Write all (WRALL) instruction is similar to the Write instruction

except that WRALL instruction will simultaneously program all

memorylocationswiththedatapatternspecifiedintheinstruction.

This instruction is valid only when the following are true:

I Protect Register has been cleared (Refer PRCLEAR

instruction)

I Device is write-enabled (Refer WEN instruction)

I PE pin is held high during this cycle

I PRE pin should be held low during this cycle

Input information (Start bit, Opcode, Address and Data) for this

WRALL instruction should be issued as listed under Table1. After

inputtingthelastbitofdata(D0bit), CSsignalmustbebroughtlow

before the next rising edge of the SK clock. This falling edge of the

CS initiates the self-timed programming cycle. It takes t_WPtime

(Refer appropriate DC and AC Electrical Characteristics table) for

the internal programming cycle to finish. During this time, the

device remains busy and is not ready for another instruction.

Status of the internal programming can be polled as described

under WRITE instruction description. While the device is busy, it

is recommended that no new instruction be issued. ReferWrite All

cycle diagram.

2) Write Enable (WEN)

When V_CCis applied to the part, it “powers up” in the Write Disable

(WDS) state. Therefore, all programming operations (for both

memory array and Protect Register) must be preceded by a Write

Enable (WEN) instruction. Once a Write Enable instruction is

executed, programming remains enabled until a Write Disable

(WDS) instruction is executed or V_CCis completely removed from

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FM93CS06 Rev. A

content of the Protect Register with a pattern of all 1s. However,

in this case, WRITE operation to the last memory address

(0x001111) is still enabled. PRCLEAR instruction is enabled

(valid) only when the following are true:

5) Write Disable (WDS)

Write Disable (WDS) instruction disables all programming opera-

tions and is recommended to follow all programming operations.

Executing this instruction after a valid write instruction would

protect against accidental data disturb due to spurious noise,

glitches,inadvertentwritesetc.Inputinformation(Startbit,Opcode

and Address) for this WDS instruction should be issued as listed

under Table1. The device becomes write-disabled at the end of

this cycle when the CS signal is brought low. Execution of a READ

instructionisindependentofWDSinstruction. ReferWriteDisable

cycle diagram.

I PREN instruction was executed immediately prior to

PRCLEAR instruction

I PE pin is held high during this cycle

I PRE pin is held high during this cycle

Inputinformation(Startbit,OpcodeandAddress)forthisPRCLEAR

instructionshouldbeissuedaslistedunderTable1. Afterinputting

the last bit of address (A0 bit), CS signal must be brought low

before the next rising edge of the SK clock. This falling edge of the

CS initiates the self-timed clear cycle. It takes t_WPtime (Refer

appropriate DC and AC Electrical Characteristics table) for the

internal clear cycle to finish. During this time, the device remains

busyandisnotreadyforanotherinstruction. Statusoftheinternal

programmingcanbepolledasdescribedunderWRITEinstruction

description. While the device is busy, it is recommended that no

new instruction be issued. Refer Protect Register Clear cycle

diagram.

Protect Register Instructions

Following five instructions, PRREAD, PREN, PRCLEAR,

PRWRITE and PRDS are specific to operations intended for

Protect Register. The PRE pin should be held high during these

instructions.

1) Protect Register Read (PRREAD)

This instruction reads the content of the internal Protect Register.

Content of this register is 6-bit wide and is the starting address of

the “write-protected” section of the memory array. All memory

locationsgreaterthanorequaltothisaddressarewrite-protected.

Inputinformation(Startbit,OpcodeandAddress)forthisPRREAD

instruction should be issued as listed under Table1. Upon receiv-

ing a valid input information, decoding of the opcode and the

address is made, followed by data transfer (address information)

from the Protect Register. This 6-bit data is then shifted out on the

DO pin with the MSB first and the LSB last. Like the READ

instruction a dummy-bit (logical 0) precedes this 6-bit data output

string. Output data changes are initiated on the rising edge of the

SK clock. After reading the 6-bit data, the CS signal can be

brought low to end the PRREAD cycle. The PRE pin should be

held high during this cycle. Refer Protect Register Read cycle

diagram.

4) Protect Register Write (PRWRITE)

Thisinstructionisusedtowritethestartingaddressofthememory

section to be write-protected into the Protect register. After the

execution of PRWRITE instruction, all memory locations greater

than or equal to this address are write-protected. PRWRITE

instruction is enabled (valid) only the following are true:

I PRCLEAR instruction was executed first (to clear the Protect

Register)

I PREN instruction was executed immediately prior to

PRWRITE instruction

I PE pin is held high during this cycle

I PRE pin is held high during this cycle

Inputinformation(Startbit,OpcodeandAddress)forthisPRWRITE