FMS988AKAC140 [ETC]
Signal Conditioner ; 信号调理\n型号: | FMS988AKAC140 |
厂家: | ETC |
描述: | Signal Conditioner
|
文件: | 总29页 (文件大小:374K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
www.fairchildsemi.com
FMS9884A
Graphics Digitizer
3x8-Bit, 108/140 Ms/s Triple Video A/D Converter with Clamps
PLL. Output data is released through either one port at full
Features
rate or both ports, each running at half-rate. Setup and control
is via registers, accessible through an SMBus/I2C compatible
• 3-channels
• 100/140 Ms/s conversion rate
serial port.
• Programmable Clamps
• 500ps PLL clock jitter
• Adjustable Gain and offset
Input amplitude range is 500–1000mV with either DC or AC
coupling. Lower reference of AC coupled inputs is estab-
lished with input clamps that are either internally generated
or externally provided.
• Internal Reference Voltage
• I2C/SMBus compatible Serial Port
• Pin Compatible with AD9884A
Common to the three channels are clamp pulses, a bandgap
reference voltage and clocks derived from a PLL or an external
source. Digital data levels are 2.5–3.3 volt CMOS compliant.
Applications
• Flat panel displays and projectors
• RGB Graphics Processing
Power can be derived from a single +3.3 Volt power supply.
Package is a 128-lead MQFP. Performance specifications are
guaranteed over 0°C to 70°C range.
Description
As a fully integrated analog interface, the FMS9884A can digi-
tize RGB graphics with resolutions up to 1280 x 1024/75Hz
refresh or 1600 x 1200/85Hz using alternate pixel sampling.
ADC sampling clock can be derived from either an external
source or incoming horizontal sync signal using the internal
Product Number
FMS988AKAC100
FMS988AKAC140
Speed
108 Ms/s
140 Ms/s
Block Diagram
RPD7-0
DRA7-0
A/D
Converter
Gain &
Offset
Clamp
Clamp
Clamp
RIN
Switch
Switch
Switch
DRB7-0
GPD7-0
BPD7-0
DGA7-0
DGB7-0
Gain &
Offset
A/D
Converter
GIN
DBA7-0
DBB7-0
Gain &
Offset
A/D
Converter
BIN
Reference
VREFIN
VREFOUT
SCK
CLAMP
INVSCK
XCK
ICLAMP
DCK
DCK
HSOUT
Timing
Generator
HS
PXCK
HSIN
COAST
LPF
PLL
SDA
SCL
A0
A1
SYNC
STRIPPER
ACSIN
Control
DCSOUT
PWRDN
REV. 1.0.2 8/11/00
PRODUCT SPECIFICATION
FMS9884A
1. Single 8-bit port at pixel rates up to 140Ms/s.
Architectural Overview
2. Dual 8-bit ports, each running at half the conversion
rate. Maximum rate is 88Ms/s per port. Data streams
may be parallel or interleaved.
Three separate digitizer channels are controlled by common
timing signals derived from the Timing Generator. A/D clock
signals can be derived from either a PLL or an external clock
XCK. With the PLL selected, A/D clocks track the incoming
horizontal sync signal connected to the HSIN input. Setup is
controlled by registers that are accessible through the serial
interface.
Timing and Control
Timing and Control logic encompasses the Timing Generator,
PLL and Serial Interface.
Timing Generator
Conversion Channels
All internal clock and synchronization signals are generated
by the Timing Generator. Master Clock source is either the
PLL or the external clock input, XCK. Bit XCKSEL selects
the Master Clock source. Two clocks are generated.
Typical RGB graphics signals, RIN, GIN, BIN are ground ref-
erenced with 700mV amplitude. If a sync signal is embedded
then the usual format is sync on green with the sync tip at
ground, the black level elevated to 300mV and peak green at
1000mV.
Sampling clock, SCK is supplied to all three A/D converters.
Phase of SCK can be adjusted in 32 11.25 degree phase
increments using the 5-bit PHASE register.
AC coupled video signals must be level shifted to establish
the lower level of the conversion range by clamping to the
black level of the back porch (see Figure 1). Clamp pulses
are derived from internal Timing and Control logic or from
the external CLAMP input.
DCK is the output data clock. DCK and DCK are supplied as
outputs for synchronizing data transfer from the digitizer
outputs.
Horizontal sync applied to the input, HSIN is propagated by
the Timing and Control to the HSOUT output with a delay
that aligns leading and trailing edges with the output data.
RIN, GIN, BIN
ICLAMP
Phase Locked Loop
With a horizontal sync signal connected to the HSIN input
pin, the PLL generates a high frequency internal clock signal,
PXCK that is fed to the Timing and Control logic. Frequency
of PXCK is set by the register programmable PLL divide
ratio, PLLN.
Figure 1. Clamping to the back-porch
Gain and Offset
A/D conversion range can be matched to the amplitude of the
incoming video signal by programming Gain Registers GR,
GG and GB, which vary sensitivity (LSB/volt) over a 2:1
range. Incoming video signal amplitudes varying from 0.5 to
1.0 volt can be accommodated.
COAST is an input that disables the PLL lock to the horizontal
sync input, HSIN. If HSIN is to be disregarded for a period
such as the vertical sync interval, COAST allows the VCO
frequency to be maintained. Omission of horizontal sync
pulses during the vertical interval can cause tearing at the top
of a picture, if COAST is not used.
Input offset voltage of each converter is programmable in 1
LSB steps through the 6-bit OSR, OSG and OSB registers.
Range of adjustment is equivalent to –31 to +32 LSB.
Two pixels per clock mode is set by programming the PLL
to half the pixel rate. By toggling the INVCK pin between
frames, even and odd pixels can be read on alternate frames.
A/D Converter
Each A/D converter digitizes the analog input into 8-bit data
words. Latency is 5–61/2 clock cycles, depending upon the
data out format.
Serial Interface
Registers are accessed through an I2C/SMBus compatible
serial port. Four serial addresses are pin selectable.
VREFIN is the source of reference voltage for the three A/D
converters. VREFIN can be connected to either the internal
bandgap voltage, VREFOUT or an external voltage.
Output Data Configuration
Output data number format for each channel is binary: 00 cor-
responds to the lowest input; FF corresponds to the highest
input. Data can be released in either of two timing formats:
2
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
Pin Assignments (128-Lead MQFP (KA) Package)
102
65
103
64
128
39
1
38
No.
1
Name
NC
No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Name
VDDP
VDDP
GND
NC
No.
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Name
DBA7
DBA6
DBA5
DBA4
DBA3
DBA2
DBA1
DBA0
GND
No.
Name
DRB5
DRB4
DRB3
DRB2
DRB1
DRB0
GND
97
2
NC
98
3
NC
99
4
VDDA
GND
GND
RIN
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
5
NC
6
NC
7
GND
HSIN
COAST
GND
VDDP
XCK
8
VDDA
GND
VDDA
VDDA
GND
GND
ACSIN
GIN
VDDO
DRA7
DRA6
DRA5
DRA4
DRA3
DRA2
DRA1
DRA0
GND
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDDO
DGB7
DGB6
DGB5
DGB4
DGB3
DGB2
DGB1
DGB0
GND
LPF
NC
GND
VDDP
GND
VDDP
GND
GND
GND
VDDO
DBB7
DBB6
DBB5
DBB4
DBB3
DBB2
DBB1
DBB0
GND
VDDO
VDDA
GND
VDDA
VDDA
GND
GND
BIN
VDDO
DCK
VDDO
DGA7
DGA6
DGA5
DGA4
DGA3
DGA2
DGA1
DGA0
GND
DCK
HSOUT
DCSOUT
GND
VDDA
GND
VDDA
GND
INVSCK
CLAMP
SDA
SCL
VDDO
GND
GND
GND
VDDA
PWRDN
VREFOUT
VREFIN
VDDA
VDDO
DRB7
DRB6
A0
A1
REV. 1.0.2 8/11/00
3
PRODUCT SPECIFICATION
FMS9884A
Pin Descriptions
Pin Name
Pin No. Type/Value Pin Function Description
Converter Channels
RIN, GIN, BIN 7, 15, 22
Input
Analog Inputs.
DRA7-0
105–112
Output
Red Channel Port A Data Output. Full rate/half rate, interleaved/
parallel data depending upon selected mode.
DRB7-0
95–102
Output
Red Channel Port B Data Output. Active for dual port mode only with
interleaved/parallel outputs. High impedance when inactive.
DGA7-0
DGB7-0
DBA7-0
DBB7-0
85–92
75–82
65–72
55–62
Output
Output
Output
Output
Green Channel Port A Data Output. See red channel port A.
Green Channel Port B Data Output. See red channel port B.
Blue Channel Port A Data Output. See red channel port A.
Blue Channel Port B Data Output. See red channel port B.
Timing Generator
CLAMP
28
27
Input
Input
External Clamp Input.
INVSCK
Invert Sampling Clock. Inverts SCK, the internal clock sampling the
analog inputs. Supports Alternate Pixel Sampling mode for capture
pixel rates up to 350Ms/s.
XCK
44
Input
External Clock input. Enabled if register bit, XCKSEL = H. Replaces
PXCK clock generated by PLL. If unused, connect to ground through a
10kΩ resistor.
DCK
DCK
115
116
Output
Output
Output Data Clock. Clock for strobing output data to external logic.
Output Data Clock Inverted. Inverted clock for strobing output data to
external logic.
HSOUT
117
Output
Horizontal Sync Output. Reconstructed HSYNC delayed by
FMS9884A latency and synchronized with DCK. Leading edge is
synchronized to start of data output. Polarity is always active HIGH.
Phase Locked Loop
HSIN
40
Schmitt
Input
Horizontal Sync input. Schmitt trigger threshold is 1.5V. A 5V source
should be clamped at 3.3V or current limited to prevent overdriving
ESD protection diodes.
COAST
41
PLL Coast. Maintain frequency of PLL output clock PXCK,
disregarding HSIN. If horizontal sync is missing during the vertical sync
interval, PXCK clock frequency can be maintained by asserting
COAST.
LPF
45
Passive
PLL Low Pass Filter. Connect recommended PLL filter to LPF pin.
(see Figure 19.)
Sync Stripper
ACSIN
14
Analog Composite Sync Input. Input to sync stripper with 150mV
threshold.
DCSOUT
Control
SDA
118
Digital Composite Sync Output. Output from sync stripper.
29
30
Bi-directional Serial Port Data. Bi-directional data.
SCL
Input
Input
Input
Input
Serial Port Clock. Clock input.
A0
31
Address bit 0. Lower bit of serial port address.
Address bit 1. Upper bit of serial port address.
A1
32
PWRDN
125
Power Down/Output Control. Powers down the FMS9884A and
tri-states the outputs.
4
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
Pin Descriptions (Continued)
Pin
Name
Pin No.
Pin Function Description
Power and Ground
VDDA
VDDP
VDDO
GND
4, 8, 10, 11, 16, 18, 19, 23,
25, 124, 128
ADC Supply Voltages. Provide a quiet noise free voltage.
33,34,43,48,50
PLL Supply Voltage. Most sensitive supply voltage. Provide a very
quiet noise free voltage.
54, 64, 74, 84, 94, 104, 114, Digital Output Supply Voltage. Decouple judiciously to avoid
120 propagation of switching noise.
5, 6, 9,12, 13, 14, 17, 20, 21, Ground. Returns for all power supplies. Connect ground pins to a
24, 26, 35, 39, 42, 47, 49, 51, solid ground plane.
52, 53, 63, 73, 83, 93, 103,
113, 119, 121, 122, 123
VREFIN
127
126
Voltage Reference Input. Common reference input to RGB
converters. Connect to VREFOUT, if internal reference is used.
VREFOUT
Voltage Reference Output. Internal band-gap reference output. Tie
to ground through a 0.1µF capacitor.
Addressable Memory
Register Map
Name
Address
Function
Default (hex)
PLLN11-4
00
PLL divide ratio, MSBs. PLLN + 1 = total number of
69 (1693)
pixels per horixontal line.
PLLN3-0
01
PLL divide ratio, LSBs. PLLN + 1 = total number of pixels
per horizontal line. PLLN3-0 stored in the four upper
register bits 7-4.
D0 (1693)
GR7-0
GG7-0
GB7-0
02
03
04
05
Gain, red channel. Adjustable from 70 to 140%.
Gain, green channel. Adjustable from 70 to 140%.
Gain, blue channel. Adjustable from 70 to 140%.
80
80
80
20
OSR5-0
Offset, red channel. OSR5-0 stored in the six upper
register bits 7-2.
OSG5-0
OSB5-0
CD7-0
06
07
08
Offset, green channel. OSG5-0 stored in the six upper
register bits 7-2.
20
20
80
Offset, blue channel. OSB5-0 stored in the six upper
register bits 7-2.
Clamp delay. Delay in pixels from trailing edge of
horizontal sync.
CW7-0
09
0A
0B
Clamp width. Width of clamp pulse in pixels.
80
F4
10
CONFIG1
PHASE7-0
Configuration Register No. 1
Sampling clock phase. PHASE4-0 stored in upper
register bits 7-3. PHASE sets the sampling clock phase in
11.25° increments.
PLLCTRL
CONFIG2
0C
0D
0E
0F
PLL Control
Configuration
Reserved
24
00
0X
00
Reserved
REV. 1.0.2 8/11/00
5
PRODUCT SPECIFICATION
FMS9884A
Register Definitions
Configuration Register 1 (0A)
Bit no.
Name
Type Description
0
1
XCKSEL
R/W
R/W
R/W
R/W
R/W
External Clock Select. Select internal clock source.
0: Internal PLL
1: XCK input.
2
3
4
5
XCLAMPOL
XCLAMP
External Clamp Polarity. Select clamp polarity.
0: Active L.
1: Active H.
External Clamp Select. Select clamp source.
0: Internally generated by PLL referenced to HSIN.
1: External CLAMP input.
COASTPOL
HSPOL
Coast Polarity. Select COAST input polarity.
0: Active L.
1: Active H.
HSIN Polarity. Select horizontal sync input polarity. PLL is locked to selected
edge:
0: Falling edge.
1: Rising edge.
6
7
PARALLEL
DEMUX
R/W
R/W
Output Data Format. Select format of data outputs.
0: Interleaved. DCK rising edge strobes port A data. DCK rising edge strobes
port B data.
1: Parallel. Rising edge of DCK strobes port A and port B data.
Output Data Porting. Data released at full rate through one port or through
two half-rate ports.
0: Single 8-bit port.
1: Dual 8-bit ports.
PLL Configuration Register (0C)
Bit no.
1-0
Name
—
Type Description
4-2
IPUMP2-0
R/W
Charge Pump Current. Selects Charge Pump current (µA).
(see Table 5. Charge Pump Current Codes)
000: 50
001: 100
010: 150
011: 250
100: 350
101: 500
110: 750
111: 1500
6-5
FVCO1-0
R/W
R/W
VCO Frequency Range. Selects VCO frequency range (MHz).
(see Table 4. VCO Frequency Codes)
00: 20–60
01: 50–90
10: 80–120
11: 110–140
7
—
Reserved.
0: Run.
1: (reserved).
6
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
Configuration Register 2 (0D)
Bit no.
Name
—
Type Description
0
3-1
4
—
R
Reserved. Set to 0.
Revision Number. Die revision number.
REV
OUTPHASE
W
Output Data Phase. In the dual port mode, selects either odd (1, 3, 5, …) or
even (2, 4, 6 ….) samples following the HSYNC leading edge to be emitted
from Port 1.
0: Even samples to Port A, odd samples to Port B.
1: Odd samples to Port A, even samples to Port B.
7-5
-
R/W
Reserved. Set to 00.
Clamps
Functional Description
If the incoming signals are not ground referenced, a clamp
There are two major sections within the FMS9884A
Digitizer:
must be used to set the incoming video range relative to
ground. Prior to each A/D converter, each channel includes a
clamp that allows a capacitively coupled input to be referenced
to the A/D converter bottom reference voltage when the
clamp pulse is active. Source of the clamp signal is deter-
mined by the XCLAMP bit.
1. Analog-to-digital Converter Channels, one for each
channel, RGB and the voltage reference.
2. Timing and Control comprising the PLL, Timing
Generator, Sync Stripper and Serial Interface.
Internal clamp timing is generated by the Timing and Con-
trol Block. Position and width of the internal clamp pulse,
ICLAMP are programmable through registers CD and CW.
External clamp input is selected by register bit XCLAMP
and the external clamp polarity selected through register bit
XCLAMPOL. To disable the clamp for DC coupled inputs,
set XCLAMP = 1 with either of these conditions:
A/D Converter Channels
Each of the three RGB channels consists of:
1. A clamp to set the lower reference level of an AC
coupled input.
2. Gain and offset stages to tune the converter to input
signal levels.
1. XCLAMPOL = 0 with input CLAMP = H.
2. XCLAMPOL = 1 with CLAMP = L.
3. An Analog-to-Digital Converter to digitize the analog
input.
Best performance will be achieved with the clamp set active
for most of the black signal level interval between the trail-
ing edge of horizontal sync and the start of active video.
Insufficient clamping can cause brightness changes at the top
of the image and slow recovery from large changes in Aver-
age Picture Level (APL). Recommended value of CD is
0x10 to 0x20 for most standard video sources.
4. A commutating switch for dual port operation.
Analog Inputs
Input signal range is 500 to 1000mV to support conversion of
single-ended signals with a typical amplitude of 700mV p-p.
With the clamp active, each input accommodates a negative
300mV excursion.
Analog-to-Digital Converter
Inputs are optimized for a source resistance of 37.5 to 75Ω.
To reduce noise sensitivity, the ultra-wide 500MHz input
bandwidth may be reduced by adding a small series inductor
prior to the 75Ω terminating resistor. See Applications Section.
Figure 2 is a block diagram of the ADC core with gain and
offset functions. G7-0, OS5-0, RGBIN and PD7-0 generically
refer to the gain and offset register values, analog input and
parallel data output of any RGB channel.
REV. 1.0.2 8/11/00
7
PRODUCT SPECIFICATION
FMS9884A
VREF
G7-0
Gain
Register
D/A
OS5-0
Current
D/A
Offset
Register
IBIAS + IOFFSET
A/D Core
RGBIN
+
Track &
Hold
-
PD7-0
A/D
RLEVEL
SCK
Figure 2. A/D Converter Architecture
Core of the ADC block is a high speed A/D encoder with dif-
ferential inputs. Within the A/D converter core are the fol-
lowing elements:
The 6-bit Offset D/A converter injects a current into RLEVEL
with two components:
1. IBIAS to establish the A/D common mode voltage.
2. IOFFSET to set the offset from the common mode level.
1. Differential track and hold.
2. Differential analog-to-digital converter.
Offset from the common mode voltage is:
255 + G7 – 0
Setting the gain register value G7-0 (GR7-0, GG7-0, GB7-0),
establishes the gain D/A converter voltage which is the A/D
reference voltage. Increasing video gain reduces the contrast
of the picture since the number of output codes is reduced.
Conversion range is defined by the gain setting according to
Table 1.
----------------------------
AOS = (OS5 – 0 – 32) •
LSB
255
D/A converter gain tracks A/D gain with 1 LSB of offset cor-
responding to 1 LSB of gain. Increasing the offset of a video
signal increases brightness of the picture. Impact of the off-
set values OSR5-0, OSG5-0, and OSB5-0 is shown in Table 2.
Table 1. Gain Calibration
G7-0
0
Conversion Range (mV)
Table 2. Offset Calibration
500
700
OS5-0
0
Equivalent Offset (bits)
66h
FFh
-31d
0
1000
1Fh
3Fh
A/D Converter sensitivity is:
32d
255
255
S = -------- •
500
----------------------------
255 + G7 – 0
LSB ⁄ mV
Sampling Clock PHASE Adjustment
Picture quality is strongly impacted by the PHASE4-0 value.
If PHASE is not set correctly, any section of an image con-
sisting of vertical lines may exhibit tearing.
Offset is set through the Single-Ended to Differential Amplifier
which translates the ground referenced input to a differential
voltage centered around A/D common mode bias voltage.
Figure 3 shows how an analog input, RINGINBIN is sampled
by the rising edge of SCK after a delay PHASE from the ris-
ing edge of either PXCK or XCK. SCK can be delayed up to
32 steps in 11.25° increments by adjusting the register value,
PHASE4-0
.
8
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
PHASE
PXCK/XCK
SCK
R
G
B
IN IN IN
RGBn
DCK
D7-0
Figure 3. Internal Sampling Clock, SCK Timing
Output data, DCK and DCK are delayed in tandem with
SCK relative to PXCK or XCK. There is a 5-51/2 clock
latency between the data sample RGBn and the correspond-
Referring to Figure 6, when the sample clock, SCK has some
jitter, if the sampling edge occurs anywhere within the zone
of uncertainty where the pixel rise time is steep, there will be
amplitude modulation of the digitized data, D7-0, due to the
sampling clock jitter. To avoid corruption of the image, set-
ting the value PHASE7-0 is critical. PHASE4-0 should be
trimmed to position the sampling edge of SCK within the
zone of serendipity.
ing data out D7-0
.
Ideally, incoming pixels would be trapezoidal with fast rise-
times and the sampling edge of the A/D clock, SCK would
be positioned along the level section of the incoming pixel
waveform as shown in Figure 4. There is a narrow zone of
uncertainly where sampling during pixel rise time would
cause an error in the value of the A/D data output, D7-0,
which is shown as a value, 0-255.
Zones of Uncertainty
RIN, GIN, BIN
Zones of Uncertainty
SCK
D7-0
RIN, GIN, BIN
SCK
Figure 6. Improper Pixel Sampling
D7-0
Voltage References
An on-chip voltage reference is generated from a bandgap
source. VREFOUT is the buffered output of this source that
can be connected to VREFIN to supply a voltage reference
that is common to the three converter channels.
Figure 4. Ideal Pixel Sampling
In practice, high-resolution pixels have long rise-times. As
shown in Figure 5, there are narrow zones of serendipity
when the pixel amplitude is level. Samples are valid in these
zones.
VREFIN, with a nominal voltage of 1.25V, is the source of the
differential reference voltages for each A/D converter.
Reference voltages supplied to the differential inputs of the
Zones of Serendipity
comparators in the A/D converters are derived from VREFIN
.
RIN, GIN, BIN
SCK
D7-0
Figure 5. Acceptable Pixel Sampling
REV. 1.0.2 8/11/00
9
PRODUCT SPECIFICATION
FMS9884A
Levels are 3.3 volt CMOS with the output supply variable
Digital Data Outputs
between 2.5 and 3.3 V. PWRDN = L sets the outputs
high-impedance. PWRDN = H enables the outputs.
Input horizontal sync, HSIN and outgoing data, D[7..0] are
resynchronized to the delayed sample clock, SCK. Output
timing characteristics are defined in Figure 7. Latency of the
first pixel, N varies according to the mode:
1. Single or dual output port.
2. Interleaved or parallel output data.
3. 1-pixel or 2-pixel.
HSIN
PHASE
N
PXCK/XCK
SCK
RGBIN
S0
DCK
tDH
DCK
tDO
D0
D[7..0]
HSOUT
Figure 7. Output Timing
Figures 13 through 21 depict data output timing relative to
the sampling clock and inputs for all modes. Timing is refer-
enced to the leading edge of HSIN when the first sample is
taken at the rising edge of SCK. Status of register bit OUT-
PHASE, determines if even samples are directed the A-port
and odd samples are directed to the B-port; or vice versa.
HS is the internal sync pulse generated from HSYNC. SCK
is the internal A/D converter sampling clock.
Output data transitions are synchronized with the falling
edge of DCK. Output data should be strobed on the rising
edge of DCK. A 5 to 6.5 clock cycle delay must be flushed
before valid data is available.
Note the timing of the HSOUT waveform:
1. HSOUT is always active HIGH.
Alternate Pixel Sampling Mode
A logic H on the CKINV pin inverts the sampling phase of
SCK. In the Alternate Pixel Sampling Mode:
2. Only the leading edge of HSOUT is active or selected by
the HSPOL register bit.
1. PLL is run at half rate. SCK, DCK and DCK are half rate.
2. CKINV is toggled between frames. (see Figure 18)
3. HSOUT is aligned with DCK.
4. Trailing edge is linked to HSIN.
5. If HSIN does not terminate before mid-line, HSOUT is
forced low. A 50% duty cycle indicates that HSPOL is
incorrectly set.
10
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2
E2O1 O1 O1 O1
E2 E2 E2 E2O1E2
E2 E2 E2 E2O1E2
E2O1 O1 O1 O1
O1
O1
O1
O1
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
O E O E
E2
E2 E2O1 O1 O1 O1
E2 E2 E2
O1 O1 O1
E2
E2 E2
O1 O1
E2 E2 E2
O1 O1 O1 O1 O1
E2 E2
E2 E2 E2
O1
E2
O1 O1 O1 O1 O1
O1
O1
O1
O1
O1
O1
O1
E2 E2
E2 E2 E2
O1
E2
O1 O1 O1 O1 O1
E2 E2
E2 E2 E2
O1
E2
O1 O1 O1 O1 O1
E2 E2
E2 E2 E2
O1
E2
O1 O1 O1 O1 O1
E2 E2
E2 E2 E2
E2
O1
O1 O1 O1 O1 O1
E2 E2
E2 E2 E2
E2
O1
O1 O1 O1 O1 O1
E2 E2
E2 E2 E2
E2
O1
O1 O1 O1 O1 O1
Figure 10. Even Pixels from Frame 2
Figure 8. Odd and Even Pixels in a Frame
On one frame, even pixels are sampled. On the other, odd
pixels are sampled.
O1E2 O1 E2 O1E2O1E2 O1E2O1E2
O1E2 O1 E2 O1E2O1E2 O1E2O1E2
O1E2 O1 E2 O1E2O1E2 O1E2O1E2
O1E2 O1 E2 O1E2O1E2 O1E2O1E2
O1E2 O1 E2 O1E2O1E2 O1E2O1E2
O1E2 O1 E2 O1E2O1E2 O1E2O1E2
O1E2 O1 E2 O1E2O1E2 O1E2O1E2
O1E2 O1 E2 O1E2O1E2 O1E2O1E2
O1E2 O1 E2 O1E2O1E2 O1E2O1E2
O1E2 O1 E2 O1E2O1E2 O1E2O1E2
O1E2 O1 E2 O1E2O1E2 O1E2O1E2
O1E2 O1 E2 O1E2O1E2 O1E2O1E2
O1E2 O1 E2 O1E2O1E2 O1E2O1E2
Alternate Pixel Sampling is similar to interlacing used in
broadcast video, except that the columns of pixels are inter-
laced instead of lines.
E1 E1 E1 E1 E1 E1
O1 O1 O1 O1 O1 O1
E1
O1
E1 E1 E1 E1 E1 E1
O1 O1 O1 O1 O1 O1
E1
O1
E1 E1 E1 E1 E1 E1
O1 O1 O1 O1 O1 O1
E1
O1
O1E1O1E1O1E1O1E1O1E1O1E1 E1
O1
O1E1O1E1O1E1O1E1O1E1O1E1 E1
O1
O1E1O1E1O1E1O1E1O1E1O1E1 E1
O1
Figure 11. Combined Frames 1 and 2 Output.
O1E1O1E1O1E1O1E1O1E1O1E1 E1
O1
O1E1O1E1O1E1O1E1O1E1O1E1
O1E1
O1E1O1E1O1E1O1E1O1E1O1
E1O1E1
O3 E2 O3 E2 O3E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3E2 O3 E2 O3 E2 O3 E2
O1E1O1E1O1E1O1E1O1 O1
E1 E1O1E1
O1E1O1E1O1E1O1 O1 O1
E1 E1 E1O1E1
Figure 9. Odd Pixels from Frame 1
Figure 12. Subsequent Output Combining Frames 2 and 3
RGBIN
HSIN
PXCK
HS
P0
P1
P2
P3
P4
P5
P6
P7
5 PIPE DELAY
SCK
DATACK
D0 D1 D2 D3 D4 D5 D6 D7
DA7-0
HSOUT
Figure 13. Single Port Mode
REV. 1.0.2 8/11/00
11
PRODUCT SPECIFICATION
FMS9884A
P2
RGBIN P0 P1
P3 P4 P5 P6 P7
5 PIPE DELAY
HSIN
PXCK
HS
SCK
DATACK
DA7-0
D0
D2
D4
D6
HSOUT
Figure 14. Single Port Mode, Alternate Pixel Sampling, (Even Pixels)
P0 P1 P2 P3 P4 P5 P6 P7
RGBIN
HSIN
PXCK
HS
5.5 PIPE DELAY
SCK
DATACK
DA7-0
D1
D3
D5
D7
HSOUT
Figure 15. Single Port Mode, Alternate Pixel Sampling, (Odd Pixels)
P0
P1
P2
P3
P4
P5
P6
P7
RGBIN
HSIN
PXCK
HS
5 PIPE DELAY
SCK
DATACK
DA7-0
D0
D2
D4
D6
DB7-0
D1
D3
D5
D7
HSOUT
Figure 16. Dual Port Mode, Interleaved Outputs
12
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
RGBIN
HSIN
PXCK
HS
P0
P1
P2
P3
P4
P5
P6
P7
6 PIPE DELAY
SCK
DATACK
DA7-0
D0
D1
D2
D3
D4
D5
D6
D7
HSOUT
Figure 17. Dual Port Mode, Parallel Outputs
P0 P1 P2 P3 P4 P5 P6 P7
RGBIN
HSIN
PXCK
HS
5 PIPE DELAY
SCK
DATACK
D0
D4
DA7-0
DB7-0
D2
D6
HSOUT
Figure 18. Dual Port Mode, Interleaved Outputs, Alternate Pixel Sampling, (Even Pixels)
P0 P1 P2 P3 P4 P5 P6 P7
RGBIN
HSIN
PXCK
HS
5.5 PIPE DELAY
SCK
DATACK
DA7-0
DB7-0
D1
D5
D3
D7
HSOUT
Figure 19. Dual Port Mode, Interleaved Outputs, Alternate Pixel Sampling, (Odd Pixels)
REV. 1.0.2 8/11/00
13
PRODUCT SPECIFICATION
FMS9884A
P1 P2 P3 P4
P0
P5 P6 P7
RGBIN
HSIN
PXCK
HS
6 PIPE DELAY
SCK
DATACK
D0
D2
D4
D6
DA7-0
DB7-0
HSOUT
Figure 20. Dual Port Mode, Parallel Outputs, Alternate Pixel Sampling, (Even Pixels)
P0 P1 P2 P3 P4 P5 P6 P7
RGBIN
HSIN
PXCK
HS
6.5 PIPE DELAY
SCK
DATACK
DA7-0
D1
D3
D5
D7
DB7-0
HSOUT
Figure 21. Dual Port Mode, Parallel Outputs, Alternate Pixel Sampling, (Odd Pixels)
The PLL consists of a phase comparator, charge pump VCO
and ÷N counter, with the charge pump connected through the
LPF pin to an external filter. These elements must be pro-
grammed to match the incoming video source to be captured.
Timing and Control
Timing and Control logic encompasses the PLL, Timing
Generator and Sync Stripper.
Phase Locked Loop
Values of IPUMP and FVCO for Standard VESA timing
parameters are shown in Table 3. Timing of many computer
video outputs does not comply with VESA recommendations.
PLLN should be optimized to avoid vertical noise bars on the
displayed image.
Two clock types originate in the PLL:
1. Data clocks DCK and DCK.
2. Internal sampling clock SCK.
Modes marked 2X are 2X-oversampled modes where the
number of samples per horizontal line is doubled. To select
this mode, the Phase-locked Loop Divide Ratio value must
changed from PLL1x to:
DCK and DCK are used to strobe data from the FMS9884A
to following digital circuits. SCK is the ADC sample clock
which has adjustable phase controlled through the PHASE
register. DCK and DCK are phase aligned with SCK.
PLL2x = 2 • (PLL1x + 1) – 1
Reference for the PLL is the horizontal sync input, HSIN
with polarity selected by the HSPOL bit.
Values of IPUMP and FVCO are set through the PLL
Configuration Register (0x0C). Recommended external filter
components are shown in Figure 22. RF Quality ±10%
ceramic capacitors with X7R dielectrc are recommended.
Frequency of the HSIN input is multiplied by the value PLLN
+ 1 derived from the PLLN11-4 and PLLN3-0 registers. PLLN
+ 1 should equal the number of pixels per horizontal line
including active and blanked sections. Typically blanking is
20–30% of active pixels. Divide ratios from 2–4095 are
supported. SCK, DCK and DCK run at a rate PLLN + 1
times the HSIN frequency.
14
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
Table 3. Recommended IPUMP and FVCO values for Standard Display Formats
Horizontal
Standard
Resolution
Refresh Rate
Frequency
Sample Rate
FVCO1-0
IPUMP2-0
VGA
640 X 480
60 Hz
72 Hz
75 Hz
85 Hz
31.5 kHz
37.7 kHz
37.5 kHz
43.3 kHz
25.175 MHz
31.500 MHz
31.500 MHz
36.000 MHz
01
01
01
100
100
100
2X
640 X 480
60 Hz
72 Hz
75 Hz
70 Hz
31.5 kHz
37.7 kHz
37.5 kHz
31.5 kHz
50 MHz
63 MHz
72 MHz
56.6MHz
01
01
01
01
111
111
111
111
720 X 400
640 X 480
800 X 600
Mac
67 Hz
35 kHz
31 MHz
10
100
SVGA
56 Hz
60 Hz
72 Hz
75 Hz
85 Hz
35.1 kHz
37.9 kHz
48.1 kHz
46.9 kHz
53.7 kHz
36.000 MHz
40.000 MHz
50.000 MHz
49.500 MHz
56.250 MHz
01
01
01
01
100
110
110
110
XGA
Mac
1024 X 768
1024 X 768
60 Hz
70 Hz
75 Hz
80 Hz
85 Hz
48.4 kHz
56.5 kHz
60.0 kHz
64.0 kHz
68.3 kHz
65.000 MHz
75.000 MHz
78.750 MHz
85.500 MHz
94.500 MHz
01
01
10
111
111
111
60 Hz
75 Hz
75 Hz
48 kHz
60 kHz
69 kHz
64 MHz
80 MHz
100 MHz
01
10
10
111
111
111
1152 X 870
1152 X 900
1280 X 1024
1280 X 1024
Sun
HP
66 Hz
60 Hz
62 kHz
63 kHz
93 MHz
10
10
111
111
108 MHz
SXGA
60 Hz
72 Hz
75 Hz
85 Hz
64.0 kHz
78.1 kHz
80.0 kHz
91.1 kHz
108.000 MHz
135.000 MHz
135.000 MHz
157.500 MHz
10
11
11
111
111
111
UXGA
1600 X 1200
60 Hz
65 Hz
70 Hz
75 Hz
85 Hz
75.0 kHz
81.3 kHz
87.5 kHz
93.8 kHz
106.3 kHz
162.000 MHz
175.500 MHz*
189.000 MHz*
202.500 MHz*
229.500 MHz*
VESA Monitor Timing Standards and Guidelines, September 17, 1998
1
* Graphics sampled at / incoming pixel rate using Alternate Pixel Sampling mode.
2
Loop performance is established by setting:
VDDP
C1
0.18µF
1. VCO frequency range through FVCO1-0. (see Table 4)
2. Charge Pump Current through IPUMP2-0. (see Table 5)
3. External loop filter component values.
C2
0.018µF
R1
1.5K
LPF
Figure 22. Schematic, PLL Filter.
REV. 1.0.2 8/11/00
15
PRODUCT SPECIFICATION
FMS9884A
Operation of COAST is depicted in Figure 23. HSOUT
polarity is always positive. When COAST = L, HSOUT
tracks HSIN (shown with postive polarity in Figure 23):
Table 4. VCO Frequency Bands
FVCO2-0 Frequency Range (MHz) KVCO (MHz/V)
00
20–75
60
1. HSOUT rising edge tracks HSIN delayed by a few pixels.
01
10
11
2. HSOUT falling edge tracks the trailing edge of HSIN
with no delay.
75–108
90
108–140
100
When COAST = H, the PLL flywheels, disregarding the
incoming HSIN references, while the HSOUT waveform
depends upon the state of HSIN.
Table 5. Charge Pump Current Levels
IPUMP2-0
000
Current (µA)
1. If HSIN = H:
50
100
150
250
350
500
750
1500
a.) HSOUT rising edge remains locked to the PLL.
001
b.) HSOUT trailing edge falls after 50% of the HSOUT
period has expired.
010
011
2. HSIN transitions:
100
101
a.) HSOUT rising edge remains locked to the PLL.
110
b.) HSOUT falling edge is terminated by the trailing
edge of HSIN.
111
3. If HSIN = L, then HSOUT = L
Setting SPHASE4-0 selects the sampling phase of SCK rela-
tive to PXCK in 32 steps of 11.25°. Phase of the output data,
DCK and DCK is slaved to the SCK phase.
Timing Generator
Timing and Control logic generates:
Clock jitter is less than 5% of pixel period in all operating
modes. At lower frequencies below 40MHz, the jitter rises
but can be reduced by over-sampling at a 2X clock rate. Data
should be read out of one port using the dual port mode. See
Performance section for jitter specifications and plots.
1. Internal sampling clock, SCK.
2. Output data clocks, DCK and DCK.
3. Output horizontal sync, HSOUT
.
4. Internal clamp pulse, ICLAMP.
COAST
With HSPOL set correctly, ICLAMP delay follows the trail-
ing edge of horizontal sync in (HSIN). Delay is set by the
CD register. Width of ICLAMP is set by the CW register.
Range of CD and CW values is 1–255 pixels.
COAST = H disables PLL lock to HSIN, while the VCO
frequency is retained. VCO frequency remains stable over
several lines without updates from HSIN. COAST can be
connected directly to the vertical sync signal or supplied by
the graphics controller.
HSIN
Trailing edge terminates HSOUT
COAST
HSOUT
50% Timeout
Figure 23.
16
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
Since the serial control port is design to interface with 3.3V
logic, the pins must be protected by series connected 150Ω
resistors if SDA and SCL signals originate from 5V logic.
(See Applications Section)
Sync Stripper
Some video signals include embedded composite sync rather
than separate horizontal and vertical sync signals, typically
sync on green. Composite sync is extracted from Composite
Video at the ACSIN pin.
Table 6. Serial Interface Address Codes
When the ACSIN signal falls below a 150mV ground refer-
enced threshold, sync is detected. Composite Sync Output,
DCSOUT reflects the ACSIN sync timing with non-inverted
CMOS digital levels.
A1-0
00
7-bit Address
4C
4D
4E
4F
01
10
Power Down
11
PWRDN = L minimizes FMS9884A power consumption.
Data outputs become high impedance. Clocks generation is
stopped. Register contents are maintained. Sync stripping
and the internal voltage reference function.
Two signals comprise the bus: clock (SCL) and bi-directional
data (SDA). When receiving and transmitting data through
the serial interface, the FMS9884A acts as a slave, responding
only to commands by the I2C/SMBus master.
Serial Interface
Register access is via a 2-wire I2C/SMBus compatible inter-
face. As a slave device, the 7-bit address is selected by the
Data received or transmitted on the SDA line must be stable
for the duration of the positive-going SCL pulse. Data on
SDA may change only when SCL = L. An SDA transition
while SCL = H is interpreted as a start or stop signal.
A
1-0 pins (see Table 6). Serial port pins SDA and SCL com-
municate with the host SMBus/I2C controller which act as a
master.
SDA
tBUFF
tSTAH
tDHO
tDSU
tSTASU
tSTOSU
tDAL
SCL
tDAH
Figure 24. Serial Bus: Read/Write Timing
SDA
SCL
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ACK
Figure 25. SerialBus: Typical Byte Transfer
SDA
SCL
A6
A5
A4
A3
A2
A1
A0
R/W\
ACK
Figure 26. Serial Bus: Slave Address with Read/Write Bit
REV. 1.0.2 8/11/00
17
PRODUCT SPECIFICATION
FMS9884A
There are five steps within an I2C/SMBus cycle:
a LOW-to-HIGH transition of SDA while SCL is HIGH.
(see Figure 23, right waveform)
1. Start signal
2. Slave address byte
3. Pointer register address byte
4. Data byte to read or write
5. Stop signal
A repeated start signal occurs when the master device driving
the serial interface generates a start signal without first gener-
ating a stop signal to terminate the current communication.
This is used to change the mode of communication (read,
write) between the slave and master without releasing the
serial interface lines.
When the Serial Bus interface is inactive, SCL = H and SDA
= H. Communications are initiated by sending a start signal
(Figure 23, left waveform) that is a HIGH-to-LOW transition
on SDA while SCL is HIGH. A start signal alerts all slaved
devices that a data transfer sequence is imminent.
Serial Interface Read/Write Examples
Examples below show how serial bus cycles can be linked
together for multiple register read and write access cycles.
For sequential register accesses, each ACK handshake ini-
tiates further SCL clock cycles from the master to transfer
the next data byte.
After a start signal, the first eight bits of data comprise a seven
bit slave address followed a single R/W bit (Read = H, Write
= L) to set the direction of data transfer: read from; or write
to the slave device. If the transmitted slave address matches
the address of the FMS9884A which set by the state of the
ADD pin, the FMS9884A acknowledges by pulling SDA
LOW on the 9th SCL pulse (see Figure 25). If the addresses
do not match, the FMS9884A does not acknowledge.
Write to one register
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte
4. Data byte to base address
5. Stop signal
For each byte of data read or written, the MSB is the first bit
of the sequence.
Write to four consecutive registers
Data Transfer via Serial Interface
1. Start signal
If a slave device, such as the FMS9884A does not acknowl-
edge the master device during a write sequence, SDA
remains HIGH so the master can generate a stop signal. Dur-
ing a read sequence, if the master device does not acknowl-
edge by bringing SDA = L, the FMS9884A interprets SDA =
H as “end of data.” SDA remains HIGH so the master can
generate a stop signal.
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte
4. Data byte to base address
5. Data byte to (base address + 1)
6. Data byte to (base address + 2)
7. Data byte to (base address + 3)
8. Stop signal
To write data to a specific FMS9884A control register, three
bytes are sent:
Read from one register
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte (= base address)
4. Stop signal (optional)
5. Start signal
1. Write the slave address byte with bit R/W = L.
2. Write the pointer byte.
3. Write to the control register indexed by the pointer.
6. Slave Address byte (R/W bit = HIGH)
7. Data byte from base address
8. Stop signal
After each byte is written, the pointer auto-increments to
allow multiple data byte transfers within one write cycle.
Data is read from the control registers of the FMS9884A in a
similar manner, except that two data transfer operations are
required:
Read from four registers
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte (= base address)
4. Stop signal (optional)
1. Write the slave address byte with bit R/W = L.
2. Write the pointer byte.
3. Write the slave address byte with bit R/W = H
4. Read the control register indexed by the pointer.
5. Start signal
6. Slave Address byte (R/W bit = HIGH)
7. Data byte from base address
8. Data byte from (base address + 1)
9. Data byte from (base address + 2)
10. Data byte from (base address + 3)
11. Stop signal
After each byte is read, the pointer auto-increments to allow
multiple data byte transfers within one read cycle.
Preceding each slave write, there must be a start cycle.
Following the pointer byte there should be a stop cycle.
After the last read, there must be a stop cycle comprising
18
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
Absolute Maximum Ratings
(beyond which the device may be damaged)1
Parameter
Power Supply Voltages
VCC (Measured to GND)
Digital Inputs
Min
Typ
Max
Unit
-0.5
4
V
Applied voltage (Measured to GND)2
Forced current 3, 4
-0.3
-5.0
VDDA
5.0
V
mA
Analog Inputs
Applied Voltage (Measured to GND)2
Forced current 3, 4
-0.5
VDDA
10.0
V
-10.0
mA
Digital Outputs
Applied voltage (Measured to GND)2
Forced current 3, 4
Forced current 3, 4
-0.5
-6.0
-8.0
V
mA
6.0
8.0
1
mA
Short circuit duration (single output in HIGH state to ground)
Temperature
second
Junction
150
300
°C
°C
°C
°C
V
Lead Soldering (10 seconds)
Vapor Phase Soldering (1 minute)
Storage
220
-65
150
Electrostatic Discharge5
±150
Notes:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if
Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
5. EIAJ test method.
Operating Conditions
Parameter
VDDA
Min
3.0
3.0
2.2
0
Nom
3.3
Max
3.6
3.6
3.6
70
Units
ADC Power Supply Voltage
PLL Power Supply Voltage
Output Power Supply Voltage
Ambient Temperature, Still Air
A/D analog input range, min.
A/D analog input range, max.
V
V
VDDP
3.3
VDDO
TA
3.3
V
°C
500
mV p-p
mV p-p
1000
REV. 1.0.2 8/11/00
19
PRODUCT SPECIFICATION
FMS9884A
Electrical Characteristics1
Parameter
Conditions
Min
Typ Max
Unit
Power Supply Currents
IDDA
IDDD
IDDP
PD
Supply current, ADC
Supply current2, Digital Output
Supply current, PLL
Operating, 25°C
Operating, 25°C
Operating, 25°C
0 to 70°C
211
47
mA
mA
mA
mW
mA
mW
30
Power dissipation
950
23
IPD
Power-down current
0 to 70°C
PDD
Powered-down disspation
0 to 70°C
75
Digital Inputs/Outputs
CI
Input Capacitance
25°C
3
pF
pF
µA
µA
V
CO
Output Capacitance
25°C
IIH
Input Current, HIGH
0 to 70°C
-1
IIL
Input Current, LOW
0 to 70°C
+1
VIH
VIL
Input Voltage, HIGH
0 to 70°C
2.5
Input Voltage, LOW
0 to 70°C
0.8
V
IOHD
IOHC
IOLD
IOLC
VOH
VOL
Output Current, HIGH, data
Output Current, HIGH, clock
Output Current, LOW, data
Output Current, LOW, clock
Output Voltage, HIGH
0 to 70°C
4
8
4
8
mA
mA
mA
mA
V
0 to 70°C
0 to 70°C
0 to 70°C
IOH = max., 0 to 70°C
IOL = max., 0 to 70°C
VDDO–0.1
Output Voltage, LOW (VDD3
)
0.1
V
Serial Bus I/O
VSMIH Input Voltage, HIGH
VSMIL Input Voltage, LOW
VSMOL Output Voltage, LOW
ISMOH Output Current, HIGH
ISMOL Output Current, HIGH
Analog Inputs
0 to 70°C
0 to 70°C
ISMOL = max.
0 to 70°C
0 to 70°C
2.5
V
V
0.8
0.1
V
µA
mA
IB
Input bias current
0 to 70°C
0 to 70°C
1
µA
EOS
Input Offset Voltage
7
50
mV
Reference Output
Output Voltage
Temperature Coefficient
0 to 70°C
0 to 70°C
1.20
1.25 1.30
V
±50
Ppm/°C
Notes:
1. Unless otherwise stated, 0 to 70°C
2. DEMUX = 1; DCK, DCK load = 15 pF; data load = 5 pF.
20
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
Switching Characteristics
Parameter
Conditions Min. Typ. Max.
Unit
Analog-to-Digital Converters
Conversion rate
0 to 70°C
0 to 70°C
10
140
2.0
Ms/s
ns
tSKEW
Timing Generator
HSIN input frequency
Data to clock skew
-0.5
0 to 70°C
0 to 70°C
15
110
20
kHz
Maximum PLL clock rate
FMS9884AKAC100
FMS9884AKAC140
108
140
MHz
Minimum PLL clock rate
0 to 70°C
MHz
Serial Bus Interface
tDAL
tDAH
SCL Pulse Width, LOW
0 to 70°C
0 to 70°C
0 to 70°C
0 to 70°C
0 to 70°C
0 to 70°C
0 to 70°C
0 to 70°C
4.7
4.0
4.0
4.7
4.0
4.7
250
0
µs
µs
µs
µs
µs
µs
ns
ns
SCL Pulse Width, HIGH
tSTAH
tSTASU
tSTOSU
tBUFF
tDSU
SDA Start Hold Time
SCL to SDA Setup Time (Stop)
SCL to SDA Setup Time (Start)
SDA Stop Hold Time Setup
SDA to SCL Data Setup Time
SDA to SCL Data Hold Time
tDHO
System Performance Characteristics
Parameter
Conditions
Min
Typ1
Max
Unit
Analog to Digital Converter
ELI
Integral Linearity Error
25°C
0 to 70°C
25°C
-1.4
-2.5
-1.0
-1.0
±0.8
±0.5
1.4
2.5
1.15
1.25
0
LSB
LSB
LSB
LSB
ELD
Differential Linearity Error
0 to 70°C
0 to 70°C
0 to 70°C
0 to 70°C
25°C
Missing Codes
Input full scale matching
Offset adjustment range
Gain tempco
5
23.5
280
500
2
%FS1
%FS1
ppm/°C
MHz
ns
22
25
BW
Analog bandwidth, full power
Transient response
25°C
25°C
tOV
Over-voltage recovery time
25°C
1.5
45
ns
SNR SNR without harmonics
dB
REV. 1.0.2 8/11/00
21
PRODUCT SPECIFICATION
FMS9884A
System Performance Characteristics (continued)
Parameter
Conditions
Min
Typ1
Max
Unit
Phase Locked Loop
tPP
Peak-to-peak PLL Jitter @
MHz
25.175
31.5
36
25°C
7.9
5.5
ns
4.5
49.5
78.75
108
3.1
2.1
1.8
135
1.1
tRMS RMS PLL Jitter @ MHz
25.175
31.5
36
25°C
1000
700
600
420
270
250
150
ps
49.5
78.75
108
135
Thermal
θJC
θJA
Resistance, junction-to-case
8.4
35
°C/W
°C/W
Resistance, junction-to-ambient
Notes:
1. % FS is percentage of full scale.
9
8
7
6
5
4
3
2
1
0
RMS
P-P
0
20
40
60
80
100
120
140
Pixel Clock (MHz)
Figure 27. Pixel Clock Jitter vs. Frequency
22
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
AC Coupled Digitizer
Applications Information
Shown in Figure 28 is an implementation of a video digitizer
with AC coupled RGB inputs. Horizontal sync input, HS is
passed through a voltage divider which attenuates the 5.0 V
logic HIGH excursion to the 3.3 V HIGH input level of the
FMS9884A. Vertical sync is also attenuated to make the
VSOUT level compatible with 3.3 V pixel processing fol-
lowing the FMS9884A.
Two applications circuits are reviewed:
1. AC coupled digitizer with clamp.
2. AC coupled digitizer with dual ported outputs and sync
stripping.
To minimize component count, use of the following on-chip
circuits is recommended:
1. ADC sampling clock.
Output data is three channel port A data only with a maxi-
mum rate of 140Ms/s 24-bit pixels. Data is clocked out on
the negative edge of DCK. HSOUT defines the active video
along a line, while incoming vertical sync, VSIN is propa-
gated as VSOUT to the output data to synchronize handling
of digitized frames of output data.
2. Clamp.
3. Voltage reference
4. Dual ported data outputs
Optimum PLL Configuration Register (address 0x0C) set-
tings for typical graphics modes are listed in Table 3. Unless
otherwise indicated, all modes are compliant with VESA
specifications. For unlisted modes, values should be adjusted
to optimize performance.
Control is through the serial port with 150Ω resistors
inserted to allow interfacing with 5V logic. If the serial bus is
operates with 3.3V levels, these resistors are unnecessary.
By adjusting the values in the gain (GR, GG, GB) and offset
(OSR, OSG, OSB) registers, the input conversion range can
be matched to the incoming analog signals.
REV. 1.0.2 8/11/00
23
PRODUCT SPECIFICATION
FMS9884A
C1
.047µF
VDDA
VDDO
VDDP
J1
RED
GREEN
BLUE
3
1
2
C2
0.18µF
C4
U1
4
5
.047µF
R1
75
AD9884
6
7
8
9
10
11
12
13
14
15
C6
0.018µF
33
34
43
48
50
55
C7
.047µF
DB _B7
DB _B6
DB _B5
DB _B4
DB _B3
DB _B2
D B_B1
DB _B0
PVD
PVD
PVD
PVD
PVD
56
57
58
59
60
61
62
R2
1.5K
R3
75
HSIN
VSIN
7
RIN
BA [7..0]
GA[7..0]
RA[7..0]
15
22
27
28
40
75
R4
GIN
65
BA7
DB _A7
DB _A6
DB _A5
DB _A4
DB _A3
DB _A2
DB _A1
DB _A0
SVGA
66
67
68
69
70
71
BA6
BA5
BA4
BA3
BA2
BA1
BIN
R5
1K
CLKINV
CLAMP
72
BA0
R6
1K
HSIN
41
44
45
29
75
COAST
CKEXT
FILT
DG_B7
DG_B6
DG_B5
DG_B4
DG_B3
DG_B2
76
77
78
79
80
81
82
R7
1.8K
R10 150
R11 150
SDA
SCL
SDA
SCL
A0
DG_B1
DG_B0
30
31
32
14
85
86
87
88
89
90
91
GA7
GA6
GA5
GA4
GA3
GA2
GA1
DG_A7
DG_A6
DG_A5
DG_A4
DG_A3
DG_A2
DG_A1
R8
1.8K
A1
ACSIN
1
2
3
36
37
38
46
92
GA0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
DG_A0
95
DR_B7
DR_B6
DR_B5
DR_B4
DR_B3
DR_B2
VDD
96
97
98
99
100
101
102
127
REFIN
DR_B1
DR_B0
R9
10K
115
105 RA7
106 RA6
DATACK
DATACK
HSOUT
PWRDN
DR_A7
DR_A6
DR_A5
DR_A4
DR_A3
DR_A2
DR_A1
116
117
125
126
RA5
108 RA4
109 RA3
107
110 RA2
111 RA1
112 RA0
DR_A0
REFOUT
118
DCSOUT
C19
0.1µF
DCK
HSOUT
VSOUT
Figure 28. Schematic, VGA Digitizer, Single-Port Outputs
DCK and DCK clocks should be timed to strobe data that is
valid between transitions.
VGA Source with Dual Ported Outputs
Shown in Figure 29 is a more complex implementation of a
video digitizer. Incoming RGB video has sync-on-green.
Output data is dual ported. COAST is shown to free wheel
the PLL when horizontal sync is inactive or 2H pulse are
present.
Composite Sync from the Sync Stripper output CSOUT is
supplied to the HSYNC input as a reference for the internal
PLL. CSSOUT contains horizontal and vertical sync signals
that can be extracted by subsequent Sync processing logic. If
the vertical sync pulse omits horizontal sync or if serrations
or equalizing pulses are present, then the sync processing
logic should emit a COAST signal to disengage the PLL
from the HSYNC input during the Vertical Sync interval.
RGB inputs signals are AC coupled to the FMS9884A RGB
inputs with the green input connected to the Sync Separator
input, CVIN.
Output data is three channel dual port data with a maximum
rate of 70Ms/s per port. Port A data is synchronzed to the
negative edge of DCK. Port B data transitions on:
Vertical and horizontal sync waveforms within CSSOUT
signal frame the active video area.
1. Positive edge of DCK in the Parallel Data Out Mode.
2. Negative edge of DCK in the Interleaved Data Out
Mode.
24
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
C1
.047µF
VPLL
VADC
VDD
J1
RED
GREEN
BLUE
1
2
3
4
C2
0.18µF
C3
.047µF
U1
C5
.047µF
R1
75
5
6
7
AD9884
BB [7..0]
C4
0.018µF
33
34
43
48
50
55 BB7
56 BB6
8
9
10
11
12
13
14
PVD
PVD
PVD
PVD
PVD
DB _B7
R2
1.5K
DB _B6
DB _B5
R4
75
57
BB5
R3
75
58 BB4
59 BB3
DB _B4
DB _B3
DB _B2
D B_B1
60 BB2
61 BB1
62 BB0
7
RIN
15
DB _B0
BA [7..0]
GB[7..0]
15
22
27
28
40
GIN
65 BA7
DB _A7
DB _A6
DB _A5
DB _A4
DB _A3
DB _A2
DB _A1
DB _A0
SVGA
66 BA6
67 BA5
68 BA4
69 BA3
70 BA2
71 BA1
BIN
CLKINV
CLAMP
72 BA0
HSIN
41
44
45
29
75 GB7
76 GB6
77 GB5
78 GB4
79 GB3
80 GB2
81 GB1
82 GB0
COAST
COAST
CKEXT
FILT
DG_B7
DG_B6
DG_B5
DG_B4
DG_B3
DG_B2
PWRDN\
SDA
SDA
SCL
A0
DG_B1
DG_B0
GA[7..0]
RB[7..0]
30
31
32
14
SCL
85 GA7
86 GA6
87 GA5
88 GA4
89 GA3
90 GA2
91 GA1
DG_A7
DG_A6
DG_A5
DG_A4
DG_A3
DG_A2
DG_A1
A1
ACSIN
1
2
3
36
37
38
46
92 GA0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
DG_A0
95 RB7
96 RB6
DR_B7
DR_B6
DR_B5
DR_B4
DR_B3
DR_B2
97 RB5
98 RB4
99 RB3
100 RB2
101 RB1
102 RB0
127
115
REFIN
DR_B1
DR_B0
RA[7..0]
105 RA7
106 RA6
107 RA5
108 RA4
109 RA3
110 RA2
111 RA1
112 RA0
DATACK
DATACK
HSOUT
PWRDN
DR_A7
DR_A6
DR_A5
DR_A4
DR_A3
DR_A2
DR_A1
116
117
125
126
DR_A0
REFOUT
118
DCSOUT
C17
0.1µF
DCK
DCK\
HSOUT
Figure 29. Schematic, VGA Digitizer, Dual Port Outputs
3. Layout traces as 75Ω transmission lines.
Printed Wiring Board Design Guidelines
Recommended strategy is to mount the FMS9884A over a
ground plane with carefully routed analog inputs and digital
outputs. All connections should be treated as transmission
lines to ensure that reflections due to mismatches are mini-
mized and ground return currents do not interfere with critical
signals.
4. Avoid running analog traces near digital traces. Due to
the wide input bandwidth (500MHz) digital noise can
easily leak into analog inputs.
5. If necessary, limit bandwidth by adding a ferrite bead in
series with each RGB input as shown in Figure 30. A
Fair-Rite #2508051217Z0 is recommended. Mismatches,
reflections and noise may cause ringing or distortion of
the incoming video signals.
Analog Inputs
Recommendations:
6. Locate the PLL filter clear of other signals.
1. Keep analog trace lengths short to minimize crosstalk.
2. Terminate analog inputs with 75Ω resistors, placed
close to the FMS9884A analog inputs, RIN, GIN and
BIN. By matching transmission line impedances,
reflections will be minimized.
REV. 1.0.2 8/11/00
25
PRODUCT SPECIFICATION
FMS9884A
7. Bypass the reference with a 0.1µF capacitor to ground.
5. If necessary terminate the HSIN input with 330/220Ω.
6. If necessary, to reduce reflections, EMI or spikes add a
L1
BEAD
50–200Ω resistor at each data output pin.
C1
47nF
7. To minimize noise within the FMS9884A, restrict the
capacitive load at the digital outputs to < 10pF.
RIN, GIN, BIN
R,G,B INPUT
R1
75
Power and Ground
A schematic of the recommended power distribution is
shown in Figure 31. Note that:
Figure 30. RGB Input Filter
1. Analog and digital circuits are layed out over a common
solid ground plane.
Digital I/O
Recommendations:
2. Each FMS9884A pin is decoupled with a 0.1µF capaci-
tor.
1. Route digital I/O signals clear of analog inputs.
2. Terminate clock lines to reduce reflections. Treat clock
lines as transmission lines.
3. A group of pins may be de-coupled through a common
capacitor if no pin is more than 5 mm from the capacitor.
3. Scale the HSIN input to 3.3V, using a resistor network
4. A separate regulated supply is used for the phase-locked
or a series 1 kΩ resistor.
loop power supply, V
.
DDP
4. Limit Serial Port inputs SDA and SDL with 150Ω
5. Capacitors are attached to each PLL pin or pin-pair.
resistors connected directly to the pins.
Pins 33, 34
C2
0.01µF
Pin43
C4
0.1µF
Pin48
C6
0.01µF
U1
RC1117-3.3
L1
BEAD
VPLL
2
4
3
Pin 50
OUT
PowerInput
IN
ADJ/GND
+ C7
10µF
C8
0.1µF
OUT
C17
C7
+
1
0.1µF
10µF
L2
BEAD
VADC Pins
C10 C11 C12 C13 C14 C15 C16
C17
+ C9
10µF
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
U2
RC1117-3.3
OUT
L3
BEAD
2
4
3
VDD Pins
IN
ADJ/GND
C18 C19 C20 C21 C22 C23 C24
OUT
C17
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
+
1
C25
10µF
0.1µF
Figure 31. Recommended Power Distribution
26
REV. 1.0.2 8/11/00
FMS9884A
PRODUCT SPECIFICATION
Physical placement of PLL power supply decoupling compo-
nents is critical. Bearing in mind the following suggestions:
3. Each VDDP/GND pin pair: 33&34/35, 43/42, 48/47, and
50/49 should be decoupled with a 100–1000p/10µF pair
of capacitors (see Figure 31). If board space is limited,
use as many capacitor pairs as possible.
1. All components should be placed in close proximity to
the FMS9884A pins.
4. Use Fair-rite 274 301 9447 bead.
2. Routing through vias should be avoided, if possible.
REV. 1.0.2 8/11/00
27
PRODUCT SPECIFICATION
FMS9884A
Mechanical Dimensions
128-Lead MQFP (KA) Package
Notes:
Millimeters
Symbol
Notes
1. All dimensions and tolerances conform to ANSI Y14.5M-1994.
Min.
Typ.
Max
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable mold protrusion is 0.254mm per side.
A
—
3.04
0.33
3.40
—
A1
A2
D
0.25
2.57
3. "N" is the number of terminals.
2.87
2.71
3, 5
4. Dimension "b" does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm in excess of the "b"
dimension at the maximum material condition.
22.60 BSC
20.00 BSC
18.00 BSC
17.20 BSC
14.00 BSC
12.00 BSC
0.70
D1
D2
E
E1
E2
L
0.65
0.13
0.95
0.28
4
N
128
0.50 BSC
e
b
—
E
E1
2
E2
.40 Min.
e
0° Min.
0.13 R Min.
Datum Plane
.13/.30 R
D2
D1/2
0–7°
D
L
1.60 Ref.
Lead Detail
A2
See Lead Detail
Base Plane
A
-C-
B
Seating Plane
A1
LEAD COPLANARITY
ccc
C
28
REV. 1.0.2 8/11/00
PRODUCT SPECIFICATION
FMS9884A
Ordering Information
Product Number
FMS9884AKAC100
FMS9884AKAC140
Temperature Range
0°C to 70°C
Screening
Package
Package Marking
Commercial
128 Lead MQFP
9884AKAC100
9884AKAC140
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
8/11/00 0.0m 006
Stock#DS30009884
2000 Fairchild Semiconductor Corporation
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