FSGL234D1 [ETC]

TRANSISTOR | MOSFET | N-CHANNEL | 250V V(BR)DSS | 7A I(D) | TO-205AF ; 晶体管| MOSFET | N沟道| 250V V( BR ) DSS | 7A I( D) | TO- 205AF\n
FSGL234D1
型号: FSGL234D1
厂家: ETC    ETC
描述:

TRANSISTOR | MOSFET | N-CHANNEL | 250V V(BR)DSS | 7A I(D) | TO-205AF
晶体管| MOSFET | N沟道| 250V V( BR ) DSS | 7A I( D) | TO- 205AF\n

晶体 晶体管 开关 脉冲
文件: 总8页 (文件大小:83K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
FSGL234R  
TM  
Data Sheet  
July 2000  
File Number 4891  
Radiation Hardened, SEGR Resistant  
N-Channel Power MOSFET  
Features  
• 7A, 250V, r  
• UIS Rated  
Total Dose  
= 0.255  
DS(ON)  
Intersil Star*Power Rad Hard  
MOSFETs have been specifically  
TM  
developed for high performance  
applications in a commercial or  
- Meets Pre-RAD Specifications to 100K RAD (Si)  
military space environment.  
Star*Power MOSFETs offer the system designer both  
• Single Event  
- Safe Operating Area Curve for Single Event Effects  
extremely low r  
and Gate Charge allowing the  
DS(ON)  
2
- SEE Immunity for LET of 82MeV/mg/cm with  
development of low loss Power Subsystems. Star*Power  
Gold FETs combine this electrical capability with total dose  
radiation hardness up to 100K RADs while maintaining the  
guaranteed performance for Single Event Effects (SEE)  
which the Intersil FS families have always featured.  
V
up to 80% of Rated Breakdown and  
of 5V Off-Bias  
DS  
V
GS  
• Dose Rate  
- Typically Survives 3E9 RAD (Si)/s at 80% BV  
DSS  
- Typically Survives 2E12 if Current Limited to I  
AS  
The Intersil family of Star*Power FETs includes a series of  
devices in various voltage, current and package styles. The  
portfolio consists of Star*Power and Star*Power Gold  
products. Star*Power FETs are optimized for total dose and  
• Photo Current  
- 4.0nA Per-RAD (Si)/s Typically  
• Neutron  
r
while exhibiting SEE capability at full rated voltage  
DS(ON)  
- Maintain Pre-RAD Specifications  
up to an LET of 37. Star*Power Gold FETs have been  
optimized for SEE and Gate Charge combining SEE  
performance to 80% of the rated voltage for an LET of 82  
with extremely low gate charge characteristics.  
2
for 1E13 Neutrons/cm  
2
- Usable to 1E14 Neutrons/cm  
Symbol  
D
This MOSFET is an enhancement-mode silicon-gate power  
field effect transistor of the vertical DMOS (VDMOS)  
structure. It is specifically designed and processed to be  
radiation tolerant. The MOSFET is well suited for  
applications exposed to radiation environments such as  
switching regulation, switching converters, power  
distribution, motor drives and relay drivers as well as other  
power control and conditioning applications. As with  
conventional MOSFETs these Radiation Hardened  
MOSFETs offer ease of voltage control, fast switching  
speeds and ability to parallel switching devices.  
G
S
Packaging  
TO-205AF  
Reliability screening is available as either TXV or Space  
equivalent of MIL-PRF-19500.  
Formerly available as type TA45232W.  
G
D
S
Ordering Information  
RAD LEVEL SCREENING LEVEL PART NUMBER/BRAND  
10K  
Engineering Samples FSGL234D1  
100K  
100K  
TXV  
FSGL234R3  
FSGL234R4  
Space  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.  
1
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000  
Star*Power™ is a trademark of Intersil Corporation.  
FSGL234R  
o
Absolute Maximum Ratings T = 25 C, Unless Otherwise Specified  
C
FSGL234R  
250  
UNITS  
Drain to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V  
V
V
DS  
Drain to Gate Voltage (R  
GS  
= 20k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
250  
DGR  
Continuous Drain Current  
o
T
T
= 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
7
4
A
A
A
V
C
D
D
o
= 100 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
C
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
28  
±30  
DM  
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V  
GS  
Maximum Power Dissipation  
o
T
T
= 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P  
25  
10  
W
W
C
T
o
= 100 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P  
C
T
o
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . . . . I  
0.20  
28  
W/ C  
A
A
A
AS  
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
7
S
Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I  
28  
SM  
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T , T  
-55 to 150  
300  
C
J
STG  
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T  
(Distance >0.063in (1.6mm) from Case, 10s Max)  
C
L
Weight (Typical)  
1.0 (Typical)  
g
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
o
Electrical Specifications  
T
= 25 C, Unless Otherwise Specified  
C
PARAMETER  
SYMBOL  
BV  
TEST CONDITIONS  
= 1mA, V = 0V  
MIN  
TYP  
MAX  
-
UNITS  
V
Drain to Source Breakdown Voltage  
Gate Threshold Voltage  
I
250  
-
DSS  
D
GS  
o
V
V
= V  
= 1mA  
,
T
T
T
T
T
T
T
= -55 C  
-
-
5.5  
4.5  
-
V
GS(TH)  
GS  
DS  
C
C
C
C
C
C
C
I
o
D
= 25 C  
2.0  
-
V
o
= 125 C  
1.0  
-
-
V
o
Zero Gate Voltage Drain Current  
Gate to Source Leakage Current  
I
V
V
= 200V,  
= 0V  
= 25 C  
-
25  
250  
100  
200  
1.82  
0.255  
0.510  
20  
40  
35  
15  
28  
12  
10  
-
µA  
µA  
nA  
nA  
V
DSS  
DS  
GS  
o
= 125 C  
-
-
o
I
V
= ±30V  
= 25 C  
-
-
GSS  
GS  
o
= 125 C  
-
-
Drain to Source On-State Voltage  
Drain to Source On Resistance  
V
V
= 12V, I = 7A  
-
-
DS(ON)  
GS  
D
o
r
I
= 4A,  
T
T
= 25 C  
-
0.215  
DS(ON)12  
D
C
V
= 12V  
o
GS  
= 125 C  
-
-
C
Turn-On Delay Time  
Rise Time  
t
V
R
R
= 125V, I = 7A,  
-
-
-
ns  
ns  
ns  
ns  
nC  
nC  
nC  
nC  
nC  
V
d(ON)  
DD  
D
= 17.9, V = 12V,  
L
GS  
t
-
r
= 7.5Ω  
GS  
Turn-Off Delay Time  
Fall Time  
t
-
-
d(OFF)  
t
-
-
f
Total Gate Charge  
Gate Charge Source  
Gate Charge Drain  
Gate Charge at 20V  
Threshold Gate Charge  
Plateau Voltage  
Q
V
= 0V to 12V  
V
= 125V,  
-
26  
10  
8
g(12)  
GS  
DD  
= 7A  
I
D
Q
-
gs  
gd  
Q
-
Q
V
= 0V to 20V  
= 0V to 2V  
-
40  
3
g(20)  
g(TH)  
GS  
Q
V
-
-
GS  
V
I
= 7A, V  
= 15V  
-
7
-
(PLATEAU)  
D
DS  
Input Capacitance  
Output Capacitance  
Reverse Transfer Capacitance  
C
V
= 25V, V = 0V,  
GS  
-
1300  
200  
8
-
pF  
pF  
pF  
ISS  
DS  
f = 1MHz  
C
C
-
-
OSS  
RSS  
-
-
o
Thermal Resistance Junction to Case  
R
-
-
5.0  
C/W  
JC  
θ
2
FSGL234R  
Source to Drain Diode Specifications  
PARAMETER  
Forward Voltage  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
1.5  
360  
-
UNITS  
V
V
I
I
= 7A  
-
-
-
-
-
SD  
SD  
Reverse Recovery Time  
Reverse Recovery Charge  
t
= 7A, dI /dt = 100A/µs  
ns  
rr  
SD  
SD  
Q
1.7  
µC  
RR  
o
Electrical Specifications up to 100K RAD T = 25 C, Unless Otherwise Specified  
C
PARAMETER  
Drain to Source Breakdown Volts  
Gate to Source Threshold Volts  
Gate to Body Leakage  
SYMBOL  
BV  
TEST CONDITIONS  
= 0, I = 1mA  
MIN  
MAX  
-
UNITS  
(Note 3)  
V
250  
V
V
DSS  
GS  
D
(Note 3)  
V
V
= V , I = 1mA  
DS  
2.0  
4.5  
GS(TH)  
GS  
D
(Notes 2, 3)  
(Note 3)  
I
V
= ±30V, V  
= 0V  
-
-
-
-
100  
25  
nA  
µA  
V
GSS  
GS  
DS  
Zero Gate Leakage  
I
V
= 0, V  
= 200V  
DSS  
GS DS  
Drain to Source On-State Volts  
Drain to Source On Resistance  
NOTES:  
(Notes 1, 3)  
(Notes 1, 3)  
V
V
= 12V, I = 7A  
1.82  
0.255  
DS(ON)  
GS  
D
r
V
= 12V, I = 4A  
DS(ON)12  
GS  
D
1. Pulse test, 300µs Max.  
2. Absolute value.  
3. Insitu Gamma bias must be sampled for both V  
GS  
= 12V, V  
DS  
= 0V and V  
GS  
= 0V, V  
= 80% BV .  
DSS  
DS  
Single Event Effects (SEB, SEGR) Note 4  
ENVIRONMENT (NOTE 5)  
APPLIED  
(NOTE 6)  
ION  
SPECIES  
TYPICAL LET  
(MeV/mg/cm)  
TYPICAL  
RANGE (µ)  
V
BIAS  
MAXIMUM  
GS  
(V)  
TEST  
SYMBOL  
SEESOA  
V
BIAS (V)  
DS  
Single Event Effects Safe Operating Area  
Br  
I
37  
60  
82  
82  
36  
32  
28  
28  
-20  
-10  
-5  
250  
250  
Au  
Au  
200  
-10  
150  
NOTES:  
4. Testing conducted at Brookhaven National Labs.  
2
o
5. Fluence = 1E5 ions/cm (Typical), T = 25 C.  
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).  
Performance Curves Unless Otherwise Specified  
2
2
LET = 37MeV/mg/cm , RANGE = 36m  
LET = 60MeV/mg/cm , RANGE = 32m  
2
LET = 82MeV/mg/cm , RANGE = 28m  
300  
250  
200  
150  
100  
50  
280  
240  
200  
160  
120  
80  
LET = 37 BROMINE  
2
FLUENCE = 1E5 IONS/cm (TYPICAL)  
LET = 82 GOLD  
40  
LET = 60 IODINE  
o
TEMP = 25 C  
0
0
0
-5 -10 -15 -20 -25 -30 -35 -40 -45 -50  
(V)  
0
-4  
-8  
-12  
(V)  
-16  
-20  
-24  
V
V
GS  
GS  
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA  
FIGURE 2. TYPICAL SEE SIGNATURE CURVE  
3
FSGL234R  
Performance Curves Unless Otherwise Specified (Continued)  
1E-3  
8
6
4
2
0
1E-4  
ILM = 10A  
30A  
1E-5  
100A  
300A  
1E-6  
1E-7  
-50  
0
50  
100  
o
150  
10  
30  
100  
300  
1000  
T
, CASE TEMPERATURE ( C)  
DRAIN SUPPLY (V)  
C
FIGURE 3. TYPICAL DRAIN INDUCTANCE REQUIRED TO  
LIMIT GAMMA DOT CURRENT TO I  
FIGURE 4. MAXIMUM CONTINUOUS DRAIN CURRENT vs  
TEMPERATURE  
AS  
100  
10  
1
o
T
= 25 C  
C
12V  
Q
G
100µs  
1ms  
Q
Q
GD  
GS  
OPERATION IN THIS  
AREA MAY BE  
V
G
10ms  
LIMITED BY r  
DS(ON)  
0.1  
1
10  
100  
1000  
V
, DRAIN TO SOURCE VOLTAGE (V)  
CHARGE  
DS  
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA  
FIGURE 6. BASIC GATE CHARGE WAVEFORM  
2.5  
40  
PULSE DURATION = 250ms, V  
GS  
= 12V, I = 4A  
D
DESCENDING ORDER  
V
= 14V  
= 12V  
= 10V  
= 8V  
2.0  
1.5  
1.0  
0.5  
0.0  
GS  
V
30  
20  
10  
0
GS  
V
GS  
V
GS  
V
= 6V  
GS  
V
= 6 V  
GS  
-80  
-40  
0
40  
80  
120  
160  
0
4
8
12  
16  
20  
o
T , JUNCTION TEMPERATURE ( C)  
V
, DRAIN TO SOURCE VOLTAGE (V)  
J
DS  
FIGURE 7. TYPICAL NORMALIZED r  
TEMPERATURE  
vs JUNCTION  
FIGURE 8. TYPICAL OUTPUT CHARACTERISTICS  
DS(ON)  
4
FSGL234R  
Performance Curves Unless Otherwise Specified (Continued)  
10  
1
0.5  
0.2  
0.1  
0.1  
0.05  
0.02  
0.01  
P
DM  
SINGLE PULSE  
0.01  
NOTES:  
DUTY FACTOR: D = t /t  
t
1
2
1
t
PEAK T = P  
DM  
x Z  
+ T  
2
J
θJC  
C
0.001  
-5  
-4  
-3  
10  
-2  
-1  
10  
0
1
10  
10  
10  
10  
10  
t, RECTANGULAR PULSE DURATION (s)  
FIGURE 9. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE  
100  
o
STARTING T = 25 C  
J
10  
1
o
STARTING T = 150 C  
J
IF R = 0  
AV  
IF R 0  
t
= (L) (I ) / (1.3 RATED BV  
- V  
DD  
)
AS DSS  
t
= (L/R) ln [(I *R) / (1.3 RATED BV  
- V ) + 1]  
DD  
AV  
AS  
DSS  
1
0.1  
0.01  
0.1  
10  
t
, TIME IN AVALANCHE (ms)  
AV  
FIGURE 10. UNCLAMPED INDUCTIVE SWITCHING  
Test Circuits and Waveforms  
ELECTRONIC SWITCH OPENS  
WHEN I IS REACHED  
AS  
V
DS  
L
BV  
+
I
-
DSS  
CURRENT  
TRANSFORMER  
AS  
t
P
V
DS  
I
AS  
V
VARY t TO OBTAIN  
DD  
P
+
50Ω  
REQUIRED PEAK I  
AS  
V
DD  
V
20V  
GS  
-
50V-150V  
DUT  
50Ω  
t
P
0V  
t
AV  
FIGURE 11. UNCLAMPED ENERGY TEST CIRCUIT  
FIGURE 12. UNCLAMPED ENERGY WAVEFORMS  
5
FSGL234R  
Test Circuits and Waveforms (Continued)  
t
t
ON  
OFF  
t
d(OFF)  
V
DD  
t
d(ON)  
t
t
f
r
R
L
V
DS  
90%  
90%  
V
DS  
V
= 12V  
GS  
10%  
10%  
DUT  
0V  
90%  
50%  
R
GS  
50%  
V
GS  
PULSE WIDTH  
10%  
FIGURE 13. RESISTIVE SWITCHING TEST CIRCUIT  
FIGURE 14. RESISTIVE SWITCHING WAVEFORMS  
Screening Information  
Screening is performed in accordance with the latest revision in effect of MIL-PRF-19500, (Screening Information Table).  
o
Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent) T = 25 C, Unless Otherwise Specified  
C
PARAMETER  
Gate to Source Leakage Current  
Zero Gate Voltage Drain Current  
Drain to Source On Resistance  
Gate Threshold Voltage  
NOTES:  
SYMBOL  
TEST CONDITIONS  
= ±30V  
GS  
MAX  
UNITS  
nA  
I
V
±20 (Note 7)  
±25 (Note 7)  
±20% (Note 8)  
±20% (Note 8)  
GSS  
I
V
= 80% Rated Value  
o
µA  
DSS  
DS  
r
T
= 25 C at Rated I  
D
DS(ON)  
C
V
I
= 1.0mA  
V
GS(TH)  
D
7. Or 100% of Initial Reading (whichever is greater).  
8. Of Initial Reading.  
Screening Information  
TEST  
JANTXV EQUIVALENT  
JANS EQUIVALENT  
= 20V, L = 0.1mH; Limit = 28A  
Unclamped Inductive Switching  
Thermal Response  
Gate Stress  
V
= 20V, L = 0.1mH; Limit = 28A  
V
GS(PEAK)  
GS(PEAK)  
t
= 10ms; V = 25V; I = 1A; LIMIT = 60mV  
t
= 10ms; V = 25V; I = 1A; LIMIT = 60mV  
H
H
H
H
H
H
V
= 45V, t = 250µs  
V
= 45V, t = 250µs  
GS  
GS  
Pind  
Optional  
Required  
MIL-PRF-19500 Group A,  
Subgroup 2 (All Static Tests at 25 C)  
Pre Burn-In Tests (Note 9)  
MIL-PRF-19500 Group A,  
Subgroup 2 (All Static Tests at 25 C)  
o
o
Steady State Gate  
Bias (Gate Stress)  
MIL-PRF-750, Method 1042, Condition B  
MIL-PRF-750, Method 1042, Condition B  
V
= 80% of Rated Value,  
V
= 80% of Rated Value,  
GS  
GS  
o
o
T = 150 C, Time = 48 hours  
T = 150 C, Time = 48 hours  
A
A
Interim Electrical Tests (Note 9)  
All Delta Parameters Listed in the Delta Tests  
and Limits Table  
All Delta Parameters Listed in the Delta Tests  
and Limits Table  
Steady State Reverse  
Bias (Drain Stress)  
MIL-PRF-750, Method 1042, Condition A  
MIL-PRF-750, Method 1042, Condition A  
V
= 80% of Rated Value,  
V
= 80% of Rated Value,  
DS  
DS  
o
o
T = 150 C, Time = 160 hours  
T = 150 C, Time = 240 hours  
A
A
PDA  
10%  
5%  
Final Electrical Tests (Note 9)  
MIL-PRF-19500, Group A, Subgroup 2  
MIL-PRF-19500, Group A,  
Subgroups 2 and 3  
NOTE:  
9. Test limits are identical pre and post burn-in.  
Additional Tests  
PARAMETER  
Safe Operating Area  
Thermal Impedance  
SYMBOL  
TEST CONDITIONS  
= 200V, t = 10ms  
MAX  
0.30  
230  
UNITS  
A
SOA  
V
DS  
= 500ms; V = 25V; I = 1A  
V  
SD  
t
mV  
H
H
H
6
FSGL234R  
Rad Hard Data Packages - Intersil Power Transistors  
TXV Equivalent  
Class S - Equivalents  
1. RAD HARD TXV EQUIVALENT - STANDARD DATA  
PACKAGE  
1. RAD HARD “S” EQUIVALENT - STANDARD DATA  
PACKAGE  
A. Certificate of Compliance  
A. Certificate of Compliance  
B. Serialization Records  
C. Assembly Flow Chart  
D. SEM Photos and Report  
B. Assembly Flow Chart  
C. Preconditioning - Attributes Data Sheet  
D. Group A  
E. Group B  
F. Group C  
G. Group D  
- Attributes Data Sheet  
- Attributes Data Sheet  
- Attributes Data Sheet  
- Attributes Data Sheet  
E. Preconditioning - Attributes Data Sheet  
- HTRB - Hi Temp Gate Stress Post  
Reverse Bias Data and Delta Data  
- HTRB - Hi Temp Drain Stress Post  
Reverse Bias Delta Data  
2. RAD HARD TXV EQUIVALENT - OPTIONAL DATA  
PACKAGE  
F. Group A  
G. Group B  
H. Group C  
I. Group D  
- Attributes Data Sheet  
- Attributes Data Sheet  
- Attributes Data Sheet  
- Attributes Data Sheet  
A. Certificate of Compliance  
B. Assembly Flow Chart  
C. Preconditioning - Attributes Data Sheet  
- Pre and Post Burn-In Read and Record  
Data  
2. RAD HARD MAX. “S” EQUIVALENT - OPTIONAL  
DATA PACKAGE  
D. Group A  
E. Group B  
- Attributes Data Sheet  
A. Certificate of Compliance  
B. Serialization Records  
C. Assembly Flow Chart  
D. SEM Photos and Report  
- Attributes Data Sheet  
- Pre and Post Read and Record Data for  
Intermittent Operating Life (Subgroup B3)  
- Bond Strength Data (Subgroup B3)  
- Pre and Post High Temperature Operating  
Life Read and Record Data (Subgroup B6)  
E. Preconditioning - Attributes Data Sheet  
- HTRB - Hi Temp Gate Stress Post  
Reverse Bias Data and Delta Data  
- HTRB - Hi Temp Drain Stress Post  
Reverse Bias Delta Data  
F. Group C  
G. Group D  
- Attributes Data Sheet  
- Pre and Post Read and Record Data for  
Intermittent Operating Life (Subgroup C6)  
- Bond Strength Data (Subgroup C6)  
- X-Ray and X-Ray Report  
- Attributes Data Sheet  
F. Group A  
G. Group B  
H. Group C  
I. Group D  
- Attributes Data Sheet  
- Subgroups A2, A3, A4, A5 and A7 Data  
- Pre and Post RAD Read and Record Data  
- Attributes Data Sheet  
- Subgroups B1, B3, B4, B5 and B6 Data  
- Attributes Data Sheet  
- Subgroups C1, C2, C3 and C6 Data  
- Attributes Data Sheet  
- Pre and Post Radiation Data  
7
FSGL234R  
TO-205AF  
3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE  
ØD  
INCHES  
MIN  
MILLIMETERS  
ØD  
1
SYMBOL  
MAX  
0.180  
0.021  
0.370  
0.355  
0.105  
0.210  
0.105  
0.020  
0.034  
0.045  
0.560  
-
MIN  
4.07  
0.41  
8.64  
8.01  
2.42  
4.83  
2.42  
0.26  
0.72  
0.74  
12.70  
1.78  
MAX  
4.57  
0.53  
9.39  
9.02  
2.66  
5.33  
2.66  
0.50  
0.86  
1.14  
14.22  
-
NOTES  
P
A
0.160  
0.016  
0.340  
0.315  
0.095  
0.190  
0.095  
0.010  
0.028  
0.029  
0.500  
0.070  
-
2, 3  
-
A
Øb  
ØD  
SEATING  
PLANE  
h
ØD  
e
-
1
L
Øb  
4
4
4
-
e
e
1
e
2
e
1
h
j
-
o
90  
2
k
-
e
2
1
3
L
P
3
5
o
45  
j
k
NOTES:  
1. These dimensions are within allowable dimensions of Rev. E of  
JEDEC TO-205AF outline dated 11-82.  
2. Lead dimension (without solder).  
3. Solder coating may vary along lead length, add typically 0.002  
inches (0.05mm) for solder coating.  
4. Position of lead to be measured 0.100 inches (2.54mm) from bottom  
of seating plane.  
5. This zone controlled for automatic handling. The variation in  
actual diameter within this zone shall not exceed 0.010 inches  
(0.254mm).  
6. Lead no. 3 butt welded to stem base.  
7. Controlling dimension: Inch.  
8. Revision 4 dated 6-00.  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-  
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site www.intersil.com  
Sales Office Headquarters  
NORTH AMERICA  
EUROPE  
ASIA  
Intersil Corporation  
Intersil SA  
Intersil Ltd.  
P. O. Box 883, Mail Stop 53-204  
Melbourne, FL 32902  
TEL: (321) 724-7000  
FAX: (321) 724-7240  
Mercure Center  
8F-2, 96, Sec. 1, Chien-kuo North,  
Taipei, Taiwan 104  
Republic of China  
TEL: 886-2-2515-8508  
FAX: 886-2-2515-8369  
100, Rue de la Fusee  
1130 Brussels, Belgium  
TEL: (32) 2.724.2111  
FAX: (32) 2.724.22.05  
8

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