FT5206 [ETC]
True Multi-Touch Capacitive Touch Panel Controller;型号: | FT5206 |
厂家: | ETC |
描述: | True Multi-Touch Capacitive Touch Panel Controller |
文件: | 总21页 (文件大小:4540K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FT5x06
True Multi-Touch
Capacitive Touch Panel Controller
INTRODUCTION
The FT5x06 Series ICs are single-chip capacitive touch panel controller ICs with a built-in 8 bit Micro-controller unit (MCU).They
adopt the mutual capacitance approach, which supports true multi-touch capability. In conjunction with a mutual capacitive touch
panel, the FT5x06 have user-friendly input functions, which can be applied on many portable devices, such as cellular phones, MIDs,
netbook and notebook personal computers.
The FT5x06 series ICs include FT5206/FT5306/FT5406, the difference of their specifications will be listed individually in this
datasheet.
FEATURES
Capable of Driving Single Channel (transmit/receive) Re-
Mutual Capacitive Sensing Techniques
sistance: Up to15K Ω
True Multi-touch with up to 10 Points of Absolution X and
Capable of Supporting Single Channel (transmit/receive)
Y Coordinates
Capacitance: 60 pF
Immune to RF Interferences
Optimal Sensing Mutual Capacitor: 1pF~4pF
12-Bit ADC Accuracy
Auto-calibration: Insensitive to Capacitance and Environ-
mental Variations
Built-in MCU with 28KB Program Memory, 6KB Data
Supports up to 28 Transmit Lines and 16 Receive Lines
Supports up to 8” Touch Screen
Memory and 256B Internal Data Space
11 Internal Interrupt Sources and 2 External Interrupt
Sources
Full Programmable Scan Sequences with Individual Ad-
justable Receive Lines and Transmit Lines to Support
Various Applications
3 Operating Modes
Active
Monitor
Hibernate
High Report Rate: More than 100Hz
Touch Resolution of 100 Dots per Inch (dpi) or above --
depending on the Panel Size
Operating Temperature Range: -20°C to +85°C
Optional Interfaces :I2C/SPI
2.8V to 3.6V Operating Voltage
Supports 1.8V/AVDD IOVCC
FocalTech Systems Co., Ltd
·
www.focaltech-systems.com
·
support@focaltech-systems.com
Document Number: D-FT5x06-1212-V4.0 (Version: 4.0)
Revised Dec. 18, 2012
From No.: F-OI-RD01-03-03-B
FT5x06
DATASHEET
TABLE OF CONTENTS
INTRODUCTION.....................................................................................................................................................I
FEATURES...............................................................................................................................................................I
1
OVERVIEW......................................................................................................................................................... 1
1.1
TYPICAL APPLICATIONS ................................................................................................................................... 1
2
FUNCTIONAL DESCRIPTION .............................................................................................................................. 1
2.1
MCU........................................................................................................................................................... 2
OPERATION MODES........................................................................................................................................ 2
HOST INTERFACE............................................................................................................................................ 3
SERIAL INTERFACE ......................................................................................................................................... 3
2.2
2.3
2.4
2.4.1
2.4.2
I2C ..................................................................................................................................................... 3
SPI..................................................................................................................................................... 4
3
ELECTRICAL SPECIFICATIONS ........................................................................................................................................... 8
3.1
3.2
3.3
ABSOLUTE MAXIMUM RATINGS ...................................................................................................................................... 8
DC CHARACTERISTICS............................................................................................................................................... 9
AC CHARACTERISTICS............................................................................................................................................... 9
3.4
3.5
I/OPORTSCIRCUITS ................................................................................................................................................10
POWER ON/RESET/WAKE SEQUENCE ..............................................................................................................................11
4
5
PIN CONFIGURATIONS..................................................................................................................................................12
PACKAGE INFORMATION...............................................................................................................................................15
5.1
PACKAGE INFORMATION OF QFN-5X5-40L PACKAGE .................................................................................................................15
PACKAGE INFORMATION OF QFN-6X6-48L PACKAGE .................................................................................................................16
PACKAGE INFORMATION OF QFN-6X6-56L PACKAGE..................................................................................................................17
PACKAGE INFORMATION OF QFN-8X8-68L PACKAGE..................................................................................................................18
ORDER INFORMATION...............................................................................................................................................19
5.2
5.3
5.4
5.5
FocalTech Systems Co., Ltd
·
www.focaltech-systems.com
·
support@focaltech-systems.com
Document Number: D-FT5x06-1212-V4.0 (Version: 4.0)
Revised Dec. 18, 2012
From No.: F-OI-RD01-03-03-B
1
OVERVIEW
1.1
Typical Applications
FT5x06 accommodate a wide range of applications with a set of buttons up to a 2D touch sensing device, their typical applications are
listed below.
Mobile phones, smart phones
MIDs
Netbook
Navigation systems, GPS
Game consoles
Car applications
POS (Point of Sales) devices
Portable MP3 and MP4 media players
Digital cameras
FT5x06 Series ICs support < 8.0” Touch Panel, users may find out their target IC from the specs listed in the following table,
Panel
RX
Package
Pin
Recommended
Pitch
Model Name
Touch Panel Size
TX
Type
Size
~5mm
~5mm
~5mm
~6mm
FT5206GE1
FT5306DE4
FT5406DQ9
FT5406EE8
15
10
12
16
16
QFN5*5
40
48
56
68
0.75-P0.4
≤3.7"
≤5.0"
≤7.0"
≤8.0"
20
26
28
QFN6*6
QFN6*6
QFN8*8
0.75-P0.4
0.55-P0.35
0.75-P0.4
Remarks: FocalTech suggests to use pitch between 4.0mm to 6.0mm; The customer can decide the pitch based on applications.
2
FUNCTIONAL DESCRIPTION
Architectural OverviewFigure2-1 shows the overall architecture for the FT5x06.
Figure 2-1 FT5x06 System Architecture Diagram
The FT5x06 is comprised of five main functional parts listed below,
Touch Panel Interface Circuits
The main function for the AFE and AFE controller is to interface with the touch panel. It scans the panel by sending AC signals to the
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panel and processes the received signals from the panel. So, it supports both Transmit (TX) and Receive (RX) functions. Key pa-
rameters to configure this circuit can be sent via serial interfaces, which will be explained in detail in a later section.
8051-based MCU
This MCU is 8051 compatible with some enhancements. For instant, larger program and data memories are supported. In addition, a
Multiplication-Division unit (MDU) is implemented to speed up the touch detection algorithms. Furthermore, a Flash ROM is im-
plemented to store programs and some key parameters.
Complex signal processing algorithms are implemented with firmware running on this MCU to process further the received signals in
order to detect the touches reliably. Communication protocol software is also implemented on this MCU to exchange data and control
information with the host processor.
External Interface
I2C/SPI: an interface for data exchange with host
INT: an interrupt signal to inform the host processor that touch data is ready for read
WAKE: an interrupt signal for the host to change FT5x06 from Hibernate to Active mode
/RST: an external low signal reset the chip.
A watch dog timer is implemented to ensure the robustness of the chip.
A voltage regulator to generate 1.8V for digital circuits from the input VDD3 supply
Power On Reset (POR) is active until VDDD is higher than some level and hold decades of μs.
2.1
MCU
This section describes some critical features and operations supported by the 8051 compatible MCU.
Figure 2-2 shows the overall structure of the MCU block. In addition to the 8051 compatible MCU core, we have added the following
circuits,
MDU: A 16x8 Multiplier and A 32/32 Divider
Program Memory: 28KB Flash
Data Memory: 6KB SRAM
Real Time Clock (RTC): A 32KHz RC Oscillator
Timer: A number of timers are available to generate different clocks
Master Clock: 24/ 48MHz from a 48MHz RC Oscillator
Clock Manager: To control various clocks under different operation conditions of the system
Figure 2-2 MCU Block Diagram
2.2
Operation Modes
FT5x06 operates in the following three modes:
Active Mode
When in this mode, FT5x06 actively scans the panel. The default scan rate is 60 frames per second. The host processor can configure
FT5x06 to speed up or to slow down.
Monitor Mode
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When in this mode, FT5x06 scans the panel at a reduced speed. The default scan rate is 25 frames per second and the host processor
can increase or decrease this rate. When in this mode, most algorithms are stopped. A simpler algorithm is being executed to determine
if there is a touch or not. When a touch is detected, FT5x06 shall enter the Active mode immediately to acquire the touch information
quickly. During this mode, the serial port is closed and no data shall be transferred with the host processor.
Hibernate Mode
In this mode, the chip is set in a power down mode. It shall only respond to the “WAKE” or “RESET” signal from the host processor.
The chip therefore consumes very little current, which help prolong the standby time for the portable devices.
2.3
Host Interface
Figure 2-3 shows the interface between a host processor and FT5x06. This interface consists of the following three sets of signals:
Serial Interface
Interrupt from FT5x06 to the Host
Wake-up Signal from the Host to FT5x06
TPModule
Serial
Interface
TX
RX
FT5x06
TP
Host
/INT
/WAKE
Figure 2-3 Host Interface Diagram
The serial interfaces of FT5x06 is I2C or SPI. The details of this interface are described in detail in Section 2.5. The interrupt signal
(/INT) is used for FT5x06 to inform the host that data are ready for the host to receive. The /WAKE signal is used for the host to wake
up FT5x06 from the Hibernate mode. After exiting the Hibernate mode, FT5x06 shall enter the Active mode.
2.4
Serial Interface
FT5x06 supports the I2C or SPI interfaces, which can be used by a host processor or other devices.
2.4.1
I2C
The I2C is always configured in the Slave mode. The data transfer format is shown in Figure 2-4.
Figure 2-4 I2C Serial Data Transfer Format
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Figure 2-5 I2C master write, slave read
Figure 2-6 I2C master read, slave write
Table 2-1 lists the meanings of the mnemonics used in the above figures.
Table 2-1 Mnemonics Description
Mnemonics
Description
S
I2C Start or I2C Restart
Slave address
A[6:0]
A[6:4]: 3’b011
A[3:0]: data bits are identical to those of I2CCON[7:4] register.
W
R
1’b0: Write
1’b1: Read
A(N)
P
ACK(NACK)
STOP: the indication of the end of a packet (if this bit is missing, S will indicate the end
of the current packet and the beginning of the next packet)
I2C Interface Timing Characteristics is shown in Table 2-2.
Table 2-2 I2C Timing Characteristics
Parameter
Unit
KHz
Min
Max
400
SCL frequency
0
Bus free time between a STOP and START condition
Hold time (repeated) START condition
Data setup time
us
us
ns
us
us
4.7
4.0
250
4.7
4.0
\
\
\
\
\
Setup time for a repeated START condition
Setup Time for STOP condition
2.4.2
SPI
SPI is a 4 wire serial interface. The following is a list of the 4 wires:
SCK: serial data clock
MOSI: data line from master to slave
MISO: data line from slave to master
SLVESEL: active low select signal
SPI transfers data at 8bit packets. The phase relationship between the data and the clock can be defined by the two registers: phase and
polck. Some data transfer examples can be found in Figure 2-7 to Figure 2-10.
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Figure 2-7 SPI Data Transfer Format (Phase=0, POLCK=0)
Figure 2-8 SPI Data Transfer Format (PHASE=0, POLCK=1)
Figure 2-9 SPI Data Transfer Format (Phase=1, POLCK=0)
Figure 2-10 SPI Data Transfer Format (Phase=1, POLCK=1)
SPI can be configured into either Master or Slave mode via the MAS bit of the SPI0CON register. When in the Master mode, the SPI
needs to supply the data clock, whose frequency relationship with the Master clock can be set by CLKDVD bits of the SPI0CON
register. When it is configured in the Slave mode, the clock, SCK, is supplied by the external Master. The maximum data clock fre-
Fmclk
quency must not be higher than
.
8
SPI Interface Timing Characteristics is shown in the following Figure2-11,Figure2-12, Figure2-13, Figure2-14 and Table 2-3.
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Figure 2-11 SPI master Timing PHASE =0
PHASE=1
Tmck
h
Tmckl
SCK(POLCK=0)
SCK(POLCK=1)
Tmh
Tmo
MOSI
MISO
Tmsr
c
SLVSEL
Tmsfc
Figure 2-12 SPI master Timing PHASE =1
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Figure 2-13 SPI slave Timing PHASE = 0
PHASE=1
Tsck
h
Tsckl
SCK(POLCK=0)
SCK(POLCK=1)
T
s
Th
MOSI
MISO
To
Tsr
c
SLVSEL
Tsfc
Figure 2-14 SPI slave Timing PHASE = 1
Table 2-3 SPI Timing Parameters
Parameter
Description
Min
Max
Units
Master Mode timing (see figure 2-11,2-12)
Tmckh
Tmckl
sck high time
sck low time
--
--
ns
ns
4×Tsysclk
4×Tsysclk
0
Tmo
Tmh
sck shift edge to mosi data change
mosi data valid to sck shift edge
--
--
ns
ns
3×Tsysclk
Tsd
slvsel falling edge to mosi data valid
--
ns
4×Tsysclk
Tmsfc
Tmsrc
slvsel falling edge to first sck edge
last sck edge to slvsel rising edge
(Tmckh+Tmckl)/2
(Tmckh+Tmckl)/2
--
--
ns
ns
Slave mode timing(See figure 2-13,2-14)
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Tsckh
Tsckl
sck high Time
sck low Time
--
--
ns
ns
4×Tsysclk
4×Tsysclk
Tsd
Ts
slvsel falling edge to Miso valid data time
Mosi Data valid to sck sample edge
sck sample edge to Mosi data change
0
4xTsysclk
ns
ns
ns
0
--
--
Th
4×Tsysclk
0
To
sck shift edge to Miso data change
slvsel falling edge to first sck edge
4xTsysclk
--
ns
ns
Tsfc
4×Tsysclk
Tsrc
last sck edge to slvsel rising edge
--
ns
4×Tsysclk
*Tsysclk is equal to one period of the device system clock
3
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
3.1
Table 3-1 Absolute Maximum Ratings
Item
Symbol
VDDA - VSSA
VDD3 – VSS
Vt
Unit
V
Value
-0.3 ~ +3.6
Note
1, 2
1, 3
1,4
1
Power Supply Voltage 1
Power Supply Voltage 2
I/O Power Supply Voltage
Operating Temperature
Storage Temperature
V
-0.3 ~ +3.6
V
-0.3 ~ IOVCC + 0.3
-20 ~ +85
Topr
℃
℃
Tstg
-55 ~ +150
1
Notes
1. If used beyond the absolute maximum ratings, FT5x06 may be permanently damaged. It is strongly recommended that the device be
used within the electrical characteristics in normal operations. If exposed to the condition not within the electrical characteristics, it
may affect the reliability of the device.
2. Make sure VDDA (high)
≥VSSA (low)
3. Make sure VDD (high)
≥VSS (low)
4. IOVCC is set to VDD3 or VDDD by software configuration.
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3.2
DC Characteristics
Table 3-2 DC Characteristics (VDDA=VDD3=2.8~3.6V, Ta=-20~85℃)
Item
Symbol
Unit
Test Condition
Min.
Typ.
Max.
Note
Input high-level voltage
Input low -level voltage
Output high -level voltage
Output low -level voltage
I/O leakage current
VIH
V
0.7 x IOVCC
--
--
--
--
--
IOVCC
VIL
VOH
VOL
ILI
V
-0.3
0.3 x IOVCC
V
IOH=-0.1mA
0.7 x IOVCC
--
V
IOH=0.1mA
--
0.3 x IOVCC
1
μA
Vin=0~VDDA
-1
Current consumption
(Normal operation mode)
Current consumption
(Monitor mode)
VDDA=VDD3 = 2.8V
Ta=25℃ MCLK=24MHz
VDDA=VDD3 = 2.8V
Ta=25℃ MCLK=24MHz
Iopr
mA
mA
--
--
6
4
--
--
Imon
Current consumption
(Sleep mode)
VDDA=VDD3 = 2.8V
Ta=25℃ MCLK=24MHz
Islp
mA
--
0.03
--
Step-up output voltage
Power Supply voltage
VDD5
V
V
VDDA=VDD3= 2.8V
5
5.25
--
5.5
3.6
VDDA
VDD3
2.8
3.3
AC Characteristics
Table 3-3 AC Characteristics of Oscillators
Item
Symbol
Unit
MHz
KHz
Test Condition
VDD3 = 2.8V
Ta=25℃
Min.
43
29
Typ.
48
32
Max.
Note
OSC clock 1
OSC clock 2
fosc1
52
VDD3 = 2.8V
Ta=25℃
fosc2
36
Table 3-4 AC Characteristics of TX & RX
Item
Symbol
Unit
Test Condition
Min
Typ
Max
Note
TX acceptable clock
TX output rise time
TX output fall time
RX input voltage
ftx
KHz
100
150
270
Ttxr
Ttxf
Trxi
nS
nS
V
--
--
20
20
--
--
--
1.2
1.6
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3.4
I/OPortsCircuits
Figure 3-1 Digital Input & Output Port Circuits
Figure 3-2 Digital In/Out Port Circuit
Figure 3-3 Reset Input Port Circuits
Figure 3-4 Wake Input Port Circuits
Figure 3-5 INT output Port Circuits
Figure 3-6 SCL/SDA Port Circuits
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3.5
POWER ON/Reset/Wake Sequence
Reset and GPIO such as Wake, INT and I2C are advised to be low before powering on. The signal of waking up should be set to be
high after powering on. INT signal will be sent to the host after initializing all parameters and then start to report points to the host. If
Power is down, the voltage of supply must be below 0.3V and Trst is more than 5ms.
T r i s
P ow e r
Figure 3-7 Power on time
T r s t
P o w e r
0 . 3 V
Figure 3-8 Power Cycle requirement
T rtp
T vdr
T vd r
Tpo n
VDD
Reset
Wake
INT
I2C/SP I
Figure 3-9 Power on / down Sequence
Reset time must be enough to guarantee reliable reset, the time of starting to report point after resetting approach to the time of
starting to report point after powering on.
Trsi
Trst
Power
RESET
INT
I2C/SPI
Figure 3-10 Reset Sequence
Wake time must be enough to wake up the system, the time of starting to report point after waking approach to the time of starting to
report point after powering on
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T w a i
T w a k
P o w e r
W a k e u p
I N T
I 2 C / S P I
Figure 3-11 Wake Sequence
Table 3-5 Power on/Reset/Wake Sequence Parameters
Parameter
Description
Min
Max
Units
Tris
Trtp
Tpon
Tvdr
Trsi
Rise time from 0.1VDD to 0.9VDD
Time of resetting to be low before powering on
Time of starting to report point after powering on
Reset time after VDD powering on
Time of starting to report point after resetting
Reset time
--
100
400
1
5
ms
μs
ms
ms
ms
ms
ms
ms
--
--
--
--
--
--
--
400
5
Trst
Twai
Twak
Time of starting to report point after waking
Wake up time
300
5
4
PIN CONFIGURATIONS
Pin List of FT5x06
Table 4-1 Pin Definition of FT5x06
Pin No.
Name
Type
Description
FT5206GE1
FT5306DE4
FT5406DQ9
FT5406EE8
VSSA
NC
40
1
1
2
56
1
2
PWR
Analog ground
Not connected
Not connected
NC
48
3
TX28
TX27
TX26
TX25
TX24
TX23
TX22
TX21
TX20
TX19
TX18
TX17
TX16
TX15
TX14
TX13
TX12
4
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
5
1
2
6
7
3
8
4
9
5
10
11
12
13
14
15
16
17
18
19
20
6
3
4
7
8
5
9
6
10
11
12
13
14
15
7
2
3
4
5
8
9
10
11
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TX11
TX10
TX9
TX8
TX7
TX6
TX5
TX4
TX3
TX2
TX1
6
12
13
14
15
16
17
18
19
20
21
22
16
17
18
19
20
21
22
23
24
25
26
21
22
23
24
25
26
27
28
29
30
31
O
O
O
O
O
O
O
O
O
O
O
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
Transmit output pin
7
8
9
10
11
12
13
14
15
16
Transmit output pin
internal generated 5V power supply,A 1μF
ceramic capacitor to ground is required.
VDD5
17
23
27
32
PWR
VDD3
VSS
18
19
24
25
28
29
33
34
PWR
PWR
Analog power supply
Analog ground
Digital power supply (1.8V), generated in-
ternal. A 1μF ceramic capacitor to ground is
required.
VDDD
20
21
26
27
30
31
35
PWR
Test mode enabled at high and float in normal
mode
TEST_EN
36
I
GPIO0
GPIO1
GPIO2
GPIO3
37
38
39
40
I/O
I/O
I/O
I/O
General Purpose Input/Output port
General Purpose Input/Output port
General Purpose Input/Output port
General Purpose Input/Output port
SPI Slave mode, chip select, active low / I2C
clock input
SSEL/SCL
SCK/GPIO
MOSI/SDA
22
23
24
28
29
30
32
33
34
41
42
43
I/O
I
SPI Slave mode, clock input / General Pur-
pose Input/Output port
SPI Slave mode, data input / I2C data input
and output
I/O
MISO
/RST
WAKE
INT
25
26
27
28
31
32
33
34
35
36
37
38
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
O
I
SPI Slave mode, data output
External Reset, Low is active
External interrupt from the host
External interrupt to the host
Not connected
I
O
NC
NC
Not connected
NC
Not connected
NC
Not connected
VDDA
RX1
RX2
RX3
RX4
RX5
RX6
RX7
RX8
RX9
30
29
31
32
33
34
35
36
37
38
35
36
37
38
39
40
41
42
43
44
39
40
41
42
43
44
45
46
47
48
PWR
Analog power supply
I
I
I
I
I
I
I
I
I
Receiver input pins
Receiver input pins
Receiver input pins
Receiver input pins
Receiver input pins
Receiver input pins
Receiver input pins
Receiver input pins
Receiver input pins
HIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO FOCALTECH SYSTEMS CO.,LTD., AND MAY NOT BE
REPRODUCED, DISCLOSED OR USED IN WHOLE OR PART WITHOUT THE EXPRESS WRITTEN PERMISSION OF
FOCALTECH SYSTEMS CO.,LTD.
Copyright © 2012, FocalTech Systems CO.,Ltd . All rights reserved
Version 3.0︱Page 13 of 21
RX10
RX11
RX12
RX13
RX14
RX15
RX16
39
45
46
47
49
50
51
52
53
54
55
62
63
64
65
66
67
68
I
I
I
I
I
I
I
Receiver input pins
Receiver input pins
Receiver input pins
Receiver input pins
Receiver input pins
Receiver input pins
Receiver input pins
FT5206GE1 Package Diagram
FT5306DE4 Package Diagram
1
VSSA
NC
51
NC
NC
NC
NC
2
50
49
48
1
TX26
42
NC
TX28
3
4
RX3
RX2
2
3
4
TX25
TX24
TX23
TX22
TX21
TX20
41
40
39
38
37
36
TX27
TX26
5
6
47
46
INT
RX1
WAKE
VDDA
7
8
5
6
7
8
TX25
TX24
TX23
TX22
TX21
TX20
45
44
INT
WAKE
/RST
/RST
MISO
9
43
42
41
40
39
38
MOSI/SDA
SCK
MISO
35
34
10
11
12
13
14
TX19
TX18
TX17
MOSI/SDA
SCK
9
SSEL/SCL
GPIO3
33
10
11
12
13
14
TX16
TX15
32 SSEL/SCL
TEST_EN
31
TX19
TX18
TX17
GPIO2
GPIO1
TX14
TX13
30
GPIO0
15
16
VDDD
37
36
29
TX16
TX15
VSS
TEST_EN
VDDD
17
35
FT5406DQ9 Package Diagram
FT5406EE8 Package Diagram
HIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO FOCALTECH SYSTEMS CO.,LTD., AND MAY NOT BE
REPRODUCED, DISCLOSED OR USED IN WHOLE OR PART WITHOUT THE EXPRESS WRITTEN PERMISSION OF
FOCALTECH SYSTEMS CO.,LTD.
Copyright © 2012, FocalTech Systems CO.,Ltd . All rights reserved
Version 3.0︱Page 14 of 21
5
PACKAGE INFORMATION
Package Information of QFN-5x5-40L Package
5.1
Millimeter
Type
Item
Symbol
Min
Max
A
0.7
0.75
0.8
Total Thickness
Stand Off
A1
A2
A3
b
0
----
0.035
0.55
0.05
0.57
Mold Thickness
L/F Thickness
0.203 REF
0.20
0.15
0.25
Lead Width
Body Size
Lead Pitch
EP Size
D
E
e
J
5 BSC
5 BSC
0.4 BSC
3.6
3.5
3.5
3.7
3.7
K
3.6
Lead Length
L
0.35
0.4
0.45
aaa
bbb
0.1
0.1
Package Edge Tolerance
Mold Flatness
0.08
Co Planarity
Lead Offset
ccc
ddd
0.1
0.1
eee
Exposed Pad Offset
HIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO FOCALTECH SYSTEMS CO.,LTD., AND MAY NOT BE
REPRODUCED, DISCLOSED OR USED IN WHOLE OR PART WITHOUT THE EXPRESS WRITTEN PERMISSION OF
FOCALTECH SYSTEMS CO.,LTD.
Copyright © 2012, FocalTech Systems CO.,Ltd . All rights reserved
Version 3.0︱Page 15 of 21
5.2
Package Information of QFN-6x6-48L Package
Millimeter
Type
Item
Symbol
Min
Max
Total Thickness
Stand Off
A
A1
A2
A3
b
0.7
0
0.75
0.035
0.55
0.8
0.05
0.57
Mold Thickness
L/F Thickness
Lead Width
----
0.203 REF
0.20
0.15
0.25
D
6 BSC
6 BSC
0.4 BSC
4.2
Body Size
Lead Pitch
EP Size
E
e
J
4.1
4.1
4.3
4.3
K
4.2
Lead Length
L
0.35
0.4
0.45
Package Edge Tolerance
Mold Flatness
aaa
bbb
ccc
ddd
eee
0.1
0.1
Co Planarity
0.08
Lead Offset
0.1
Exposed Pad Offset
0.1
HIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO FOCALTECH SYSTEMS CO.,LTD., AND MAY NOT BE
REPRODUCED, DISCLOSED OR USED IN WHOLE OR PART WITHOUT THE EXPRESS WRITTEN PERMISSION OF
FOCALTECH SYSTEMS CO.,LTD.
Copyright © 2012, FocalTech Systems CO.,Ltd . All rights reserved
Version 3.0︱Page 16 of 21
5.3
Package Information of QFN-6x6-56L Package
Millimeter
Type
Item Name
Symbol
Min
0.5
0
Max
0.6
Total Thickness
Stand Off
A
A1
A2
A3
b
0.55
0.035
0.4
0.05
----
Mold Thickness
L/F Thickness
Lead Width
----
0.152 REF
0.18
0.13
0.23
D
6 BSC
6 BSC
0.35 BSC
4.7
Body Size
Lead Pitch
EP Size
E
e
J
4.6
4.6
4.8
4.8
K
4.7
Lead Length
Package Edge Tolerance
Mold Flatness
L
0.35
0.4
0.45
aaa
bbb
ccc
ddd
eee
0.1
0.1
Coplanarity
0.08
Lead Offset
0.1
Exposed Pad Offset
0.1
HIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO FOCALTECH SYSTEMS CO.,LTD., AND MAY NOT BE
REPRODUCED, DISCLOSED OR USED IN WHOLE OR PART WITHOUT THE EXPRESS WRITTEN PERMISSION OF
FOCALTECH SYSTEMS CO.,LTD.
Copyright © 2012, FocalTech Systems CO.,Ltd . All rights reserved
Version 3.0︱Page 17 of 21
5.4
Package Information of QFN-8x8-68L Package
Millimeter
Type
Item Name
Symbol
Min
0.7
0
Max
0.8
Total Thickness
Stand Off
A
A1
A2
A3
b
0.75
0.035
0.55
0.05
0.57
Mold Thickness
L/F Thickness
Lead Width
----
0.203 REF
0.20
0.15
0.25
D
8 BSC
8 BSC
0.4 BSC
6.2
Body Size
Lead Pitch
EP Size
E
e
J
6.1
6.1
6.3
6.3
K
6.2
Lead Length
Package Edge Tolerance
Mold Flatness
L
0.35
0.4
0.45
aaa
bbb
ccc
ddd
eee
0.1
0.1
Coplanarity
0.08
Lead Offset
0.1
Exposed Pad Offset
0.1
HIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO FOCALTECH SYSTEMS CO.,LTD., AND MAY NOT BE
REPRODUCED, DISCLOSED OR USED IN WHOLE OR PART WITHOUT THE EXPRESS WRITTEN PERMISSION OF
FOCALTECH SYSTEMS CO.,LTD.
Copyright © 2012, FocalTech Systems CO.,Ltd . All rights reserved
Version 3.0︱Page 18 of 21
5.5
Order Information
QFN
Package Type
Product Name
40Pin(5 * 5 )/48Pin( 6 * 6 )/56Pin( 6 * 6 )/68Pin ( 8 * 8 )
0.75 - P0.4/0.55 - P0.35
FT5206GE1/ FT5306DE4/ FT5406DQ9/FT5406EE8
Note:
1). The lasttwolettersintheproduct nameindicatethepackage type and lead pitch andthickness.
2). Thesecond lastletterindicatesthe package type.
D:QFN-6*6 , E:QFN-8*8, G :QFN-5*5
3). The last letter indicates the lead pitch and thickness.
E:0.75-P0.4, Q:0.55-P0.35
T: Track Code
F/R:”F” for Lead Free process,
”R” for Halogen Free process
Y: Year Code
F T 5x06xxx
T F Y W W S V
WW: Week Code
S: Lot Code
V:
IC Version
Product Name
Package Type
# TX Pins
# RX Pins
FT5206GE1
FT5306DE4
FT5406DQ9
FT5406EE8
QFN-40L
QFN-48L
QFN-56L
QFN-68L
15
20
26
28
10
12
16
16
END OF DATASHEET
HIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO FOCALTECH SYSTEMS CO.,LTD., AND MAY NOT BE
REPRODUCED, DISCLOSED OR USED IN WHOLE OR PART WITHOUT THE EXPRESS WRITTEN PERMISSION OF
FOCALTECH SYSTEMS CO.,LTD.
Copyright © 2012, FocalTech Systems CO.,Ltd . All rights reserved
Version 3.0︱Page 19 of 21
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