GE28F640W30B85 [ETC]
EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC ;
| 型号： | GE28F640W30B85 |
| 厂家： | 
ETC |
| 描述： | EEPROM|FLASH|4MX16|CMOS|BGA|56PIN|PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总91页 (文件大小：974K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.8 Volt Intel® Wireless Flash Memory
with 3 Volt I/O
28F320W30, 28F640W30, 28F128W30
Datasheet
Product Features
■ High Performance Read-While-Write/Erase
— Burst Frequency at 40 MHz
— 70 ns Initial Access Speed
— 25 ns Page-Mode Read Speed
— 20 ns Burst-Mode Read Sp eed
— Burst and Page Mode in All Blocks and
across All Partition Boundaries
— Burst Suspend Feature
■ Flash Architecture
— Multiple 4-Mbit Partitions
— Dual Operation: RWW or RWE
— Parameter Block Size = 4-Kword
— Main block size = 32-Kword
— Topand Bottom Parameter Devices
■ Flash Software
— 5/9 µs (typ.) Program/Erase Suspend Latency
Time
— Enhanced Factory Programming:
3.5 µs per Word Program Time
— Programmable WAIT Signal Polarity
■ Quality and Reliability
— Intel® Flash Data Integrator (FDI) and
Common Flash Interface (CFI) Compatible
■ Flash Power
— Operating Temperature:
— VCC = 1.70 V – 1.90 V
–40 °C to +85 °C
— VCCQ = 2.20 V – 3.30 V
— Standby Current = 6 µA (typ.)
— Read Current = 7 mA
— 100K Minimum Erase Cycles
— 0.13 µm ETOX™ VII Process
■ Flash Security
(4 word burst, typ.)
— 128-bit Protection Register: 64 Unique Device ■ Density and Packaging
Identifier Bits; 64 User OTP Protection
Register Bits
— 32-, 64-, and 128-Mbit Densities in VF BGA
Package
— Absolute Write Protection with VPP at Ground
— Program and Erase Lockout during Power
Transitions
— 56 Active Ball Matrix, 0.75 mm Ball-Pitch in
VF BGA Packages
— 16-bit Data Bus
— Individual and Instantaneous Block Locking/
Unlocking with Lock-Down
The 1.8 Volt Intel®Wireless Flash Memory with 3 Volt I/O combines state-of-the-art Intel® Flash technology to
provide the most versatile memory solution for high performance, low power, board constraint memory
applications.
The 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O offers a multi-partition, dual-operation flash architecture
that enables the device to read from one partition while programming or erasing in another partition. This Read-
While-Write or Read-While-Erase capability makes it possible to achieve higher data throughput rates as compared
to single partition devices and it allows two processors to interleave code execution because program and erase
operations can now occur as background processes.
The 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O incorporates a new Enhanced Factory Programming
(EFP) mode to improve 12 V factory programming performance. This new feature helps eliminate manufacturing
bottlenecks associated with programming high density flash devices. Compare the EFP program time of 3.5 µs per
word to the standard factory program time of 8.0 µs per word and save significant factory programming time for
improved factory efficiency.
Additionally, the 1.8 Volt Intel Wireless Flash Memory with 3 Volt I/O includes block lock-down, programmable
WAIT signal polarity and is supported by an array of software tools. All these features make this product a perfect
solution for any demanding memory application.
Notice: This document contains information on new products in production. The specifications
are subject to change without notice. Verify with your local Intel sales office that you have the lat-
est datasheet before finalizing a design.
290702-004
April 2002
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2000 - 2002.
*Other names and brands may be claimed as the property of others.
2
Datasheet
28F320W30, 28F640W30, 28F128W30
Contents
1.0 Introduction ...............................................................................................................................7
1.1 Document Purpose ................................................................................................................7
1.2 Nomenclature.........................................................................................................................7
1.3 Conventions...........................................................................................................................7
2.0 Device Description..................................................................................................................8
2.1 Product Overview...................................................................................................................8
2.2 Package Diagram ................................................................................................................10
2.3 Signal Descriptions ..............................................................................................................11
2.4 Memory Map and Partitioning..............................................................................................12
3.0 Device Operations.................................................................................................................14
3.1 Bus Operations ....................................................................................................................15
3.1.1 Read .......................................................................................................................15
3.1.2 Burst Suspend ........................................................................................................16
3.1.3 Standby...................................................................................................................16
3.1.4 Reset.......................................................................................................................16
3.1.5 Write........................................................................................................................17
3.2 Device Commands...............................................................................................................17
3.3 Command Sequencing ........................................................................................................20
4.0 Read Operations....................................................................................................................21
4.1 Read Array...........................................................................................................................21
4.2 Read Device ID....................................................................................................................21
4.3 Read Query (CFI) ................................................................................................................22
4.4 Read Status Register...........................................................................................................22
4.5 Clear Status Register...........................................................................................................24
5.0 Program Operations.............................................................................................................24
5.1 Word Program......................................................................................................................24
5.2 Factory Programming ..........................................................................................................26
5.3 Enhanced Factory Program (EFP).......................................................................................27
5.3.1 EFP Requirements and Considerations..................................................................27
5.3.2 Setup.......................................................................................................................28
5.3.3 Program ..................................................................................................................28
5.3.4 Verify.......................................................................................................................28
5.3.5 Exit..........................................................................................................................29
6.0 Program and Erase Operations.......................................................................................31
6.1 Program/Erase Suspend and Resume ................................................................................31
6.2 Block Erase..........................................................................................................................33
6.3 Read-While-Write and Read-While-Erase ...........................................................................35
7.0 Security Modes.......................................................................................................................36
7.1 Block Lock Operations.........................................................................................................36
7.1.1 Lock ........................................................................................................................37
7.1.2 Unlock.....................................................................................................................37
Datasheet
3
28F320W30, 28F640W30, 28F128W30
7.1.3 Lock-Down.............................................................................................................. 37
7.1.4 Block Lock Status ................................................................................................... 38
7.1.5 Lock During Erase Suspend ................................................................................... 38
7.1.6 Status Register Error Checking .............................................................................. 38
7.1.7 WP# Lock-Down Control ........................................................................................39
7.2 Protection Register .............................................................................................................. 39
7.2.1 Reading the Protection Register.............................................................................40
7.2.2 Programing the Protection Register........................................................................ 40
7.2.3 Locking the Protection Register.............................................................................. 41
7.3 VPP Protection .................................................................................................................... 42
8.0 Set Configuration Register................................................................................................ 43
8.1 Read Mode (CR[15])............................................................................................................45
8.2 First Access Latency Count (CR[13:11]) .............................................................................45
8.3 WAIT Signal Polarity (CR[10]) ............................................................................................. 47
8.4 WAIT Signal Function..........................................................................................................47
8.5 Data Hold (CR[9]) ................................................................................................................ 48
8.6 WAIT Delay (CR[8]) .............................................................................................................49
8.7 Burst Sequence (CR[7])....................................................................................................... 49
8.8 Clock Edge (CR[6]).............................................................................................................. 51
8.9 Burst Wrap (CR[3]) .............................................................................................................. 51
8.10 Burst Length (CR[2:0])......................................................................................................... 52
9.0 Power Consumption.............................................................................................................52
9.1 Active Power........................................................................................................................52
9.2 Automatic Power Savings (APS) ......................................................................................... 52
9.3 Standby Power .................................................................................................................... 53
9.4 Power-Up/Down Characteristics.......................................................................................... 53
9.4.1 System Reset and RST# ........................................................................................53
9.4.2 VCC, VPP, and RST# Transitions .......................................................................... 53
9.5 Power Supply Decoupling.................................................................................................... 54
10.0 Thermal and DC Characteristics..................................................................................... 54
10.1 Absolute Maximum Ratings................................................................................................. 54
10.2 Operating Conditions........................................................................................................... 55
10.3 DC Current Characteristics..................................................................................................56
10.4 DC Voltage Characteristics..................................................................................................58
11.0 AC Characteristics................................................................................................................ 59
11.1 Read Operations ................................................................................................................. 59
11.2 AC Write Characteristics...................................................................................................... 69
11.3 Erase and Program Times................................................................................................... 73
11.4 Reset Specifications ............................................................................................................74
11.5 AC I/O Test Conditions........................................................................................................75
11.6 Device Capacitance............................................................................................................. 76
Appendix A Write State Machine States.............................................................................77
Appendix B Common Flash Interface ................................................................................. 80
4
Datasheet
28F320W30, 28F640W30, 28F128W30
Appendix C Mechanical Specifications ..............................................................................89
Appendix D Ordering Information.........................................................................................91
Datasheet
5
28F320W30, 28F640W30, 28F128W30
Revision History
Date of
Version
Revision
Description
09/19/00
03/14/01
-001
-002
Original Version
28F3208W30 product references removed (product was discontinued)
28F640W30 product added
Revised Table 2, Signal Descriptions (DQ
Revised Section 3.1, Bus Operations
, ADV#, WAIT, S-UB#, S-LB#, V
)
CCQ
15–0
Revised Table 5, Command Bus Definitions, Notes 1 and 2
Revised Section 4.2.2, First Latency Count (LC ); revised Figure 6, Data Output
2–0
withLC Setting at Code 3 ; added Figure 7, First Access Latency Configuration
Revised Section 4.2.3, WAIT Signal Polarity (WT)
Added Section 4.2.4, WAIT Signal Function
Revised Section 4.2.5, Data Output Configuration (DOC)
Added Figure 8, Data Output Configuration withWAIT Signal Delay
Revised Table 13, Status Register DWS and PWS Description
Revised entire Section 5.0, Program and Erase Voltages
Revised entire Section 5.3, Enhanced Factory Programming (EFP)
Revised entire Section 8.0, FlashSecurity Modes
Revised entire Section 9.0, FlashProtection Register ; added Table 15, Simulta-
neous Operations Allowed withthe Protection Register
Revised Section 10.1, Power-Up/Down Characteristics
Revised Section 11.3, DC Characteristics. Changed I
I
I
Specs from
CCS, CCWS, CCES
18 µA to 21µA; changed I
Spec from 12 mA to 15 mA (burst length = 4)
CCR
Added Figure 20, WAIT Signal in Synchronous Non-Read Array Operation Wave-
form
Added Figure 21, WAIT Signal in Asynchronous Page-Mode Read Operation
Waveform
Added Figure 22, WAIT Signal in Asynchronous Single-Word Read Operation
Waveform
Revised Figure 23, Write Waveform
Revised Section 12.4, Reset Operations
Clarified Section 13.2, SRAM Write Operation, Note 2
Revised Section 14.0, Ordering Information
Minor text edits
04/05/02
04/24/02
-003
-004
Deleted SRAM Section
Added 128M DC and AC Specifications
Added Burst Suspend
Added Read While Write Transition Waveforms
Various text edits
Revised Device ID
Revised Write Speed Bin
Various text edits
6
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
1.0
Introduction
1.1
Document Purpose
This datasheet contains information about the 1.8 Volt Intel® Wireless Flash memory with
3 Volt I/O family. Section 1.0 provides a flash memory overview. Section 2.0 through Section 9.0
describe the memory functionality. Section 10.0 describes the electrical specifications for extended
temperature product offerings. Packaging specifications and order information can be found in
Appendix C and Appendix D, respectively.
1.2
Nomenclature
Many acronyms that describe product features or usage are defined here:
• APSAutomatic Power Savings
• BBA Block Base Address
• CFI Common Flash Interface
• CUI Command User Interface
• EFP Enhanced Factory Programming
• FDI Flash Data Integrator
• NCNo Connect
• OTP One-Time Programmable
• PBA Partition Base Address
• RWE Read-While-Erase
• RWWRead-While-Write
• SRDStatus Register Data
• VF BGAVery thin, Fine pitch, Ball Grid Array
• WSMWrite State Machine
1.3
Conventions
Many abbreviated terms and phrases are used throughout this document:
• The term “1.8 V” refers to the full VCC voltage range of 1.7 V – 1.95 V (except where noted)
and “VPP = 12 V” refers to 12 V 5%.
• When referring to registers, the term set means the bit is a logical 1, and clear means the bit is
a logical 0.
• The terms pin and signal are often used interchangeably to refer to the external signal
connections on the package. (ball is the term used for VF BGA).
• A word is 2 bytes, or 16 bits.
Datasheet
7
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
• Signal names are in all CAPS (see Section 2.3, “Signal Descriptions” on page 11.)
• Voltage applied to the signal is subscripted, for example, VPP.
Throughout this document, references are made to top, bottom, parameter, and partition. To clarify
these references, the following conventions have been adopted:
• A block is a groupof bits (or words) that erase simultaneously with one block erase
instruction.
• A main block contains 32 Kwords.
• A parameter block contains 4 Kwords.
• The BlockBase Address (BBA) is the first address of a block.
• A partition is a groupof blocks that share erase and program circuitry and a common status
register.
• The Partition Base Address (PBA) is the first address of a partition. For example, on a 32-
Mbit top-parameter device, partition number 5 has a PBA of 140000h.
• The top partition is located at the highest physical device address. This partition may be a
main partition or a parameter partition.
• The bottom partition is located at the lowest physical device address. This partition may be a
main partition or a parameter partition.
• A main partition contains only main blocks.
• A parameter partition contains a mixture of main blocks and parameter blocks.
• A top parameter device (TPD) has the parameter partition at the top of the memory map with
the parameter blocks at the top of that partition. This was formerly referred to as top-boot
device.
• A bottom parameter device (BPD) has the parameter partition at the bottom of the memory
mapwith the parameter blocks at the bottom of that partition. This was formerly referred to as
bottom-boot block flash device.
2.0
Device Description
This section provides an overview of the 1.8 Volt Intel Wireless Flash memory features, packaging,
signal naming, and device architecture.
2.1
Product Overview
The 1.8 Volt Intel Wireless Flash memory provides Read-While-Write (RWW) and Read-White-
Erase (RWE) capability with high-performance synchronous and asynchronous reads on package-
compatible densities with a 16-bit data bus. Individually-erasable memory blocks are optimally
sized for code and data storage. Eight 4-Kword parameter blocks are located in the parameter
partition at either the top or bottom of the memory map. The rest of the memory array is grouped
into 32-Kword main blocks.
8
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
The memory architecture for the 1.8 Volt Intel Wireless Flash memory consists of multiple 4-Mbit
partitions, the exact number depending on device density. By dividing the memory array into
partitions, program or erase operations can take place simultaneously during read operations. Burst
reads can traverse partition boundaries, but user application code is responsible for ensuring that
they don’t extend into a partition that is actively programming or erasing. Although each partition
has burst-read, write, and erase capabilities, simultaneous operation is limited to write or erase in
one partition while other partitions are in a read mode.
Augmented erase-suspend functionality further enhances the RWW capabilities of this device. An
erase can be suspended to perform a program or read operation within any block, except that which
is erase-suspended. A program operation nested within a suspended erase can subsequently be
suspended to read yet another memory location.
After device power-up or reset, the 1.8 Volt Intel Wireless Flash memory defaults to asynchronous
read configuration. Writing to the device’s configuration register enables synchronous burst-mode
read operation. In synchronous mode, the CLK input increments an internal burst address
generator. CLK also synchronizes the flash memory with the host CPU and outputs data on every,
or on every other, valid CLK cycle after an initial latency. A programmable WAIT output signals to
the CPU when data from the flash memory device is ready.
In addition to its improved architecture and interface, the 1.8 Volt Intel Wireless Flash memory
with 3 Volt I/O incorporates Enhanced Factory Programming (EFP), a feature that enables fast
programming and low-power designs. The EFP feature provides the fastest currently-available
program performance, which can increase a factory’s manufacturing throughput.
The device supports read operations at 1.8 V and erase and program operations at 1.8 V or 12 V.
With the 1.8-V option, VCC and VPP can be tied together for a simple, ultra-low-power design. In
addition to voltage flexibility, the dedicated VPP input provides complete data protection when
V
PP ≤ VPPLK.
A 128-bit protection register enhances the user’s ability to implement new security techniques and
data protection schemes. Unique flash device identification and fraud-, cloning-, or content-
protection schemes are possible through a combination of factory-programmed and user-OTP data
cells. Zero-latency locking/unlocking on any memory block provides instant and complete
protection for critical system code and data. An additional block lock-down capability provides
hardware protection where software commands alone cannot change the block’s protection status.
The device’s Command User Interface (CUI) is the system processor’s link to internal flash
memory operation. A valid command sequence written to the CUI initiates device Write State
Machine (WSM) operation that automatically executes the algorithms, timings, and verifications
necessary to manage flash memory program and erase. An internal status register provides ready/
busy indication results of the operation (success, fail, and so on).
Three power-saving features– Automatic Power Savings (APS), standby, and RST#– can
significantly reduce power consumption. The device automatically enters APS mode following
read cycle completion. Standby mode begins when the system deselects the flash memory by
de-asserting CE#. Driving RST# low produces power savings similar to standby mode. It also
resets the part to read-array mode (important for system-level reset), clears internal status registers,
and provides an additional level of flash write protection.
Datasheet
9
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
2.2
Package Diagram
The 1.8 Volt Intel® Wireless Flash memory with is available in a 56 active-ball matrix VF BGA
Chip Scale Package with 0.75 mm ball pitch that is ideal for board-constrained applications. Figure
1 shows device ballout.
Figure 1. 56-Active-Ball Matrix
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
A11
A12
A13
A15
VCCQ
VSS
D7
A8
A9
vSS
vCC
CLK
ADV#
A16
vPP
RST#
WE#
D12
A18
A17
A19
WP#
D1
A6
A5
A4
A3
A4
A3
A2
A1
A0
A6
A5
A7
A18
vPP
vCC
VSS
A8
A11
A20
A17
RST# CLK
A20
A9
A12
A13
A15
VCCQ
VSS
D7
A10
A14
D15
D14
VSSQ
A21
A7
A2
A19
WE#
D12
D2
ADV#
A21
A10
WAIT
D6
A22
CE#
D0
A1
WP#
D1
A16
WAIT
D6
A14
A22
CE#
D0
D4
D2
A0
D4
D15
D14
VSSQ
D13
D11
D10
D9
OE#
VSSQ
OE#
VSSQ
D9
D10
D11
D13
G
G
D5
vCC
D3
VCCQ
D8
D8
VCCQ
D3
VCC
D5
Top View - Ball Side Down
Complete Ink Mark Not Shown
Bottom View - Ball Side Up
NOTES:
1. On lower density devices, upper address balls can be treated as NC. (Example: For 32-Mbit density, A
will be NC).
23-21
2. See Appendix C, “Mechanical Specifications” on page 89 for mechanical specifications for the package.
10
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
2.3
Signal Descriptions
Table 1 describes ball usage.
Table 1. Signal Descriptions
Symbol
Type
Name and Function
A[22:0]
D[15:0]
I
ADDRESS INPUTS: For memory addresses. 32 Mbit: A[20:0]; 64 Mbit: A[21:0]; 128 Mbit: A[22:0]
DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during
memory, status register, protection register, and configuration code reads. Data pins float when the
chip or outputs are deselected. Data is internally latched during writes.
I/O
ADDRESS VALID: ADV# indicates valid address presence on address inputs. During synchronous
read operations, all addresses are latched on ADV#’s rising edge or CLK’s rising (or falling) edge,
whichever occurs first.
ADV#
CE#
I
I
I
I
I
CHIP ENABLE: Asserting CE# activates internal control logic, I/O buffers, decoders, and sense amps.
De-asserting CE# deselects the device, places it in standby mode, and tri-states all outputs.
CLOCK: CLK synchronizes the device to the system bus frequency during synchronous reads and
increments an internal address generator. During synchronous read operations, addresses are latched
on ADV#’s rising edge or CLK’s rising (or falling) edge, whichever occurs first.
CLK
OUTPUT ENABLE: When asserted, OE# enables the device’s output data buffers during a read cycle.
When OE# is deasserted, data outputs are placed in a high-impedance state.
OE#
RESET: When low, RST# resets internal automation and inhibits write operations. This provides data
protection during power transitions. de-asserting RST# enables normal operation and places the
device in asynchronous read-array mode.
RST#
WAIT: The WAIT signal indicates valid data during synchronous read modes. It can be configured to be
asserted-high or asserted-low based on bit 10 of the Configuration Register. WAIT is tri-stated if CE# is
deasserted. WAIT is not gated by OE#.
WAIT
WE#
WP#
O
I
WRITE ENABLE: WE# controls writes to the CUIand array. Addresses and data are latched on the
rising edge of WE#.
WRITE PROTECT: Disables/enables the lock-down function. When WP# is asserted, the lock-down
mechanism is enabled and blocks marked lock-down cannot be unlocked through software. See
Section 7.1, “Block Lock Operations” on page 36 for details on block locking.
I
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when V ≤ V
not be attempted.
. Block erase and program at invalid V voltages should
PP
PPLK
PP
Set V = V for in-system program and erase operations. To accommodate resistor or diode drops
PP
CC
VPP
VCC
Pwr/I
Pwr
from the system supply, the V level of V can be as low as V
min to perform in-system flash modification. VPP may be 0 V during read operations.
min. V must remain above V
IH
PP
PP1 PP PP1
V
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500 cycles.
PP2
VPP can be connected to 12 V for a cumulative total not to exceed 80 hours. Extended use of this pin
at 12 V may reduce block cycling capability.
DEVICE POWER SUPPLY: Writes are inhibited at V ≤ V
. Device operations at invalid V
CC
CC
LKO
voltages should not be attempted.
OUTPUT POWER SUPPLY: Enables all outputs to be driven at V
VCC.
. This input may be tied directly to
CCQ
VCCQ
VSS
Pwr
Pwr
Pwr
GROUND: Pins for all internal device circuitry must be connected to system ground.
OUTPUT GROUND: Provides ground to all outputs which are driven by VCCQ. This signal may be tied
directly to VSS.
VSSQ
DON’T USE: Do not use this pin. This pin should not be connected to any power supplies, signals or
other pins and must be floated.
DU
NC
NO CONNECT: No internal connection; can be driven or floated.
Datasheet
11
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
2.4
Memory Map and Partitioning
The 1.8 Volt Intel Wireless Flash memory is divided into 4-Mbit physical partitions, which allows
simultaneous RWW or RWE operations and allows users to segment code and data areas on 4-Mbit
boundaries. The device’s memory array is asymmetrically blocked, which enables system code and
data integration within a single flash device. Each block can be erased independently in block erase
mode. Simultaneous program and erase operations are not allowed; only one partition at a time can
be actively programming or erasing. See Table 2, “Bottom Parameter Memory Map” on page 13
and Table 3, “Top Parameter Memory Map” on page 14.
The 32-Mbit device has eight partitions, the 64-Mbit device has 16 partitions, and the 128-Mbit
device has 32 partitions. Each device density contains one parameter partition and several main
partitions. The 4-Mbit parameter partition contains eight 4-Kword parameter blocks and seven 32-
Kword main blocks. Each 4-Mbit main partition contains eight 32-Kword blocks each.
The bulk of the array is divided into main blocks that can store code or data, and parameter blocks
that allow storage of frequently updated small parameters that are normally stored in EEPROM. By
using software techniques, the word-rewrite functionality of EEPROMs can be emulated.
.
12
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Table 2. Bottom Parameter Memory Map
Size
(KW)
Blk #
32 Mbit
Blk #
64 Mbit
Blk #
128 Mbit
32
262
7F8000-7FFFFF
32
32
32
32
32
32
32
32
32
32
135
134
71
70
39
38
31
30
23
22
400000-407FFF
3F8000-3FFFFF
200000-207FFF
1F8000-1FFFFF
100000-107FFF
0F8000-0FFFFF
0C0000-0C7FFF
0B8000-0BFFFF
080000-087FFF
078000-07FFFF
134
71
70
39
38
31
30
23
22
3F8000-3FFFFF
200000-207FFF
1F8000-1FFFFF
100000-107FFF
0F8000-0FFFFF
0C0000-0C7FFF
0B8000-0BFFFF
080000-087FFF
078000-07FFFF
70
39
38
31
30
23
22
1F8000-1FFFFF
100000-107FFF
0F8000-0FFFFF
0C0000-0C7FFF
0B8000-0BFFFF
080000-087FFF
078000-07FFFF
32
32
15
14
040000-047FFF
038000-03FFFF
15
14
040000-047FFF
038000-03FFFF
15
14
040000-047FFF
038000-03FFFF
32
4
8
7
008000-00FFFF
007000-007FFF
8
7
008000-00FFFF
007000-007FFF
8
7
008000-00FFFF
007000-007FFF
4
0
000000-000FFF
0
000000-000FFF
0
000000-000FFF
Datasheet
13
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Table 3. Top Parameter Memory Map
Size
(KW)
Blk #
32 Mbit
Blk #
64 Mbit
Blk #
128 Mbit
4
70
1FF000-1FFFFF
134
3FF000-3FFFFF
262
7FF000-7FFFFF
4
63
62
1F8000-1F8FFF
1F0000-1F7FFF
127
126
3F8000-3F8FFF
3F0000-3F7FFF
255
254
7F8000-7F8FFF
7F0000-7F7FFF
32
32
32
32
32
32
32
32
32
32
32
32
32
32
56
55
48
47
40
39
32
31
0
1C0000-1C7FFF
1B8000-1BFFFF
18000-187FFF
178000-17FFFF
140000-147FFF
138000-13FFFF
100000-107FFF
0F8000-0FFFFF
000000-007FFF
120
119
112
111
104
103
96
3C0000-3C7FFF
3B8000-3BFFFF
380000-387FFF
378000-37FFFF
340000-347FFF
338000-33FFFF
300000-307FFF
2F8000-2FFFFF
200000-207FFF
1F8000-1FFFFF
000000-007FFF
248
247
240
239
232
231
224
223
192
191
128
127
0
7C0000-7C7FFF
7B8000-7BFFFF
780000-787FFF
778000-77FFFF
740000-747FFF
738000-73FFFF
700000-707FFF
6F8000-6FFFFF
600000-607FFF
5F8000-5FFFFF
400000-407FFF
3F8000-3FFFFF
000000-007FFF
95
64
63
0
3.0
Device Operations
This section provides an overview of device operations. The 1.8 Volt Intel® Wireless Flash memory
with family includes an on-chipWSM to manage block erase and program algorithms. Its CUI
allows minimal processor overhead with RAM-like interface timings.
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Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
3.1
Bus Operations
Table 4. Bus Operations
Mode
Notes
RST#
CE#
OE#
WE#
ADV#
WAIT
D[15:0]
Read
4
1
V
V
V
V
V
V
V
V
V
See Note
High-Z
High-Z
High-Z
High-Z
D
OUT
IH
IH
IH
IL
IL
IH
IL
IH
IH
IL
Output Disable
Standby
Reset
V
X
High-Z
High-Z
High-Z
IH
1
V
X
X
X
X
1,2
3
V
X
X
X
IL
Write
V
V
V
V
V
D
IN
IH
IL
IH
IL
IL
NOTES:
1. X must be V or V for control pins and addresses.
IL
IH
SS
2. RST# must be at V
0.2 V to meet the maximum specified power-down current.
3. Refer to the Table 6, “Bus Cycle Definitions” on page 19 for valid D during a write operation.
IN
4. WAIT is only valid during synchronous array read operations.
3.1.1
Read
The 1.8 Volt Intel Wireless Flash memory has several read configurations:
• Asynchronous page mode read.
• Synchronous burst mode read — outputs four, eight, sixteen, or continuous words, from main
blocks and parameter blocks.
Several read modes are available in each partition:
• Read-array mode: read accesses return flash array data from the addressed locations.
• Read identifier mode: reads return manufacturer and device identifier data, block lock status,
and protection register data. Identifier information can be accessed starting at 4-Mbit partition
base addresses; the flash array is not accessible in read identifier mode.
• Read query mode: reads return device CFI data. CFI information can be accessed starting at
4-Mbit partition base addresses; the flash array is not accessible in read query mode.
• Read status register mode: reads return status register data from the addressed partition. That
partition’s array data is not accessible. A system processor can check the status register to
determine an addressed partition’s state or monitor program and erase progress.
All partitions support the synchronous burst mode that internally sequences addresses with respect
to the input CLK to select and supply data to the outputs.
Identifier codes, query data, and status register read operations execute as single-synchronous or
asynchronous read cycles. WAIT is asserted during these reads.
Access to the modes listed above is independent of VPP. An appropriate CUI command places the
device in a read mode. At initial power-up or after reset, the device defaults to asynchronous read-
array mode.
Asserting CE# enables device read operations. The device internally decodes upper address inputs
to determine which partition is accessed. Asserting ADV# opens the internal address latches.
Asserting OE# activates the outputs and gates selected data onto the I/O bus. In asynchronous
mode, the address is latched when ADV# is deasserted (when the device is configured to use
Datasheet
15
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
ADV#). In synchronous mode, the address is latched by either the rising edge of ADV# or the
rising (or falling) CLK edge while ADV# remains asserted, whichever occurs first. WE# and RST#
must be at deasserted during read operations.
3.1.2
Burst Suspend
The Burst Suspend feature allows the system to temporarily suspend a synchronous burst operation
if the system needs to use the flash address and data bus for other purposes. Burst accesses can be
suspended during the initial latency (before data is received) or after the device has output data.
When a burst access is suspended, internal array sensing continues and any previously latched
internal data is retained.
Burst Suspend occurs when CE# is asserted, the current address has been latched (either ADV#
rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it
is at VIH or VIL. To resume the burst access, OE# is reasserted and CLK is restarted. Subsequent
CLK edges resume the burst sequence where it left off.
Within the device, CE# gates WAIT. Therefore, during Burst Suspend WAIT remains asserted and
does not revert to a high-impedance state when OE# is deasserted. This can cause contention with
another device attempting to control the system’s READY signal during a Burst Suspend. System
using the Burst Suspend feature should not connect the device’s WAIT signal directly to the
system’s READY signal.
Refer to Figure 26, “Burst Suspend” on page 68.
3.1.3
3.1.4
Standby
De-asserting CE# deselects the device and places it in standby mode, substantially reducing device
power consumption. In standby mode, outputs are placed in a high-impedance state independent of
OE#. If deselected during a program or erase algorithm, the device shall consume active power
until the program or erase operation completes.
Reset
The device enters a reset mode when RST# is asserted. In reset mode, internal circuitry is turned
off and outputs are placed in a high-impedance state.
After returning from reset, a time tPHQV is required until outputs are valid, and a delay (tPHWV) is
required before a write sequence can be initiated. After this wake-upinterval, normal operation is
restored. The device defaults to read-array mode, the status register is set to 80h, and the
configuration register defaults to asynchronous page-mode reads.
If RST# is asserted during an erase or program operation, the operation aborts and the memory
contents at the aborted block or address are invalid. See Figure 32, “Reset Operations Waveforms”
on page 74 for detailed information regarding reset timings.
Like any automated device, it is important to assert RST# during system reset. When the system
comes out of reset, the processor expects to read from the flash memory array. Automated flash
memories provide status information when read during program or erase operations. If a CPU reset
occurs with no flash memory reset, proper CPU initialization may not occur because the flash
memory may be providing status information instead of array data. 1.8 Volt Intel Flash memories
allow proper CPU initialization following a system reset through the use of the RST# input. In this
application, RST# is controlled by the same CPU reset signal, RESET#.
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
3.1.5
Write
A write occurs when CE# and WE# are asserted and OE# is deasserted. Flash control commands
are written to the CUI using standard microprocessor write timings. Proper use of the ADV# input
is needed for proper latching of the addresses. Refer to Section 11.2, “AC Write Characteristics” on
page 69 for details. The address and data are latched on the rising edge of WE#. Write operations
are asynchronous; CLK is ignored (but still may be kept active/toggling).
The CUI does not occupy an addressable memory location within any partition. The system
processor must access it at the correct address range depending on the kind of command executed.
Programming or erasing may occur in only one partition at a time. Other partitions must be in one
of the read modes or erase suspend mode.
Table 5, “Command Codes and Descriptions” on page 17 shows the available commands.
Appendix A, “Write State Machine States” on page 77 provides information on moving between
different operating modes using CUI commands.
3.2
Device Commands
The device’s on-chipWSM manages erase and program algorithms. This local CPU (WSM)
controls the device’s in-system read, program, and erase operations. Bus cycles to or from the flash
memory conform to standard microprocessor bus cycles. RST#, CE#, OE#, WE#, and ADV#
control signals dictate data flow into and out of the device. WAIT informs the CPU of valid data
during burst reads. Table 4, “Bus Operations” on page 15 summarizes bus operations.
Device operations are selected by writing specific commands into the device’s CUI. Table 5,
“Command Codes and Descriptions” on page 17 lists all possible command codes and
descriptions. Table 6, “Bus Cycle Definitions” on page 19 lists command definitions. Because
commands are partition-specific, it is important to issue write commands within the target address
range.
Table 5. Command Codes and Descriptions (Sheet 1 of 2)
Device
Command
Operation
Code
Description
FFh
70h
Read Array
Places selected partition in read-array mode.
Read Status
Register
Places selected partition in status register read mode. The partition enters this
mode after a Program or Erase command is issued to it.
Puts the selected partition in read identifier mode. Device reads from partition
Read Identifier addresses output manufacturer/device codes, configuration register data, block
lock status, or protection register data on D[15:0].
90h
98h
50h
Read
Puts the addressed partition in read query mode. Device reads from the partition
addresses output CFIinformation on D[7:0].
Read Query
The WSM can set the status register’s block lock (SR[1]), V (SR[3]), program
PP
Clear Status
Register
(SR[4]), and erase (SR[5]) status bits, but it cannot clear them. SR[5:3,1] can only
be cleared by a device reset or through the Clear Status Register command.
Datasheet
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Table 5. Command Codes and Descriptions (Sheet 2 of 2)
Device
Command
Operation
Code
Description
This preferred program command’s first cycle prepares the CUIfor a program
operation. The second cycle latches address and data, and executes the WSM
program algorithm at this location. Status register updates occur when CE# or
OE# is toggled. A Read Array command is required to read array data after
programming.
Word Program
Setup
40h
Alternate
Setup
10h
30h
D0h
20h
Equivalent to a Program Setup command (40h).
Program
This program command activates EFP mode. The first write cycle sets up the
command. If the second cycle is an EFP Confirm command (D0h), subsequent
writes provide program data. All other commands are ignored after EFP mode
begins.
EFP Setup
If the first command was EFP Setup (30h), the CUI latches the address and data,
and prepares the device for EFP mode.
EFP Confirm
Erase Setup
This command prepares the CUIfor Block Erase. The device erases the block
addressed by the Erase Confirm command. If the next command is not Erase
Confirm, the CUIsets status register bits SR[5:4] to indicate command sequence
error and places the partition in the read status register mode.
Erase
If the first command was Erase Setup (20h), the CUI latches address and data,
and erases the block indicated by the erase confirm cycle address. During
D0h
B0h
Erase Confirm program or erase, the partition responds only to Read Status Register, Program
Suspend, and Erase Suspend commands. CE# or OE# toggle updates status
register data.
This command, issued at any device address, suspends the currently executing
program or erase operation. Status register data indicates the operation was
successfully suspended if SR[2] (program suspend) or SR[6] (erase suspend) and
SR[7] are set. The WSM remains in the suspended state regardless of control
Program
Suspend or
Erase
Suspend
Suspend
signal states (except RST#).
Suspend
Resume
This command, issued at any device address, resumes the suspended program or
erase operation.
D0h
60h
01h
D0h
2Fh
This command prepares the CUIlock configuration. If the next command is not
Lock Block, Unlock Block, or Lock-Down, the CUIsets SR[5:4] to indicate
command sequence error.
Lock Setup
Lock Block
Unlock Block
Lock-Down
If the previous command was Lock Setup (60h), the CUI locks the addressed
block.
Block Locking
If the previous command was Lock Setup (60h), the CUI latches the address and
unlocks the addressed block. If previously locked-down, the operation has no
effect.
If the previous command was Lock Setup (60h), the CUI latches the address and
locks-down the addressed block.
This command prepares the CUIfor a protection register program operation. The
second cycle latches address and data, and starts the WSM’s protection register
program or lock algorithm. Toggling CE# or OE# updates the flash status register
data. To read array data after programming, issue a Read Array command.
Protection
Program
Setup
Protection
C0h
This command prepares the CUIfor device configuration. fI Set Configuration
Register is not the next command, the CUIsets SR[5:4] to indicate command
sequence error.
Configuration
Setup
60h
03h
Configuration
Set
Configuration
Register
If the previous command was Configuration Setup (60h), the CUI latches the
address and writes the data from A[15:0] into the configuration register.
Subsequent read operations access array data.
NOTE: Do not use unassigned commands. Intel reserves the right to redefine these codes for future functions.
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Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Table 6. Bu s Cycle Definitions
First Bu s Cycle
Second Bu s Cycle
Bus
Operation
Command
Cycles
Oper
Addr1
Data2,3
Oper
Addr1
Data2,3
Read
Address
Array
Data
Read Array/Reset
≥1
Write
PnA
FFh
Read
Read Identifier
Read Query
≥ 2
≥ 2
2
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
PnA
PnA
PnA
XX
90h
98h
Read
Read
Read
PBA+IA
PBA+QA
PnA
IC
QD
Read Status Register
Clear Status Register
Block Erase
70h
SRD
1
50h
2
BA
20h
Write
Write
Write
BA
WA
WA
D0h
WD
D0h
Word Program
EFP
2
WA
WA
XX
40h/10h
30h
>2
1
Program/Erase Suspend
Program/Erase Resume
Lock Block
B0h
D0h
60h
1
XX
2
BA
Write
Write
Write
BA
BA
BA
01h
D0h
2Fh
Unlock Block
2
BA
60h
Lock-Down Block
2
BA
60h
Protection Program
2
2
Write
Write
PA
C0h
C0h
Write
Write
PA
PD
Lock Protection Program
LPA
LPA
FFFDh
Set Configuration Register
2
2
Write
Write
CD
CD
60h
60h
Write
Write
CD
CD
03h
03h
Set Configuration Register
NOTES:
1. First-cycle command addresses should be the same as the operation’s target address. Examples: the first-
cycle address for the Read Identifier command should be the same as the Identification code address (IA);
the first-cycle address for the Word Program command should be the same as the word address (WA) to be
programmed; the first-cycle address for the Erase/Program Suspend command should be the same as the
address within the block to be suspended; etc.
XX = Any valid address within the device.
IA = Identification code address.
BA = Block Address. Any address within a specific block.
LPA = Lock Protection Address is obtained from the CFI(through the Read Query command). The 1.8 Volt
Intel Wireless Flash memory family’s LPA is at 0080h.
PA = User programmable 4-word protection address.
PnA = Any address within a specific partition.
Datasheet
19
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
PBA = Partition Base Address. The very first address of a particular partition.
QA = Query code address.
WA = Word address of memory location to be written.
2. SRD = Status register data.
WD = Data to be written at location WA.
IC = Identifier code data.
PD = User programmable 4-word protection data.
QD = Query code data on D[7:0].
CD = Configuration register code data presented on device addresses A[15:0]. A[MAX:16] address bits can
select any partition. See Table 13, “Configuration Register Definitions” on page 44 for configuration register
bits descriptions.
3. Commands other than those shown above are reserved by Intel for future device implementations and
should not be used.
3.3
Command Sequencing
When issuing a 2-cycle write sequence to the flash device, a read operation is allowed to occur
between the two write cycles. The setupphase of a 2-cycle write sequence places the addressed
partition into read-status mode, so if the same partition is read before the second “confirm” write
cycle is issued, status register data will be returned. Reads from other partitions, however, can
return actual array data assuming the addressed partition is already in read-array mode. Figure 2 on
page 20 and Figure 3 on page 20 illustrate these two conditions.
Figure 2. Normal Write and Read Cycles
Address [A]
WE# [W]
OE# [G]
Partition A
Partition A
Partition A
Data [Q]
20h
Block Erase Setup
D0h
Block Erase Conf irm
FFh
Read Array
Figure 3. Interleaving a 2-Cycle Write Sequence with an Array Read
Address [A]
WE# [W]
OE# [G]
Partition B
Partition A
Partition B
Partition A
Data [Q]
FFh
Read Array
20h
Erase Setup
Array Data
Bus Read
D0h
Erase Confirm
By contrast, a write bus cycle may not interrupt a 2-cycle write sequence. Doing so causes a
command sequence error to appear in the status register. Figure 4 illustrates a command sequence
error.
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Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 4. Improper Command Sequencing
Address [A]
WE# [W]
Partition X
Partition Y
Partition X
Partition X
OE# [G]
Data [D/Q]
20h
FFh
D0h
SR Data
4.0
Read Operations
4.1
Read Array
The Read Array command places (or resets) the partition in read-array mode and is used to read
data from the flash memory array. Upon initial device power-up, or after reset (RST# transitions
from VIL to VIH), all partitions default to asynchronous read-array mode. To read array data from
the flash device, first write the Read Array command (FFh) to the CUI and specify the desired
word address. Then read from that address. If a partition is already in read-array mode, issuing the
Read Array command is not required to read from that partition.
If the Read Array command is written to a partition that is erasing or programming, the device
presents invalid data on the bus until the program or erase operation completes. After the program
or erase finishes in that partition, valid array data can then be read. If an Erase Suspend or Program
Suspend command suspends the WSM, a subsequent Read Array command places the addressed
partition in read-array mode. The Read Array command functions independently of VPP.
4.2
Read Device ID
The read identifier mode outputs the manufacturer/device identifier, block lock status, protection
register codes, and configuration register data. The identifier information is contained within a
separate memory space on the device and can be accessed along the 4-Mbit partition address range
supplied by the Read Identifier command (90h) address. Reads from addresses in Table 7 retrieve
ID information. Issuing a Read Identifier command to a partition that is programming or erasing
places that partition’s outputs in read ID mode while the partition continues to program or erase in
the background.
Datasheet
21
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Table 7. Device Identification Codes
Address1
Item
Data
Description
Base
Offset
Manufacturer ID
Device ID
Partition
00h
0089h
8852h
32-Mbit TPD
8853h
32-Mbit BPD
8854h
64-Mbit TPD
Partition
01h
8855h
64-Mbit BPD
8856h
128-Mbit TPD
8857h
128-Mbit BPD
D0 = 0
Block is unlocked
Block is locked
Block is not locked-down
Block is locked down
Block Lock Status(2)
Block
Block
02h
02h
D0 = 1
D1 = 0
Block Lock-Down Status(2)
D1 = 1
Configuration Register
Partition
Partition
05h
80h
Register Data
Lock Data
Protection Register Lock Status
Multiple reads required to read
Register Data the entire 128-bit Protection
Register.
Protection Register
Partition
81h - 88h
NOTES:
1. The address is constructed from a base address plus an offset. For example, to read the Block Lock Status
for block number 38 in a BPD, set the address to the BBA (0F8000h) plus the offset (02h), i.e. 0F8002h.
Then examine bit 0 of the data to determine if the block is locked.
2. See Section 7.1.4, “Block Lock Status” on page 38 for valid lock status.
4.3
4.4
Read Query (CFI)
This device contains a separate CFI query database that acts as an “on-chipdatasheet.” The CFI
information within this device can be accessed by issuing the Read Query command and supplying
a specific address. The address is constructed from the base address of a partition plus a particular
offset corresponding to the desired CFI field. Appendix B, “Common Flash Interface” on page 80
shows accessible CFI fields and their address offsets. Issuing the Read Query command to a
partition that is programming or erasing puts that partition in read query mode while the partition
continues to program or erase in the background.
Read Status Register
The device’s status register displays program and erase operation status. A partition’s status can be
read after writing the Read Status Register command to any location within the partition’s address
range. Read-status mode is the default read mode following a Program, Erase, or Lock Block
command sequence. Subsequent single reads from that partition will return its status until another
valid command is written.
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
The read-status mode supports single synchronous and single asynchronous reads only; it doesn’t
support burst reads. The first falling edge of OE# or CE# latches and updates status register data.
The operation doesn’t affect other partitions’ modes. Because the status register is 8 bits wide, only
DQ [7:0] contains valid status register data; DQ [15:8] contains zeros. See Table 8, “Status
Register Definitions” on page 23 and Table 9, “Status Register Descriptions” on page 23.
Each 4-Mbit partition contains its own status register. Bits SR[6:0] are unique to each partition, but
SR[7], the Device WSM Status (DWS) bit, pertains to the entire device. SR[7] provides program
and erase status of the entire device. By contrast, the Partition WSM Status (PWS) bit, SR[0],
provides program and erase status of the addressed partition only. Status register bits SR[6:1]
present information about partition-specific program, erase, suspend, VPP, and block-lock states.
Table 10, “Status Register Device WSM and Partition Write Status Description” on page 24
presents descriptions of DWS (SR[7]) and PWS (SR[0]) combinations.
Table 8. Status Register Definitions
DWS
7
ESS
6
ES
5
PS
4
VPPS
3
PSS
2
DPS
1
PWS
0
Table 9. Status Register Descriptions
Bit
Name
State
Description
SR[7] indicates erase or program completion in the
device. SR[6:1] are invalid while SR[7] = 0. See Table
10 for valid SR[7] and SR[0] combinations.
DWS
0 = Device WSM is Busy
1 = Device WSM is Ready
7
Device WSM Status
After issuing an Erase Suspend command, the WSM
halts and sets SR[7] and SR[6]. SR[6] remains set until
the device receives an Erase Resume command.
ESS
0 = Erase in progress/completed
6
Erase Suspend Status 1 = Erase suspended
ES
0 = Erase successful
1 = Erase error
SR[5] is set if an attempted erase failed. A Command
Sequence Error is indicated when SR[7,5:4] are set.
5
4
Erase Status
PS
0 = Program successful
1 = Program error
SR[4] is set if the WSM failed to program a word.
Program Status
The WSM indicates the V level after program or
erase completes. SR[3] does not provide continuous
PP
VPPS
0 = V OK
PP
3
2
VPP Status
1 = V low detect, operation aborted
PP
V
feedback and isn’t guaranteed when V ≠ V
.
PP
PP
PP1/2
PSS
After receiving a Program Suspend command, the
WSM halts execution and sets SR[7] and SR[2]. They
remain set until a Resume command is received.
0 = Program in progress/completed
1 = Program suspended
Program Suspend
Status
0 = Unlocked
If an erase or program operation is attempted to a
DPS
1
0
locked block (if WP# = V ), the WSM sets SR[1] and
1 = Aborted erase/program attempt on
locked block
IL
Device Protect Status
aborts the operation.
Addressed partition is erasing or programming. In EFP
mode, SR[0] indicates that a data-stream word has
finished programming or verifying depending on the
particular EFP phase. See Table 10 for valid SR[7] and
SR[0] combinations.
0 = This partition is busy, but only if
SR[7]=0
PWS
Partition Write Status 1 = Another partition is busy, but only if
SR[7]=0
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Table 10. Status Register Device WSM and Partition Write Status Description
DWS
(SR[7])
PWS
(SR[0])
Description
The addressed partition is performing a program/erase operation.
0
0
0
1
EFP: device has finished programming or verifying data, or is ready for data.
A partition other than the one currently addressed is performing a program/erase operation.
EFP: the device is either programming or verifying data.
No program/erase operation is in progress in any partition. Erase and Program suspend bits (SR[6,2])
indicate whether other partitions are suspended.
1
1
0
1
EFP: the device has exited EFP mode.
Won’t occur in standard program or erase modes.
EFP: this combination does not occur.
4.5
Clear Status Register
The Clear Status Register command clears the status register and leaves all partition output states
unchanged. The WSM can set all status register bits and clear bits SR[7:6,2,0]. Because bits
SR[5,4,3,1] indicate various error conditions, they can only be cleared by the Clear Status Register
command. By allowing system software to reset these bits, several operations (such as
cumulatively programming several addresses or erasing multiple blocks in sequence) can be
performed before reading the status register to determine error occurrence. If an error is detected,
the Status Register must be cleared before beginning another command or sequence. Device reset
(RST# = VIL) also clears the status register. This command functions independently of VPP.
5.0
Program Operations
5.1
Word Program
When the Word Program command is issued, the WSM executes a sequence of internally timed
events to program a word at the desired address and verify that the bits are sufficiently
programmed. Programming the flash array changes specifically addressed bits to 0; 1 bits do not
change the memory cell contents.
Programming can occur in only one partition at a time. All other partitions must be in either a read
mode or erase suspend mode. Only one partition can be in erase suspend mode at a time.
The status register can be examined for program progress by reading any address within the
partition that is busy programming. However, while most status register bits are partition-specific,
the Device WSM Status bit, SR[7], is device-specific; that is, if the status register is read from any
other partition, SR[7] indicates program status of the entire device. This permits the system CPU to
monitor program progress while reading the status of other partitions.
CE# or OE# toggle (during polling) updates the status register. Several commands can be issued to
a partition that is programming: Read Status Register, Program Suspend, Read Identifier, and Read
Query. The Read Array command can also be issued, but the read data is indeterminate.
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
After programming completes, three status register bits can signify various possible error
conditions. SR[4] indicates a program failure if set. If SR[3] is set, the WSM couldn’t execute the
Word Program command because VPP was outside acceptable limits. If SR[1] is set, the program
was aborted because the WSM attempted to program a locked block.
After the status register data is examined, clear it with the Clear Status Register command before a
new command is issued. The partition remains in status register mode until another command is
written to that partition. Any command can be issued after the status register indicates program
completion.
If CE# is deasserted while the device is programming, the devices will not enter standby mode until
the program operation completes.
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 5. Word Program Flowchart
WORD PROGRAM PROCEDURE
Bus
Operation
Start
Command
Comments
Program Data = 40h
Write
Write
Read
Setup
Addr = Location to program (WA)
Write 40h,
Word Address
Data = Data to program (WD)
Addr = Location to program (WA)
Data
Write Data
Word Address
Read SRD
Toggle CE# or OE# to update SRD
Suspend
Program
Loop
Read Status
Register
Check SR[7]
1 = WSM ready
0 = WSM busy
Standby
No
Yes
Suspend
Program
0
SR[7] =
1
Repeat for subsequent programming operations.
Full status register check can be done after each program or
after a sequence of program operations.
Full Program
Status Check
(if desired)
Program
Complete
FULL PROGRAM STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[3]
1 = VPP error
Standby
Standby
VPP Range
Error
1
1
1
SR[3] =
0
Check SR[4]
1 = Data program error
Check SR[1]
Program
Error
SR[4] =
0
Standby
1 = Attempted program to locked block
Program aborted
SR[3] MUST be cleared before the WSM will allow further
program attempts
Device
Protect Error
SR[1] =
0
Only the Clear Staus Register command clears SR[4:3,1].
If an error is detected, clear the status register before
attempting a program retry or other error recovery.
Program
Successful
5.2
Factory Programming
The standard factory programming mode uses the same commands and algorithm as the Word
Program mode (40h/10h). When VPP is at VPP1, program and erase currents are drawn through
VCC. If VPP is driven by a logic signal, VPP1 must remain above the VPP1Min value to perform in-
system flash modifications. When VPP is connected to a 12 V power supply, the device draws
program and erase current directly from VPP. This eliminates the need for an external switching
transistor to control the VPP voltage. Figure 14, “Examples of VPP Power Supply Configurations”
on page 42 shows examples of flash power supply usage in various configurations.
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
The 12-V VPP mode enhances programming performance during the short time period typically
found in manufacturing processes; however, it is not intended for extended use.12 V may be
ap p lied to V during program and erase operations as specified in Section 10.2, “Operating
Conditions”PoPn p age 55. VPP may be connected to 12 V for a total of tPPH hours maximum.
Stressing the device beyond these limits may cause permanent damage.
5.3
Enhanced Factory Program (EFP)
EFP substantially improves device programming performance through a number of enhancements
to the conventional 12 Volt word program algorithm. EFP's more efficient WSM algorithm
eliminates the traditional overhead delays of the conventional word program mode in both the host
programming system and the flash device. Changes to the conventional word programming
flowchart and internal WSM routine were developed because of today's beat-rate-sensitive
manufacturing environments; a balance between programming speed and cycling performance was
attained.
The host programmer writes data to the device and checks the Status Register to determine when
the data has completed programming. This modification essentially cuts write bus cycles in half.
Following each internal program pulse, the WSM increments the device's address to the next
physical location. Now, programming equipment can sequentially stream program data throughout
an entire block without having to setupand present each new address. In combination, these
enhancements reduce much of the host programmer overhead, enabling more of a data streaming
approach to device programming.
EFP further speeds up programming by performing internal code verification. With this, PROM
programmers can rely on the device to verify that it has been programmed properly. From the
device side, EFP streamlines internal overhead by eliminating the delays previously associated to
switch voltages between programming and verify levels at each memory-word location.
EFP consists of four phases: setup, program, verify and exit. Refer to Figure 6, “Enhanced Factory
Program Flowchart” on page 30 for a detailed graphical representation of how to implement EFP.
5.3.1
EFP Requirements and Considerations
EFP requirements:
• Ambient temperature: TA = 25 °C 5 °C
• VCC within specified operating range
• VPP within specified VPP2 range
• Target block unlocked
EFP considerations:
• Block cycling below 100 erase cycles 1
• RWW not supported2
• EFP programs one block at a time
• EFP cannot be suspended
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
1. Recommended for optimum performance. Some degradation in performance may occur if this limit is
exceeded, but the internal algorithm will continue to work properly.
2. Code or data cannot be read from another partition during EFP.
5.3.2
Setup
After receiving the EFP Setup(30h) and EFP Confirm (D0h) command sequence, SR[7] transitions
from a 1 to a 0 indicating that the WSM is busy with EFP algorithm startup. A delay before
checking SR[7] is required to allow the WSM time to perform all of its setups and checks (VPP
level and block lock status). If an error is detected, status register bits SR[4], SR[3], and/or SR[1]
are set and EFP operation terminates.
Note: After the EFP Setupand Confirm command sequence, reads from the device automatically output
status register data. Do not issue the Read Status Register command; it will be interpreted as data to
program at WA0.
5.3.3
Program
After setup completion, the host programming system must check SR[0] to determine “data-stream
ready" status (SR[0]=0). Each subsequent write after this is a program-data write to the flash array.
Each cell within the memory word to be programmed to 0 receives one WSM pulse; additional
pulses, if required, occur in the verify phase. SR[0]=1 indicates that the WSM is busy applying the
program pulse.
The host programmer must poll the device's status register for the "program done" state after each
data-stream write. SR[0]=0 indicates that the appropriate cell(s) within the accessed memory
location have received their single WSM program pulse, and that the device is now ready for the
next word. Although the host may check full status for errors at any time, it is only necessary on a
block basis, after EFP exit.
Addresses must remain within the target block. Supplying an address outside the target block
immediately terminates the program phase; the WSM then enters the EFP verify phase.
The address can either hold constant or it can increment. The device compares the incoming
address to that stored from the setupphase (WA 0); if they match, the WSM programs the new data
word at the next sequential memory location. If they differ, the WSM jumps to the new address
location.
The program phase concludes when the host programming system writes to a different block
address, and data supplied must be FFFFh. Upon program phase completion, the device enters the
EFP verify phase.
5.3.4
Verify
A high percentage of the flash bits program on the first WSM pulse. However, for those cells that
do not completely program on their first attempt, EFP internal verification identifies them and
applies additional pulses as required.
The verify phase is identical in flow to the program phase, except that instead of programming
incoming data, the WSM compares the verify-stream data to that which was previously
programmed into the block. If the data compares correctly, the host programmer proceeds to the
next word. If not, the host waits while the WSM applies an additional pulse(s).
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
The host programmer must reset its initial verify-word address to the same starting location
supplied during the program phase. It then reissues each data word in the same order as during the
program phase. Like programming, the host may write each subsequent data word to WA0 or it may
increment upthrough the block addresses.
The verification phase concludes when the interfacing programmer writes to a different block
address; data supplied must be FFFFh. Upon completion of the verify phase, the device enters the
EFP exit phase.
5.3.5
Exit
SR[7]=1 indicates that the device has returned to normal operating conditions. A full status check
should be performed at this time to ensure the entire block programmed successfully. After EFP
exit, any valid CUI command can be issued.
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 6. Enhanced Factory Program Flowchart
ENHANCED FACTORY PROGRAMMING PROCEDURE
EFP Setup
EFP Program
EFP Verify
EFP Exit
Read
Status Register
Read
Status Register
Read
Status Register
Start
VPP = 12V
Unlock Block
SR[0]=1=N
SR[0]=1=N
SR[7]=0=N
Data Stream
Ready?
Verify Stream
Ready?
EFP
Exited?
SR[0] =0=Y
SR[0] =0=Y
SR[7]=1=Y
Write 30h
Address = WA0
Write Data
Address = WA0
Write Data
Address = WA0
Full Status Check
Procedure
Write D0h
Address = WA0
Read
Status Register
Read
Status Register
Operation
Complete
EFP setup time
Program
Done?
Verify
Done?
Read
Status Register
SR[0]=0=Y
SR[0]=0=Y
N
N
Last
Data?
Last
Data?
EFP Setup
Done?
Y
Y
SR[7]=1=N
Check VPP & Lock
errors (SR[3,1])
Write FFFFh
Write FFFFh
Address ≠ BBA
Address
≠
BBA
Exit
EFP Setup
EFP Program
EFP Verify
Bus
State
Bus
State
Bus
State
Comments
Comments
Comments
Read
Status Register
Check SR[0]
Read
Status Register
Verify Check SR[0]
Unlock VPP = 12V
Block Unlock block
Write
Data
Standby Stream 0 = Ready for data
Ready? 1 = Not ready for data
Standby Stream 0 = Ready for verify
Ready? 1 = Not ready for verify
EFP
Data = 30h
Write
Write
Setup Address = WA0
EFP Data = D0h
Confirm Address = WA0
Write
Data = Data to program
Address = WA0
Write
Data = Word to verify
Address = WA0
(note 1)
(note 2)
Read
Status Register
Read
Status Register
Standby
Read
EFP setup time
Check SR[0]
0 = Program done
1 = Program not done
Check SR[0]
0 = Verify done
1 = Verify not done
Program
Done?
Standby Verify
(note 3) Done?
Status Register
Check SR[7]
Standby
EFP
Standby Setup 0 = EFP ready
Last
Device automatically
Last
Device automatically
Standby
Standby
Done? 1 = EFP not ready
Data? increments address.
Data? increments address.
I f SR[7] = 1:
Error
Exit Data = FFFFh
Write Program Address not within same
Phase BBA
Exit Data = FFFFh
Verify Address not within same
Phase BBA
Check SR[3,1]
Standby Condition
SR[3] = 1 = VPP error
Check
Write
SR[1] = 1 = locked block
EFP Exit
1. WA0 = first Word Address to be programmed within the target block. The BBA (Block Base
Address) must remain constant throughout the program phase data stream; WA can be held
Read
Status Register
Check SR[7]
EFP
constant at the first address location, or it can be written to sequence up through the addresses
within the block. Writing to a BBA not equal to that of the block currently being written to
terminates the EFP program phase, and instructs the device to enter the EFP verify phase.
2. For proper verification to occur, the verify data stream must be presented to the device in the
same sequence as that of the program phase data stream. Writing to a BBA not equal to WA
terminates the EFP verify phase, and instructs the device to exit EFP .
3. Bits that did not fully program with the single WSM pulse of the EFP program phase receive
additional program-pulse attempts during the EFP verify phase. The device will report any
program failure by setting SR[4]=1; this check can be performed during the full status check after
EFP has been exited for that block, and will indicate any error within the entire data stream.
Standby
0 = Exit not finished
Exited?
1 = Exit completed
Repeat for subsequent operations.
After EFP exit, a Full Status Check can
determine if any program error occurred.
See the Full Status Check procedure in the
Word Program flowchart.
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
6.0
Program and Erase Operations
6.1
Program/Erase Suspend and Resume
The Program Suspend and Erase Suspend commands halt an in-progress program or erase
operation. The command can be issued at any device address. The partition corresponding to the
command’s address remains in its previous state. A suspend command allows data to be accessed
from memory locations other than the one being programmed or the block being erased.
A program operation can be suspended only to perform a read operation. An erase operation can be
suspended to perform either a program or a read operation within any block, except the block that
is erase suspended. A program command nested within a suspended erase can subsequently be
suspended to read yet another location. Once a program or erase process starts, the Suspend
command requests that the WSM suspend the program or erase sequence at predetermined points
in the algorithm. The partition that is actually suspended continues to output status register data
after the Suspend command is written. An operation is suspended when status bits SR[7] and SR[6]
and/or SR[2] are set.
To read data from blocks within the partition (other than an erase-suspended block), you can write
a Read Array command. Block erase cannot resume until the program operations initiated during
erase suspend are complete. Read Array, Read Status Register, Read Identifier (ID), Read Query,
and Program Resume are valid commands during Program or Erase Suspend. Additionally, Clear
Status Register, Program, Program Suspend, Erase Resume, Lock Block, Unlock Block, and Lock-
Down Block are valid commands during erase suspend.
To read data from a block in a partition that is not programming or erasing, the operation does not
need to be suspended. If the other partition is already in read array, ID, or Query mode, issuing a
valid address returns corresponding data. If the other partition is not in a read mode, one of the read
commands must be issued to the partition before data can be read.
During a suspend, CE# = VIH places the device in standby state, which reduces active current. VPP
must remain at its program level and WP# must remain unchanged while in suspend mode.
A resume command instructs the WSM to continue programming or erasing and clears status
register bits SR[2] (or SR[6]) and SR[7]. The Resume command can be written to any partition.
When read at the partition that is programming or erasing, the device outputs data corresponding to
the partition’s last mode. If status register error bits are set, the status register can be cleared before
issuing the next instruction. RST# must remain at VIH. See Figure 7, “Program Suspend / Resume
Flowchart” on page 32, and Figure 8, “Erase Suspend / Resume Flowchart” on page 33.
If a suspended partition was placed in read array, read status register, read identifier (ID), or read
query mode during the suspend, the device remains in that mode and outputs data corresponding to
that mode after the program or erase operation is resumed. After resuming a suspended operation,
issue the read command appropriate to the read operation. To read status after resuming a
suspended operation, issue a Read Status Register command (70h) to return the suspended partition
to status mode.
A minimum tWHWH time should elapse between an Erase command and a subsequent Erase
Suspend command to ensure that the device achieves sufficient cumulative erase time. Occasional
Erase-to-Suspend interrupts do not cause problems, but Erase-to-Suspend commands issued too
frequently may produce unexpected results.
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 7. Program Suspend / Resume Flowchart
PROGRAM SUSPEND / RESUME PROCEDURE
Bus
Operation
Start
Command
Comments
Data = B0h
Addr = Any address within programming
partition
Program
Suspend
Write
Write
Write B0h
Any Address
Read
Data = 70h
Status Addr = Any address in same partition
Write 70h
Same Partition
Read SRD
Read
Toggle CE# or OE# to update SRD
Addr = Any address in same partition
Read Status
Register
Check SR[7]
Standby
Standby
1 = WSM ready
0 = WSM busy
0
0
SR[7] =
1
Check SR[2]
1 = Program suspended
0 = Program completed
Program
Completed
SR[2] =
1
Data = FFh
Addr = Any device address (except word
being programmed)
Read
Array
Write
Read
Write
Write FFh
Susp Partition
Read array data from block other than
the one being programmed
Read Array
Data
Program Data = D0h
Resume Addr = any device address
If the suspended partition was placed in Read Array mode:
Done
No
Reading
Return partition to status mode:
Read
Write
Data = 70h
Yes
Status
Addr = address within same partition
Write D0h
Write FFh
Any Address
Pgm'd Partition
Program
Resumed
Read Array
Data
Write 70h
Same Partition
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 8. Erase Suspend / Resume Flowchart
ERASE SUSPEND / RESUME PROCEDURE
Bus
Start
Command
Operation
Comments
Erase
Data = B0h
Write
Write
Suspend Addr = Any address
Write B0h
Any Address
Read
Data = 70h
Status Addr = Any address in same partition
Write 70h
Same Partition
Read SRD
Read
Toggle CE# or OE# to update SRD
Addr = Any address in same partition
Read Status
Register
Check SR[7]
Standby
1 = WSM ready
0 = WSM busy
0
0
SR[7] =
1
Check SR[6]
1 = Erase suspended
0 = Erase completed
Standby
Write
Erase
Completed
SR[6] =
1
Data = FFh or 40h
Read Array
Addr = Any device address (except
or Program
block being erased)
Read or
Write
Read array or program data from/to
block other than the one being erased
Read
Program
Read or
Program?
Read Array
Data
Program
Loop
Erase
Data = D0h
No
Write
Resume Addr = Any address
If the suspended partition was placed in
Read Array mode or a Program Loop:
Done?
Yes
Return partition to status mode:
Data = 70h
Status
Read
Write
Write D0h
Any Address
Write FFh
Erased Partition
Addr = Address within same partition
Read Array
Data
Erase Resumed
Write 70h
Same Partition
6.2
Block Erase
The 2-cycle block erase command sequence, consisting of Erase Setup(20h) and Erase Confirm
(D0h), initiates one block erase at the addressed block. Only one partition can be in an erase mode
at a time; other partitions must be in a read mode. The Erase Confirm command internally latches
the address of the block to be erased. Erase forces all bits within the block to 1. SR[7] is cleared
while the erase executes.
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
After writing the Erase Confirm command, the selected partition is placed in read status register
mode and reads performed to that partition return the current status data. The address given during
the Erase Confirm command does not need to be the same address used in the Erase Setup
command. So, if the Erase Confirm command is given to partition B, then the selected block in
partition B will be erased even if the Erase Setup command was to partition A.
The 2-cycle erase sequence cannot be interrupted with a bus write operation. For example, an Erase
Setupcommand must be immediately followed by the Erase Confirm command in order to execute
properly. If a different command is issued between the setup and confirm commands, the partition
is placed in read-status mode, the status register signals a command sequence error, and all
subsequent erase commands to that partition are ignored until the status register is cleared.
The CPU can detect block erase completion by analyzing SR[7] of that partition. If an error bit
(SR[5,3,1]) was flagged, the status register can be cleared by issuing the Clear Status Register
command before attempting the next operation. The partition remains in read-status mode until
another command is written to its CUI. Any CUI instruction can follow after erasing completes.
The CUI can be set to read-array mode to prevent inadvertent status register reads.
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 9. Block Erase Flowchart
BLOCK ERASE PROCEDURE
Bus
Start
Command
Comments
Operation
Block
Erase
Setup
Data = 20h
Addr = Block to be erased (BA)
Write
Write 20h
Block Address
Erase
Data = D0h
Write
Read
Confirm Addr = Block to be erased (BA)
Write D0h and
Block Address
Read SRD
Toggle CE# or OE# to update SRD
Suspend
Erase
Loop
Read Status
Register
Check SR[7]
1 = WSM ready
0 = WSM busy
Standby
No
Suspend
Erase
0
Yes
SR[7] =
1
Repeat for subsequent block erasures.
Full status register check can be done after each block erase
or after a sequence of block erasures.
Full Erase
Status Check
(if desired)
Block Erase
Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[3]
1 = VPP error
Standby
Standby
Standby
VPP Range
Error
1
1
1
1
SR[3] =
0
Check SR[5:4]
Both 1 = Command sequence error
Command
Sequence Error
Check SR[5]
1 = Block erase error
SR[5:4] =
0
Check SR[1]
Standby
1 = Attempted erase of locked block
Erase aborted
Block Erase
Error
SR[5] =
0
SR[3,1] must be cleared before the WSM will allow further
erase attempts.
Erase of
Locked Block
Aborted
SR[1] =
0
Only the Clear Status Register command clears SR[5:3,1].
If an error is detected, clear the Status register before
attempting an erase retry or other error recovery.
Block Erase
Successful
6.3
Read-While-Write and Read-While-Erase
The 1.8 Volt Intel® Wireless Flash memory with supports flexible multi-partition dual-operation
architecture. By dividing the flash memory into many separate partitions, the device can read from
one partition while programing or erasing in another partition; hence the terms, RWW and RWE.
Both of these features greatly enhance data storage performance.
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
The product does not support simultaneous program and erase operations. Attempting to perform
operations such as these results in a command sequence error. Only one partition can be
programming or erasing while another partition is reading. However, one partition may be in erase
suspend mode while a second partition is performing a program operation, and yet another partition
is executing a read command. Table 5, “Command Codes and Descriptions” on page 17 describes
the command codes available for all functions.
7.0
Security Modes
The 1.8 Volt Intel Wireless Flash memory with 3 Volt I/O offers both hardware and software
security features to protect the flash data. The software security feature is used by executing the
Lock Block command. The hardware security feature is used by executing the Lock-Down Block
command and by asserting the WP# signal.
Refer to Figure 10, “Block Locking State Diagram” on page 37 for a state diagram of the flash
security features. Also see Figure 11, “Locking Operations Flowchart” on page 39.
7.1
Block Lock Operations
Individual instant block locking protects code and data by allowing any block to be locked or
unlocked with no latency. This locking scheme offers two levels of protection. The first allows
software-only control of block locking (useful for frequently changed data blocks), while the
second requires hardware interaction before locking can be changed (protects infrequently changed
code blocks).
The following sections discuss the locking system operation. The term “state [XYZ]” specifies
locking states; for example, “state [001],” where X = WP# value, Y = block lock-down status bit
D1, and Z = Block Lock status register bit D0. Figure 10, “Block Locking State Diagram” on
page 37 defines possible locking states.
The following summarizes the locking functionality.
• All blocks power-up in a locked state.
• Unlock commands can unlock these blocks, and lock commands can lock them again.
• The Lock-Down command locks a block and prevents it from being unlocked when WP# is
asserted.
— Locked-down blocks can be unlocked or locked with commands as long as WP# is
deasserted
— When WP# is asserted, previously locked-down blocks return to lock-down.
— The lock-down status bit is cleared only when the device is reset or powered-down.
Block lock registers are not affected by the VPP level. They may be modified and read even if VPP
≤ VPPLK
.
Each block’s locking status can be set to locked, unlocked, and lock-down, as described in the
following sections. See Figure 11, “Locking Operations Flowchart” on page 39.
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 10. Block Locking State Diagram
Locked-
Down4,5
Hardware
Locked 5
Locked
Power-Up/Reset
[X01]
[011]
[011]
WP# Hardware Control
Software
Locked
Unlocked
Unlocked
[X00]
[111]
[110]
Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0)
Software Block Lock-Down (0x60/0x2F)
WP# hardware control
NOTE: The notation [X,Y,Z] denotes the locking state of a block, The current locking state of a block is defined
by the state of WP# and the two bits of the block-lock status D[1:0].
7.1.1
7.1.2
7.1.3
Lock
All blocks default to locked (state [x01]) after initial power-up or reset. Locked blocks are fully
protected from alteration. Attempted program or erase operations to a locked block will return an
error in SR[1]. Unlocked blocks can be locked by using the Lock Block command sequence.
Similarly, a locked block’s status can be changed to unlocked or lock-down using the appropriate
software commands.
Unlock
Unlocked blocks (states [x00] and [110]) can be programmed or erased. All unlocked blocks return
to the locked state when the device is reset or powered-down. An unlocked block’s status can be
changed to the locked or locked-down state using the appropriate software commands. A locked
block can be unlocked by writing the Unlock Block command sequence if the block is not locked-
down.
Lock-Down
Locked-down blocks (state [011]) offer the user an additional level of write protection beyond that
of a regular locked block. A block that is locked-down cannot have it’s state changed by software if
WP# is asserted. A locked or unlocked block can be locked-down by writing the Lock-Down Block
command sequence. If a block was set to locked-down, then later changed to unlocked, a Lock-
Down command should be issued prior asserting WP# will put that block back to the locked-down
state. When WP# is deasserted, locked-down blocks are changed to the locked state and can then
be unlocked by the Unlock Block command.
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
7.1.4
Block Lock Status
Every block’s lock status can be read in read identifier mode. To enter this mode, issue the Read
Identifier command to the device. Subsequent reads at Block Base Address + 02h will output that
block’s lock status. For example, to read the block lock status of block 10, the address sent to the
device should be 50002h (for a top-parameter device). The lowest two data bits of the read data, D1
and D0, represent the lock status. D0 indicates the block lock status. It is set by the Lock Block
command and cleared by the Block Unlock command. It is also set when entering the lock-down
state. D1 indicates lock-down status and is set by the Lock-Down command. The lock-down status
bit cannot be cleared by software–only by device reset or power-down. See Table 11.
Table 11. Write Protection Truth Table
VPP
WP#
RST#
Write Protection
Device inaccessible
X
X
V
IL
IH
IH
IH
V
X
V
V
V
Word program and block erase prohibited
All lock-down blocks locked
IL
X
V
IL
X
V
All lock-down blocks can be unlocked
IH
7.1.5
Lock During Erase Suspend
Block lock configurations can be performed during an erase suspend operation by using the
standard locking command sequences to unlock, lock, or lock-down a block. This feature is useful
when another block requires immediate updating.
To change block locking during an erase operation, first write the Erase Suspend command. After
checking SR[6] to determine the erase operation has suspended, write the desired lock command
sequence to a block; the lock status will be changed. After completing lock, unlock, read, or
program operations, resume the erase operation with the Erase Resume command (D0h).
If a block is locked or locked-down during a suspended erase of the same block, the locking status
bits change immediately. When the erase operation is resumed, it will complete normally.
Locking operations cannot occur during program suspend. Appendix A, “Write State Machine
States” on page 77 shows valid commands during erase suspend.
7.1.6
Status Register Error Checking
Using nested locking or program command sequences during erase suspend can introduce
ambiguity into status register results.
Because locking changes require 2-cycle command sequences, for example, 60h followed by 01h
to lock a block, following the Configuration Setupcommand (60h) with an invalid command
produces a command sequence error (SR[5:4]=11b). If a Lock Block command error occurs during
erase suspend, the device sets SR[4] and SR[5] to 1 even after the erase is resumed. When erase is
complete, possible errors during the erase cannot be detected from the status register because of the
previous locking command error. A similar situation occurs if a program operation error is nested
within an erase suspend.
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
7.1.7
WP# Lock-Down Control
The Write Protect signal, WP#, adds an additional layer of block security. WP# only affects blocks
that once had the Lock-Down command written to them. After the lock-down status bit is set for a
block, asserting WP# forces that block into the lock-down state [011] and prevents it from being
unlocked. After WP# is deasserted, the block’s state reverts to locked [111] and software
commands can then unlock the block (for erase or program operations) and subsequently re-lock it.
Only device reset or power-down can clear the lock-down status bit and render WP# ineffective.
Figure 11. Locking Operations Flowchart
LOCKING OPERATIONS PROCEDURE
Start
Bus
Operation
Command
Comments
Write 60h
Block Address
Lock
Setup
Data = 60h
Addr = Block to lock/unlock/lock-down (BA)
Write
Write
Write 01,D0,2Fh
Block Address
Lock,
Unlock, or
Lockdown
Data = 01h (Lock block)
D0h (Unlock block)
2Fh (Lockdown block)
Confirm Addr = Block to lock/unlock/lock-down (BA)
Write 90h
BBA + 02h
Write
Read ID Data = 90h
(Optional)
Plane
Addr = BBA + 02h
Read Block Lock
Status
Read
(Optional)
Block Lock Block Lock status data
Status Addr = BBA + 02h
Locking
Change?
No
Confirm locking change on DQ[1:0].
(See Block Locking State Transitions Table
for valid combinations.)
Standby
(Optional)
Yes
Read
Array
Data = FFh
Addr = Any address in same partition
Write
Write FFh
Partition Address
Lock Change
Complete
7.2
Protection Register
The 1.8 Volt Intel Wireless Flash memory includes a 128-bit protection register. This protection
register is used to increase system security and for identification purposes. The protection register
value can match the flash component to the system’s CPU or ASIC to prevent device substitution.
The lower 64 bits within the protection register are programmed by Intel with a unique number in
each flash device. The upper 64 OTP bits within the protection register are left for the customer to
program. Once programmed, the customer segment can be locked to prevent further programming.
Note: The individual bits of the user segment of the protection register are OTP, not the register in total.
The user may program each OTP bit individually, one at a time, if desired. After the protection
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
register is locked, however, the entire user segment is locked and no more user bits can be
programmed.
The protection register shares some of the same internal flash resources as the parameter partition.
Therefore, RWW is only allowed between the protection register and main partitions. Table 12
describes the operations allowed in the protection register, parameter partition, and main partition
during RWW and RWE.
Table 12. Simultaneous Operations Allowed with the Protection Register
Parameter
Partition
Array Data
Protection
Register
Main
Partitions
Description
While programming or erasing in a main partition, the protection register can be
read from any other partition. Reading the parameter partition data is not
allowed if the protection register is being read from addresses within the
parameter partition.
See
Description
Read
Write/Erase
Write/Erase
Write/Erase
While programming or erasing in a main partition, read operations are allowed
in the parameter partition. Accessing the protection registers from parameter
partition addresses is not allowed.
See
Description
Read
Read
While programming or erasing in a main partition, read operations are allowed
in the parameter partition. Accessing the protection registers in a partition that
is different from the one being programmed or erased, and also different from
the parameter partition, is allowed.
Read
Write
While programming the protection register, reads are only allowed in the other
main partitions. Access to the parameter partition is not allowed. This is
because programming of the protection register can only occur in the
parameter partition, so it will exist in status mode.
No Access
Allowed
Read
Read
While programming or erasing the parameter partition, reads of the protection
registers are not allowed in any partition. Reads in other main partitions are
supported.
No Access
Allowed
Write/Erase
7.2.1
Reading the Protection Register
Writing the Read Identifier command allows the protection register data to be read 16 bits at a time
from addresses shown in Table 7, “Device Identification Codes” on page 22. The protection
register is read from the Read Identifier command and can be read in any partition.Writing the
Read Array command returns the device to read-array mode.
7.2.2
Programing the Protection Register
The Protection Program command should be issued only at the bottom partition followed by the
data to be programmed at the specified location. It programs the upper 64 bits of the protection
register 16 bits at a time. Table 7, “Device Identification Codes” on page 22 shows allowable
addresses. See also Figure 12, “Protection Register Programming Flowchart” on page 41. Issuing a
Protection Program command outside the register’s address space results in a status register error
(SR[4]=1).
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
7.2.3
Locking the Protection Register
PR-LK.0 is programmed to 0 by Intel to protect the unique device number. PR-LK.1 can be
programmed by the user to lock the user portion (upper 64 bits) of the protection register (See
Figure 13, “Protection Register Locking). This bit is set using the Protection Program command to
program “FFFDh” into PR-LK.
After PR-LK register bits are programmed (locked), the protection register’s stored values can’t be
changed. Protection Program commands written to a locked section result in a status register error
(SR[4]=1, SR[5]=1).
Figure 12. Protection Register Programming Flowchart
PROTECTION REGISTER PROGRAMMINGPROCEDURE
Bus
Operation
Start
Command
Comments
Protection
Program
Setup
Data = C0h
Addr = Protection address
Write
Write
Read
Write C0h
Addr=Prot addr
Protection Data = Data to program
Program Addr = Protection address
Write Protect.
Register
Address / Data
Read SRD
Toggle CE# or OE# to update SRD
Read Status
Register
Check SR[7]
1 = WSM Ready
0 = WSM Busy
Standby
No
SR[7] = 1?
Yes
Protection Program operations addresses must be within the
protection register address space. Addresses outside this
space will return an error.
Repeat for subsequent programming operations.
Full Status
Check
(if desired)
Full status register check can be done after each program or
after a sequence of program operations.
Program
Complete
FULL STATUS CHECK PROCEDURE
Bus
Operation
Read SRD
SR[4:3] =
Command
Comments
SR[1] SR[3] SR[4]
Standby
Standby
Standby
0
0
1
0
1
1
VPP Error
1,1
1,0
1,1
VPP Range Error
Protection register
program error
1
0
1
Register locked;
SR[4,1] =
SR[4,1] =
Programming Error
Operation aborted
SR[3] MUST be cleared before the WSM will allow further
program attempts.
Locked-Register
Program Aborted
Only the Clear Staus Register command clears SR[4:3,1].
If an error is detected, clear the status register before
attempting a program retry or other error recovery.
Program
Successful
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 13. Protection Register Locking
0x88
User-Programmable
0x85
0x84
Intel Factory-Programmed
PR Lock Register 0
0x81
0x80
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
7.3
VPP Protection
The 1.8 Volt Intel® Wireless Flash memory with provides in-system program and erase at VPP1. For
factory programming, it also includes a low-cost, backward-compatible 12 V programming
feature.(See “Factory Programming” on page 26.) The EFP feature can also be used to greatly
improve factory program performance as explained in Section 5.3, “Enhanced Factory Program
(EFP)” on p age 27.
In addition to the flexible block locking, holding the VPP programming voltage low can provide
absolute hardware write protection of all flash-device blocks. If VPP is below VPPLK, program or
erase operations result in an error displayed in SR[3]. (See Figure 14.)
Figure 14. Examples of VPP Power Supply Configurations
System supply
VCC
System supply
VCC
VPP
12 V supply
Prot# (logic signal)
VPP
≤
Ω
10K
•
•
•
•
12 V fast programming
Absolute write protection with VPP VPPLK
Low-voltage programming
Absolute write protection via logic signal
≤
System supply
VCC
System supply
VCC
(Note 1)
VPP
VPP
12 V supply
•
•
Low voltage and 12 V fast programming
Low-voltage programming
NOTE: I f the V supply can sink adequate current, you can use an appropriately valued resistor.
CC
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
8.0
Set Configuration Register
The Set Configuration Register command sets the burst order, frequency configuration, burst
length, and other parameters.
A two-bus cycle command sequence initiates this operation. The configuration register data is
placed on the lower 16 bits of the address bus (A[15:0]) during both bus cycles. The Set
Configuration Register command is written along with the configuration data (on the address bus).
This is followed by a second write that confirms the operation and again presents the configuration
register data on the address bus. The configuration register data is latched on the rising edge of
ADV#, CE#, or WE# (whichever occurs first). This command functions independently of the
applied VPP voltage. After executing this command, the device returns to read-array mode. The
configuration register’s contents can be examined by writing the Read Identifier command and
then reading location 05h. (See Table 13 and Table 14.)
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Table 13. Configuration Register Definitions
Data
Output
Config
Read
Mode
First Access Latency
Count
WAIT
Polarity
WAIT
Config
Burst
Seq
Clock
Config
Burst
Wrap
Res’d
Res’d Res’d
Burst Length
RM
15
R
LC2
13
LC1
12
LC0
11
WT
10
DOC
9
WC
8
BS
7
CC
6
R
5
R
4
BW
3
BL2
2
BL1
1
BL0
0
14
Table 14. Configuration Register Descriptions
Bit
Name
Description
Notes1
RM
0 = Synchronous Burst Reads Enabled
15
14
2
5
1 = Asynchronous Reads Enabled (Default)
Reserved
Read Mode
R
LC2-0
001 = Reserved
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5
111 = Reserved (Default)
13-11
First Access Latency
Count
WT
0 = WAIT signal is asserted low
1 = WAIT signal is asserted high (Default)
10
9
3
WAIT Signal Polarity
DOC
0 = Hold Data for One Clock
1 = Hold Data for Two Clock (Default)
Data Output Configuration
WC
0 = WAIT Asserted During Delay
1 = WAIT Asserted One Data Cycle before Delay (Default)
8
WAIT Configuration
BS
0 = Intel Burst Order
1 = Linear Burst Order (Default)
7
Burst Sequence
CC
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge (Default)
6
Clock
Configuration
5
4
R
R
Reserved
Reserved
5
5
BW
0 = Wrap bursts within burst length set by CR[2:0]
1 = Don’t wrap accesses within burst length set by CR[2:0].(Default)
3
Burst Wrap
001 = 4-Word Burst
010 = 8-Word Burst
BL2-0
2-0
4
011 = 16-Word Burst (Available on the .13 µm lithography)
111 = Continuous Burst (Default)
Burst Length
NOTES:
1. Undocumented combinations of bits are reserved by Intel for future implementations.
2. Synchronous and page read mode configurations affect reads from main blocks and parameter blocks. Status register and
configuration reads support single read cycles. CR[15]=1 disables configuration set by CR[14:0].
3. Data is not ready when WAIT is asserted.
4. Set the synchronous burst length. In asynchronous page mode, the burst length equals four words.
5. Set all reserved configuration register bits to zero.
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
8.1
8.2
Read Mode (CR[15])
All partitions support two high-performance read configurations: synchronous burst mode and
asynchronous page mode (default). CR[15] sets the read configuration to one of these modes.
Status register, query, and identifier modes support only asynchronous and single-synchronous read
operations.
First Access Latency Count (CR[13:11])
The First Access Latency Count (CR[13:11]) configuration tells the device how many clocks must
elapse from ADV# de-assertion (VIH) before the first data word should be driven onto its data pins.
The input clock frequency determines this value. See Table 13, “Configuration Register
Definitions” on page 44 for latency values. Figure 15 shows data output latency from ADV#
assertion for different latencies.
Figure 15. First Access Latency Configuration
CLK [C]
Valid
Address
Address [A]
ADV# [V]
Code 2
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
D[15:0] [Q]
Code 3
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
D[15:0] [Q]
Code 4
Valid
Output
Valid
Output
Valid
Output
Valid
Output
D[15:0] [Q]
Code 5
Valid
Output
Valid
Output
Valid
Output
D[15:0] [Q]
NOTE: Other First Access Latency Configuration settings are reserved.
Use these equations to calculate First Access Latency Count:
(1)
(2)
Clock Period (T) = 1 ÷ Frequency
Choose the number of CLK cycles, n, such that:
n × T ≥ tAVQV + tADD-DELAY + tDATA
(3)
First Access Latency Count (LC) = n – 2
You must use LC = n - 1 when the starting address is not aligned to a 4-word boundary and
CR[3]=1 (no-wrap).
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
)
Table 15. First Latency Count (LC)
Burst
Length
Aligned to 4-word
WAIT Asserted on 16-Word
Boundary Crossing?
LC Setting
Wrap
Boundary?
Yes, Occurs on Every 16 word
boundary crossing
n–1
4, 8, 16
Disabled
No
n–2
n–2
n–2
n–1
4, 8, 16
4, 8, 16
Disabled
Enabled
Enabled
X
Yes
No
Yes
X
No
No
4, 8, 16
No
Continuous
Yes, Occurs Once1
NOTE: 1. See Section 8.10, “Burst Length (CR[2:0])” on page 52 for details.
Figure 16. Word Boundary
Word 0 - 3
Word 4 - 7
Word 8 - B
Word C - F
0
1 2 3 4 5 6 7 8 9 A B C D E F
16 Word Boundary
4 Word Boundary
NOTE: The 16-word boundary is the end of the device sense word-line.
Parameters defined by CPU:
tADD-DELAY = Clock to CE#, ADV#, or Address Valid, whichever occurs last.
tDATA = Data setup to Clock.
Parameters defined by flash:
tAVQV = Address to Output Delay.
Example:
CPU Clock Speed = 40 MHz
tADD-DELAY = 6 ns (typical speed from CPU) (max)
tDATA = 4 ns (typical speed from CPU) (min)
t
AVQV = 70 ns (from AC Characteristic - Read Only Operations Table)
From Eq. (1):
From Eq. (2)
1/40 (MHz) = 25 ns
n(25 ns) ≥ 70 ns + 6 ns + 4 ns
n(25 ns) ≥ 80 ns
n ≥ 80/25 = 3.2 = 4 (Integer)
n - 1= 4 - 1 = 3 (assuming the starting address is at the 4-
From Eq. (3)
word unaligned, must use n-1)
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
First Access Latency Count Setting to the CR is Code 3.
(Figure 17, “Data Output with LC Setting at Code 3” on page 47 displays sample
data.)
The formula tAVQV (ns) + ADD-DELAY (ns) + tDATA (ns) is also known as initial access time.
t
Figure 17 shows the data output available and valid after four clocks from the assertion of ADV# in
the first clock period with the LC setting at 3.
Figure 17. Data Output with LC Setting at Code 3
tADD-DELAY
tDATA
2rd
0st
1nd
3th
4th
CLK (C)
CE# (E)
ADV# (V)
AMAX-0 (A)
Valid Address
High Z
Code 3
Valid
Output
Valid
Output
DQ15-0 (D/Q)
R103
8.3
8.4
WAIT Signal Polarity (CR[10])
If the WT bit is cleared (CR[10]=0), then WAIT is configured to be asserted low. This means that a
0 on the WAIT signal indicates that data is not ready and the data bus contains invalid data.
Conversely, if CR[10] is set, then WAIT is asserted high. In either case, if WAIT is deasserted, then
data is ready and valid. WAIT is asserted during asynchronous page mode reads.
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(CR[15]=0), and when addressing a partition that is currently in read-array mode. The WAIT signal
is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-read-array mode, such as read status, read ID, or
read query, WAIT is set to an “asserted” state as determined by CR[10]. See Figure 25, “WAIT
Signal in Synchronous Non-Read Array Operation Waveform” on page 67.
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
When the device is operating in asynchronous page mode or asynchronous single word read mode,
WAIT is set to an “asserted” state as determined by CR[10]. See Figure 21, “Page-Mode Read
Operation Waveform” on page 63, and Figure 19, “Asynchronous Read Operation Waveform” on
page 61.
From a system perspective, the WAIT signal is in the asserted state (based on CR[10]) when the
device is operating in synchronous non-read-array mode (such as Read ID, Read Query, or Read
Status), or if the device is operating in asynchronous mode (CR[15]=1). In these cases, the system
software should ignore (mask) the WAIT signal, because it does not convey any useful information
about the validity of what is appearing on the data bus.
CONDITION
WAIT
CE# = VIH
CE# = VIL
Tri-State
Active
OE#
No-Effect
Active
Synchronous Array Read
Synchronous Non-Array Read
Asserted
All Asynchronous Read and all Write Asserted
8.5
Data Hold (CR[9])
The Data Output Configuration bit (CR[9]) determines whether a data word remains valid on the
data bus for one or two clock cycles. The processor’s minimum data set-up time and the flash
memory’s clock-to-data output delay determine whether one or two clocks are needed.
A Data Output Configuration set at 1-clock data hold corresponds to a 1-clock data cycle; a Data
Output Configuration set at 2-clock data hold corresponds to a 2-clock data cycle. The setting of
this configuration bit depends on the system and CPU characteristics. For clarification, see Figure
18, “Data Output Configuration with WAIT Signal Delay” on page 49.
A method for determining this configuration setting is shown below.
To set the device at 1-clock data hold for subsequent reads, the following condition must be
satisfied:
tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)
As an example, use a clock frequency of 54 MHz and a clock period of 25 ns. Assume the data
output hold time is one clock. Apply this data to the formula above for the subsequent reads:
20 ns + 4 ns ≤ 25 ns
This equation is satisfied, and data output will be available and valid at every clock period. If tDATA
is long, hold for two cycles.
During page-mode reads, the initial access time can be determined by the formula:
tADD-DELAY (ns) + tDATA (ns) + tAVQV (ns)
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Subsequent reads in page mode are defined by:
tAPA (ns) + tDATA (ns) (minimum time)
Figure 18. Data Output Configuration with WAIT Signal Delay
CLK [C]
WAIT (CR.8 = 1)
Note 1
Note 1
tCHQV
WAIT (CR.8 = 0)
1 CLK
Valid
Output
Valid
Output
Valid
Output
DQ15-0 [Q]
Data Hold
WAIT (CR.8 = 0)
tCHTL/H
Note 1
Note 1
tCHQV
WAIT (CR.8 = 1)
2 CLK
Valid
Output
Valid
Output
DQ15-0 [Q]
Data Hold
NOTE: WAIT shown asserted high (CR[10]=1).
8.6
WAIT Delay (CR[8])
The WAIT configuration bit (CR[8]) controls WAIT signal delay behavior for all synchronous
read-array modes. Its setting depends on the system and CPU characteristics. The WAIT can be
asserted either during, or one data cycle before, a valid output.
In synchronous linear read array (no-wrapmode CR[3]=1) of 4-, 8-, 16-, or continuous-word burst
mode, an output delay may occur when a burst sequence crosses its first device-row boundary (16-
word boundary). If the burst start address is 4-word boundary aligned, the delay does not occur. If
the start address is misaligned to a 4-word boundary, the delay occurs once per burst-mode read
sequence. The WAIT signal informs the system of this delay.
8.7
Burst Sequence (CR[7])
The burst sequence specifies the synchronous-burst mode data order (see Table 16, “Sequence and
Burst Length” on page 50). Set this bit for linear or Intel burst order. Continuous burst mode
supports only linear burst order.
When operating in a linear burst mode, either 4-, 8-, or 16-word burst length with the burst wrap bit
(CR[3]) set, or in continuous burst mode, the device may incur an output delay when the burst
sequence crosses the first 16-word boundary. (See Figure 16, “Word Boundary” on page 46 for
word boundary description.) This depends on the starting address. If the starting address is aligned
to a 4-word boundary, there is no delay. If the starting address is the end of a 4-word boundary, the
output delay is one clock cycle less than the First Access Latency Count; this is the worst-case
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
delay. The delay takes place only once, and only if the burst sequence crosses a 16-word boundary.
The WAIT pin informs the system of this delay. For timing diagrams of WAIT functionality, see
these figures:
• Figure 22, “Single Synchronous Read-Array Operation Waveform” on page 64
• Figure 23, “Synchronous 4-Word Burst Read Operation Waveform” on page 65
• Figure 24, “WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform” on
page 66
Table 16. Sequence and Burst Length (Sheet 1 of 2)
Burst Addressing Sequence (Decimal)
Start
Addr.
(Dec)
Continuous
Burst
4-Word Burst
CR[2:0]=001b
8-Word Burst
CR[2:0]=010b
16-Word Burst1
CR[2:0]=011b
CR[2:0]=111b
Linear
Intel
Linear
Intel
Linear
Intel
Linear
0
1
2
3
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0-1-2...14-15
0-1-2-3-4...14-15 0-1-2-3-4-5-6-...
1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3...14-15-0 1-0-3-2-5...15-14 1-2-3-4-5-6-7-...
2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4...15-0-1 2-3-0-1-6...12-13 2-3-4-5-6-7-8-...
3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5...15-0-1-2 3-2-1-0-7...13-12 3-4-5-6-7-8-9-...
4-5-6-7-0-1-2- 4-5-6...15-0-1-2-
4
5
6
4-5-6-7-0-1-2-3
4-5-6-7-0...10-11 4-5-6-7-8-9-10...
3-
3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 5-6-7...15-0-1...4 5-4-7-6-1...11-10 5-6-7-8-9-10-11...
6-7-8-9-10-11-12-
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8...15-0-1...5
6-7-4-5-2...8-9
...
7-8-9-10-11-12-
13...
7
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9...15-0-1...6
7-6-5-4-3...9-8
14
15
14-15-0-1...13
15-0-1-2-3...14
14-15-12-13-10...0- 14-15-16-17-18-19-
1
20-...
15-14-13-12-11...1-
0
15-16-17-18-19-...
50
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Table 16. Sequence and Burst Length (Sheet 2 of 2)
0
1
2
0-1-2-3
1-2-3-4
2-3-4-5
NA
NA
NA
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
NA
NA
NA
0-1-2...14-15
1-2-3...15-16
2-3-4...16-17
NA
NA
NA
0-1-2-3-4-5-6-...
1-2-3-4-5-6-7-...
2-3-4-5-6-7-8-...
3-4-5-6-7-8-9-
10
3
4
5
6
7
3-4-5-6
NA
NA
NA
NA
NA
NA
3-4-5...17-18
4-5-6...18-19
5-6-7...19-20
6-7-8...20-21
7-8-9...21-22
NA
NA
NA
NA
NA
3-4-5-6-7-8-9-...
4-5-6-7-8-9-10...
5-6-7-8-9-10-11...
4-5-6-7-8-9-10-
11
5-6-7-8-9-10-
11-12
6-7-8-9-10-11-
12-13
6-7-8-9-10-11-12-
...
7-8-9-10-11-
12-13-14
7-8-9-10-11-12-
13...
14-15-16-17-18-
19-20-...
14
15
14-15...28-29
15-16...29-30
NA
NA
15-16-17-18-19-
20-21-...
NOTE: Available on the .13 µm lithography
8.8
8.9
Clock Edge (CR[6])
Configuring the valid clock edge enables a flexible memory interface to a wide range of burst
CPUs. Clock configuration sets the device to start a burst cycle, output data, and assert WAIT on
the clock’s rising or falling edge.
Burst Wrap (CR[3])
The burst wrapbit determines whether 4-, 8-, or 16-word burst accesses wrapwithin the burst-
length boundary or whether they cross word-length boundaries to perform linear accesses. No-
wrapmode (CR[3]=1) enables WAIT to hold off the system processor, as it does in the continuous
burst mode, until valid data is available. In no-wrapmode (CR[3]=0), the device operates similarly
to continuous linear burst mode but consumes less power during 4-, 8-, or 16-word bursts.
For example, if CR[3]=0 (wrap mode) and CR[2:0] = 1h (4-word burst), possible linear burst
sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, 3-0-1-2.
If CR[3]=1 (no-wrapmode) and CR[2:0] = 1h (4-word burst length), then possible linear burst
sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. CR[3]=1 not only enables limited non-
aligned sequential bursts, but also reduces power by minimizing the number of internal read
operations.
Setting CR[2:0] bits for continuous linear burst mode (7h) also achieves the above 4-word burst
sequences. However, significantly more power may be consumed. The 1-2-3-4 sequence, for
example, consumes power during the initial access, again during the internal pipeline lookup as the
Datasheet
51
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
processor reads word 2, and possibly again, depending on system timing, near the end of the
sequence as the device pipelines the next 4-word sequence. CR[3]=1 while in 4-word burst mode
(no-wrap mode) reduces this excess power consumption.
8.10
Burst Length (CR[2:0])
The burst length is the number of words the device outputs in a synchronous read access. 4-, 8-,
16-, and continuous-word are supported. In 4-, 8-, or 16-word burst configuration, the burst wrap
bit (CR[3]) determines if burst accesses wrapwithin word-length boundaries or whether they cross
word-length boundaries to perform a linear access. Once an address is given, the device outputs
data until it reaches the end of its burstable address space. Continuous burst accesses are linear only
(burst wrapbit CR[3] is ignored during continuous burst) and do not wrapwithin word-length
boundaries (see Table 16, “Sequence and Burst Length” on page 50).
9.0
Power Consumption
1.8 Volt Intel® Wireless Flash memory with devices have a layered approach to power savings that
can significantly reduce overall system power consumption. The APS feature reduces power
consumption when the device is selected but idle. If CE# is deasserted, the memory enters its
standby mode, where current consumption is even lower. Asserting RST# provides current savings
similar to standby mode. The combination of these features can minimize memory power
consumption, and therefore, overall system power consumption.
9.1
9.2
Active Power
With CE# at VIL and RST# at VIH, the device is in the active mode. Refer to Section 10.3, “DC
Current Characteristics” on page 56, for ICC values. When the device is in “active” state, it
consumes the most power from the system. Minimizing device active current therefore reduces
system power consumption, especially in battery-powered applications.
Automatic Power Savings (APS)
Automatic Power Saving (APS) provides low-power operation during a read’s active state. During
APS mode, ICCAPS is the average current measured over any 5 ms time interval 5 µs after the
following events happen:
• There is no internal sense activity;
• CE# is asserted;
• The address lines are quiescent, and at VSSQ or VCCQ
.
OE# may be asserted during APS.
52
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
9.3
Standby Power
With CE# at VIH and the device in read mode, the flash memory is in standby mode, which disables
most device circuitry and substantially reduces power consumption. Outputs are placed in a high-
impedance state independent of the OE# signal state. If CE# transitions to VIH during erase or
program operations, the device continues the operation and consumes corresponding active power
until the operation is complete. ICCS is the average current measured over any 5 ms time interval 5
µs after a CE# de-assertion.
9.4
Power-Up/Down Characteristics
The device is protected against accidental block erasure or programming during power transitions.
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected together; so it
doesn’t matter whether VPP or VCC powers-up first. If VCCQ and/or VPP are not connected to the
system supply, then VCC should attain VCCMIN before applying VCCQ and VPP. Device inputs
should not be driven before supply voltage = VCCMIN. Power supply transitions should only occur
when RST# is low.
9.4.1
System Reset and RST#
The use of RST# during system reset is important with automated program/erase devices because
the system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU initialization will not occur because the flash memory
may be providing status information instead of array data. To allow proper CPU/flash initialization
at system reset, connect RST# to the system CPU RESET# signal.
System designers must guard against spurious writes when VCC voltages are above VLKO
.
Because both WE# and CE# must be low for a command write, driving either signal to VIH inhibits
writes to the device. The CUI architecture provides additional protection because alteration of
memory contents can only occur after successful completion of the two-step command sequences.
The device is also disabled until RST# is brought to VIH, regardless of its control input states. By
holding the device in reset (RST# connected to system PowerGood) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
9.4.2
VCC, VPP, and RST# Transitions
The CUI latches commands issued by system software and is not altered by VPP or CE# transitions
or WSM actions. Read-array mode is its power-up default state after exit from reset mode or after
VCC transitions above VLKO (Lockout voltage).
After completing program or block erase operations (even after VPP transitions below VPPLK), the
Read Array command must reset the CUI to read-array mode if flash memory array access is
desired.
Datasheet
53
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
9.5
Power Supply Decoupling
When the device is accessed, many internal conditions change. Circuits are enabled to charge
pumps and switch voltages. This internal activity produces transient noise. To minimize the effect
of this transient noise, device decoupling capacitors are required. Transient current magnitudes
depend on the device outputs’ capacitive and inductive loading. Two-line control and proper
decoupling capacitor selection suppresses these transient voltage peaks. Each flash device should
have a 0.1 µF ceramic capacitor connected between each power (VCC, VCCQ, VPP), and ground
(VSS, VSSQ) signal. High-frequency, inherently low-inductance capacitors should be as close as
possible to package signals.
10.0
Thermal and DC Characteristics
10.1
Absolute Maximum Ratings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage.
These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended,
and extended exposure beyond the “Operating Conditions” may affect device reliability.
Notice: This datasheet contains information on products in the design phase of development. The information
here is subject to change without notice. Do not finalize a design with this information.
Table 17. Absolute Maximum Ratings
Parameter
Note
Maximum Rating
–40 °C to +85 °C
Temperature under Bias
Storage Temperature
–65 °C to +125 °C
–0.5 V to +2.45 V
–0.2 V to +14 V
–0.2 V to +2.45 V
100 mA
Voltage on Any Pin (except VCC, VCCQ, VPP)
VPP Voltage
1,2,3
VCC and VCCQ Voltage
Output Short Circuit Current
NOTES:
1
4
1. All specified voltages are relative to VSS. Minimum DC voltage is –0.5 V on input/output pins and
–0.2 V on VCC and VPP pins. During transitions, this level may undershoot to –2.0 V for periods < 20
ns which, during transitions, may overshoot to VCC +2.0 V for periods < 20 ns.
2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns.
3. VPP program voltage is normally VPP1. VPP can be 12 V 0.6 V for 1000 cycles on the main blocks
and 2500 cycles on the parameter blocks during program/erase.
4. Output shorted for no more than one second. No more than one output shorted at a time.
54
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
10.2
Operating Conditions
Table 18. Extended Temperature Operation
Symbol
Parameter1
Note
Min
Nom
Max
Unit
TA
Operating Temperature
–40
1.7
25
1.8
85
1.95
3.3
°C
VCC
VCCQ
VPP1
VPP2
tPPH
VCC Supply Voltage
3
3
2
2
2
I/O Supply Voltage
2.2
3.0
V
VPP Voltage Supply (Logic Level)
Factory Programming VPP
0.90
11.4
1.80
12.0
1.95
12.6
80
Maximum VPP Hours
VPP = 12 V
PP ≤ VCC
Hours
Main and Parameter
Blocks
V
2
100,000
Block
Erase
Cycles
Cycles
Main Blocks
VPP = 12 V
PP = 12 V
2
2
1000
2500
Parameter Blocks
V
NOTES:
1. See Section 10.3, “DC Current Characteristics” on page 56 and Section 10.4, “DC Voltage Characteristics”
on page 58 for specific voltage-range specifications.
2. VPP is normally VPP1. VPP can be connected to 11.4 V–12.6 V for 1000 cycles on main blocks for
extended temperatures and 2500 cycles on parameter blocks at extended temperature.
3. Contact your Intel field representative for VCC/VCCQ operations down to 1.65 V.
4. See the tables in Section 10.0, “Thermal and DC Characteristics” on page 54 and in Section 11.0, “AC
Characteristics” on page 59 for operating characteristics
Datasheet
55
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
10.3
DC Current Characteristics
Table 19. DC Current Characteristics (Sheet 1 of 2)
V
= 3.0 V
CCQ
Sym
Parameter (1)
Note 32/64 Mbit
128 Mbit
Unit
Test Condition
Typ Max Typ Max
VCC = VCCMax
ILI
Input Load
9
2
2
µA
µA
V
V
CCQ = VCCQMax
IN = VCCQ or GND
VCC = VCCMax
Output
Leakage
ILO
DQ[15:0]
10
10
V
V
CCQ = VCCQMax
IN = VCCQ or GND
VCC = VCCMax
V
CCQ = VCCQMax
ICCS
VCC Standby
10
6
21
6
30
µA
µA
CE# = VCC
RST# =VCC or GND
VCC = VCCMax
V
CE# = VSSQ
RST# =VCCQ
All other inputs =VCCQ or
VSSQ
CCQ = VCCQMax
ICCAPS APS
11
2
6
4
21
7
6
4
30
10
Asynchronous
Page Mode
f=13 MHz
mA 4 Word Read
Burst length
VCC
CCMax
CE# = VIL
OE# = VIH
Inputs = VIH
or VIL
=
7
9
15
16
19
22
7
9
15
16
19
22
mA
= 4
V
Average
VCC
Read
ICCR
Burst length
mA
= 8
Synchronous
CLK = 40 MHz
2
Burst length
=16
11
12
11
12
mA
Burst length
mA
= Continuous
V
PP = VPP1, Program in
18
8
40
15
40
15
21
21
18
8
40
15
40
15
30
30
mA
mA
mA
mA
µA
Progress
ICCW
VCC Program
3,4,5
3,4,5
V
PP = VPP2, Program in
Progress
PP = VPP1, Block Erase in
V
18
8
18
8
Progress
ICCE
VCC Block Erase
VPP = VPP2, Block Erase in
Progress
CE# = VCC, Program Sus-
pended
ICCWS VCC Program Suspend
6
6
6
6
CE# = VCC, Erase Sus-
pended
ICCES
VCC Erase Suspend
6
6
µA
56
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Table 19. DC Current Characteristics (Sheet 2 of 2)
V
= 3.0 V
CCQ
Sym
Parameter (1)
Note 32/64 Mbit
128 Mbit
Unit
Test Condition
Typ Max Typ Max
IPPS
VPP Standby
VPP Program Suspend
PP Erase Suspend
(IPPWS
,
IPPES
3
0.2
2
5
0.2
2
5
µA
µA
V
PP <VCC
V
)
VPP ≤ VCC
IPPR
VPP Read
15
15
V
PP = VPP1, Program in
0.05 0.10 0.05 0.10
22 16 37
0.05 0.10 0.05 0.10
22 22
Progress
IPPW
VPP Program
4
4
mA
mA
VPP = VPP2, Program in
Progress
8
VPP = VPP1, Erase in
Progress
IPPE
VPP Erase
VPP = VPP2, Erase in
Progress
8
8
NOTES:
1. All currents are RMS unless noted. Typical values at typical VCC, TA = +25°C.
2. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation. See
ICCRQ specification for details.
3. Sampled, not 100% tested.
4. VCC read + program current is the sum of VCC read and VCC program currents.
5. VCC read + erase current is the sum of VCC read and VCC erase currents.
6. ICCES is specified with device deselected. If device is read while in erase suspend, current is ICCES plus
ICCR
.
7. VPP <= VPPLK inhibits erase and program operations. Don’t use VPPL and VPPH outside their valid ranges.
8. VIL can undershoot to –0.4V and VIH can overshoot to VCCQ+0.4V for durations of 20 ns or less.
9. If VIN>VCC the input load current increases to 10 µA max.
10.ICCS is the average current measured over any 5ms time interval 5µs after a CE# de-assertion.
11.Refer to section Section 9.2, “Automatic Power Savings (APS)” on page 52 for ICCAPS measurement
details.
12.TBD values are to be determined pending silicon characterization.
Datasheet
57
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
10.4
DC Voltage Characteristics
Table 20. DC Voltage Characteristics
V
= 3.0 V
CCQ
Sym
Parameter (1)
Note
32/64 Mbit
128 Mbit
Unit
Test Condition
Min
Max
Min
Max
VIL
Input Low
8
0
0.4
0
0.4
V
V
VCCQ
– 0.4
VCCQ
– 0.4
VIH
Input High
VCCQ
0.1
VCCQ
0.1
VOL
Output Low
VCC = VCCMin
V
V
VCCQ = VCCQMin
IOL = 100 µA
VOH
Output High
VCC = VCCMin
VCCQ
– 0.1
VCCQ
– 0.1
V
CCQ = VCCQMin
IOH = –100 µA
VPPLK
VLKO
VPP Lock-Out
VCC Lock
7
0.4
1.0
0.9
0.4
1.0
0.9
V
V
V
VILKOQ VCCQ Lock
NOTE: For all numbered note references in this table, refer to the notes in Table 19, “DC Current
Characteristics” on page 56.
58
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
11.0
AC Characteristics
11.1
Read Operations
Table 21. Read Operations (Sheet 1 of 2)
32-Mbit
128-Mbit
64-Mbit
#
Sym
Parameter 1,2
Notes
Unit
-70
-85
-90
Min Max Min Max Min Max
Asynchronous Specifications
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
tAVAV
tAVQV
tELQV
tGLQV
Read Cycle Time
7,8
7,8
7,8
4
70
85
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address to Output Valid
CE# Low to Output Valid
OE# Low to Output Valid
70
70
85
85
90
90
30
30
30
tPHQV RST# High to Output Valid
150
150
150
tELQX
tGLQX
tEHQZ
CE# Low to Output Low-Z
OE# Low to Output Low-Z
CE# High to Output High-Z
5
0
0
0
0
0
0
4,5
5
20
14
20
14
20
14
tGHQZ OE# High to Output High-Z
tOH CE# (OE#) High to Output Low-Z
4,5
4,5
0
0
0
Latching Specifications
R101 tAVVH
R102 tELVH
R103 tVLQV
R104 tVLVH
R105 tVHVL
R106 tVHAX
R108 tAPA
Address Setup to ADV# High
10
10
10
10
12
12
ns
ns
ns
ns
ns
ns
ns
CE# Low to ADV# High
ADV# Low to Output Valid
ADV# Pulse Width Low
7,8
3
70
85
90
10
10
9
10
10
9
12
12
9
ADV# Pulse Width High
Address Hold from ADV# High
Page Address Access Time
25
40
25
33
30
33
Clock Specifications
R200 fCLK
R201 tCLK
R202 tCH/L
R203 tCHCL
CLK Frequency
MHz
ns
CLK Period
25
30
30
CLK High or Low Time
CLK Fall or Rise Time
9.5
9.5
9.5
ns
3
5
5
ns
Datasheet
59
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Table 21. Read Operations (Sheet 2 of 2)
32-Mbit
64-Mbit
128-Mbit
-90
#
Sym
Parameter 1,2
Notes
Unit
-70
-85
Min Max Min Max Min Max
Synchronous Specifications
R301 tAVCH
R302 tVLCH
R303 tELCH
Address Valid Setup to CLK
9
10
9
9
10
9
10
10
9
ns
ns
ns
ns
ns
ns
ADV# Low Setup to CLK
CE# Low Setup to CLK
R304 tCHQV CLK to Output Valid
R305 tCHQX Output Hold from CLK
8
3
20
20
22
22
22
22
5
5
5
R306 tCHAX
R307 tCHTV
R308 tELTV
R309 tEHTZ
R310 tEHEL
Address Hold from CLK
CLK to WAI
10
10
10
T Valid
8
20
22
22
ns
CE# Low to WAIT Valid
6
ns
ns
ns
CE# High to WAI T High-Z
CE# Pulse Width High
5,6
6
25
25
25
20
20
20
x
NOTES:
1. See Figure 33, “AC Input/Output Reference Waveform” on page 75 for timing measurements and maximum
allowable input slew rate.
2. AC specifications assume the data bus voltage is less than or equal to VCCQ when a read operation is
initiated.
3. Address hold in synchronous-burst mode is defined as tCHAX or tVHAX, whichever timing specification is
satisfied first.
4. OE# may be delayed by up to tELQV– tGLQV after the falling edge of CE# without impact to tELQV
.
5. Sampled, not 100% tested.
6. Applies only to subsequent synchronous reads.
7. During the initial access of a synchronous burst read, data from the first word may begin to be driven onto the
data bus as early as the first clock edge after tAVQV
.
8. All specs above apply to all densities.
60
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 19. Asynchronous Read Operation Waveform
R1
VIH
VIL
Valid
Address
Address [A]
CE# [E]
R2
R3
VIH
VIL
R8
R9
VIH
VIL
R4
OE# [G]
R7
VIH
VIL
WE# [W]
WAIT [T]
VOH
VOL
High Z
High Z
Note 1
VOH
VOL
High Z
Valid
Output
Data [D/Q]
RST# [P]
R5
R10
VIH
VIL
NOTES:.
1. WAIT shown asserted (CR.10=0)
2. ADV# assumed to be driven to VI L in this waveform
Datasheet
61
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 20. Latched Asynchronous Read Operation Waveform
R1
VIH
Valid
Valid
A[MAX:2] [A]
Address
Address
VIL
VIH
Valid
Valid
A[1:0] [A]
Address
Address
VIL
R2
R101
R105
VIH
R106
R103
ADV# [V]
CE# [E]
VIL
R104
R102
VIH
VIL
R3
R6
R4
R8
R9
VIH
VIL
OE# [G]
WE# [W]
Data [Q]
RST# [P]
R7
VIH
VIL
VOH
VOL
High Z
Valid
Output
R5
R10
VIH
VIL
62
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 21. Page-Mode Read Operation Waveform
R1
VIH
VIL
Valid
Address
A[MAX:2] [A]
A[1:0] [A]
R2
VIH
VIL
Valid
Valid
Valid
Valid
Address
Address
Address
Address
R101
R105
VIH
R106
R103
ADV# [V]
CE# [E]
OE# [G]
VIL
R104
R102
VIH
VIL
R3
R6
R4
R8
R9
VIH
VIL
R7
VIH
WE# [W]
WAIT [T]
VIL
VOH
High Z
High Z
R108
Note 1
VOL
VOH
VOL
High Z
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Data [D/Q]
RST# [P]
R5
R10
VIH
VIL
NOTE: WAIT shown asserted (CR.10 = 0).
Datasheet
63
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 22. Single Synchronous Read-Array Operation Waveform
VIH
Note 1
CLK [C]
VIL
R301
R306
VIH
VIL
Valid
Address
Address [A]
R2
R101
R302
R104
R105
VIH
R106
ADV# [V]
CE# [E]
VIL
R103
VIH
VIL
R3
R102
R4
R8
R9
VIH
VIL
OE# [G]
WE# [W]
WAIT [T]
Data [Q]
RST# [P]
R303
R7
VIH
VIL
R309
R10
R308
VOH
VOL
High Z
High Z
Note 2
R304
R305
VOH
VOL
High Z
Valid
Output
R5
VIH
VIL
NOTES:
1. Section 8.2, “First Access Latency Count (CR[13:11])” on page 45 describes how to insert clock cycles during
the initial access.
2. WAIT (shown asserted; CR.10=0) can be configured to assert either during, or one data cycle before, valid
data.
3. This waveform illustrates the case in which an x-word burst is initiated to the main array and it is terminated
by a CE# de-assertion after the first word in the burst. If this access had been done to Status, ID, or Query
reads, the asserted (low) WAIT signal would have remained asserted (low) as long as CE# is asserted (low).
64
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 23. Synchronous 4-Word Burst Read Operation Waveform
VIH
VIL
Note 1
CLK [C]
0
1
R301
R306
VIH
VIL
Valid
Address
Address [A]
R2
R101
R302
R104
R105
VIH
R106
ADV# [V]
CE# [E]
VIL
R103
R310
R8
VIH
VIL
R3
R102
R303
R4
VIH
VIL
OE# [G]
WE# [W]
WAIT [T]
Data [Q]
RST# [P]
R7
R9
VIH
VIL
R309
R10
R308
R307
VOH
VOL
High Z
High Z
Note 2
R304
R305
VOH
VOL
High Z
High Z
Valid
Output
Valid
Output
Valid
Output
Valid
Output
R5
VIH
VIL
NOTES:
1. Section 8.2, “First Access Latency Count (CR[13:11])” on page 45 describes how to insert clock cycles during
the initial access.
2. WAIT (shown asserted; CR.10 = 0) can be configured to assert either during, or one data cycle before, valid
data.
Datasheet
65
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 24. WAIT Functionality for EOWL (End-of-Word Line) Condition Waveform
VIH
Note 1
CLK [C]
0
1
VIL
R301
R306
VIH
VIL
Valid
Address
Address [A]
R2
R101
R302
R104
R105
VIH
R106
ADV# [V]
CE# [E]
VIL
R103
VIH
VIL
R3
R102
R4
VIH
VIL
OE# [G]
WE# [W]
WAIT [T]
Data [D/Q]
R303
R7
VIH
VIL
R308
R307
VOH
VOL
High Z
High Z
Note 2
R304
R305
VOH
VOL
High Z
Valid
Output
Valid
Output
Valid
Output
Valid
Output
R5
VIH
RST# [P]
VIL
NOTES:
1. Section 8.2, “First Access Latency Count (CR[13:11])” on page 45 describes how to insert clock cycles during
the initial access.
2. WAIT (shown asserted; CR.10=0) can be configured to assert either during, or one data cycle before, valid
data. (assumed wait delay of two clocks for example)
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Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 25. WAIT Signal in Synchronous Non-Read Array Operation Waveform
VIH
VIL
Note 1
CLK [C]
R301
R306
VIH
VIL
Valid
Address
Address [A]
R2
R101
R302
R104
R105
VIH
R106
ADV# [V]
CE# [E]
VIL
R103
VIH
VIL
R3
R102
R4
R8
R9
VIH
VIL
OE# [G]
WE# [W]
WAIT [T]
Data [Q]
RST# [P]
R303
R7
VIH
VIL
R309
R10
R308
VOH
VOL
High Z
High Z
Note 2
R304
R305
VOH
VOL
High Z
Valid
Output
R5
VIH
VIL
NOTES:
1. Section 8.2, “First Access Latency Count (CR[13:11])” on page 45 describes how to insert clock cycles during
the initial access.
2. WAIT shown asserted (CR.10=0).
Datasheet
67
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 26. Burst Suspend
R304
R305
R305
R305
CLK
R1
R2
Address [A]
R101
R105
R106
ADV#
CE# [E]
OE# [G]
R3
R8
R9
R4
R9
R4
R13
R12
WAIT [T]
WE# [W]
R7
R6
R304
Q1
R304
Q2
DATA [D/Q]
Q0
Q1
NOTE:
1. During Burst Suspend Clock signal can be held high or low
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Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
11.2
AC Write Characteristics
Table 22. AC Write Characteristics
32-Mbit
64-Mbit
128-Mbit
#
Sym
Parameter 1,2
Notes
Unit
-70
-85/-90
Min Max Min Max
tPHWL
(tPHEL
RST# High Recovery to WE#
(CE#) Low
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
3
4
150
0
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
)
tELWL
(tWLEL
CE# (WE#) Setup to WE# (CE#)
Low
)
tWLWH
(tELEH
WE# (CE#) Write Pulse Width
Low
45
45
45
0
60
60
60
0
)
tDVWH
(tDVEH
Data Setup to WE# (CE#) High
)
tAVWH
Address Setup to WE# (CE#)
High
(tAVEH
)
tWHEH
(tEHWH
CE# (WE#) Hold from WE# (CE#)
High
)
tWHDX
Data Hold from WE# (CE#) High
0
0
(tEHDX
)
tWHAX
Address Hold from WE# (CE#)
High
0
0
(tEHAX
)
tWHWL
WE# (CE#) Pulse Width High
VPP Setup to WE# (CE#) High
5,6,7
3
25
200
25
200
(tEHEL
)
tVPWH
(tVPEH
tQVVL
tQVBL
tBHWH
)
W11
W12
VPP Hold from Valid SRD
WP# Hold from Valid SRD
3,8
3,8
0
0
0
0
ns
ns
W13
W14
W16
WP# Setup to WE# (CE#) High
Write Recovery before Read
WE# High to Valid Data
3
200
0
200
0
ns
ns
ns
(tBHEH
)
tWHGL
(tEHGL
)
tAVQV
+ 40
tAVQV
+ 50
tWHQV
3,6,10
W18
W19
W20
tWHAV
tWHCV
tWHVH
WE# High to Address Valid
WE# High to CLK Valid
WE# High to ADV# High
3,9,10
3,10
0
0
ns
ns
ns
20
20
20
20
3,10
NOTES:
1. Write timing characteristics during erase suspend are the same as during write-only operations.
2. A write operation can be terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or
WE# high (whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH
.
5. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE#
low (whichever is last). Hence, tWHWL = tEHEL = tWHEL = tEHWL
.
Datasheet
69
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
6. System designers should take this into account and may insert a software No-Op instruction to delay the first
read after issuing a command.
7. For commands other than resume commands.
8. VPP should be held at VPP1 or VPP2 until block erase or program success is determined.
9. Applicable during asynchronous reads following a write.
10.tWHCH/L OR tWHVH must be met when transitioning from a write cycle to a synchronous burst read. tWHCH/L and
tWHVH both refer to the address latching event (either the rising/falling clock edge or the rising ADV# edge,
whichever occurs first).
NOTES:
Figure 27. Write Operations Waveform
VIH
VIL
CLK [C]
W19
Note 1
Note 2
W5
Note 3
Note 4
W18
Note 5
VIH
VIL
Valid
Address
Valid
Address
Valid
Address
Address [A]
R101
R105
VIH
R106
W8
ADV# [V]
VIL
R104
W2
W20
VIH
VIL
Note 6
CE# (WE#) [E(W)]
OE# [G]
W6
VIH
VIL
W3
W14
W9
VIH
VIL
Note 6
WE# (CE#) [W(E)]
Data [Q]
W1
W7
W16
VIH
VIL
Valid
SRD
Data In
Data In
W4
VIH
VIL
RST# [P]
W12
W11
W13
W10
VIH
VIL
WP# [B]
VPPH
VPPLK
VIL
VPP [V]
NOTES:
1. VCC power-up and standby.
2. Write Program or Erase Setup command.
3. Write valid address and data (for program) or Erase Confirm command.
4. Automated program/erase delay.
5. Read status register data (SRD) to determine program/erase operation completion.
6. OE# and CE# must be asserted and WE# must be deasserted for read operations.
7. CLK is ignored. (but may be kept active/toggling)
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Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 28. Asynchronous Read to Write Operation Waveform
R1
R2
W5
W8
Address [A]
CE# [E}
R3
R8
R4
R9
OE# [G]
W3
W2
W6
WE# [W]
R7
R6
W7
R10
W4
Data [D/Q]
RST# [P]
Q
D
R5
Figure 29. Asynchronous Write to Read Operation
W5
W8
R1
Address [A]
W2
W6
R10
CE# [E}
W3
W18
WE# [W]
W14
OE# [G]
R4
R2
R3
W7
R9
W4
R8
Data [D/Q]
RST# [P]
D
Q
W1
Datasheet
71
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 30. Synchronous Read to Write Operation
Latency Count
R301
R302
R306
CLK[C]
R2
W5
R101
W18
Address [A]
R105
R106
R102
R104
W20
ADV# [V]
R303
R3
R11
W6
CE# [E]
R4
R8
OE# [G]
W15
W19
W9
W3
W2
W8
WE#
R12
R307
R304
WAIT [T]
R13
R7
R305
W7
Data [D /Q]
Q
D
D
Figure 31. Synchronous Write To Read Operation
Lat ency Count
R2
R302
R301
CLK
W5
W8
R306
Address [A]
ADV#
W20
R106
R104
W6
R303
W2
R11
CE# [E}
W18
W19
W3
WE# [W]
OE# [G]
WAIT [T]
R4
R12
R307
W7
R304
R304
R305
W4
R3
Data [D/Q]
RST# [P]
D
Q
Q
W1
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Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
11.3
Erase and Program Times
Table 23. Erase and Program Times
V
V
PP2
PP1
Operation
Symbol
Parameter
Description1
Notes
Unit
Typ
Max
Typ
Max
Erasing and Suspending
W500
Erase Time
tERS/PB
tERS/MB
tSUSP/P
tSUSP/E
4-Kword Parameter Block
32-Kword Main Block
Program Suspend
2,3
2,3
2
0.3
0.7
5
2.5
4
0.25
0.4
5
2.5
4
s
s
W501
W600
10
20
10
20
µs
µs
Suspend
Latency
W601
Erase Suspend
2
5
5
Programming
W200
tPROG/W
tPROG/PB
tPROG/MB
Single Word
2
12
0.05
0.4
150
.23
1.8
8
130
0.07
0.6
µs
s
Program
Time
W201
4-Kword Parameter Block
32-Kword Main Block
2,3
2,3
0.03
0.24
W202
s
Enhanced Factory Programming5
W400
W401
W402
W403
W404
W405
tEFP/W
Single Word
4
N/A
N/A
N/A
N/A
3.5
15
16
µs
ms
ms
µs
µs
µs
Program
tEFP/PB
tEFP/MB
tEFP/SETUP
tEFP/TRAN
tEFP/VERIFY
4-Kword Parameter Block
32-Kword Main Block
EFP Setup
2,3
2,3
120
N/A
N/A
N/A
5
Operation
Latency
Program to Verify Transition
Verify
N/A
N/A
2.7
1.7
5.6
130
NOTES:
1. Unless noted otherwise, all parameters are measured at TA = +25 °C and nominal voltages, and they are sampled, not 100%
tested.
2. Excludes external system-level overhead.
3. Exact results may vary based on system overhead.
4. W400-Typ is the calculated delay for a single programming pulse. W400-Max includes the delay when programming within a
new word-line.
5. Some EFP performance degradation may occur if block cycling exceeds 10.
Datasheet
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
11.4
Reset Specifications
Table 24. Reset Specifications
#
Symbol
Parameter1
Notes
Min
Max
Unit
P1
tPLPH
RST# Low to Reset during Read
RST# Low to Reset during Block Erase
RST# Low to Reset during Program
VCC Power Valid to Reset
1, 2, 3, 4
1, 3, 4, 5
1, 3, 4, 5
1,3,4,5,6
100
ns
µs
µs
µs
20
10
P2
tPLRH
tVCCPH
P3
60
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. The device may reset if tPLPH< tPLPHMin, but this is not guaranteed.
3. Not applicable if RST# is tied to VCC.
4. Sampled, but not 100% tested.
5. If RST# is tied to VCC, the device is not ready until tVCCPH occurs after when VCC ≥ VCCMin.
6. I f RST# is tied to any supply/signal with VCCQ voltage levels, the RST# input voltage must not exceed VCC until VCC
CCMin.
≥
V
Figure 32. Reset Operations Waveforms
P1
P2
P2
P3
R5
VIH
VIL
(
A) Reset during
RST# [P]
RST# [P]
RST# [P]
VCC
read mode
Abort
Complete
R5
(B) Reset during
VIH
VIL
program or block erase
P1
≤ P2
Abort
Complete
R5
(C) Reset during
VIH
VIL
program or block erase
P1
≥ P2
VCC
0V
(D) VCC Power-up to
RST# high
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Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
11.5
AC I/O Test Conditions
Figure 33. AC Input/Output Reference Waveform
VCCQ
Test Points
Input
V
CCQ/2
VCCQ/2
Output
0V
NOTE: Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns.
Worst case speed conditions are when VCC = VCCMin.
Figure 34. Transient Equivalent Testing Load Circuit
VCCQ
R1
Device
Under Test
Out
CL
R2
NOTE: See Table 17 for component values.
Table 25. Test Configuration Component Values for Worst Case Speed Conditions
Test Configuration
VCCQMin Standard Test
C
(pF)
R
(kΩ)
R (kΩ)
2
L
1
30
25
25
NOTE: CL includes jig capacitance.
Figure 35. Clock Input AC Waveform
R201
VIH
CLK [C]
VIL
R202
R203
Datasheet
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
11.6
Device Capacitance
TA = +25 °C, f = 1 MHz
Symbol
CIN
Parameter§
Typ
Max
Unit
Condition
Input Capacitance
Output Capacitance
CE# Input Capacitance
6
8
8
pF
pF
pF
VIN = 0.0 V
VOUT = 0.0 V
VIN = 0.0 V
COUT
CCE
12
12
10
§Sampled, not 100% tested.
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Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Appendix A Write State Machine States
This table shows the command state transitions based on incoming commands. Only one partition
can be actively programming or erasing at a time.
Figure 36. Write State Machine — Next State Table (Sheet 1 of 2)
Chip Next State after Command Input
Enhanced BE Confirm,
Factory P/E Resume,
Clear
Status
Register(6)
Program/
Erase
Suspend
Read
Array(3)
Program
Setup(4,5)
Erase
Setup(4,5)
Read
Status
Read
ID/Query
Current Chip
State(8)
Pgm
Setup(4)
ULB
Confirm(9)
(FFH)
(10H/40H)
(20H)
(30H)
(D0H)
(B0H)
(70H)
(50H)
(90H, 98H)
Program
Setup
Erase
Setup
EFP
Setup
Ready
Ready
Ready
Lock/CR Setup
OTP
Ready (Lock Error)
Ready
Ready (Lock Error)
Setup
Busy
OTP Busy
Setup
Busy
Program Busy
Program
Erase
Program Busy
Pgm Susp
Program Busy
Suspend
Setup
Busy
Program Suspend
Ready (Error)
Pgm Busy
Program Suspend
Ready (Error)
Erase Busy
Erase Busy
Erase Susp
Erase Busy
Pgm in
Erase
Susp Setup
Erase
Suspend
Suspend
Erase Suspend
Erase Busy
Erase Suspend
Setup
Busy
Program in Erase Suspend Busy
Pgm Susp in
Erase Susp
Program in
Erase Suspend
Program in Erase Suspend Busy
Program in Erase Suspend Busy
Pgm in Erase
Susp Busy
Suspend
Program Suspend in Erase Suspend
Program Suspend in Erase Suspend
Lock/CR Setup in Erase
Suspend
Erase Suspend
(Lock Error)
Erase Suspend (Lock Error)
Ready (Error)
Erase Susp
Setup
EFP Busy
EFP Busy(7)
Verify Busy(7)
Ready (Error)
Enhanced
Factory
EFP Busy
EFP Verify
Program
Output Next State after Command Input
Pgm Setup,
Erase Setup,
OTP Setup,
Pgm in Erase Susp Setup,
EFP Setup,
Status
EFP Busy,
Verify Busy
Lock/CR Setup,
Lock/CR Setup in Erase Susp
Status
OTP Busy
Status
Ready,
Pgm Busy,
Pgm Suspend,
Erase Busy,
Erase Suspend,
Pgm In Erase Susp Busy,
Pgm Susp In Erase Susp
Output
does not
change
Array(3)
Status
Output does not change
Status
ID/Query
Datasheet
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 36. Write State Machine — Next State Table (Sheet 2 of 2)
Chip Next State after Command Input
Lock,
Unlock,
Lock-down,
CR setup(5)
Lock-
Enhanced
Fact Pgm
Exit (blk add
<> WA0)
Lock
Block
Confirm(9)
Illegal
commands or
EFP data(2)
OTP
Setup(5)
Down
Block
Confirm(9)
Write CR
Confirm(9)
WSM
Operation
Completes
Current Chip
State(8)
(60H)
(C0H)
(01H)
(2FH)
(03H)
Ready
Ready
(XXXXH)
(other codes)
Lock/CR
Setup
OTP
Setup
Ready
N/A
Lock/CR Setup
OTP
Ready (Lock Error)
Ready
Ready
Ready (Lock Error)
Setup
Busy
OTP Busy
Ready
N/A
Setup
Busy
Program Busy
Program Busy
Program Suspend
Ready (Error)
Program
Erase
Ready
Suspend
Setup
Busy
N/A
Erase Busy
Erase Busy
Ready
Lock/CR
Setup in
Erase Susp
Suspend
Erase Suspend
N/A
Setup
Busy
Program in Erase Suspend Busy
Program in Erase Suspend Busy
Erase
Suspend
Program in
Erase Suspend
Suspend
Program Suspend in Erase Suspend
Lock/CR Setup in Erase
Suspend
Erase Suspend
(Lock Error)
Erase Susp Erase Susp Erase Susp Erase Suspend (Lock Error)
N/A
Setup
Ready (Error)
EFP Verify
Enhanced
Factory
Program
EFP Busy(7)
Verify Busy(7)
EFP Busy(7)
EFP Verify(7)
EFP Busy
EFP Verify
Ready
Ready
Output Next State after Command Input
Pgm Setup,
Erase Setup,
OTP Setup,
Pgm in Erase Susp Setup,
EFP Setup,
Status
EFP Busy,
Verify Busy
Lock/CR Setup,
Lock/CR Setup in Erase Susp
Status
Array
Status
Output does
not change
OTP Busy
Ready,
Pgm Busy,
Pgm Suspend,
Erase Busy,
Output does
not change
Status
Output does not change
Array
Erase Suspend,
Pgm In Erase Susp Busy,
Pgm Susp In Erase Susp
NOTES:
1. The output state shows the type of data that appears at the outputs if the partition address is the same as the
command address.
A partition can be placed in Read Array, Read Status or Read ID/CFI, depending on the command issued.
Each partition stays in its last output state (Array, ID/CFI or Status) until a new command changes it. The next
WSM state does not depend on the partition's output state.
For example, if partition #1's output state is Read Array and partition #4's output state is Read Status, every
read from partition #4 (without issuing a new command) outputs the Status register.
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Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
2. Illegal commands are those not defined in the command set.
3. All partitions default to Read Array mode at power-up. A Read Array command issued to a busy partition
results in undermined data when a partition address is read.
4. Both cycles of 2 cycles commands should be issued to the same partition address. If they are issued to
different partitions, the second write determines the active partition. Both partitions will output status
information when read.
5. If the WSM is active, both cycles of a 2 cycle command are ignored. This differs from previous Intel devices.
6. The Clear Status command clears status register error bits except when the WSM is running (Pgm Busy,
Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, EFP modes) or suspended (Erase Suspend, Pgm
Suspend, Pgm Suspend In Erase Suspend).
7. EFP writes are allowed only when status register bit SR.0 = 0. EFP is busy if Block Address = address at EFP
Confirm command. Any other commands are treated as data.
8. The "current state" is that of the WSM, not the partition.
9. Confirm commands (Lock Block, Unlock Block, Lock-down Block, Configuration Register) perform the
operation and then move to the Ready State.
10.In Erase suspend, the only valid two cycle commands are "Program Word", "Lock/Unlock/Lockdown Block",
and "CR Write". Both cycles of other two cycle commands ("OEM CAM program & confirm", "Program OTP &
confirm", "EFP Setup & confirm", "Erase setup & confirm") will be ignored. In Program suspend or Program
suspend in Erase suspend, both cycles of all two cycle commands will be ignored.
Datasheet
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1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Appendix B Common Flash Interface
This appendix defines the data structure or “database” returned by the Common Flash Interface
(CFI) Query command. System software should parse this structure to gain critical information
such as block size, density, x8/x16, and electrical specifications. Once this information has been
obtained, the software will know which command sets to use to enable flash writes, block erases,
and otherwise control the flash component. The Query is part of an overall specification for
multiple command set and control interface descriptions called Common Flash Interface, or CFI.
B.1
Query Structure Output
The Query database allows system software to obtain information for controlling the flash device.
This section describes the device’s CFI-compliant interface that allows access to Query data.
Query data are presented on the lowest-order data outputs (DQ0-7) only. The numerical offset
value is the address relative to the maximum bus width supported by the device. On this family of
devices, the Query table device starting address is a 10h, which is a word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,” appear on
the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00h data on upper
bytes. The device outputs ASCII “Q” in the low byte (DQ0-7) and 00h in the high byte (DQ8-15).
At Query addresses containing two or more bytes of information, the least significant data byte is
presented at the lower address, and the most significant data byte is presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal notation, so the
“h” suffix has been dropped. In addition, since the upper byte of word-wide devices is always
“00h,” the leading “00” has been dropped from the table notation and only the lower byte value is
shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
Table 26. Summary of Query Structure Output as a Function of Device and Mode
Hex
Hex
ASCII
Device
Offset Code Value
00010:
00011:
00012:
51
52
59
"Q"
"R"
"Y"
Device Addresses
Table 27. Example of Query Structure Output of x16- and x8 Devices
Word Addressing:
Byte Addressing:
Offset
AX–A0
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
...
Hex Code
D15–D0
0051
0052
0059
P_IDLO
P_IDHI
PLO
Value
Offset
AX–A0
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
...
Hex Code
D7–D0
51
52
59
P_IDLO
P_IDLO
P_IDHI
...
Value
"Q"
"R"
"Y"
"Q"
"R"
"Y"
PrVendor
ID #
PrVendor
TblAdr
AltVendor
ID #
PrVendor
I D #
I D #
PHI
...
A_IDLO
A_IDHI
...
...
80
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
B.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI)
Query structure or “database.” The structure sub-sections and address locations are summarized
below.
Table 28. Query Structure
Description(1)
Offset
Sub-Section Name
00000h
Manufacturer Code
00001h
Device Code
Block-specific information
(BA+2)h(2)
Block Status register
00004-Fh Reserved
Reserved for vendor-specific information
Command set ID and vendor data offset
Device timing & voltage information
Flash device layout
00010h
0001Bh
00027h
CFIquery identification string
System interface information
Device geometry definition
Vendor-defined additional information specific
to the Primary Vendor Algorithm
P(3)
Primary Intel-specific Extended Query Table
NOTES:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a
function of device bus width and mode.
2. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is
32K-word).
3. Offset 15 defines “P” which points to the Primary Intel-specific Extended Query Table.
B.3
Block Status Register
The Block Status Register indicates whether an erase operation completed successfully or whether
a given block is locked or can be accessed for flash program/erase operations.
Block Erase Status (BSR.1) allows system software to determine the success of the last block erase
operation. BSR.1 can be used just after power-up to verify that the VCC supply was not
accidentally removed during an erase operation.
Table 29. Block Status Register
Offset
Length
Description
Block Lock Status Register
Add.
BA+2 --00 or --01
Value
(BA+2)h(1)
1
BSR.0 Block lock status
0 = Unlocked
BA+2 (bit 0): 0 or 1
1 = Locked
BSR.1 Block lock-down status
0 = Not locked down
1 = Locked down
BA+2 (bit 1): 0 or 1
BA+2 (bit 2–7): 0
BSR 2–7: Reserved for future use
NOTES:
1. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is
32K-word).
B.4
CFI Query Identification String
The Identification String provides verification that the component supports the Common Flash
Interface specification. It also indicates the specification version and supported vendor-specified
command set(s).
Datasheet
81
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Table 30. CFI Identification
Hex
Code
--51
--52
--59
--03
--00
--39
--00
--00
--00
--00
--00
Offset
Length
Description
Query-unique ASCII string “QRY“
Add.
10:
11:
12:
13:
14:
15:
16:
17:
18:
19:
1A:
Value
"Q"
"R"
10h
3
"Y"
2
2
2
2
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms
Extended Query Table primary algorithm address
13h
15h
17h
19h
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists
Secondary algorithm Extended Query Table address.
0000h means none exists
Table 31. System Interface Information
Hex
Offset
Length
Description
Add. Code Value
1Bh
1
V
CC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
1B:
1C:
1D:
1E:
--17 1.7V
--19 1.9V
--B4 11.4V
--C6 12.6V
--04 16µs
1Ch
1Dh
1Eh
1
1
1
VCC logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VPP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
VPP [programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
“n” such that typical single word program time-out = 2n µ-sec
“n” such that typical max. buffer write time-out = 2n µ-sec
“n” such that typical block erase time-out = 2n m-sec
1Fh
20h
21h
22h
23h
24h
25h
26h
1
1
1
1
1
1
1
1
1F:
20:
21:
22:
23:
24:
25:
26:
--00
--0A
--00
NA
1s
NA
“n” such that typical full chip erase time-out = 2n m-sec
“n” such that maximum word program time-out = 2n times typical
“n” such that maximum buffer write time-out = 2n times typical
“n” such that maximum block erase time-out = 2n times typical
“n” such that maximum chip erase time-out = 2n times typical
--04 256µs
--00
--03
--00
NA
8s
NA
82
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
B.5
Device Geometry Definition
Table 32. Device Geometry Definition
Offset
27h
Length
Description
Code
See table below
“n” such that device size = 2n in number of bytes
Flash device interface code assignment:
1
27:
28:
"n" such that n+1 specifies the bit field that represents the flash
device width capabilities as described in the table:
7
6
5
4
3
2
1
0
28h
2
—
—
—
—
x64
x32
x16
9
x8
8
--01
x16
0
15
14
13
12
11
10
—
—
—
—
—
—
—
—
29:
2A:
2B:
2C:
--00
--00
--00
“n” such that maximum number of bytes in write buffer = 2n
2
1
2Ah
2Ch
Number of erase block regions (x) within device:
1. x = 0 means no erase blocking; the device erases in bulk
2. x specifies the number of device regions with one or
more contiguous same-size erase blocks.
See table below
3. Symmetrically blocked partitions have one blocking region
Erase Block Region 1 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
4
4
4
2Dh
31h
35h
2D:
2E:
2F:
30:
31:
32:
33:
34:
35:
36:
37:
38:
See table below
See table below
See table below
Erase Block Region 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Reserved for future erase block region information
32 Mbit
64 Mbit
128 Mbit
–B
Address
–B
–T
–B
–T
–T
27:
28:
29:
2A:
2B:
2C:
2D:
2E:
2F:
30:
31:
32:
33:
34:
35:
36:
37:
38:
--16
--01
--00
--00
--00
--02
--07
--00
--20
--00
--3E
--00
--00
--01
--00
--00
--00
--00
--16
--01
--00
--00
--00
--02
--3E
--00
--00
--01
--07
--00
--20
--00
--00
--00
--00
--00
--17
--01
--00
--00
--00
--02
--07
--00
--20
--00
--7E
--00
--00
--01
--00
--00
--00
--00
--17
--01
--00
--00
--00
--02
--7E
--00
--00
--01
--07
--00
--20
--00
--00
--00
--00
--00
--18
--01
--00
--00
--00
--02
--07
--00
--20
--00
--FE
--00
--00
--01
--00
--00
--00
--00
--18
--01
--00
--00
--00
--02
--FE
--00
--00
--01
--07
--00
--20
--00
--00
--00
--00
--00
Datasheet
83
B.6
Intel-Specific Extended Query Table
Table 33. Primary Vendor-Specific Extended Query
Offset(1)
P = 39h
Hex
Length
Description
(Optional flash features and commands)
Primary extended query table
Add. Code Value
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
(P+8)h
3
39:
3A:
3B:
3C:
3D:
3E:
3F:
40:
41:
--50
--52
--49
--31
--33
--E6
--03
--00
--00
"P"
"R"
"I"
"1"
"3"
Unique ASCII string “PRI“
1
1
4
Major version number, ASCII
Minor version number, ASCII
Optional feature and command support (1=yes, 0=no)
bits 10–31 are reserved; undefined bits are “0.” If bit 31 is
“1” then another 31 bit field of Optional features follows at
the end of the bit–30 field.
bit 0 Chip erase supported
bit 1 Suspend erase supported
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
bit 7 Pagemode read supported
bit 8 Synchronous read supported
bit 0 = 0
No
Yes
Yes
No
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 1
bit 8 = 1
bit 9 = 1
No
Yes
Yes
Yes
Yes
Yes
bit 9 Simultaneous operations supported
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
(P+9)h
1
2
42:
--01
bits 1–7 reserved; undefined bits are “0”
bit 0 Program supported after erase suspend
Block status register mask
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Down Bit Status active
VCC logic supply highest performance program/erase voltage
bit 0 = 1
Yes
(P+A)h
(P+B)h
43:
44:
--03
--00
bit 0 = 1
bit 1 = 1
Yes
Yes
(P+C)h
(P+D)h
1
1
45:
--18 1.8V
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
PP optimum program/erase supply voltage
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
V
46:
--C0 12.0V
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Table 34. Protection Register Information
Offset(1)
Hex
Length
Description
P = 39h
(P+E)h
(Optional flash features and commands)
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection fields are available
Protection Field 1: Protection Description
This field describes user-available One Time Programmable
(OTP) Protection register bytes. Some are pre-programmed
with device-unique serial numbers. Others are user
programmable. Bits 0–15 point to the Protection register Lock
byte, the section’s first byte. The following bytes are factory
pre-programmed and user-programmable.
Add. Code Value
1
4
47:
--01
1
(P+F)h
(P+10)h
(P+11)h
(P+12)h
48:
49:
4A:
4B:
--80
--00
--03 8 byte
--03 8 byte
80h
00h
bits 0–7 = Lock/bytes Jedec-plane physical low address
bits 8–15 = Lock/bytes Jedec-plane physical high address
bits 16–23 = “n” such that 2n = factory pre-programmed bytes
bits 24–31 = “n” such that 2n = user programmable bytes
Table 35. Burst Read Information for Non-muxed Device
Offset(1)
P = 39h
Hex
Length
Description
(Optional flash features and commands)
Add. Code Value
(P+13)h
1
Page Mode Read capability
4C:
--03 8 byte
bits 0–7 = “n” such that 2n HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read page buffer.
(P+14)h
(P+15)h
1
1
Number of synchronous mode read configuration fields that
4D:
4E:
--04
--01
4
4
follow. 00h indicates no burst capability.
Synchronous mode read capability configuration 1
Bits 3–7 = Reserved
bits 0–2 “n” such that 2n+1 HEX value represents the
maximum number of continuous synchronous reads when
the device is configured for its maximum word width. A value
of 07h indicates that the device is capable of continuous
linear bursts that will output data until the internal burst
counter reaches the end of the device’s burstable address
space. This field’s 3-bit value can be written directly to the
Read Configuration Register bits 0–2 if the device is
configured for its maximum word width. See offset 28h for
word width to determine the burst data output width.
Synchronous mode read capability configuration 2
Synchronous mode read capability configuration 3
Synchronous mode read capability configuration 4
(P+16)h
(P+17)h
(P+18)h
1
1
1
4F:
50:
51:
--02
--03
--07 Cont
8
16
Table 36. Partition and Erase-block Region Information
Offset(1)
See table below
Address
Len
P = 39h
Description
(Optional flash features and commands)
Bot
Top
Bottom
Top
(P+19)h (P+19)h Number of device hardware-partition regions within the device.
x = 0: a single hardware partition device (no fields follow).
x specifies the number of device partition regions containing
one or more contiguous erase block regions.
1
52:
52:
Datasheet
85
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Partition Region 1 Information
Offset(1)
P = 39h
See table below
Address
Description
Bot
53:
54:
55:
Top
53:
54:
55:
Bottom
(P+1A)h (P+1A)h
(P+1B)h (P+1B)h
Top
(Optional flash features and commands)
Number of identical partitions within the partition region
Len
2
(P+1C)h (P+1C)h Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
1
1
bits 4–7 = number of simultaneous Erase operations
(P+1D)h (P+1D)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+1E)h (P+1E)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+1F)h (P+1F)h Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
56:
57:
58:
56:
57:
58:
1
1
(P+20)h (P+20)h Partition Region 1 Erase Block Type 1 Information
4
59:
5A:
5B:
5C:
5D:
5E:
5F:
59:
5A:
5B:
5C:
5D:
5E:
5F:
(P+21)h (P+21)h
(P+22)h (P+22)h
(P+23)h (P+23)h
(P+24)h (P+24)h
(P+25)h (P+25)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Partition 1 (Erase Block Type 1)
Minimum block erase cycles x 1000
2
1
(P+26)h (P+26)h Partition 1 (erase block Type 1) bits per cell; internal ECC
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+27)h (P+27)h Partition 1 (erase block Type 1) page mode and synchronous
mode capabilities defined in Table 10.
1
4
60:
60:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
(P+28)h
(P+29)h
(P+2A)h
(P+2B)h
(P+2C)h
(P+2D)h
(P+2E)h
Partition Region 1 Erase Block Type 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(bottom parameter device only)
Partition 1 (Erase block Type 2)
Minimum block erase cycles x 1000
61:
62:
63:
64:
65:
66:
67:
2
1
Partition 1 (Erase block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+2F)h
Partition 1 (Erase block Type 2) pagemode and synchronous
mode capabilities defined in Table 10
1
68:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
86
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Partition Region 2 Information
Offset(1)
P = 39h
See table below
Description
Address
Bot
Top
61:
62:
63:
Bottom
Top
(Optional flash features and commands)
Len
2
(P+30)h (P+28)h Number of identical partitions within the partition region
(P+31)h (P+29)h
(P+32)h (P+2A)h Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
69:
6A:
6B:
1
1
1
1
(P+33)h (P+2B)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+34)h (P+2C)h Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+35)h (P+2D)h Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
6C:
6D:
6E:
64:
65:
66:
(P+36)h (P+2E)h Partition Region 2 Erase Block Type 1 Information
4
6F:
70:
71:
72:
73:
74:
75:
67:
68:
69:
6A:
6B:
6C:
6D:
(P+37)h (P+2F)h
(P+38)h (P+30)h
(P+39)h (P+31)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
(P+3A)h (P+32)h Partition 2 (Erase block Type 1)
(P+3B)h (P+33)h Minimum block erase cycles x 1000
(P+3C)h (P+34)h Partition 2 (Erase block Type 1) bits per cell
bits 0–3 = bits per cell in erase region
2
1
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+3D)h (P+35)h Partition 2 (erase block Type 1) pagemode and synchronous
mode capabilities as defined in Table 10.
1
4
76:
6E:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
(P+36)h Partition Region 2 Erase Block Type 2 Information
6F:
70:
71:
72:
73:
74:
75:
(P+37)h
(P+38)h
(P+39)h
(P+3A)h
(P+3B)h
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Partition 2 (Erase Block Type 2)
Minimum block erase cycles x 1000
2
1
(P+3C)h Partition 2 (Erase Block Type 2) bits per cell
bits 0–3 = bits per cell in erase region
bit 4 = reserved for “internal ECC used” (1=yes, 0=no)
bits 5–7 = reserved for future use
(P+3D)h Partition 2 (Erase block Type 2) pagemode and synchronous
mode capabilities as defined in Table 10.
1
76:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
(P+3E)h (P+3E)h Features Space definitions (Reserved for future use)
(P+3F)h (P+3F)h Reserved for future use
TBD
Resv'd 78:
77:
77:
78:
Datasheet
87
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Partition and Erase-block Region Information
Address
32 Mbit
64Mbit
128Mbit
–B
–T
–B
–T
–B
–T
52:
53:
54:
55:
56:
57:
58:
59:
5A:
5B:
5C:
5D:
5E:
5F:
60:
61:
62:
63:
64:
65:
66:
67:
68:
69:
6A:
6B:
6C:
6D:
6E:
6F:
70:
71:
72:
73:
74:
75:
76:
--02
--01
--00
--11
--00
--00
--02
--07
--00
--20
--00
--64
--00
--01
--03
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--02
--07
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--01
--00
--11
--00
--00
--02
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--20
--00
--64
--00
--01
--03
--02
--01
--00
--11
--00
--00
--02
--07
--00
--20
--00
--64
--00
--01
--03
--06
--00
--00
--01
--64
--00
--01
--03
--0F
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--02
--0F
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--01
--00
--11
--00
--00
--02
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--20
--00
--64
--00
--01
--03
--02
--01
--00
--11
--00
--00
--02
--07
--00
--20
--00
--64
--00
--01
--03
--06
--00
--00
--01
--64
--00
--01
--03
--1F
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--02
--1F
--00
--11
--00
--00
--01
--07
--00
--00
--01
--64
--00
--01
--03
--01
--00
--11
--00
--00
--02
--06
--00
--00
--01
--64
--00
--01
--03
--07
--00
--20
--00
--64
--00
--01
--03
NOTES:
1. The variable P is a pointer which is defined at CFIoffset 15h.
2. TPD - Top parameter device; BPD - Bottom parameter device.
3. Partition: Each partition is 4Mb in size. It can contain main blocks OR a combination of both main and
parameter blocks.
4. Partition Region: Symmetrical partitions form a partition region. (there are two partition regions, A. contains
all the partitions that are made up of main blocks only. B. contains the partition that is made up of the
parameter and the main blocks.
88
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Appendix C Mechanical Specifications
Figure 37. 32-Mbit and 64-Mbit VF BGA, 0.75 mm Ball Pitch, 7×8 Ball Matrix Package Drawing
Pin # 1
Indicator
Pin # 1
Corner
s
D
1
s
2
1
2
3
4
5
6
7
8
8
7
6
5
4
3 2 1
A
B
A
B
C
D
E
F
C
D
E
E
F
G
G
e
b
Top View – Silicon Backside
Complete Ink Mark Not Shown
Bottom View – Bump Side Up
A
1
A2
A
Seating
Plane
Y
Side View
Datasheet
89
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Figure 38. 128-Mbit VF BGA, 0.75 mm Ball Pitch, 7×8 Ball Matrix Package Drawing
Ball A1
Corner
Ball A1
Corner
S1
D
S2
1
2
3
4
5
6
7
8
9
10
10
9
8
7
6
5
4
3
2 1
A
B
C
D
E
F
A
B
C
D
E
F
E
e
G
H
J
G
H
J
b
Top View - Bump Side
Down
Bottom View - Ball Side
Up
A1
A2
A
Seating
Plane
Y
Side View
Note: Drawing not to scal e
Table 37. 32-Mbit and 64-Mbit Package Dimensions
Millimeters
Nom
Inches
Dimension
Symbol
Min
Max
Min
Nom
Max
Package Height
Ball Height
A
A1
A2
b
0.850
0.150
0.615
0.325
7.600
12.400
8.900
11.900
1.000
0.0335
0.0059
0.0242
0.0128
0.2992
0.4882
0.3503
0.4685
0.0394
Package Body Thickness
0.665
0.375
7.700
12.500
9.000
12.000
0.750
56
0.715
0.425
7.800
0.0262
0.0148
0.3031
0.4921
0.3543
0.4724
0.0295
56
0.0281
0.0167
0.3071
0.4961
0.3583
0.4764
Ball (Lead) Width
Package Body Width (32Mb/64Mb)
Package Body Width (128Mb)
Package Body Length (32Mb/64Mb)
Package Body Length (128Mb)
Pitch
D
D
12.600
9.100
E
E
12.100
[e]
N
Ball (Lead) Count (32Mb/64Mb)
Ball (Lead) Count (128Mb)
N
60
60
Seating Plane Coplanarity
Y
0.100
1.325
2.975
2.350
3.100
0.0039
0.0522
0.1171
0.0925
0.1220
Corner to Ball A1 Distance Along D (32Mb/64Mb)
Corner to Ball A1 Distance Along D (128Mb)
Corner to Ball A1 Distance Along E (32Mb/64Mb)
Corner to Ball A1 Distance Along E (128Mb)
S1
S1
S2
S2
1.125
2.775
2.150
2.900
1.225
2.875
2.250
3.000
0.0443
0.1093
0.0846
0.1142
0.0482
0.1132
0.0886
0.1181
90
Datasheet
1.8 Volt Intel® Wireless Flash Memory with 3 Volt I/O
Appendix D Ordering Information
Figure 39. Component Ordering Information
R D 2 8 F 6 4 0 8 W 3 0 T 7 0
Package Designator,
Extended Temperature
(-25 C to +85 C)
GE = 0.75 MM VF BGA
RD = Stacked CSP
GT = 0.75 MM µBGA*
Access Speed
70 ns
85 ns
Parameter Partition
T = Top Parameter
Device
B = Bottom Parameter
Device
Product line designator
for all Intel® Flash products
Product Family
W30 = 1.8 Volt Intel®
Wireless Flash Memory
with 3 Volt I/O and SRAM
VCC = 1.70 V - 1.90 V
VCCQ = 2.20 V - 3.30 V
Flash Density
320 = x16 (32-Mbit)
640 = x16 (64-Mbit)
128 = x16 (128-Mbit)
SRAM Density for
Stacked-CSP Products
Only
4 = x16 (4-Mbit)
8 = x16 (8-Mbit)
Datasheet
91
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