GLT44108-40FC [ETC]
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE; 512K ×8 CMOS动态的，快速页模式内存
| 型号： | GLT44108-40FC |
| 厂家： | 
ETC |
| 描述： | 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| 文件： | 总16页 (文件大小：401K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
Features :
Description :
The GLT44108 is a 524,288 x 8 bit high-
performance CMOS dynamic random access
memory. The GLT44108 offers Fast Page mode with
asymmetric address and accepts 512-cycle refresh in
8ms interval.
*
*
*
524,288 words by 8 bits organization.
Fast access time and cycle time.
Low power dissipation.
Operating Current-150mA max.
TTL Standby Current-2mA max.
All inputs are TTL compatible. Fast Page Mode
RAS
-Only Refresh,
*
Read-Modify-Write,
operation allows random access up to 512 x 8 bits
within a page, with cycle times as short as 22ns.
The GLT44108 is best suited for graphics, digital
signal processing and high performance peripherals.
CAS
-Before-RAS Refresh, Hidden
Refresh and Test Mode Capability.
1024 refresh cycles/16ms.
Available in 28pin 400 mil SOJ
Single +5.0V±10% Power Supply.
All inputs and Outputs are TTL-
compatible.
*
*
*
*
*
Fast Page Mode supports sustained data
rates up to 50MHZ.
PIN CONFIGURATION :
GLT44108
28 Lead SOJ
Vcc
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
DQ
7
DQ0
DQ1
DQ2
DQ3
NC
WE
RAS
A9
A0
A1
A2
A3
VCC
DQ6
DQ5
DQ4
CAS
OE
NC
A8
A7
A6
A5
9
10
11
12
13
14
A
4
VSS
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 1 -
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
HIGH PERFORMANCE
-40
-50
-60
40 ns
50 ns
60 ns
RAS
Max.
Access Time, (tRAC)
Max. Column Address Access Time, (tAA)
Min. Fast Page Mode Cycle Time, (tPC)
Min. Read/Write Cycle Time, (tRC)
20 ns
22 ns
75 ns
12 ns
25 ns
31 ns
90 ns
13 ns
30 ns
40 ns
110 ns
15 ns
CAS
Max.
Access Time (tCAC
)
Pin Descriptions:
Name
Function
A0 – A9
Address Inputs
Row Address Strobe
Column Address Strobe
Write Enable
RAS
CAS
WE
Output Enable
OE
DQ0 - DQ7
VCC
VSS
Data Inputs / Outputs
+5V Power Supply
Ground
Block Diagram:
O E
W E
C A S
R A S
R A S
C A S
C L O C K
G E N E R A T O R
W E
O E
C L O C K
G E N E R A T O R
C L O C K
C L O C K
G E N E R A T O R
G E N E R A T O R
V C C
V S S
Data I/O B U S
I/O0
I/O1
I/O2
I/O3
I/O4
C O L U M N D E C O D E R S
S E N S E A M P L I F I E R S
I/O
B U F F E R
R E F R E S H
C O U N T E R
I/O5
I/O6
I/O7
Y 0 - Y8
5 1 2 × 8
9
1 0 2 4
A 0
A 1
.
A D D R E S S B U F F E R S
A N D P R E D E C O D E R S
R O W
D E C O D E R S
M E M O R Y
A R R A Y
.
A 8
A 9
X 0 - x9
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 2 -
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
Absolute Maximum Ratings*
Capacitance*
TA=25°C, VCC=5V±10%, VSS=0V
Operating Temperature, TA (ambient)
Symbol
Parameter
Max. Unit
......................................-10°C to +80°C
CIN1 Address Input
5
7
7
pF
pF
pF
Storage Temperature(plastic)....-55°C to +150°C
Voltage Relative to VSS...............-1.0V to + 7.0V
Short Circuit Output Current......................50mA
Power Dissipation......................................1.0W
CIN2
RAS CAS WE OE
,
,
,
COUT
Data Input/Output
*Note:Operation above Absolute Maximum Ratings can *Note: Capacitance is sampled and not 100% tested
adversely affect device reliability.
Electrical Specifications
l All voltages are referenced to GND.
CAS
RAS
RAS
or only
l After power up, wait more than 200ms and then, execute eight
before
refresh cycles as dummy cycles to initialize internal circuit.
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 3 -
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC=5V±10%, VSS=0V, unless otherwise specified.
Sym.
Parameter
Test Conditions
Access Min. Typ Max. Unit Notes
Time
ILI
Input Leakage Current
(any input pin)
-10
+10
0V £ VIN £ 5.5V
(All other pins not under
test=0V)
mA
ILO
Output Leakage Current
(for High-Z State)
-10
+10
0V £ Vout £ 5.5V
Output is disabled (Hiz)
mA
ICC1
Operating Current,
Random READ/WRITE
tRAC = 40ns
tRAC = 50ns
tRAC = 60ns
150
140
120
tRC = tRC (min.)
mA
1,2
ICC2
Standby Current,(TTL)
RAS
, CAS , at VIH
other inputs ³ VSS
RAS
2
mA
mA
ICC3
Refresh Current,
t
RAC = 40ns
150
140
120
cycling,
tRAC = 50ns
tRAC = 60ns
2
RAS
-Only
CAS at VIH
tRC = tRC (min.)
ICC4
Operating Current,
FAST Page Mode
tRAC = 40ns
tRAC = 50ns
tRAC = 60ns
150
140
120
RAS
at VIL,
mA
mA
1,2
1
CAS ,address
cycling:tPC=tPC(min.)
ICC5
Refresh Current,
tRAC = 40ns
tRAC = 50ns
tRAC = 60ns
150
140
120
RAS
, CAS ,
RAS
CAS Before
address cycling:
tRC=tRC(min.)
ICC6
Standby Current, (CMOS)
RAS
³ VCC-0.2V,
1
mA
CAS
³ VCC-0.2V,
All other inputs ³ VSS
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
-1
+0.8
VCC+1
0.4
V
V
V
V
3
3
VIH
VOL
2.4
IOL = 4.2mA
IOH = -5mA
VOH Output High Voltage
2.4
Notes:
1.ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output
open.
2.ICC is dependent upon the number of address transitions specified. ICC(max.) is measured with a maximum of one transition
per address cycle in random Read/Write and Fast Page Mode.
3. Specified VIL(min.) is steady state operation. During transitions, VIL(min.) may undershoot to -1.0V for a period
not to exceed 20ns.All AC parameters are measured with VIL(min.)³ Vss and VIH(max.)£Vcc.
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 4 -
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
AC Characteristics (0°C£TA£70°C,See note 1,2)
Test condition:VCC=5.0V±10%, VIH/VIL=2.4V/0.8V,VOH/VOL=2.0V/0.8V
Parameter
40 ns
50 ns
60 ns
Symbol
tRC
tRWC
MIN. MAX. MIN. MAX. MIN. MAX. Unit
Notes
Read/Write Cycle Time
Read Midify Write Cycle Time
75
120
-
-
-
40
90
140
-
-
-
50
110
160
-
-
-
60
ns
ns
ns
tRAC
3,4
3,4
RAS
Access Time from
Access Time from
tCAC
-
12
-
13
-
15
ns
CAS
Access Time from Column Address
tAA
tCLZ
-
0
20
-
-
0
25
-
-
0
30
-
ns
ns
3,4
3
CAS to Output in Low-Z
0
10
0
13
tOFF
0
8
ns
7
2
Output Buffer Turn-off Delay from CAS
Transition Time(Rise and Fall)
3
30
50
-
3
40
50
-
tT
tRP
3
25
50
-
ns
ns
RAS Precharge Time
RAS Pulse Width
50
13
50
13
18
13
5
10000
60
15
60
15
20
15
5
10000
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
40
12
40
12
16
11
5
10000
ns
ns
ns
ns
ns
ns
ns
-
-
-
RAS Hold Time
-
10000
37
-
10000
45
-
10000
30
CAS Hold Time
CAS Pulse Width
4
4
8
RAS to CAS Delay Time
RAS to Column Address Delay Time
25
30
22
-
-
-
CAS to RAS Precharge Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time Referenced
0
8
0
8
40
-
-
-
-
-
0
10
0
10
45
-
-
-
-
-
tASR
tRAH
tASC
tCAH
tAR
0
6
0
6
30
-
-
-
-
-
ns
ns
ns
ns
ns
to RAS
25
-
30
-
Column Address Lead Time Referenced
tRAL
20
-
ns
to RAS
0
0
-
-
0
0
-
-
Read Command Setup Time
Read Command Hold Time Referenced
tRCS
tRRH
0
0
-
-
ns
ns
9
9
to RAS
0
-
0
-
Read Command Hold Time Referenced
tRCH
0
-
ns
to CAS
7
-
-
10
45
-
-
tWCH
tWCR
6
-
-
ns
ns
10
5
WE
Hold Time Referenced to CAS
40
Write Command Hold Time Referenced
30
to RAS
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 5 -
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
Parameter
40 ns
50 ns
60 ns
Symbol MIN. MAX. MIN. MAX. MIN. MAX. Unit
Notes
10
7
-
-
-
10
15
15
-
-
-
tWP
6
-
-
-
ns
ns
ns
WE Pulse Width
17
14
tRWL
tCWL
13
13
WE Lead Time Referenced to RAS
WE Lead Time Referenced to CAS
Data-In Setup Time
Data-In Hold Time
0
7
40
-
-
-
0
10
45
-
-
-
tDS
tDH
tDHR
0
6
33
-
-
-
ns
ns
ns
11
11
6
Data Hold Time Referenced to RAS
Refresh Time(256cycles)
-
0
8
-
-
0
8
-
tREF
tWCS
-
0
8
-
ms
ns
5
5
5
5
WE Setup Time
70
33
43
5
-
-
-
-
85
38
53
5
-
-
-
-
tRWD
tCWD
tAWD
tCSR
60
28
38
5
-
-
-
-
ns
ns
ns
ns
RAS to WE Delay Time
CAS to WE Delay Time
Column Address to WE Delay Time
CAS Setup Time( CAS before RAS
Refresh)
10
-
10
-
tCHR
10
-
ns
CAS Hold Time( CAS before RAS
Refresh)
5
-
-
5
-
-
tRPC
tCPT
5
-
-
ns
ns
RAS to CAS Precharge Time
20
20
20
CAS Precharge Time(CBR Counter Test
Cycle)
-
30
-
35
tCPA
tPC
-
25
ns
3
Access Time from CAS Precharge
Fast Page mode Read/Write Cycle Time
35
80
-
-
40
90
-
-
30
65
-
-
ns
ns
Fast Page mode Read Modify Write Cycle tPRWC
Time
8
50
30
-
-
10
60
35
-
-
tCP
7
40
25
-
-
ns
ns
ns
ns
ns
ns
CAS Precharge Time(Fast Page mode)
125000
125000
125000
tRASP
RAS Pulse Width(Fast Page mode)
-
-
tRHCP
-
10
-
RAS Hold Time from CAS Precharge
13
-
15
-
tOEA
OE
Access Time from
OE
10
0
13
0
tOED
tOEZ
8
to Delay Time
10
13
Output Buffer Turn-off Delay Time from
0
8
7
OE
0
-
-
0
-
-
tOEH
0
-
-
ns
ns
OE
Hold Time
15
15
tWHR
15
WE Hold Time(Hidden Refresh Cycle)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 6 -
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
Notes
RAS
CAS
only Refresh or
1. An initial pause of 200ms is required after power-up followed by any 8
before RAS Refresh cycles to initialize the internal circuit.
2. VIH(min.) and VIL(min.) are reference levels for measuring timing of input signals. Transition times
are measured between VIH(min.) and VIL(max.) are assumed to be 5ns for all inputs.
3. Measured with an equivalent to 1 TTL loads and 50pF.
4. For read cycles, the access time is defined as follows:
Input Conditions
RAD £ tRAD(MAX.) and tRCD £ tRCD(MAX.)
tRAD(max.)< tRAD and tRCD £ tRCD(MAX.)
Access Time
tRAC(MAX.)
tAA(MAX.)
t
tRCD(max.)< tRCD
tCACMAX.)
tRAD(MAX.) and tRCD(MAX.) indicate the points which the access time changes and are not the limits of
operation.
5. tWCS,tRWD,tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet
as electric characteristics only. If tWCS ³ tWCS(min.), the cycle is an early write cycle and the data output
will remain high impedance for the duration of the cycle.If tCWD ³ tCWD min.),tRWD ³ tRWD (min.) and
(
tAWD ³ tAWD(min.), then the cycle is a read-modify-write cycle and the data output will contain the data
read from the selected address. If neither of the above conditions is satisfied, the condition of the
data
out is indeterminate.
6. tAR,tWCR, and tDHR are referenced to tRAD(max.)
.
7. tOFF(max.) and tOEZ(max.) define the time at which the output achieves the open circuit condition and are
not referenced to VOH or VOL.
8. tCRP(min) requirement should be applicable for RAS , CAS cycle preceded by any cycles.
9. Either tRCH(min.) or tRRH(min.) must be satisfied for a read cycle.
10. tWP(min.) is applicable for late write cycle or read modify write cycle. In early write cycles,tWCH(min.)
should be satisfied.
WE
11.This specification is referenced to CAS falling edge in early write cycles and to
falling edge in
late write or read modify write cycles.
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 7 -
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
Read Cycle
tRC
tRAS
tRP
VIH-
RAS
VIL-
CSH
t
tCRP
tCRP
tRCD
tRSH
V
IH-
CAS
tCAS
tRAL
V
IL-
tRAD
tRAH
tASR
ROW
tASC
tCAH
V
IH-
COLUMN
Address
ADDRESS
ADDRESS
V
IL-
tRCH
tRRH
tRCS
V
IH-
WE
OE
IL-
V
AR
t
tOFF
tAA
tOEZ
VIH-
OEA
t
V
IL-
tCAC
tCLZ
tRAC
V
OH-
DQ
DATA-OUT
OPEN
VOL-
Don't Care
Early Write Cycle NOTE : DOUT = Open
tRC
tRP
tRAS
VIH-
RAS
VIL-
tCSH
tCRP
tCRP
tRCD
tRSH
VIH-
CAS
tCAS
tRAL
VIL-
tRAD
tASC
tASR
tRAH
ROW
ADDRESS
tCAH
COLUMN
VIH-
Address
ADDRESS
VIL-
tCWL
tRWL
tAR
tWCR
tWCH
tWP
tWCS
VIH-
VIL-
WE
OE
VIH-
VIL-
tDHR
tDS
tDH
VIH-
VIL-
DQ
DATA - IN
Don't Care
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 8 -
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
Late Write Cycle ( OE Controlled Write) NOTE : DOUT = Open
tRC
tRP
t
RAS
V
IH-
RAS
CAS
VIL-
t
CSH
tCRP
tCRP
tRCD
tRSH
V
IH-
tCAS
V
IL-
t
RAD
tRAL
t
ASR
tCAH
tASC
t
RAH
V
IH-
ROW
ADDRESS
COLUMN
ADDRESS
Address
V
IL-
tCWL
tRWL
tRCS
V
IH-
t
WP
WE
OE
DQ
VIL-
VIH-
t
OEH
tOED
V
IL-
tDS
t
DH
VIH-
COLUMN
ADDRESS
VIL-
Don't Care
Read - Modify - Write Cycle
tRC
tRP
tRAS
VIH-
RAS
VIL-
t
CRP
tCRP
tRCD
tRSH
V
IH-
tCAS
CAS
V
IL-
t
CSH
t
RAD
t
ASR
tCAH
t
ASC
t
RAH
V
IH-
ROW
ADDR.
COLUMN
ADDRESS
Address
V
IL-
tAWD
tRWL
tCWD
tCWL
V
IH-
WE
OE
tWP
V
IL-
VIH-
tOEA
V
IL-
t
OED
t
CLZ
tDS
t
CAC
t
OEZ
t
AA
tDH
V
DQ
V
I/OH-
VALID
DATA-OUT
VALID
DATA-IN
I/OL-
tRAC
Don't Care
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 9 -
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
Fast Page Read Cycle
tRASP
tRP
VIH-
RAS
VIL-
tPC
tPC
tCRP
tASR
tRCD
tCAS
tCP
tCAS
tCP
tRSH
VIH-
CAS
tCAS
VIL-
tRAD
tCSH
tRAH
tASC
tCAH
tCAH
tASC
tASC
tCAH
VIH-
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
Address
VIL-
tRRH
tRCS
tRCS
tRCS
tRCH
tRCH
VIH-
WE
VIL-
tCAC
tOEA
tCAC
tOEA
VIH-
OE
VIL-
tAA
tOFF
tOEZ
tAA
tOFF
tOEZ
tAA
tOFF
tRAC
tCLZ
tCLZ
tCLZ
tOEZ
VIH-
DQ
VIL-
VALID
DATA-UOT
VALID
DATA-UOT
VALID
DATA-UOT
Don't Care
Fast Page Write Cycle NOTE : DOUT = Open
tRASP
tRP
VIH-
tRHCP
RAS
IL-
V
tPC
tPC
tCAS
tCRP
tRCD
tCAS
tCP
tCP
tRSH
tCAS
VIH-
VIL-
CAS
tRAD
tRAH
tASC
tCSH
tCAH
tCAH
tCAH
tASR
tASC
tASC
VIH-
VIL-
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
Address
tWCH
tWCS
tWCH
tWP
tWCS
tWP
tWCH
tWCS
tWP
VIH-
VIL-
WE
OE
tCWL
tCWL
tCWL
tRWL
VIH-
VIL-
tDS
tDH
tDS
tDS
tDS
tDS
VIH-
VIL-
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
DQ
Don't Care
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 10 -
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
Fast Page Mode Late Write Cycle
tRASP
tRP
VIH-
tRHCP
RAS
IL-
V
tCSH
tPC
tCAS
tCRP
tRCD
tCAS
tCP
tCP
tRSH
tCAS
tCRP
VIH-
VIL-
CAS
tRAD
tRAH
tCAH
tASC
tRAL
tCAH
tCAH
tASR
tASC
tASC
VIH-
VIL-
COLUMN
ADDRESS
COLUMN
ADDRESS
ROW
ADDR.
COLUMN
ADDRESS
Address
tCWL
tRWL
tWP
tCWL
tWP
tCWL
tWP
tRCS
tRCS
tRCS
VIH-
VIL-
WE
OE
tOEH
tOEH
tOEH
VIH-
VIL-
tOED tDS
tDS
tOED
tOED tDS
tDH
tDH
tDH
Hi-Z
Hi-Z
Hi-Z
VIH-
VIL-
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
DQ
Don't Care
Fast Page Read - Modify - Write Cycle
tRASP
tRP
IH-
V
V
tCSH
RAS
IL-
tRSH
tCAS
tRCD
tCAS
tCP
tCRP
VIH-
VIL-
CAS
tRAD
tPRWC
tRAL
tRAH
tCAH
tASR
tCAH
tASC
tASC
VIH-
VIL-
ROW
ADDR.
COL.
ADDR.
COL.
ADDR.
Address
WE
tRWL
tCWL
tWP
tCWL
tRCS
IH-
IL-
V
tCWD
tAWD
tCPWD
WP
t
tCWD
tAWD
V
tOEH
tRWD
VIH-
VIL-
tOEA
tOEA
OE
tDH
tCAC
tAA
tRAC
tCAC
tAA
tOED
tOEZ
tDH
tDS
tOED
tOEZ
DS
t
I/OH-
V
DQ
I/OL-
V
tCLZ
tCLZ
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
Don't Care
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 11 -
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
Before
Refresh Cycle
CAS
RAS
tRC
tRC
tRP
tRAS
tRAS
tRP
VIH-
RAS
VIL-
tCSR
tCHR
tRPC
tCSR
tCHR
tRPC
tCRP
VIH-
VIL-
CAS
RAS -Only Refresh Cycle
tRC
tRC
tRP
tRAS
tRAS
tRP
V
IH-
RAS
IL-
V
tCRP
tRPC
tCRP
V
IH-
CAS
VIL-
tRAH
tASR
tASR
tRAH
ROW
V
IH-
ROW
Address
VIL-
Hidden Refresh Cycle ( Read )
tRC
tRC
tRP
tRAS
tRAS
tRP
V
IH-
RAS
V
IL-
tCRP
tRCD
tRSH
tCHR
V
IH-
CAS
V
IL-
tRAD
tRAL
tASR
tCAH
tASC
tCAH
V
IH-
ROW
ADDRESS
COLUMN
ADDRESS
Address
V
IL-
tRCS
tWHR
V
IH-
WE
OE
tAA
V
IL-
tOEA
VIH-
VIL-
tCAC
tOFF
t
CLZ
tOEZ
t
RAC
V
IH-
DATA-OUT
DQ
OPEN
V
IL-
Don't Care
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 12 -
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
Hidden Refresh Cycle ( Write ) NOTE : DOUT =Open
tRC
tRC
tRP
tRAS
tRAS
tRP
V
IH-
RAS
V
IL-
tRCD
tCRP
tRSH
tCHR
V
IH-
CAS
V
IL-
tRAD
tASC
tCAH
tASC
t
CAH
V
IH-
ROW
ADDRESS
COLUMN
ADDRESS
Address
IL-
V
t
WCS
tWCH
tWP
VIH-
WE
OE
V
IL-
VIH-
VIL-
DS
t
DH
t
V
IH-
DATA-IN
DQ
V
IL-
Don't Care
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 13 -
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
- Before
Refresh Counter Test Cycle
RAS
CAS
tRP
tRAS
VIH-
VIL-
RAS
CAS
t
RSH
tCPT
tCSR
tCHR
t
CAS
VIH-
VIL-
tRAL
tASC
tCAH
IH-
V
COLUMN
ADDRESS
Address
VIL-
t
AA
CAC
tRRH
Read Cycle
tWRP
tWRH
t
tRCH
VIH-
VIL-
t
RCS
WE
OE
tOEA
IH-
V
VIL-
t
CEZ
tOEZ
tCLZ
VOH-
VOL-
VALID DATA-OUT
DQ
tWRP
tWRH
tRWL
Write Cycle
t
CWL
WCH
WP
tWCS
t
VIH-
t
WE
VIL-
VIH-
VIL-
OE
tDS
t
DH
VIH-
VIL-
DQ
OPEN
VALID DATA-IN
tAWD
t
CWL
RWL
WP
Read-Modify-Write
tRCS
t
CWD
t
t
VIH-
VIL-
WE
tCAC
tAA
tOEA
VIH-
OE
VIL-
tOED
tDH
tCLZ
tOEZ
t
DS
VI/OH-
DQ
VI/OL-
VALID
DATA-OUT DATA-IN
VALID
Don't Care
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 14 -
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
Ordering Information
Part Number
GLT44108-40J4
GLT44108-50J4
GLT44108-60J4
SPEED POWER
FEATURE
FPM
PACKAGE
SOJ 400mil 28L
SOJ 400mil 28L
SOJ 400mil 28L
40ns
50ns
60ns
Normal
Normal
Normal
FPM
FPM
Parts Numbers (Top Mark) Definition :
GLT 4 41
08 - 40 J4
PACKAGE
4 : DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
-SRAM
064 : 8K
256 : 256K
512 : 512K
100 : 1M
-DRAM
10 : 1M(C/EDO)*
11 : 1M(C/FPM)*
12 : 1M(H/EDO)*
13 : 1M(H/FPM)*
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
*See note
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
SPEED
-SRAM
T : PDIP(300mil)
TS : TSOP(Type I)
TC : TSOP(Type ll)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
VOLTAGE
Blank : 5V
L : 3.3V
TQ : TQFP
M : Mix Voltage
Ù
Ù
Note : C CDROM , H HDD.
Example :
1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type.
2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type.
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 15 -
G-LINK
GLT44108
512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE
Preliminary Aug 1999 (Rev.2.1)
Package Information
400mil 28 Lead Small Outline J-form Package (SOJ)
G-Link Technology
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation,Taiwan
6F, No.24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
- 16 -
相关型号：
©2020 ICPDF网 联系我们和版权申明