GLT5640L32-10 [ETC]
CMOS Synchronous DRAM 2M x 32 SDRAM; CMOS同步DRAM 2M ×32 SDRAM
| 型号： | GLT5640L32-10 |
| 厂家： | 
ETC |
| 描述： | CMOS Synchronous DRAM 2M x 32 SDRAM |
| 文件： | 总49页 (文件大小：879K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
2M x 32 SDRAM
512K x 32bit x 4Banks
Synchronous DRAM
G-Link Technology Corporation
G-Link Technology Corporation,TaiwanWeb :
www.glink.com.tw
Email : sales@glink.com.tw
TEL : 886-2-26599658
GLINK reserves the right to change products or specification without notice.
G-Link Technology Corp.
Dec 2003 Rev.0.3
1
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
TABLE OF CONTENTS
Table of Contents
… 2
… 3
… 4
… 5
… 5
… 6
… 6
… 6
… 7
… 8
… 9
… 10
… 11
… 12
… 13
… 14
… 14
Operations
Bank/Row Activation
Read Operation
Write Operation
Precharge
… 19
… 20
… 26
… 28
… 28
… 29
… 29
Device Description & Feature
Pin Assignment
Pin Description
Absolute Maximum Rating
Capacitance
Power-Down
Clock Suspend
Burst Read/Single Write
DC Characteristics & Operating Condition
AC Operating Condition
DC Characteristics
Concurrent Auto Precharge
Read with Auto Precharge
Write with Auto Precharge
… 30
… 30
… 31
AC Characteristics-I
Timing Waveforms
AC Characteristics-II
Initialize and Load Mode Register
Power-Down Mode
… 32
… 33
… 34
… 35
… 35
Device Operating Option Table
Command Truth Table
Functional Block Diagram
Simplified State Diagram
Function Description
Clock Suspend Mode
Auto Refresh Mode
Self Refresh Mode
Read Operations
Single Read without Auto Precharge
Read Without Auto Precharge
Read With Auto Precharge
Alternating Bank Read Accesses
Read Full-Page Burst
… 36
… 37
… 38
… 39
… 40
… 41
Initialization
Register Definition
Mode Register
Burst Length
Burst Type
CAS Latency
Operating Mode
Write Burst Mode
… 14
… 14
… 15
… 16
… 16
… 16
Read DQM Operation
Write Operations
Single Write without Auto Precharge
Write Without Auto Precharge
Write With Auto Precharge
Alternating Bank Write Accesses
Write Full-Page Burst
… 42
… 43
… 44
… 45
… 46
… 47
… 48
… 49
Commands
Command Inhibit
No Operation (NOP)
Load Mode Register
Active
… 17
… 17
… 17
… 17
… 17
… 17
… 17
… 18
… 18
… 18
… 18
Write DQM Operation
Memory Part Numbering
Package Dimensions
Read
Write
Precharge
Auto Precharge
Burst Terminate
Auto Refresh
Self Refresh
G-Link Technology Corp.
Dec 2003 Rev.0.3
2
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
DESCRIPTION
The G-Link GLT5640L32 is a high speed 67,108,864bits CMOS Synchronous DRAM organized as 4 banks of 524,288 words x
32 bits.
GLT5640L32 is offering fully synchronous operation and is referenced to a positive edge of the clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All
input and output voltage levels are compatible with LVTTL.
FEATURES
• JEDEC standard 3.3V power supply.
• Auto refresh and self refresh.
• Programmable CAS Latency : 2,3 clocks.
• All inputs and outputs referenced to the positive edge of
the system clock.
• All device pins are compatible with LVTTL interface.
• 4096 refresh cycle / 64ms.
• Data mask function by DQM0,1,2 and 3.
• Internal four banks operation.
• JEDEC standard 86pin 400mil TSOP-II with 0.5mm of pin
pitch.
• Burst Read Single Write operation.
• Programmable Burst Length and Burst Type.
- 1, 2, 4, 8 or Full Page for Sequential Burst.
- 4 or 8 for Interleave Burst.
• Automatic precharge, includes CONCURRENT Auto
Precharge Mode and controlled Precharge
ORDERING INFORMATION
PART No.
CLOCK Freq.
POWER
ORGANIZATION
INTERFACE
LVTTL
PACKAGE
GLT5640L32-5
GLT5640L32 -5.5
GLT5640L32 -6
GLT5640L32 -7
GLT5640L32 -8
GLT5640L32 -10
200MHz
183MHz
166MHz
143MHz
125MHz
100MHz
4 Banks
x 512K bits
x 32
86pin
400mil
TSOP-II
Normal Power
G-Link Technology Corp.
Dec 2003 Rev.0.3
3
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
PIN ASSIGNMENT (TOP VIEW)
VDD
DQ0
1
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
2
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
N.C
VDDQ
DQ1
3
4
DQ2
5
VSSQ
DQ3
6
7
DQ4
8
VDDQ
DQ5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DQ6
VSSQ
DQ7
N.C
VDD
VSS
DQM0
/WE
DQM1
N.C
/CAS
/RAS
/CS
N.C
86Pin TSOP (II)
0.5 mm Pin pitch
(400mil x 875mil)
CLK
CKE
A9
N.C
BA0
A8
BA1
A7
A10/AP
A0
A6
A5
A1
A4
A2
A3
DQM2
VDD
DQM3
VSS
N.C
N.C
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
G-Link Technology Corp.
Dec 2003 Rev.0.3
4
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
PIN DESCRIPTIONS
PIN
PIN NAME
DESCRIPTIONS
The system clock input. All other inputs are registered to the
SDRAM on the rising edge CLK
CLK
CKE
System Clock
Controls internal clock signal and when deactivated, the
SDRAM will be one of the states among power down,
suspend or self refresh
Clock Enable
CS
Chip select
Enable or disable all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
BA0, BA1
Bank Address
Row Address
Column Address
Auto-precharge flag
: RA0~RA10,
: CA0~CA7,
: A10
A0~A10/AP
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
RAS, CAS, WE
DQM0~3
Controls output buffers in read mode and masks input data in
write mode
Data Input / Output Mask
DQ0~DQ31
VDD / VSS
VDDQ / VSSQ
NC
Data Input / Output
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Power Supply/Ground
Data Output Power / Ground
No Connection
ABSOLUTE MAXIMUM RATING
PARAMETER
SYMBOL
RATING
UNIT
Ambient Temperature
Storage Temperature
TA
TSTG
0~70
-55~125
-1.0~4.6
-1.0~4.6
50
°C
°C
V
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
VIN,VOUT
VDD, VDDQ
IOS
V
mA
W
PD
1
G-Link Technology Corp.
Dec 2003 Rev.0.3
5
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
CAPACITANCE (TA=25 ℃,f=1MHz, VDD=3.3V)
PARAMETER
PIN
SYMBOL
MIN
MAX
UNIT
CLK
Cl1
2.5
4.0
pF
Input Capacitance
A0~A10,BA0, BA1, CKE, CS,
RAS, CAS, WE, DQM0~3
Cl2
2.5
4.0
5.0
6.5
pF
pF
Data Input / Output
Capacitance
DQ0~DQ31
Cl/O
DC CHARACTERISTICS & OPERATING CONDITION (TA=0 to 70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Power Supply Voltage
VDD, VDDQ
3.0
3.3
3.6
V
1, 2
Input High Voltage
VIH
2.0
3.0
VDDQ+0.3
V
1, 3
Input Low Voltage
VIL
ILI
ILO
VOH
VOL
VSSQ-0.3
-1.0
0
-
-
-
-
0.8
1.0
1.5.
-
V
1, 4
5
6
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Law Voltage
uA
uA
V
-1.5
2.4
-
IOH = -2.0mA
IOL = +2.0mA
0.4
V
Notice :
1. All voltages are referenced to VSS =0V
2. VDD/VDDQ(min) is 3.15V for GLT5640L32-5/5.5/6
3. VIH(max) is acceptable 5.6V AC pulse width with ≤ 3ns of duration with no input clamp diodes
4. VIL(min) is acceptable –2.0V AC pulse width with ≤ 3ns of duration with no input clamp diodes
5. VIN = 0 to 3.6V, All other pins are not under test = 0
6. DOUT is disabled, VOUT=0 to 3.6V
AC OPERATING CONDTION (TA=0 to 70°C, 3.0V≤VDD≤3.6V, VSS=0V - Note1)
PARAMETER
SYMBOL
TYP.
UNIT
NOTE
AC Input High / Low Level Voltage
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
Output Timing Measurement Reference Level
Output Load Capacitance for Access Time Measurement
VIH / VIL
2.4 / 0.4
V
V
ns
V
pF
-
-
-
-
Vtrip
1.4
1 / 1
1.4
tR / tF
Voutref
CL
30
2
G-Link Technology Corp.
Dec 2003 Rev.0.3
6
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
DC CHARACTERISTICS (DC Operating Conditions Unless Otherwise Noted)
SPEED
UNIT NOTE
PARAMETER
SYM.
TEST CONDITION
5
-5.5 -6 -7 -8 -10
BURST Length = 1, One Bank Active
tRAS ≥ tRAS(min), tRP ≥ tRP(min)
IOL = 0 mA
Operating Current
IDD1
230 220 200 1800 170 150
mA
1
IDD2P
CKE ≤ VIL(max), tCK = 15ns
CKE ≤ VIL(max), tCK= ∞
2
2
mA
mA
-
-
Precharge Standby Current
in Power-down Mode
IDD2PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCK= 15ns
Input signals are changed on time during 2CKLS
All this pins ≥ VDD - 0.2 or ≤ 0.2V
IDD2N
30
mA
-
Precharge Standby Current
in Non Power-down Mode
CKE ≥ VIH(min), tCK= ∞
Input signals are stable
IDD2NS
20
mA
-
IDD3P
CKE ≥ VIL(max), tCK = 15ns
CKE ≥ VIL(max), tCK= ∞
15
15
mA
mA
-
-
Active Standby Current in
Power-down Mode
IDD3PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCK=15ns
Input signals are changed on time during 2CLKS
All other pin ≥ VDD - 0.2V or ≤ 0.2V
IDD3N
IDD3NS
IDD4
60
mA
mA
mA
-
-
Active Standby Current in
Non Power-down Mode
CKE ≥ VIH(min), tCK= ∞
Input signals are stable
50
tCK ≥ tCK(min)
CL=3 440 410 380 340 300 250
Operating Current
(Burst Mode)
1
tRAS ≥ tRAS(min), IOL = 0 mA
All Bank Active
CL=2
-
-
-
-
250 200
Operating Current
IDD5
IDD6
tRRC ≥ tRRC(min) All banks active
CKE ≤ 0.2V
250 240 220 200 190 180
2
mA
mA
2
3
Self Refresh Current
Notice :
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3. GLT5640L32-5/5.5/6/7/8/10
G-Link Technology Corp.
Dec 2003 Rev.0.3
7
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
AC CHARACTERISTICS - I (AC Operating Conditions Unless Otherwise Noted)
-5
-5.5
-6
-7
-8
-10
UNIT NOTE
PARAMETER
SYM.
Min Max Min Max Min Max Min Max Min Max Min Max
5.0
-
5.5
-
6.0
-
7.0
-
8.0
10.0
3.0
3.0
-
10.0
12.0
3.5
3.5
-
CAS Latency = 3
tCK
tCK
1000
1000
1000
1000
1000
1000
System Clock Cycle Time
-
CAS Latency = 2
2.0
2.0
-
-
2.5
2.5
-
-
2.5
2.5
-
-
3.0
3.0
-
-
-
-
-
-
1
1
Clock High Pulse Width
Clock Pulse Width
tCHW
tCLW
tAC
-
-
-
-
4.5
5.0
5.5
5.5
6.0
8.0
-
8.0
8.0
-
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
2
-
-
-
-
-
-
-
-
-
-
tAC
ns
1.5
1.5
1.0
1.0
-
-
2.0
1.5
1.0
1.0
-
-
2.0
1.5
1.0
1.0
-
-
2.0
1.75
1.0
1.0
-
-
2.5
2.0
1.0
1.0
-
2.5
2.5
1.0
1.0
-
-
Data-out Hold Time
tOH
-
-
-
-
-
-
1, 3
1, 3
-
Input Signal Setup Time
Input Signal Hold Time
tIS
-
-
-
-
-
-
-
-
-
-
tIH
-
-
CLK to Data Output in Low Z-Time
tOLZ
tOHZ
tOHZ
4.5
-
5.0
-
5.5
-
5.5
-
6.0
6.0
6.0
8.0
CAS Latency = 3
CAS Latency = 2
CLK to Data Output in High
Z-Time
-
-
-
-
-
-
-
Notice :
1. Assume tR/tF (input rise and fall time) is 1ns. If tR & tF is longer than 1ns, transient time compensation should be considered.
2. If clock rising time is longer than 1ns, (tR/2-0.5) ns should be added to the parameter.
3. Setup and hold time for Data-Input, Address, CKE and Command pin
G-Link Technology Corp.
Dec 2003 Rev.0.3
8
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
AC CHARACTERISTICS - II (AC Operating Conditions Unless Otherwise Noted)
-5
-5.5
-6
-7
-8
-10
UNIT NOTE
PARAMETER
SYM.
Min Max Min Max Min Max Min Max Min Max Min Max
55
55
15
55
55
60
60
18
70
70
20
70
70
20
70
70
20
Operation
tRC
tRRC
tRCD
tRAS
tRP
-
-
-
-
-
-
-
-
-
-
-
-
RAS Cycle Time
Auto Refresh
16.5
RAS to CAS Delay
ns
1
40 100K 38.5 100K 42 100K 49 100K 48 100K 50 100K
RAS Active Time
15
10
1
1
4
2
0
2
3
-
-
-
16.5
11
1
-
-
18
12
1
1
4
2
0
2
3
-
-
-
20
14
1
1
4
2
0
2
3
-
-
-
20
16
1
-
-
20
20
1
-
-
RAS Precharge Time
RAS to RAS Bank Active Delay
CAS to CAS Delay
tRRD
tCCD
tDPL
tDAL
tDQZ
tDQM
tMRD
tPROZ
tPROZ
tPDE
tSRE
tREF
-
-
-
-
-
-
-
1
-
-
-
1
-
1
-
Data-in to Precharge Command
Data-in to Active Command
DQM to Data-out Hi-Z
DQM to Data-in Mask
MRS to New Command
-
4
-
-
-
4
-
4
-
-
-
2
-
-
-
2
-
2
-
-
0
-
-
-
0
-
0
-
CLK
-
2
-
-
-
2
-
2
-
-
3
-
-
-
3
-
3
-
CAS Latency = 3
CAS Latency = 2
2
Precharge to Data-out Hi-Z
-
-
-
-
-
2
-
2
-
1
1
-
-
1
-
1
1
-
-
1
1
-
-
1
-
1
-
-
3
-
Power Down Exit Time
Self Refresh Exit Time
Refresh Time
-
1
-
-
-
1
-
1
-
64
-
64
64
64
-
64
-
64
ms
Notice :
1. The minimum number of clock cycle is determined by dividing the minimum time required with clock cycle time and them
rounding off to the next higher integer.
2. In case of row precharge interrupt, auto precharge and read burst stop.
3. A new command can be given tRC after self refresh exit.
G-Link Technology Corp.
Dec 2003 Rev.0.3
9
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
DEVICE OPERATING OPTION TABLE
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
GLT5640L32-5
200MHz
(5.0ns)
(5.5ns)
(6.0ns)
3 CLKs
3 CLKs
3 CLKs
3CLKs
3CLKs
3CLKs
8CLKs
7CLKs
7CLKs
11CLKs
10CLKs
10CLKs
3CLKs
3CLKs
3CLKs
4.5 ns
5.0 ns
5.5 ns
1.5 ns
2.0 ns
2.0 ns
183MHz
166MHz
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
GLT5640L32-5.5
183MHz
166MHz
143MHz
(5.5ns)
(6.0ns)
(7.0ns)
3 CLKs
3 CLKs
3 CLKs
3CLKs
3CLKs
3CLKs
7CLKs
7CLKs
7CLKs
10CLKs
10CLKs
10CLKs
3CLKs
3CLKs
3CLKs
5.0 ns
5.5 ns
5.5 ns
2.0 ns
2.0 ns
2.0 ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
GLT5640L32-6
166MHz
(6.0ns)
(7.0ns)
(8.0ns)
3 CLKs
3 CLKs
3 CLKs
3CLKs
3CLKs
3CLKs
7CLKs
7CLKs
6CLKs
10CLKs
10CLKs
9 CLKs
3CLKs
3CLKs
3CLKs
5.5 ns
5.5 ns
6.0 ns
2.0 ns
2.0 ns
2.5 ns
143MHz
125MHz
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
GLT5640L32-7
143MHz
(7.0ns)
(8.0ns)
(10.0ns)
3 CLKs
3 CLKs
2 CLKs
3CLKs
3CLKs
2CLKs
7CLKs
6CLKs
5CLKs
10CLKs
9CLKs
7CLKs
3CLKs
3CLKs
2CLKs
5.5 ns
6.0 ns
6.0 ns
2.0 ns
2.5 ns
2.5 ns
125MHz
100MHz
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
GLT5640L32-8
125MHz
(8.0ns)
3 CLKs
2 CLKs
2 CLKs
3CLKs
2CLKs
2CLKs
6CLKs
5CLKs
4CLKs
9CLKs
7CLKs
6CLKs
3CLKs
2CLKs
2CLKs
6.0 ns
6.0 ns
6.0 ns
2.5 ns
2.5 ns
2.5 ns
100MHz
83MHz
(10.0ns)
(12.0ns)
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
GLT5640L32-10
100MHz
83MHz
66MHz
(10.0ns)
(12.0ns)
(15.0ns)
3 CLKs
2 CLKs
2 CLKs
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6.0 ns
6.0 ns
6.0 ns
2.5 ns
2.5 ns
2.5 ns
G-Link Technology Corp.
Dec 2003 Rev.0.3
10
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
COMMAND TRUTH TABLE
A10/AP
COMMAND
CKEn-1 CKEn CS RAS CAS WE DQM ADDR
BA NOTE
Read With Autoprecharge
No Operation
H
H
H
H
X
X
X
X
L
L
L
L
L
X
H
L
L
X
H
H
L
X
H
H
X
X
X
X
OP Code
X
-
-
Bank Active
Read
RA
L
V
V
-
-
L
L
H
H
L
L
H
H
CA
CA
X
Read With Autoprecharge
Write
Write With Autoprecharge
Precharge All Banks
Precharge Selected Bank
Burst Stop
H
L
H
H
L
H
H
X
X
X
V
-
-
X
V
X
X
L
L
L
H
H
L
L
H
H
H
H
H
X
L
L
X
H
X
H
X
H
X
V
X
V
X
X
X
X
X
-
-
-
DQM
Auto Refresh
Entry
H
L
L
L
H
L
H
L
H
L
L
L
H
H
X
H
X
H
X
H
X
V
1
Self Refresh
X
H
X
H
X
H
X
V
X
X
X
Exit
L
H
L
H
L
X
X
X
1
-
Exit
Precharge
Power Down
Exit
H
-
Entry
H
L
H
L
L
X
X
-
-
Clock Suspend
Exit
H
X
Notice :
1. Exiting Self Refresh occurs by asynchronously bring CKE from low to high.
2. X = Don’t Care, H = Logic High, L = Logic Low, BA = Bank Address, RA = Row Address, CA = Column Address,
OP Cpde = Operand Code, NOP = No Operation.
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CMOS Synchronous DRAM
FUNCTIONAL DIAGRAM
CLK
CKE
CLOCK
GENERATOR
BANK D
BANK C
ADDRESS
BANK B
ROW
BANK A
ADDRESS
BUFFER &
REFRESH
COUNTER
MODE
REGISTER
SENSE AMPLIFIER
COLUMN DECODER
CS
RAS
CAS
WE
&
LATCH CIRCUIT
COLUMN
ADDRESS
BUFFER &
BURST
COUNTER
DATA CONTROL CIRCUIT
DQM
LATCH CIRCUIT
INPUT & OUTPUT
BUFFER
DQ
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SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
MRS
MODE
REGISTER
SET
CBR
REF
IDLE
REFRESH
POWER
DOWN
CKE ↓
CKE
ACTIVE
POWER
DOWN
ROW
ACTIVE
READ
WRITE
CKE ↓
CKE ↓
READ
WRITE
READ
WRITE
READ
SUSPEND
SUSPEND
WRITE
CKE
CKE
CKE ↓
CKE ↓
WRITE A
WRITE A
SUSPEND
READ A
READ A
SUSPEND
CKE
CKE
PRECHARGE
POWER
ON
PRE-
CHARGE
Automatic Sequence
Manual Input
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FUNCTIONAL DESCRIPTION
In general, this 64Mb SDRAM (512K x 32 x 4 banks) is a quad-bank DRAM that operates at 3.3V and in-cludes a synchronous interface (all
signals are regis-tered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 256
columns by 32-bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and con-tinue for a programmed number of
locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0
and BA1 select the bank, A0-A10 select the row). The address bits (A0-A7) registered coincident with the READ or WRITE command are used
to select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization,
register defi-nition, command descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in
undefined operation. Once power is applied to VDD and VDDQ (simulta-neously) and the clock is stable (stable clock is defined as a signal
cycling within timing constraints specified for the clock pin), the SDRAM requires a 100ms delay prior to issuing any command other than a
COM-MAND INHIBIT or a NOP. Starting at some point during this 100ms period and continuing at least through the end of this period,
COMMAND INHIBIT or NOP com-mands should be applied.
Once the 100ms delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE
command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready
for Mode Register pro-gramming. Because the Mode Register will power up in an unknown state, it should be loaded prior to applying any
operational command.
Register Definition
MODE REGISTER
The Mode Register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a
burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 1. The Mode Register is programmed via the LOAD
MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power.
Mode Register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or inter-leaved), M4-M6 specify the CAS latency,
M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 is reserved for future use.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent
operation. Violating either of these requirements will result in unspecified operation.
Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length
determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8
locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-
page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE
command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 when the burst length is set
to two; by A2-A7 when the burst length is set to four; and by A3-A7 when the burst length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached.
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CMOS Synchronous DRAM
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected
via bit M3. The ordering of accesses within a burst is deter-mined by the burst length, the burst type and the starting column address, as shown
in Table 1.
BA1
BA0
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Bus
10
9
8
7
6
5
4
3
2
1
0
Mode Register(Mx)
0
0
Reserved* WB
Op Mode
CAS Latency
BT
Burst Length
M8 M7 M6 - M0 Operating Mode
M3
0
Burst Type
Sequential
Interleave
Burst Length
M2 M1 M0
0
-
0
-
Defined Standard Operation
M3 = 0
1
M3 = 1
1
-
All Other States Reserved
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
2
M9
0
Burst Type
M6 M5 M4
CAS Latency
Reserved
1
4
4
Programmed Burst Length
Single Location Access
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
Figure 1.
Mode Register Definition
*Should Program M10 = 0,
to ensure compatibility with future device.
Order of Access Within a Burst
Table 1.
Burst Definition
Burst
Starting Column
Address
Length
Type = Sequential Type = Interleaved
A0
0
2
4
0>1
1>0
0>1
1>0
1
A1
0
A0
0
Notice :
0>1>2>3
1>2>3>0
2>3>0>1
3>0>1>2
0>1>2>3
1>0>3>2
2>3>0>1
3>2>1>0
0
1
1. For a burst length of two, A1-A7 select the block-of-two burst;
A0 selects the starting column within the block.
1
0
1
1
2. For a burst length of four, A2-A7 select the lock-of-four burst;
A0-A1 select the starting column within the block.
A2
0
A1 A0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0>1>2>3>4>5>6>7 0>1>2>3>4>5>6>7
1>2>3>4>5>6>7>0 1>0>3>2>5>4>7>6
2>3>4>5>6>7>0>1 2>3>0>1>6>7>4>5
3>4>5>6>7>0>1>2 3>2>1>0>7>6>5>4
4>5>6>7>0>1>2>3 4>5>6>7>0>1>2>3
5>6>7>0>1>2>3>4 5>4>7>6>1>0>3>2
6>7>0>1>2>3>4>5 6>7>4>5>2>3>0>1
7>0>1>2>3>4>5>6 7>6>5>4>3>2>1>0
0
3. For a burst length of four, A3-A7 select the lock-of-four burst;
A0-A2 select the starting column within the block.
0
8
0
4. For a full-page burst, the full row is selected and A0-A7 select
the starting column
1
1
1
5. Whenecer a boundart of the block is reached within a given
sequence above, the following access wraps within the block.
6. For a burst length of one, A0-A7 select the unique column to
be accessed, and Mode Register bit M3 is ignored.
1
Cn, Cn+1. Cn+2,
Not
Full page
(256)
N = A0 > A7
(Location 0>256)
Cn+3, Cn+4…
Supported
…Cn-1, Cn...
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CAS Latency
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data.
The atency can be set to one, two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be
available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant
access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access
times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the
data will be valid by T2, as shown in Figure 2. Table 2 below,
T0
T1
T2
T0
T1
T2
T3
CLK
CLK
COMMAND
READ
tLZ
NOP
tOH
Dout
COMMAND
READ
NOP
NOP
tOH
Dout
tLZ
DQ
DQ
tAC
tAC
CAS Latency=2
CAS Latency=1
T0
T1
T2
T3
T4
CLK
ALLOWABLE OPERATING
FREQUENCY (MHz)
SPEED
CAS
CAS
CAS
COMMAND
READ
NOP
NOP
NOP
tOH
Dout
LATENCY = 1
LATENCY = 2
LATENCY =3
tLZ
-6.0
-7.0
-8.0
60
100
166
143
125
DQ
50
40
100
100
tAC
CAS Latency=3
DON’T CARE
UNDEFINED
Figure 2.
CAS Latency
Table 2.
CAS Latency
indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future
use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be
used because unknown operation or incompatibility with future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length
applies to READ bursts, but write accesses are single-location (nonburst) accesses.
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COMMANDS
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is
enabled. The SDRAM is effectively deselected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted
commands from being registered during idle or wait states. Operations already in progress are not affected.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-A10. See Mode Register heading in the Register Definition sec-tion. The LOAD MODE REGISTER
command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t MRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0 and BA1 inputs
selects the bank, and the address provided on inputs A0-A10 selects the row. This row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on the BA0 and BA1 (B1) inputs selects the bank, and
the address provided on inputs A0-A7 selects the starting column location. The value on input A10 determines whether or not AUTO
PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the READ burst; if AUTO
PRECHARGE iis not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on
the DQM inputs two clocks earlier. If a given DQMx signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the
DQMx signal was registered LOW, the corresponding DQs will provide valid data. DQM0 corresponds to DQ0-DQ7, DQM1 corresponds to DQ8-
DQ15, DQM2 corresponds to DQ16-DQ23 and DQM3 corresponds to DQ24-DQ31.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value on the BA0 and BA1 inputs selects the bank, and the
address provided on inputs A0-A7 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE
is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is
not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the
DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to
memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that
byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available
for a subsequent row access a specified time ( tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks
are to be precharged, and in the case where only one bank is to be precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1
are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank.
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AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same individual-bank PRECHARGE function described above, without requiring an
explicit command. This is accomplished by using A10 to enable AUTO PRECHARGE in conjunction with a specific READ or WRITE command.
A PRECHARGE of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ
or WRITE burst, except in the full-page burst mode, where AUTO PRECHARGE does not apply. AUTO PRECHARGE is nonpersistent in that it
is either enabled or disabled for each individual READ or WRITE com-mand.
AUTO PRECHARGE ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another
command to the same bank until the precharge time ( tRP) is completed. This is determined as if an explicit PRECHARGE command was
issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE
command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM and is analagous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional
DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required.
The addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command.
The 64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms ( tREF), regardless of width option. Providing a distributed AUTO
REFRESH command every 15.625µs will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO
REFRESH commands can be issued in a burst at the minimum cycle rate ( tRC), once every 64ms.
SELF REFRESH
The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self
refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command
except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care” with the
exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The
SDRAM must remain in self refresh mode for a minimum period equal to t RAS and may remain in self refresh mode for an indefinite period
beyond that.
The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling
within timing con-straints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands
issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal refresh in progress.
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Operation
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is
accomplished via the ACTIVE command, which selects both the bank and the row to be activated. See Figure 4.
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification.
tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the
ACTIVE command on which a READ or WRITE command can be issued. For example, at RCD specification of 20ns with a 125 MHz clock (8ns
period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 3, which covers any case where 2 < t RCD (MIN)/tCK
3. (The same
procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive
ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total
row-access over-head. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
T0
T1
T2
T3
CLK
tCK
tCK
tCK
READ or
WRITE
COMMAND
NOP
NOP
ACTIVE
tRCD(MIN)*
tRCD(MIN) +0.5 tCK
* tRCD(MIN) = 20ns, tCK = 8ns
tRCD(MIN) x tCK
DON’T CARE
where x = number of clocks to be true.
Figure 3.
Example : Meeting tRCD(MIN) When 2 < tRCD(MIN)/tCK 3
CLK
CKE
CS#
HIGH
RAS#
CAS#
WE#
ROW
ADDRESS
A0 - A10
BANK
ADDRESS
BA0, BA1
Figure 4.
Activating a Specific Row in a
Specific Bank
DON’T CARE
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READ Operation
READ bursts are initiated with a READ command, as shown in Figure 5. The starting column and bank addresses are pro-vided with the READ
command, and AUTOPRECHARGE is either enabled or disabled for that burst access. If AUTO PRECHARGE is enabled, the row being
accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, AUTO PRECHARGE
is disabled.
During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ
command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 6 shows general timing for each possible
CAS latency setting.
T0
T1
T2
CLK
CLK
CKE
CS#
HIGH
COMMAND
READ
tLZ
NOP
tOH
Dout
DQ
tAC
CAS Latency=1
RAS#
T0
T1
T2
T3
CLK
CAS#
WE#
COMMAND
READ
NOP
tLZ
NOP
tOH
Dout
DQ
tAC
COLUMN
ADDRESS
CAS Latency=2
A0 - A7
T0
T1
T2
T3
T4
CLK
A8, A9
A10
COMMAND
READ
NOP
NOP
tLZ
NOP
tOH
Dout
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
DQ
tAC
BANK
ADDRESS
CAS Latency=3
BA0, 1
DON’T CARE
UNDEFINED
DON’T CARE
Figure 6.
Figure 5.
CAS Latency
READ Command
Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until
terminated. (At the end of the page, it will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately
followed by data from a READ command. In either case, a continu-ous flow of data can be maintained. The first data element from the new burst
follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ
command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus
one.
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CMOS Synchronous DRAM
This is shown in Figure 7 for CAS latencies of one, two and three; data element n + 3 is either the last of a burst of four or the last desired of a
longer burst. This 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture.
T0
T1
T2
T3
T4
T5
CLK
COMMAND
NOP
NOP
READ
NOP
READ
NOP
X = 0 cycles
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
Dout,
n
Dout,
n+1
Dout,
n+2
Dout,
n+3
Dout,
b
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
NOP
NOP
READ
NOP
READ
NOP
NOP
X = 1 cycles
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
Dout,
n
Dout,
n+1
Dout,
n+2
Dout,
n+3
Dout,
b
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
NOP
NOP
READ
NOP
READ
NOP
NOP
NOP
X = 2 cycles
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
Dout,
n
Dout,
n+1
Dout,
n+2
Dout,
n+3
Dout,
b
CAS Latency = 3
Notice : Each READ command may be to either bank. DQM is LOW
DON’T CARE
Figure 7.
Consecutive READ Bursts
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A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be
performed to the same bank, as shown in Figure 8, or each subsequent READ may be performed to a different bank.
T0
T1
T2
T3
T4
CLK
COMMAND
READ
READ
READ
READ
NOP
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
ADDRESS
DQ
Dout
n
Dout
a
Dout
x
Dout
m
CAS Latency = 1
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
READ
READ
READ
NOP
NOP
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
ADDRESS
DQ
Dout
n
Dout
a
Dout
Dout
x
m
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
NOP
NOP
NOP
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
ADDRESS
DQ
Dout
n
Dout
Dout
Dout
a
x
m
CAS Latency = 3
Notice : Each READ command may be to either bank. DQM is LOW
DON’T CARE
Figure 8.
Random READ Access
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CMOS Synchronous DRAM
Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be
immediately followed by data from a WRITE command (subject to bus turn-around limitations). The WRITE burst may be initiated on the clock
edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given
system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at
least a single-cycle delay should occur between the last read data and the WRITE command.
The DQM input is used to avoid I/O contention, as shown in Figures 9 and 10. The DQM signal must be asserted (HIGH) at least two clocks
prior to the WRITE command (DQM latency is two clocks for output buff-ers) to suppress data-out from the READ. Once the WRITE command
is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal; provided the DQM was active on the clock
just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM
was low during T4 in Figure 10, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.
The DQM signal must be deasserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data
is not masked. Figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and
Figure 10 shows the case where the additional NOP is needed.
T0
T1
T2
T3
T4
T0
T1
T2
T3
T4
T5
CLK
CLK
DQM
DQM
COMMAND
ADDRESS
COMMAND
ADDRESS
NOP
NOP
NOP
NOP
NOP
READ
NOP
WRITE
READ
NOP
WRITE
BANK,
COL n
BANK,
COL b
BANK,
COL n
BANK,
COL b
tCK
tHZ
tHZ
Dout n
DQ
Din b
DQ
Dout n
Din b
tDS
tDS
DON’T CARE
Notice :
Notice :
A CAS latency of three is used for illustration. The READ command
may be to any bank,and the WRITE command may be to any bank.
If a burst of one is used, then DQM is not required.
A CAS latency of three is used for illustration. The READ command may be to any bank,
and the WRITE command may be to any bank.
Figure 9.
Figure 10.
READ to WRITE
READ to WRITE With Extra Clock Cycle
G-Link Technology Corp.
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ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that AUTO
PRECHARGE was not acti-vated), and a full-page burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE
command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency
minus one. This is shown in Figure 11 for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of
a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that
part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the optimum time (as described above) provides the same
T0
T1
T2
T3
T4
T5
T6
T7
CLK
tRP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 0 cycles
BANK a,
COL n
BANK
(a or all)
BANK a,
ROW
ADDRESS
DQ
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
T7
CLK
tRP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 1 cycle
BANK a,
COL n
BANK
(a or all)
BANK a,
ROW
ADDRESS
DQ
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
tRP
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 2 cycle
BANK a,
COL n
BANK
(a or all)
BANK a,
ROW
ADDRESS
DQ
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
CAS Latency = 3
Notice : DQM is LOW
DON’T CARE
Figure 11.
READ to PRECHARGE
G-Link Technology Corp.
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ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
operation that would result from the same fixed-length burst with AUTO PRECHARGE. The disadvantage of the PRECHARGE command is that
it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE
command is that it can be used to truncate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a
BURST TERMINATE command, provided that AUTO PRECHARGE was not activated. The BURST TERMINATE command should be issued x
cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure
12 for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst.
T0
T1
T2
T3
T4
T5
T6
CLK
BURST
TERMINATE
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
X = 0 cycles
BANK,
COL n
ADDRESS
DQ
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
CAS Latency = 1
T0
T1
T2
T3
T4
T5
T6
CLK
BURST
TERMINATE
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
X = 1 cycle
BANK,
COL n
ADDRESS
DQ
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
BURST
TERMINATE
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
NOP
X = 2 cycle
BANK a,
COL n
ADDRESS
DQ
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
CAS Latency = 3
Notice : DQM is LOW
DON’T CARE
Figure 12.
Terminating a READ Burst
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GLT5640L32
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CMOS Synchronous DRAM
WRITE Operation
WRITE bursts are initiated with a WRITE command, as shown in Figure 13. The starting column and bank addresses are provided with the
WRITE command, and AUTO PRECHARGE is either enabled or disabled for that access. If AUTO PRECHARGE is enabled, the row being
accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, AUTO
PRECHARGE is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command.
Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no
other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 14). A full-page burst
will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.)
Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be
immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous
T0
T1
T2
T3
CLK
CLK
CKE
HIGH
COMMAND
WRITE
NOP
NOP
NOP
CS#
RAS#
CAS#
WE#
BANK,
COL n
ADDRESS
DQ
Din
n
Din
n+1
Notice : Burst length = 2. DQM is LOW
Figure 14.
WRITE Burst
COLUMN
ADDRESS
A0 - A7
A8, A9
A10
T0
T1
T2
CLK
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
COMMAND
WRITE
NOP
WRITE
BANK
ADDRESS
BA0, 1
BANK,
COL n
BANK,
COL b
ADDRESS
DQ
Figure 13.
WRITE Command
Din
n
Din
n+1
Din
b
Notice : DQM is LOW. Each WRITE command may be to
any bank
DON’T CARE
Figure 15.
WRITE to WRITE
WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 15.
Data n + 1 is either the last of a burst of two or the last desired of a longer burst. This 64Mb SDRAM uses a pipelined architecture and therefore
does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous
WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 16, or each
subsequent WRITE may be performed to a different bank.
G-Link Technology Corp.
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GLT5640L32
G-LINK
CMOS Synchronous DRAM
Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately
followed by a READ command. Once the READ command is regis-tered, the data inputs will be ignored, and WRITEs will not be executed. An
example is shown in Figure 17. Data n + 1 is either the last of a burst of two or the last desired of a longer burst.
Data for a fixed-length WRITE burst may be fol-lowed by, or truncated with, a PRECHARGE command to the same bank (provided that AUTO
PRECHARGE was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued t WR after the clock edge at which the last desired input data element is registered. The “two-clock”
write-back requires at least one clock plus time, regardless of frequency,
T0
T1
T2
T3
T4
T5
T6
T0
T1
T2
T3
CLK
CLK
tWR = 1 CLK (tCK = tWR)
DQM
COMMAND
WRITE
WRITE
WRITE
WRITE
tRP
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
PRECHARGE
WRITE
NOP
NOP
NOP
ACTIVE
NOP
COMMAND
ADDRESS
DQ
BANK a,
COL n
BANK
(a or all)
BANK a,
ROW
ADDRESS
Din
n
Din
a
Din
x
Din
m
tWR
Din
n
Din
n+1
DQ
Notice : Each WRITE command may be to any bank. DQM is LOW.
tWR = 2 CLK (when tWR > tCK)
DQM
Figure 16.
Random WRITE Cycle
T0
T1
T2
T3
T4
T5
tRP
CLK
PRECHARGE
WRITE
NOP
NOP
NOP
NOP
ACTIVE
COMMAND
ADDRESS
BANK a,
COL n
BANK
(a or all)
BANK a,
ROW
WRITE
NOP
READ
NOP
NOP
NOP
COMMAND
tWR
BANK,
COL b
BANK,
COL n
Din
n
Din
n+1
ADDRESS
DQ
DQ
Notice : DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
Din
n+1
Dout
b+1
Din
n
Dout
b
DON’T CARE
Notice : The WRITE command may be to any bank, and the READ command may
be to any bank. DQM is LOW. CAS latency = 2 for illustration.
Figure 17.
Figure 18.
WRITE to READ
WRITE to PRECHARGE
in auto precharge mode. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior
to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 18. Data n + 1 is either the last of a burst of
two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued
until tRP is met. The precharge will actually begin coincident with the clock-edge (T2 in Figure 18) on a “one-clock” tWR and sometime between
the first and second clock on a “two-clock” tWR (between T2 and T3 in Figure 18.) In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the
same fixed-length burst with AUTO PRECHARGE. The disadvantage of the PRECHARGE command is that it requires that the command and
address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used
to truncate fixed-length or full-page bursts.
G-Link Technology Corp.
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GLT5640L32
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CMOS Synchronous DRAM
Fixed-length or full-page WRITE bursts can be trun-cated with the BURST TERMINATE command. When truncating a WRITE burst, the input
data applied coin-cident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time)
will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 19, where data n is the last
desired data element of a longer burst.
T0
T1
T2
CLK
CKE
CLK
HIGH
NEXT
COMMAND
BURST
TERMINATE
COMMAND
WRITE
CS#
RAS#
CAS#
WE#
BANK,
COL n
ADDRESS
DQ
(ADDRESS)
(DATA)
Din
n
Notice : DQM is LOW.
DON’T CARE
Figure 19.
Terminating a WRITE Burst
A0 - A9
A10
All Banks
CLK
CLE
Bank Selected
≥ tCKS
tCKS
BANK
ADDRESS
BA0, 1
COMMAND
NOP
NOP
ACTIVE
tRCD
Figure 20.
All banks idle
PRECHARGE Command
Input buffers gated off
tRAS
tRC
Enter power-down mode.
Exit power-down mode.
DON’T CARE
Figure 21.
Power-Down
PRECHARGE
The PRECHARGE command (Figure 20) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will
be available for a subsequent row access some specified time ( tRP) after the PRECHARGE command is issued. Input A10 determines whether
one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0 and BA1 select the bank. When all
banks are to be precharged, inputs BA0 and BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must
be activated prior to any READ or WRITE commands being issued to that bank.
POWER-DOWN
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress (see Figure
21). If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row
active in either bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding
CKE, for maximum power savings while in standby. The device may not remain in the power-down state longer than the refresh period (64ms)
since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting tCKS).
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CMOS Synchronous DRAM
CLOCK SUSPEND
The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend
mode, the internal clock is deactivated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is sus-pended. Any
command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the
DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See examples in Figures
22 and 23.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the
subsequent positive clock edge.
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming the write burst mode bit (M9) in the Mode Register to a logic 1. In this mode, all
WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands
access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0).
T0
T1
T2
T3
T4
T5
T6
T0
T1
T2
T3
T4
T5
CLK
CKE
CLK
CKE
INTERNAL
CLOCK
INTERNAL
CLOCK
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
WRITE
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COL n
BANK,
COL n
Dout
n+1
Dout
n+2
Dout
n+2
Dout
Din
n+1
Din
n+2
Din
n
n
Notice : For this example, CAS latency = 2, burst length = 4 or greater, and DQM is LOW.
Notice : For this example, burst length = 4 greater, and DQM is LOW.
DON’T CARE
Figure 22.
Figure 23.
Clock Suspend During WRITE Burst
Clock Suspend During READ Burst
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GLT5640L32
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CMOS Synchronous DRAM
CONCURRENT AUTO PRECHARGE
An access command to (READ or WRITE) another bank while an access command with AUTOPRECHARGE enabled is executing is not
allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. SDRAMs support CONCURRENT AUTO
PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below.
READ with AUTO PRECHARGE
1. Interrupted by a READ (with or without AUTO PRECHARGE): A READ to bank m will interrupt a READ on bank n, CAS latency later. The
PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24).
2. Interrupted by a WRITE (with or without AUTO PRECHARGE): A WRITE to bank m will interrupt a READ on bank n when registered. DQM
should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the
WRITE to bank m is registered (Figure 25).
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
Idle
COMMAND
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
tRP - BANK n
BANK n
Internal
States
tRP-BANK m
BANK m
ADDRESS
DQ
Page Active
READ with Burst of 4
Precharge
BANK n,
COL a
BANK m,
COL d
Dout
a
Dout
a + 1
Dout
d
Dout
d + 1
CAS latency=3 (BANK n)
Notice : DQM is LOW.
CAS latency=3 (BANK m)
Figure 24.
READ With Auto Precharge Interrrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page
Active
BANK n
READ with Burst of 4
Interrupt Burst, Precharge
tRP - BANK n
Idle
Internal
States
tWR-BANK m
Write-Back
BANK m
Page Active
READ with Burst of 4
BANK n,
COL a
BANK m,
COL d
ADDRESS
1
DQM
Dout
a
Din
d
Din
d+1
Din
d+2
Din
d+3
DQ
CAS latency=3 (BANK n)
DON’T CARE
Notice : DQM is HIGH at T2 to prevent Dout-a+1 from contending with Din-d at T4.
Figure 25.
READ With Auto Precharge Interrrupted by a WRITE
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GLT5640L32
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CMOS Synchronous DRAM
WRITE with AUTO PRECHARGE
3. Interrupted by a READ (with or without AUTO PRECHARGE): A READ to bank m will interrupt a WRITE on bank n when registered, with the
data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank
m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 26).
4. Interrupted by a WRITE (with or without AUTO PRECHARGE): A WRITE to bank m will interrupt a WRITE on bank n when registered. The
PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data
WRITE to bank n will be data registered one clock prior to a WRITE to bank m (Figure 27).
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE-AP
BANK n
READ-AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Interrupt Burst, Write-Back
Precharge
BANK n
Page Active
WRITE with Burst of 4
Internal
States
tRP-BANK n
tWR-BANK n
tRP-BANK m
BANK m
Page Active
READ with Burst of 4
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
Din
a
Din
a+1
Dout
d
Dout
d+1
CAS latency=3 (BANK m)
Notice : DQM is LOW.
Figure 26.
WRITE With Auto Precharge Interrrupted by a WRITE
T0
T1
T2
T3
T4
T5
T7
T6
CLK
WRITE-AP
BANK n
WRITE-AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Interrupt Burst, Write-Back
tWR-BANK n
BANK n
Page Active
WRITE with Burst of 4
Precharge
Internal
States
tRP-BANK n
tWR-BANK m
BANK m
Page Active
WRITE with Burst of 4
Write-Back
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
Din
a
Din
a+1
Din
a+2
Din
d
Din
Din
Din
d+1
d+2
d+3
Notice : DQM is LOW.
DON’T CARE
Figure 27.
WRITE With Auto Precharge Interrrupted by a READ
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GLT5640L32
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CMOS Synchronous DRAM
TIMING WAVEFORMS
INITIALIZE AND LOAD MODE REGISTER
Notice :
1
The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.
2 Outputs are guaranteed High-Z after command is issued.
T0
T1
T n+1
tCHW
T o+1
T p+1
T p+2
T p+3
tCK
tCLW
CLK
CKE
tCKS tCKH
tIS
tIH
tIS
tIH
tIS
tIH
AUTO
REFRESH
AUTO
REFRESH
LOAD MODE
REFRESH
COMMAND
DQM 0-3
NOP
PRECHARGE
NOP NOP
NOP NOP
NOP
ACTIVE
tIS
tIS
tIH
A0 - A9
A10
CODE
tIH
ROW
ROW
ALL BANKS
CODE
SINGLE BANK
BA0
ALL BANKS
BANK
High-Z
DQ
T = 100us
(MIN)
tRP
tRC
tRC
tMRD
Power-up :
VDD and
CLK stable
Precharge
all banks
Program Mode Register 1, 2
AUTO REFRESH
AUTO REFRESH
DON’T CARE
UNDEFINED
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GLT5640L32
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CMOS Synchronous DRAM
1
POWER-DOWN MODE
Notice :
1
Violating refresh requirements during power-down may result in a loss of data.
T0
T1
T 2
T n+1
T n+2
tCK
tCLW
CLK
CKE
tCHW
tIS
tIS
tIH
tIS
tIH
COMMAND
DQM 0-3
NOP
NOP
ACTIVE
NOP
PRECHARGE
A0 - A9
A10
ROW
ROW
ALL BANKS
SINGLE BANK
tIS
tIH
BA0
DQ
BANK(S)
BANK
High-Z
Two clock cycles
Input buffers gated off while in
Power-down mode
All banks idle
Precharge all
active banks
All banks idle, enter
power-down mode
Exit power-down mode
DON’T CARE
UNDEFINED
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GLT5640L32
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CMOS Synchronous DRAM
1
CLOCK SUSPEND MODE
Notice :
1
For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is disabled.
A8 and A9 = “ Don’t’ Care.”
2
T0
T1
T 2
T3
T4
T 5
T 6
T7
T 8
T 9
tCK
tCLW
CLK
CKE
tCHW
tIH
tCLW
tIS
tIS
tIS
tIH
tIH
COMMAND
DQM 0-3
READ
NOP
NOP
NOP
WRITE
COLUMN e2
BANK
NOP
NOP
NOP
tIS
tIH
tIS
tIH
COLUMN m2
A0 - A9
A10
tIS
tIS
tIH
tIH
BA0
BANK
tAC
tAC
tIH
tIS
tOH
tOHZ
DQ
Dout m
Dout m+1
Dout e
Dout e+1
tOLZ
DON’T CARE
UNDEFINED
G-Link Technology Corp.
Dec 2003 Rev.0.3
34
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
AUTO REFERSH MODE
T0
T1
T n+1
tCHW
T n+1
T o+1
tCLW
CLK
tCK
CKE
tIS
tIS
tIH
tIH
AUTO
REFRESH
AUTO
REFRESH
COMMAND
DQM 0-3
NOP
PRECHARGE
NOP NOP
NOP NOP
ACTIVE
A0 - A9
A10
ROW
ROW
ALL BANKS
SINGLE BANK
tIS
tIH
BA0, BA1
DQ
BANK(S)
BANK
High-Z
tRP
tRC
tRC
Precharge all
active banks
DON’T CARE
SELF REFERSH MODE
T0
T1
T2
T n+1
T o+1
T o+2
tCLW
CLK
tCK
tCHW
tIS
tIH
CKE
tIS
tIS
tIH
tIS
tIH
AUTO
REFRESH
AUTO
REFRESH
NOP
PRECHARGE
NOP
COMMAND
DQM 0-3
A0 - A9
A10
ALL BANKS
SINGLE BANK
tIS
tIH
BANK(S)
BA0, BA1
DQ
High-Z
tRP
tSRE
Precharge all
active banks
Exit self refresh mode
(Restart refresh time base)
Enter self refresh mode
CLK stable prior to exiting
self refresh mode
DON’T CARE
G-Link Technology Corp.
Dec 2003 Rev.0.3
35
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
READ OPERATIONS
1
SIGNAL READ, WITHOUT AUTO PRECHARGE
Notice :
1
For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by “manual” PRECHARGE.
A8 and A9 = “ Don’t’ Care.”
2
T0
T1
T 2
T 3
T 4
T 5
tCK
tCLW
CLK
tCHW
tIS
tIH
tIH
CKE
tIS
COMMAND
ACTIVE
READ
PRECHARGE
NOP
ACTIVE
NOP
tIS
tIH
DQM /
DQML, DQMH
tIS
tIH
ROW
ROW
COLUMN m2
ROW
ROW
BANK
A0 - A9
tIS
tIH
ALL BANKS
A10
SINGLE BANK
DISABLE AUTO PRECHARGE
BANK
tIS
tIH
BA0,BA1
DQ
BANK
BANK
tAC
tOH
DOUTm
tRCD
CAS Latency
tOLZ
tRP
tOHZ
tRAS
tRC
DON’T CARE
UNDEFINED
G-Link Technology Corp.
Dec 2003 Rev.0.3
36
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
1
READ, WITHOUT AUTO PRECHARGE
Notice :
1
For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by “manual” PRECHARGE.
A8 and A9 = “ Don’t’ Care.”
2
T0
T1
T 2
T3
T4
T 5
T 6
T7
T 8
tCK
tCLW
CLK
CKE
tCHW
tIS
tIH
tIH
tIS
COMMAND
DQM 0-3
ACTIVE
READ
NOP
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
tIS
tIH
tIS
tIH
ROW
tIH
COLUMN m2
A0 - A9
A10
ROW
ROW
tIS
tIS
ALL BANKS
CODE
ROW
tIH
SINGLE BANK
DISABLE AUTO PRECHARGE
BANK
BA0,BA1
ROW
BANK
BANK
tAC
m
tAC
tOH
tAC
tOH
tAC
tOH
DOUT
DOUT m + 1
DOUT m + 2
DOUT m + 3
tOHZ
DQ
tLZ
tRP
tRCD
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
G-Link Technology Corp.
Dec 2003 Rev.0.3
37
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
1
READ, WITH AUTO PRECHARGE
Notice :
1
For this example, the burst length = 4, the CAS latency = 2.
A8 and A9 = “ Don’t’ Care.”
2
T0
T1
T 2
T 3
T 4
T 5
T 6
T 7
T 8
tCK
tCLW
tCLW
CLK
CKE
tCHW
tIH
tIS
tIS
tIH
COMMAND
DQM 0-3
ACTIVE
NOP
READ
tIH
NOP
NOP
NOP
NOP
NOP
ACTIVE
tIS
tIH
tIS
ROW
tIH
COLUMNm2
ROW
ROW
BANK
A0 - A9
A10
tIS
tIS
ENABLE AUTO PRECHARGE
ROW
tIH
BA0,BA1
BANK
BANK
tAC
tAC
tAC
tAC
tOH
tOH
tOH
tOH
DQ
DOUTm
DOUT m+1
DOUT m+2
DOUT m+3
tOLZ
tOHZ
tRCD
tRAS
tRC
CAS Latency
tRP
DON’T CARE
UNDEFINED
G-Link Technology Corp.
Dec 2003 Rev.0.3
38
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
1
ALTERNATING BANK READ ACCESS
Notice :
1
For this example, the burst length = 4, the CAS latency = 2.
A8 and A9 = “ Don’t’ Care.”
2
T0
T1
T 2
T 3
T 4
T 5
T 6
T 7
T 8
tCK
tCLW
CLK
CKE
tCHW
tIH
tIS
tIS
tIH
COMMAND
DQM 0-3
ACTIVE
NOP
READ
tIH
NOP
ACTIVE
NOP
READ
NOP
ACTIVE
tIS
tIH
tIS
ROW
tIH
COLUMNm2
ROW
ROW
COLUMNb2
ROW
ROW
A0 - A9
A10
tIS
tIS
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
tIH
BA0,BA1
BANK 0
BANK 0
BANK 4
BANK 4
BANK 0
tAC
tAC
tAC
tAC
tAC
tAC
tOH
tOH
tOH
tOH
tOH
DQ
DOUT
m
DOUTm+1
DOUTm+2
DOUTm+3
DOUTb
tOLZ
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRRD
CAS Latency - BANK 0
tRP - BANK 0
tRCD - BANK 0
tRCD - BANK 4
CAS Latency - BANK 4
DON’T CARE
UNDEFINED
G-Link Technology Corp.
Dec 2003 Rev.0.3
39
ADVANCED
GLT5640L32
CMOS Synchronous DRAM
G-LINK
READ, FULL-PAGE BURST
Notice :
1
1
For this example CAS latency = 2.
2
A8 and A9 = “ Don’t’ Care.”
3
Page left open ; no tRP.
T0
T1
T 2
T 3
T 4
T5
T6
T n+1
Tn+2
Tn+3
T n+4
tCK
tCLW
CLK
CKE
tCH
W
tIH
tIS
tIH
tIS
BURST
TERM
COMMAND
DQM 0-3
ACTIVE
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
tIS
tIH
tIS
tIH
ROW
ROW
ROW
COLUMNm2
A0 - A9
A10
tIS
tIS
tIH
BA0,BA1
BANK
tAC
tAC
tAC
tAC
tAC
tOH
tAC
tOH
tOH
tOH
tOH
tOH
DQ
DOUT
m
DOUT m+1
DOUT m+2
DOUT m-1
DOUT
m
DOUT m+1
tOLZ
tOHZ
tRCD
CAS Latency
256 LOCATIONS WITHIN SAME ROW
Full-page completed
DON’T CARE
UNDEFINED
Full-page burst does not self-terminate
Can use BURST TERMINATE command.3
G-Link Technology Corp.
Dec 2003 Rev.0.3
40
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
1
READ, DQM OPERATION
Notice :
1
For this example CAS latency = 2.
2
A8 and A9 = “ Don’t’ Care.”
T0
T1
T 2
T 3
T 4
T 5
T 6
T 7
T 8
tCK
tCLW
CLK
CKE
tCHW
tIH
tIS
tIS
tIH
COMMAND
DQM 0-3
ACTIVE
NOP
READ
tIH
NOP
NOP
NOP
NOP
NOP
NOP
tIS
tIS
tIH
ROW
tIH
COLUMNm2
A0 - A9
A10
tIS
tIS
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ROW
tIH
BA0,BA1
BANK
tAC
tAC
tOH
tAC
tOH
tOH
DQ
Dout m
Dout m+2
Dout m+3
tOLZ
tRCD
CAS Latency
tOHZ
tOLZ
tOHZ
DON’T CARE
UNDEFINED
G-Link Technology Corp.
Dec 2003 Rev.0.3
41
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
WRITE OPERATIONS
1
SINGLE WRITE, WITHOUT AUTO PRECHARGE
Notice :
1
For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2
3
10ns is required between <DIN m> and the PRECHARGE command, regardless of frequenct, to meet tWR.
A8 and A9 = “Don’t Care.”
T0
T1
T 2
T 3
T4
T5
T 6
tCK
CLK
CKE
tCHW
tCLW
tIS
tIS
tIH
tIH
COMMAND
ACTIVE
NOP
WRITE
tIS
NOP
PRECHARGE
NOP
ACTIVE
tIH
DQM /
DQML, DQMH
tIS
tIH
ROW
COLUMN m3
ROW
ROW
A0 - A9
tIS
tIH
ALL BANKS
A10
ROW
DISABLE AUTO PRECHARGE
BANK
SINGLE BANK
tIS
tIH
BA0,BA1
BANK(S)
BANK
BANK
tIS
tIH
DQ
Din m
tRCD
tWR2
tRP
tRAS
tRC
DON’T CARE
G-Link Technology Corp.
Dec 2003 Rev.0.3
42
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
1
WRITE, WITHOUT AUTO PRECHARGE
Notice :
1
For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
Faster frequencies require two clocks (when tWR > tCK).
A8 and A9 = “Don’t Care.”
2
3
T0
T1
T 2
T 3
T 4
T5
T6
T7
T8
tCK
tCLW
CLK
CKE
tCHW
tIH
tIS
tIH
tIS
COMMAND
DQM 0-3
PRECHARGE
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
ACTIVE
tIS
tIH
tIS
tIH
ROW
tIH
COLUMNm3
ROW
ROW
BANK
A0 - A9
A10
tIS
tIS
ALL BANKs
ROW
tIH
SINGLE BANK
ENABLE AUTO PRECHARGE
BANK
BA0,BA1
ROW
BANK
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
DIN
m
DIN m+1
DIN m+2
DIN m+3
DQ
tWR2
tRP
tRCD
tRAS
tRC
DON’T CARE
G-Link Technology Corp.
Dec 2003 Rev.0.3
43
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
1
WRITE, WITH AUTO PRECHARGE
Notice :
1
For this example, the burst length = 4.
2
Faster frequencies require two clocks (when tWR > tCK).
A8 and A9 = “Don’t Care.”
3
T0
T1
T 2
T 3
T 4
T5
T6
T7
T8
T9
tCK
tCLW
CLK
CKE
tCH
W
tIH
tIS
tIH
tIS
COMMAND
DQM 0-3
ACTIVE
NOP
WRITE
tIH
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
tIS
tIS
tIH
ROW
tIH
COLUMNm3
ROW
ROW
ROW
A0 - A9
A10
tIS
tIS
ENABLE AUTO PRECHARGE
ROW
tIH
BA0,BA1
ROW
BANK
tIS tIH
tIS
tIH
tIS
tIH
tIS
tIH
DIN
m
DIN m+1
DIN m+2
DIN m+3
DQ
tWR2
tRP
tRCD
tRAS
tRC
DON’T CARE
G-Link Technology Corp.
Dec 2003 Rev.0.3
44
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
1
ALTERNATING BANK WRITE ACCESS
Notice :
1
For this example, the burst length = 4.
2
Faster frequencies require two clocks (when tWR > tCK).
3
A8 and A9 = “Don’t Care.”
T0
T1
T 2
T 3
T 4
T5
T6
T7
T8
T9
tCK
tCLW
CLK
CKE
tCH
W
tIH
tIS
tIH
tIS
COMMAND
DQM 0-3
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
tIS
tIH
tIH
tIS
tIS
tIS
ROW
tIH
COLUMN m3
ROW
ROW
BANK 1
COLUMN b3
ROW
ROW
BANK 0
A0 - A9
A10
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
ROW
tIH
BA0,BA1
BANK 0
BANK 0
BANK 1
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
tIS
tIH
DIN
m
DIN m+1
DIN m+2
DIN m+3
DIN
b
DIN b+1
DIN b+2
DIN b+3
DQ
tWR2 - BANK 0
tRP - BANK 0
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRRD
tRCD - BANK 0
tRCD - BANK 4
tWR - BANK 4
DON’T CARE
G-Link Technology Corp.
Dec 2003 Rev.0.3
45
ADVANCED
GLT5640L32
CMOS Synchronous DRAM
G-LINK
WRITE, FULL-PAGE BURST
Notice :
1
1
A8 and A9 = “Don’t Care.”
2
tWR must be satisfied prior to PRECHARGE command.
Page left open ; no tRP.
3
T0
T1
T 2
T 3
T 4
T 5
T n+1
T n+2
T n+3
tCL
tCKE
CLK
CKE
tCHW
tIH
tIS
tIS
tIH
COMMAND
DQM 0-3
BURST TERM
ACTIVE
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
tIS
tIH
tIS
tIH
ROW
tIH
COLUMNm1
A0 - A9
A10
tIS
tIS
ROW
tIH
BA0,BA1
BANK
BANK
tIH
tIH
tIH
tIH
tIH
tIS
tIS
tIS
tIS
tIS
DQ
Din m
Din m+1
Din m+2
Din m+3
Din m-1
tRCD
Full page burst does
not self-terminate. Can
use BURST TERMINATE
command to stop. 2,3
256 locations within same row
Full page completed
DON’T CARE
G-Link Technology Corp.
Dec 2003 Rev.0.3
46
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
1
WRITE, DQM OPERATION
Notice :
1
For this example, the burst length = 4.
A8 and A9 = “Don’t Care.”
2
T0
T1
T 2
T 3
T4
T5
T 6
T 7
tCK
CLK
CKE
tCLW
tCHW
tIS
tIS
tIH
tIH
COMMAND
DQM 0 - 3
ACTIVE
NOP
WRITE
tIS
NOP
NOP
NOP
NOP
NOP
tIH
tIS
tIH
ROW
COLUMN m2
A0 - A9
tIS
tIH
ENABLE AUTO PRECHARGE
A10
ROW
DISABLE AUTO PRECHARGE
BANK
tIS
tIH
BA0,BA1
BANK
tIS
tIH
tIS
tIH
tIS
tIH
DQ
Din m
Din m+2
Din m+3
tRCD
DON’T CARE
G-Link Technology Corp.
Dec 2003 Rev.0.3
47
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
GLT 5 640 L 32
- 10 TC
4 : DRAM
5 : Synchronous
DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
9 : SGRAM
PACKAGE
-SRAM
064 : 8K
256 : 256K
512 : 512K
100 : 1M
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
SPEED
T : PDIP(300mil)
TS : TSOP(Type I)
TC : TSOP(Type ll)
PL : PLCC
-SRAM
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
30 : 30ns
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
SDRAM :
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
-DRAM
10 : 1M(C/EDO)
11 : 1M(C/FPM)
12 : 1M(H/EDO)
13 : 1M(H/FPM)
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
160 : 16M(EDO)
161 : 16M(FPM)
640 : 64M(EDO)
641 : 64M(FPM)
VOLTAGE
Blank : 5V
L : 3.3V
M : 2.5V
N : 2.1V
TQ : TQFP
FG : 48Pin BGA 9x12
FH : 48Pin BGA 8x10
FI : 48Pin BGA 6x8
5
: 5ns/200 MHZ
5.5 : 5.5ns/182 MHZ
6
7
: 6ns/166 MHZ
: 7ns/143 MHZ
10 : 10ns/100 MHZ
-SDRAM
40 : 4M
160 : 16M
640 : 64M
POWER
Blank : Standard
L : Low Power
LL : Low Low Power
SL : Super Low Power
Temperature Range
E : Extended Temperature
I : Industrial Temperature
Blank : Commercial Temperature
G-Link Technology Corp.
Dec 2003 Rev.0.3
48
ADVANCED
GLT5640L32
G-LINK
CMOS Synchronous DRAM
PACKAGE DIMENSIONS
86 PIN TSOP-II 400mil PLASTIC
DETAIL - A
DETAIL - A
86
44
θ
GAGE PLANE
1
43
0.5
(20
0.1
4 )
0.8
(32
0.2
7 )
Ps. θ ≤ 7
DETAIL - B
DETAIL - B
22.22 / Typ.
(875)
0.2
(8
0.03
1 )
0.10
0.5 / Typ.
(20)
0.61 / Typ.
(24)
Notice : Dimension UNIT, Milimeter(mil).
G- Li nk Technol ogy Cor p.
G-Link Technology Corp.
Dec 2003 Rev.0.3
49
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