GM71C4100CT-60 [ETC]
x1 Fast Page Mode DRAM ; X1快速页模式DRAM
| 型号： | GM71C4100CT-60 |
| 厂家： | 
ETC |
| 描述： | x1 Fast Page Mode DRAM
|
| 文件： | 总9页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GM71C(S)4100C/CL
4,194,304 WORDS x 1BIT
LG Semicon Co.,Ltd.
CMOS DYNAMIC RAM
Description
Features
The GM71C(S)4100C/CL is the new generation
dynamic RAM organized 4,194,304 words x 1 bit.
GM71C(S)4100C/CL has realized higher density,
higher performance and various functions by
utilizing advanced CMOS process technology. The
GM71C(S)4100C/CL offers Fast Page Mode as a
high speed access Mode. Multiplexed address
inputs permit the GM71C(S)4100C/CL to the
packaged in a standard 300mil 20(26) pin plastic
SOJ and standard 300mil 20(26) pin plastic TSOP
II. The package size provides high system bit
densities and is compatible with widely available
automated testing and insertion equipment. System
oriented features include single power supply of
5V+/-10% tolerance, direct interfacing capability
with high performance logic families such as
Schottky TTL.
* 4,194,304 Words x 1 Bit Organization
* Fast Page Mode Capability
* Single Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time
(Unit: ns)
t
RAC
60
t
CAC
15
t
RC
t
PC
110
130
150
40
45
50
GM71C(S)4100C/CL-60
GM71C(S)4100C/CL-70
GM71C(S)4100C/CL-80
70
20
80
20
* Low Power
Active : 605/550/495mW (MAX)
Standby : 5.5mW (CMOS level : MAX)
1.1mW (L-version)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 1024 Refresh Cycles/16ms
* 1024 Refresh Cycles/128ms (L-version)
* Battery Back Up Operation (L-version)
Pin Configuration
20 (26) SOJ
20 (26) TSOP II
1
20
1
20
20
1
DIN
WE
RAS
NC
VSS
DIN
WE
RAS
NC
VSS
VSS
DIN
WE
RAS
NC
2
3
19 DOUT
18 CAS
2
3
19 DOUT
18 CAS
DOUT 19
CAS 18
2
3
4
5
17 NC
4
5
17 NC
NC 17
4
5
16
16
16
A10
A9
A10
A9
A9
A10
A0
A1
A2
A3
6
7
8
9
15 A8
14 A7
A0
A1
A2
A3
6
7
8
9
15 A8
14 A7
A8 15
A7 14
6
7
8
9
A0
A1
A2
A3
13
13
13
A6
A6
A6
12
12
12
A5
A5
A5
VCC 10
11 A4
VCC 10
11 A4
A4 11
10 VCC
NORMAL TYPE
REVERSE TYPE
(Top View)
(Top View)
1
GM71C(S)4100C/CL
LG Semicon
Pin Description
Pin
Function
Address Inputs
Pin
CAS
WE
Function
Column Address Strobe
Read/Write Enable
Power (+5V)
A0-A10
A0-A9
Refresh Address Inputs
Data Input
DIN
VCC
DOUT
Data Output
VSS
Ground
RAS
Row Address Strobe
NC
No Connection
Ordering Information
Type No.
Access Time
Package
GM71C(S)4100CJ/CLJ-60
GM71C(S)4100CJ/CLJ-70
GM71C(S)4100CJ/CLJ-80
60ns
70ns
80ns
300 Mil, 20 (26) Pin
Plastic SOJ
GM71C(S)4100CT/CLT-60
GM71C(S)4100CT/CLT-70
GM71C(S)4100CT/CLT-80
60ns
70ns
80ns
300 Mil, 20 (26) Pin
Plastic TSOP II
(Normal Type)
GM71C(S)4100CR/CLR-60
GM71C(S)4100CR/CLR-70
GM71C(S)4100CR/CLR-80
60ns
70ns
80ns
300 Mil, 20 (26) Pin
Plastic TSOP II
(Reverse Type)
Absolute Maximum Ratings*
Symbol
Parameter
Ambient Temperature under Bias
Rating
0 ~ 70
Unit
C
TA
TSTG
VIN/VOUT
VCC
Storage Temperature (Plastic)
Voltage on any Pin Relative to VSS
Voltage on VCC Relative to VSS
Short Circuit Output Current
Power Dissipation
-55 ~ 125
-1.0 ~ 7.0
-1.0 ~ 7.0
50
C
V
V
IOUT
mA
W
PD
1.0
*Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Recommended DC Operating Conditions (TA = 0 ~ 70C)
Symbol
VCC
Parameter
Supply Voltage
Min
4.5
Typ
Max
5.5
Unit
5.0
V
V
V
VIH
Input High Voltage
Input Low Voltage
2.4
-
-
6.5
VIL
-1.0
0.8
2
GM71C(S)4100C/CL
LG Semicon
DC Electrical Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C)
Symbol
Parameter
Min Max Unit Note
VOH
Output Level
Output Level Voltage (IOUT = -5mA)
2.4
0
VCC
V
V
VOL
ICC1
Output Level
Output Level Voltage (IOUT = 4.2mA)
0.4
OperatingCurrent
Average Power Supply Operating Current
(RAS, CAS, Address Cycling: tRC = tRC min)
60ns
70ns
80ns
-
-
-
110
100
90
mA 1, 2
mA
ICC2
ICC3
Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS= VIH, DOUT = High-Z)
-
2
RAS-Only Refresh Current
Average Power Supply Current
RAS-Only Refresh Mode
60ns
70ns
80ns
60ns
70ns
-
-
-
-
-
110
100
90
mA
2
(RAS Cycling, CAS = VIH, tRC = tRC min)
Fast Page Mode Current
Average Power Supply Current
Fast Page Mode
ICC4
110
100
mA 1, 3
(RAS = VIL, CAS, Address Cycling: tPC = tPC min)
80ns
-
-
90
1
Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS >= VCC - 0.2V)
ICC5
ICC6
mA
5
-
200 uA
110
4, 5
CAS-before-RAS Refresh Current
(tRC = tRC min)
60ns
70ns
80ns
-
-
-
100
90
mA
ICC7
ICC8
Battery Back Up Current (Standby with CBR Refresh)
(tRC=125us, tRAS<=1us, WE=VIH, CAS=VIL,
OE, Address and DIN=VIH or VIL, DOUT=High-Z)
-
-
300 uA
4, 5
1
Standby Current RAS = VIH
CAS = VIL
5
mA
DOUT = Enable
II(L)
Input Leakage Current
Any Input (0V<=VIN<=7V)
-10
-10
10
10
uA
uA
Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<=7V)
IO(L)
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL
.
3. Address can be changed once or less while CAS = VIH
.
4. L-version.
5. VCC-0.2V<=VIH<=6.5V, 0V<=VIL<=0.2V.
3
GM71C(S)4100C/CL
LG Semicon
Capacitance (VCC = 5V+/-10%, TA = 25C)
Symbol
CI1
Parameter
Input Capacitance (Address, DIN
Input Capacitance (Clocks)
Min
Max
Unit
§Ü
Note
1
)
-
-
-
5
7
7
§Ü
CI2
1
§Ü
CO
Output Capacitance (DOUT
)
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT
.
AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C, Notes 1, 2, 15)
Test Conditions
§Ü
)
Input rise and fall times: 5ns
Output load : 2 TTL gate + C
L
(100
Input, output timing reference levels: 0.8V, 2.4V
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
GM71C(S)4100 GM71C(S)4100 GM71C(S)4100
C/CL-60
C/CL-70
C/CL-80
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RC
Random Read or Write Cycle Time
RAS Precharge Time
110
40
-
-
130
50
-
-
150
60
-
-
ns
ns
ns
ns
ns
ns
ns
ns
RP
RAS
CAS
ASR
RAH
ASC
CAH
RCD
RAD
RSH
CSH
CRP
T
RAS Pulse Width
60 10,000
15 10,000
70 10,000
20 10,000
80 10,000
20 10,000
CAS Pulse Width
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
0
10
0
-
-
-
-
0
10
0
-
-
-
-
0
10
0
-
-
-
-
15
15
15
20 45
15 30
20 50
15 35
20 60
15 40
ns
ns
ns
ns
ns
8
9
15
60
10
-
-
-
20
70
10
-
-
-
20
80
10
-
-
-
CAS Hold Time
CAS to RAS Precharge Time
Transition Time
(Rise and Fall)
3
50
3
50
3
50
ns
7
Refresh Period
-
-
16
-
-
16
-
-
16
ms
ms
t
REF
Refresh Period (L-version)
128
128
128
4
GM71C(S)4100C/CL
LG Semicon
Read Cycle
GM71C(S)4100 GM71C(S)4100 GM71C(S)4100
C/CL-60 C/CL-70 C/CL-80
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
t
t
RAC
CAC
Access Time from RAS
-
-
60
15
-
-
70
20
-
-
80
20
ns
ns
2,3,16
3, 4,
14, 16
Access Time from CAS
3, 5,
14, 16
t
AA
Access Time from Address
-
30
-
35
-
40
ns
t
t
t
t
t
RCS
RCH
RRH
RAL
OFF
Read Command Setup Time
0
-
-
0
-
-
0
-
-
ns
ns
ns
ns
ns
Read Command Hold Time to CAS
Read Command Hold Time to RAS
Column Address to RAS Lead Time
Output Buffer Turn-off Time
0
0
0
0
0
0
-
-
-
30
0
-
35
0
-
40
0
-
15
20
20
6
Write Cycle
GM71C(S)4100 GM71C(S)4100 GM71C(S)4100
C/CL-60 C/CL-70 C/CL-80
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
t
t
WCS
WCH
Write Command Setup Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Setup Time
0
15
10
15
15
0
-
-
-
-
-
-
-
0
15
10
20
20
0
-
-
-
-
-
-
-
0
15
10
20
20
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
10
t
WP
t
t
t
t
RWL
CWL
DS
11
11
DH
Data-in Hold Time
15
15
15
Read- Modify-Write Cycle
GM71C(S)4100 GM71C(S)4100 GM71C(S)4100
C/CL-60 C/CL-70 C/CL-80
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
t
t
t
t
RWC
RWD
CWD
AWD
Read-Modify-Write Cycle Time
RAS to WE Delay Time
130
60
-
-
-
-
155
70
-
-
-
-
175
80
-
-
-
-
ns
ns
ns
ns
10
10
10
CAS to WE Delay Time
15
20
20
Column Address to WE Delay Time
30
35
40
5
GM71C(S)4100C/CL
LG Semicon
Refresh Cycle
GM71C(S)4100 GM71C(S)4100 GM71C(S)4100
C/CL-60 C/CL-70 C/CL-80
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
t
t
CSR
CAS Set-up Time
(CAS-before-RAS Refresh Cycle)
10
10
-
-
10
10
-
-
10
10
-
-
ns
ns
CHR
CAS Hold Time
(CAS-before-RAS Refresh Cycle)
t
t
RPC
CPN
RAS Precharge to CAS Hold Time
CAS Precharge Time in Normal Mode
10
10
-
-
10
10
-
-
10
10
-
-
ns
ns
Fast Page Mode Cycle
GM71C(S)4100 GM71C(S)4100 GM71C(S)4100
C/CL-60 C/CL-70 C/CL-80
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
t
t
t
t
t
PC
Fast Page Mode Cycle Time
40
10
-
-
-
45
10
-
-
-
50
10
-
-
-
ns
ns
CP
Fast Page Mode CAS Precharge Time
Fast Page Mode RAS Pulse Width
Access Time from CAS Precharge
RAS Hold Time from CAS Precharge
100,000
100,000
100,000
RASP
ACP
RHCP
ns
ns
ns
14
-
35
-
-
40
-
-
45
-
3,14,16
35
40
45
Fast Page Mode Read-Modify-Write Cycle
GM71C(S)4100 GM71C(S)4100 GM71C(S)4100
C/CL-60 C/CL-70 C/CL-80
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
t
t
PRWC
CPW
Fast Page Mode Read-Modify-Write Cycle
Time
60
35
-
-
70
40
-
-
75
45
-
-
ns
ns
CAS Precharge to WE Delay Time
Test Mode Cycle
GM71C(S)4100 GM71C(S)4100 GM71C(S)4100
C/CL-60 C/CL-70 C/CL-80
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
t
t
WS
Test Mode WE Setup Time
Test Mode WE Hold Time
0
-
-
0
-
-
0
-
-
ns
ns
WH
10
10
10
6
GM71C(S)4100C/CL
LG Semicon
Counter Test Cycle
GM71C(S)4100 GM71C(S)4100 GM71C(S)4100
C/CL-60 C/CL-70 C/CL-80
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
40 40 40
t
CPT
CAS Precharge Time in Counter Test
Cycle
-
-
-
ns
Notes:
1. AC Measurements assume tT = 5ns.
2. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
§Ü
Measured with a load circuit equivalent to 2TTL loads and 100
.
3.
4. Assumes that tRCD>=tRCD(max) and tRAD<=tRAD(max).
Assumes that tRCD<=tRCD(max) and tRAD>=tRAD(max).
5.
6.
tOFF(max) defines the time at which the output achieves the open circuit condition and is not
referenced to output voltage levels.
7. VIH(max) and VIL(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH and VIL.
8. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
9. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
10. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only if tWCS >=tWCS(min) the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if
tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) and tCPW>=tCPW(min), the cycle is a read
modify write and the data output will contain data read from the selected cell; if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
11. These parameters are referenced to CAS leading edge in early write cycles and to WE leading
edge in delayed write or a read modify write cycle.
12. An initial pause of 100us is required after power up followed by a minimum of eight
initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal
refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required.
13. tRASP defines RAS pulse width in fast page mode cycles.
14. Access time is determined by the longer of tAA or tCAC or tACP.
7
GM71C(S)4100C/CL
LG Semicon
15.
Test mode operation specified in this data sheet is 8 bit test function controlled by control
address bits RA10, CA10 and CA0. This test mode operation can be performed by WE and CAS
before RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by
normal read cycles or by WCBR refresh cycles. When the state of eight test bits accord each
other, the condition of the output data is high level. When the state of test bits do not accord, the
condition of the output data is low level. Data output pin is DOUT and data input pin is DIN. In
order to end this test mode operation, perform a RAS only refresh cycle or a CAS before RAS
refresh cycle.
16.
In a test mode read cycle, the value of tRAC, tAA, tCAC and tACP is delayed for 2ns to 5ns for the
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.
8
GM71C(S)4100C/CL
LG Semicon
Package Dimension
20(26) SOJ
Unit: Inches (mm)
0.025(0.63) MIN
0.039(1.00) MAX
0.008(0.20)
0.085(2.16) MIN
0.103(2.61) MAX
0.661(16.80) MIN
0.669(17.00) MAX
0.128(3.25) MIN
0.148(3.76) MAX
0.050(1.27)
TYP
0.026(0.66) MIN
0.036(0.91) MAX
0.015(0.38) MIN
0.021(0. 53) MAX
20 (26) TSOP (TYPE II)
0 ~ 8 o
0.012(0.30) MIN
0.028(0.70) MAX
0.009(0.22) MAX
0.667(16.94) MIN
0.690(17.54) MAX
0.041(1.03) MIN
0.048(1.23) MAX
0.012(0.30) MIN
0.020(0.50) MAX
0.050(1.27)
0.001(0.03) MIN
0.009(0.23) MAX
TYP
23
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