GM71C4800CJ-60 [ETC]
x8 Fast Page Mode DRAM ; X8快速页模式DRAM\n
| 型号： | GM71C4800CJ-60 |
| 厂家： | 
ETC |
| 描述： | x8 Fast Page Mode DRAM
|
| 文件： | 总10页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GM71C4800C
GM71CS4800CL
524,288WORDS x 8 BIT
CMOS DYNAMIC RAM
LG Semicon Co.,Ltd.
Description
Features
The GM71C4800C/CL is the new generation
dynamic RAM organized 524,288 bit.
* 524,288 Words x 8 Bit Organization
* Fast Page Mode Capability
x
8
GM71C4800C/CL has realized higher density, higher
performance and various functions by utilizing
* Single Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time
(Unit: ns)
advanced CMOS process technology.
GM71C4800C/CL offers Fast Page Mode as a high
speed access mode. Multiplexed address inputs
The
t
RAC
t
CAC
t
RC
t
PC
GM71C(S)4800C/CL-60
GM71C(S)4800C/CL-70
18
20
110
130 45
60
70
40
permit the GM71C4800C/CL to be packaged in
standard 400 mil 28pin plastic SOJ. The package
size provides high system bit densities and is
compatible with widely available automated testing
and insertion equipment. System oriented features
include single power supply of 5V+/-10% tolerance,
direct interfacing capability with high performance
logic families such as Schottky TTL.
* Low Power
Active : 715/660 mW(MAX)
Standby : 5.5mW (CMOS level : MAX)
1.1mW (L-series)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
§Â
* 1024 Refresh Cycles/16
§Â
* 1024 Refresh Cycles/128 (L-series)
* Battery Back Up Operation (L-series)
* Self-Refresh Operation (GM71C4800C/CL)
Pin Configuration
28 SOJ
VSS
I/O0
I/O1
I/O2
I/O3
VSS
1
28
I/O7
I/O6
I/O5
I/O4
2
3
4
5
27
26
25
24
NC
6
23
CAS
OE
7
22
21
20
19
WE
8
RAS
A9
NC
A8
9
10
11
12
13
14
A7
A0
A1
18 A6
17
A5
A2
16
A4
A3
15
VSS
VCC
(Top View)
1
GM71C4800C
GM71CS4800CL
Pin Description
Pin
A0-A9
A0-A9
I/O0-I/O7
RAS
Function
Address Inputs
Pin
WE
OE
Function
Read/Write Enable
Refresh Address Inputs
Data-In/Out
Output Enable
Power (+5V)
Ground
VCC
VSS
Row Address Strobe
Column Address Strobe
NC
No Connection
CAS
Ordering Information
Type No.
Access Time
Package
GM71C4800CJ-60
GM71C4800CJ-70
60ns
400 Mil
28 Pin
Plastic SOJ
§À
70
400 Mil
28Pin
Plastic SOJ
60ns
§À
GM71CS4800CLJ-60
GM71CS4800CLJ-70
70
2
GM71C4800C
GM71CS4800CL
Absolute Maximum Ratings*
Symbol
TA
Parameter
Rating
0 ~ 70
Unit
C
Ambient Temperature under Bias
Storage Temperature (Plastic)
Voltage on any Pin Relative to VSS
Voltage on VCC Relative to VSS
Short Circuit Output Current
Power Dissipation
TSTG
-55 ~ 125
-1.0 ~ 7.0
-1.0 ~ 7.0
50
C
VIN/VOUT
VCC
V
V
IOUT
mA
W
PD
1.0
*Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Recommended DC Operating Conditions* (TA = 0 ~ 70C)
Symbol
VCC
Parameter
Supply Voltage
Min
4.5
Typ
Max
5.5
Unit
V
5.0
VIH
Input High Voltage
Input Low Voltage
2.4
-
-
6.5
V
VIL
-1.0
0.8
V
*Note: All voltage reffered to Vss
Truth Table
RAS
CAS
H
H
L
WE
H
H
H
H
H
L
OE
H
H
L
L
L
H
H
H
H
-
I/O0-I/O7
High-Z
I/O8-I/O15
High-Z
Operation
Standby
Refresh
L
L
High-Z
High-Z
DOUT
High-Z
Lower Byte Read
Upper Byte Read
Word Read
H
L
High-Z
DOUT
L
L
DOUT
DOUT
L
DIN
Don't Care
Lower Byte Write
Upper Byte Write
Word Write
L
H
L
L
Don't Care
DIN
L
L
DIN
DIN
L
L
H
-
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
H to L
H to L
H to L
L
CBR Refresh
or
H
L
-
-
Self Refresh
-
-
3
GM71C4800C
GM71CS4800CL
DC Electrical Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C)
Symbol
Parameter
Min Max Unit Note
Output Level
Output "H" Level Voltage (IOUT = -2mA)
V
OH
2.4
0
VCC
V
V
V
OL
Output Level
Output "L" Level Voltage (IOUT = 2mA)
0.4
ICC1
Operating Current
Average Power Supply Operating Current
(RAS, CAS Cycling: tRC = tRC min)
130
120
§À
§À
60
-
-
mA
mA
mA
1, 2
70
Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS = VIH, DOUT = High-Z)
I
CC2
-
2
ICC3
-
-
§À
60
130
120
RAS-Only Refresh Current
Average Power Supply Current
(tRC = tRC min)
2
§À
70
-
-
ICC4
§À
§À
130
120
60
Fast Page mode current
Average Power Supply Current
(tPC = tPC min)
mA
1, 3
70
Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS, WE, OE>=VCC-0.2V, DOUT=High-Z)
ICC5
-
-
1
mA
uA
4
200
4,5
§À
§À
-
-
130
120
60
ICC6
CAS-before-RAS Refresh Current
(tRC = tRC min)
mA
70
I
CC7
Battery Back Up Current
(Standby with CBR Refresh)
(tRC=125¥ì S , tRAS<=1¥ì S , WE, OE=VIH, CAS =VIL, DOUT=High-Z)
300
5
uA 4, 5
-
-
Standby Current RAS = VIH
CAS = VIL
ICC8
mA
1
6
DOUT = Enable
GM71C4800C
GM71CS4800CL
-
-
1
mA
uA
Self-Refresh Mode Current
(RAS, CAS<=0.2V, DOUT = High-Z)
ICC9
200
I
I(L)
Input Leakage Current
Any Input (0V<=VIN<=6.5V)
-10
-10
10
10
uA
uA
Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<=6.5V)
IO(L)
Note: 1. ICC depends on output load condition when the device is selected. ICC(max) is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL
3. Address can be changed once or less while LCAS and UCAS = VIH
4. VIH>=VCC-0.2V, 0<=VIL<=0.2V, Address can be changed once or less while RAS=VIL
.
.
.
5. L-Series.
6. Self-refresh series. (GM71C(S)4800C/CL)
4
GM71C4800C
GM71CS4800CL
Capacitance (VCC = 5V+/-10%, TA = 25C)
Parameter
Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-In/Out)
Min
Max
Unit
§Ü
Note
1
Symbol
CI1
-
-
-
5
7
7
§Ü
CI2
1
§Ü
CI/O
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. OE= VIH to disable DOUT
.
AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ 70C, Notes 1, 14, 15, 17, 18)
Test Conditions
Input rise and fall times : 5ns
Output timing reference level : 0.8V, 2.4V
Output load : 2TTL gate + CL (100pF)
Input level : VIL = 0V , VIH = 3.0V
Input timing reference level : 0.8V, 2.4V
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
GM71C(S)4800
C/CL-60
GM71C(S)4800
C/CL-70
Unit Note
Symbol
Parameter
Min
Max
Min
110
40
Max
§À
§À
t
RC
Random Read or Write Cycle Time
130
-
t
t
t
RP
CP
RAS Precharge Time
CAS Percharge Time
RAS Pulse Width
50
-
-
-
10
60
15
22
§À
§À
10
70
10,000
RAS
CAS
ASR
RAH
ASC
CAH
RCD
RAD
RSH
CSH
CRP
OED
DZO
DZC
T
10,000
§À
§À
§À
§À
§À
§À
§À
§À
§À
§À
§À
§À
§À
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CAS Pulse Width
20
0
10,000
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
-
-
0
-
-
-
10
0
10
0
-
19
19
8
15
20
15
20
15
20
70
5
-
50
35
-
45
30
-
9
15
15
60
CAS Hold Time
-
-
CAS to RAS Precharge Time
OE to DIN Delay Time
-
20
24
5
-
15
20
0
-
-
OE Delay Time from DIN
CAS Setup Time from DIN
-
0
0
-
25
25
0
-
-
TransitionTime
(Rise and Fall)
3
§À
3
50
7
50
§Â
§Â
Refresh Period
-
-
16
-
-
16
t
REF
Refresh Period (L-Series)
128
128
5
GM71C4800C
GM71CS4800CL
Read Cycle
GM71C(S)4800
C/CL-70
GM71C(S)4800
C/CL-60
Unit
Note
Symbol
Parameter
Access Time from RAS
Min
Min
Max
60
Max
70
§À
§À
-
-
2, 3
-
-
t
t
t
t
t
RAC
CAC
3, 4, 13
Access Time from CAS
20
15
§À 3, 5, 13
Access Time from Address
Access Time from OE
-
-
35
20
-
-
-
30
15
-
AA
§À
§À
3
OAC
RCS
Read Command Setup Time
0
0
0
19
§À
§À
Read Command Hold Time to CAS
Read Command Hold Time to RAS
-
-
-
-
-
0
0
-
-
16, 19
16
t
t
RCH
RRH
0
§À
§À
§À
Column Address to RAS Lead Time
Column Address to CAS Lead Time
CAS to Output in Low-Z
30
30
0
35
35
0
-
-
-
t
t
t
t
t
t
t
t
RAL
CAL
CLZ
OH
§À
§À
Output Data Hold Time
5
5
-
-
-
-
5
5
0
Output Data Hold Time from OE
OHO
§À
§À
§À
Output Buffer Turn-off Time
Output Buffer Turn-off Time from OE
CAS to DIN Delay Time
0
0
20
20
-
6
6
15
15
-
OFF
OEZ
0
20
24
CDD
15
Write Cycle
GM71C(S)4800
C/CL-70
GM71C(S)4800
C/CL-60
Note
Unit
Symbol
Parameter
Min
Min
Max
Max
§À 10, 19
0
-
0
-
-
-
-
-
-
t
t
WCS
WCH
Write Command Setup Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Setup Time
§À
§À
§À
§À
§À
19
15
10
20
20
0
-
-
-
-
-
15
10
t
WP
t
t
t
RWL
CWL
DS
15
15
0
21
11, 21
§À
-
15
-
11, 21
15
t
DH
Data-in Hold Time
6
GM71C4800C
GM71CS4800CL
Read- Modify-Write Cycle
GM71C(S)4800
C/CL-60
GM71C(S)4800
C/CL-70
Unit Note
Symbol
Parameter
Min
Max
Min
Max
-
-
-
-
-
§À
180
95
45
60
20
-
-
-
-
-
t
RWC
Read-Modify-Write Cycle Time
RAS to WE Delay Time
150
80
§À
§À
§À
§À
10
10
10
t
t
RWD
CWD
CAS to WE Delay Time
35
t
AWD
Column Address to WE Delay Time
OE Hold Time from WE
50
15
t
OEH
Refresh Cycle
GM71C(S)4800
C/CL-70
GM71C(S)4800
C/CL-60
Unit Note
Symbol
Parameter
Min
Max
Min
Max
CAS Setup Time
(CAS-before-RAS Refresh Cycle)
§À
§À
-
10
10
-
19
t
CSR
10
CAS Hold Time
(CAS-before-RAS Refresh Cycle)
-
-
t
CHR
20
19
10
§À
§À
-
-
-
-
t
RPC
RAS Precharge to CAS Hold Time
WE Setup time( CBR refresh cycle )
10
10
10
10
t
WRP
Fast Page Mode Cycle
GM71C(S)4800
C/CL- 7 0
GM71C(S)4800
C/CL- 6 0
Unit
Symbol
Parameter
Note
Min
Max
Max
Min
§À
§À
t
t
t
PC
40
-
45
-
100,000
40
-
Fast Page Mode Cycle Time
100,000
12
RASC
ACP
Fast Page Mode RAS Pulse Width
-
-
3, 13,
20
§À
§À
-
35
-
Access Time from CAS Precharge
RAS Hold Time from CAS Precharge
40
65
-
-
t
t
RHCP
CPW
35
55
Fast Page ModeRead-Modify-Write
Cycle CAS Precharge to WE Delay Time
§À
§À
-
-
10,20
Fast Page Mode Read-Modify-Write
Cycle Time
95
-
t
PCM
80
7
GM71C4800C
GM71CS4800CL
Self-Refresh Mode
GM71C(S)4800
C/CL-70
GM71C(S)4800
C/CL-60
Unit
Note
Symbol
Parameter
Min
Max
Min
Max
100
110
-50
-
-
-
-
-
-
ns
100
130
-50
t
RASS
RAS Pulse Width (Self-Refresh)
RAS Precharge Time (Self-Refresh)
CAS Hold Time (Self-Refresh)
§À
§À
t
RPS
21
t
CHS
Notes:
1. AC Measurements assume tT = 5
§À
.
2. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
§Ü
Measured with a load circuit equivalent to 2 TTL loads and 100
.
3.
4. Assumes that tRCD>=tRCD(max) and tRAD<=tRAD(max).
Assumes that tRCD<=tRCD(max) and tRAD>=tRAD(max).
5.
6.
tOFF(max) define the time at which the output achieves the open circuit condition and are not
referenced to output voltage levels.
7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH and VIL.
8. Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
9. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
10.
tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only ; if tWCS >=tWCS(min), the cycle is an early write cycle
and thedata out pin will remain open circuit (high impedance) throughout the entire cycle; if
tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) and tCPW>=tCPW(min), the cycle is a read
modify write and the data output will contain data read from the selected cell; if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
11. These parameters are referred to CAS leading edge in early write cycle and to WE leading edge
in a delayed write or a read modify write cycle.
12. tRASC defines RAS pulse width in Fast Page mode cycles.
13. Access time is determined by the longer of tAA or tCAC or tACP.
¥ì
14. An initial pause of 100
S
is required after power up followed by a minimum of eight
initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal
refresh counter is used, a minimum of eitht CAS before RAS refresh cycles is required.
8
GM71C4800C
GM71CS4800CL
15.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
16.
17.
Either TRCH or TRRH must be satisfied for a read cycle.
The supply voltage with all Vcc pins must be on the same level.
The supply voltage with all Vcc pins must be on the same level.
18. Do not enable DOUT buffer when using delayed write timing.
¥ì
If you use distributed CBR refresh mode with 15.6 S interval in normal read/write cycle, CBR
19.
20.
21.
¥ì
refresh should be executed within 15.6 S immediately affter exiting from and before entering
into self refresh mode.
If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 cycles
of distributed CBR refresh with 15.6us interval should be executed within 16ms immediately
after exiting from and before entering into self refresh mode.
Repetitive self refresh mode without refreshing all memory is not allowed. once you exit from
self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
9
GM71C4800C
GM71CS4800CL
Package Dimensions
Unit: Inches (mm)
SOJ
0.025(0.64) MIN
0.7197(18.28) MIN
0.730(18.54) MAX
0.128(3.25) MIN
0.148(3.76) MAX
0.050(1.27)
TYP
0.026(0.66) MIN
0.032(0.81) MAX
0.015(0.38) MIN
0.020(0.51) MAX
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