GM71CS16160CLJ-5_技术文档

GM71C16160C

GM71CS16160CL

1,048,576 WORDS x 16 BIT

CMOS DYNAMIC RAM

Description

F eatur es

T h e G M 7 1 C ( S ) 1 6 1 6 0 C /CL is the new

generation dynamic RAM organized 1,048,576

x 16 bit. GM71C(S)16160C/CL has realized

higher density, higher performance and various

functions by utilizing advanced CMOS process

technology. The GM71C(S)16160C/CL offers

Fast Page Mode as a high speed access mode.

M u l t i p l e x e d a d d r e s s i n p u t s p e r m i t t h e

G M 7 1 C ( S ) 1 6 1 6 0 C /CL to be packaged in

standard 400 mil 42 pin plastic SOJ , and

standard 400mil 44(50)pin plastic TSOP II. The

package size provides high system bit densities

and is compatible with widely available

automated testing and insertion equipment.

* 1 ,048,576 Words x 16 Bit Organization

* Fast Page Mode Capability

* S ingle Power Supply (5V+/-10%)

* Fast Access Time & Cycle Time

(Unit: ns)

tRAC

tCAC

t

R C

t

PC

GM71C(S)16160C/CL-5

GM71C(S)16160C/CL-6

GM71C(S)16160C/CL-7

50

60

70

13

15

18

90

35

40

45

110

130

* Low Power

Active : 605/550/495mW (MAX)

Standby : 11mW (CMOS level : MAX )

0.83mW (L-version : MAX )

* RAS Only Refresh, CAS before RAS Refresh,

Hidden Refresh Capability

* All inputs and outputs TTL Compatible

* 4096 Refresh Cycles/64ms

* 4096 Refresh Cycles/128ms (L-version)

* Self Refresh Operation (L-version)

* B attery B ack Up Operation (L-version)

* 2 CAS byte Control

Pin Configuration

42 SOJ

44(50) TSOP II

1

V S S

5 0

V CC

1

4 2

4 1

V S S

V CC

I/O0

I/O1

I/O2

I/O3

V CC

I/O4

I/O5

I/O6

I/O7

NC

4 9

2

3

4

I/O0

I/O1

I/O2

I/O3

V CC

I/O15

I/O14

I/O13

2

3

I/O15

4 8

4 7

4 0 I/O14

3 9 I/O13

4

5

6

7

4 6 I/O12

^{4 5}V S S

3 8

I/O12

6

3 7

V S S

4 4

I/O4

I/O5

I/O11

7

3 6

I/O11

8

9

4 3 I/O10

4 2 I/O9

^{4 1}I/O8

8

3 5

I/O10

I/O6

I/O7

NC

1 0

1 1

9

3 4

3 3

3 2

3 1

3 0

I/O9

I/O8

NC

4 0

NC

1 0

1 1

1 2

1 3

LCAS

UCAS

OE

NC

W E

NC

^{3 6}NC

1 5

1 6

3 5

LCAS

3 4

1 4

1 5

2 9

2 8

1 7

1 8

R A S

A11

A10

A0

W E

UCAS

3 3

R A S

A9

OE

3 2

A9

1 9

2 0

A11

A10

A0

1 6

1 7

1 8

1 9

2 7

A8

3 1

A8

2 6 A7

3 0

A7

2 1

2 2

2 3

2 5

A6

A1

A2

2 9

A6

A1

2 4

A5

2 8 A5

2 7 A4

A2

2 0

2 1

2 3 A4

A3

2 4

2 5

A3

2 6

2 2

V S S

V CC

V S S

(Top View)

Rev 0.1 / Apr’01

GM71C16160C

GM71CS16160CL

Pin Descr iption

P in

F unction

Address Inputs

P in

W E

OE

C C

F unction

Read/W rite Enable

Output Enable

Power (+5V)

Refresh Address Inputs

Data Input/ Data Output

Row Address Strobe

V

S S

Ground

R A S

UCAS, LCAS

Column Address Strobe

NC

No Connection

Ordering Information

T ype No.

Access Time

Package

GM71C(S)16160CJ/CLJ -5

GM71C(S)16160CJ/CLJ -6

GM71C(S)16160CJ/CLJ -7

50ns

60ns

70ns

400 Mil

42 Pin

Plastic SOJ

GM71C(S)16160CT/CLT -5

GM71C(S)16160CT/CLT -6

GM71C(S)16160CT/CLT -7

50ns

60ns

70ns

400 Mil

44(50) Pin

Plastic TSOP II

Absolute Maximum Ratings*

Symbol

Parameter

Ambient Temperature under B ias

Rating

0 ~ +70

Unit

C

T

V

A

STG

IN/OUT

CC

S torage Temperature (Plastic)

Voltage on any Pin Relative to VS S

Voltage on VC C Relative to V S S

Short Circuit Output Current

-55 ~ +125

-1.0 ~ +7.0V

C

V

-1.0 ~ +7.0V

50

I

OUT

mA

W

P

D

1.0

Power Dissipation

Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.

Rev 0.1 / Apr’01

GM71C16160C

GM71CS16160CL

R ecommended DC Operating Conditions (TA = 0 ~ +70C)

Symbol

Parameter

M in

4.5

T yp

Max

5.5

Unit

VCC

VIH

VIL

S upply Voltage

5.0

V

Input High Voltage

Input Low Voltage

2.4

-

6.0

-1.0

0.8

Note: All voltage referred to V ss.

T he supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be

on the same level.

T r uth Table

RAS

LCAS UCAS

W E

O E

Output

Operation

Notes

H

D

L

D

Open

S tandby

1,3

L

H

L

H

L

Valid

Lower byte

1,3

H

L

Read cycle

Upper byte

L

Valid

H

L

Word

D

L

H

L

Open

Lower byte

Open

Early write cycle

D

H

Upper byte

H

L

1,2,3

1,3

L

Open

Word

H

L

Undefined

L

Lower byte

Upper byte

Delayed Write

cycle

H

L

Undefined

Valid

Word

H

Lower byte

L

H to L

L to H

Read-modify

-write cycle

H

L

Upper byte

Valid

L

H

L

H to L

D

L to H

D

Valid

Open

Word

H to L

L

CBR Refresh

or

Self Refresh

(L-series)

H

D

Open

Word

1,3

L

RAS-only

Refresh cycle

Open

Word

H

L

H

D

H

D

H

L

1,3

Read cycle

(Output disabled)

L

Notes: 1. H: High (inactive) L: Low(active) D: H or L

2. tW C S >= 0ns Early write cycle

tW C S <= 0ns Delayed write cycle

3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of

UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However

write OPERATION and output High-Z control are done independently by each UCAS,LCAS.

ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.

Rev 0.1 / Apr’01

GM71C16160C

GM71CS16160CL

CC = 5V+/-10%, Vss

A = 0 ~ 70C)

Symbol

Parameter

M in Max Unit Note

V

OH

Output Level

Output "H" Level Voltage (IO U T = -5mA)

2.4

0

V

C C

V

Output Level

V

O L

0.4

Output "L" Level Voltage (IO U T = 4.2mA)

50ns

ns

110

100

Operating Current

I

C C 1

mA

1, 2

(RAS, UCAS or LCAS Cycling: tR C = tR C min)

-

70

90

I

C C 2

S tandby Current (TTL)

2

Power Supply Standby Current

(RAS, UCAS, LCAS = VIH, D OUT = High-Z)

50ns

ns

110

100

90

C C 3

RAS Only Refresh Current

Average Power Supply Current

RAS Only Refresh Mode

(tR C = tR C min)

2

-

70

I

C C 4

50ns

ns

115

105

Fast Page Mode Current

mA

Fast Page Mode

(

PC = tPC min)

-

70

95

1

S tandby Current (CMOS)

I

C C 5

Power Supply Standby Current

150

5

(RAS, UCAS or LCAS >= VCC - 0.2V, DOUT = High-Z)

CAS-before-RAS Refresh Current

(tR C = tR C min)

C C 6

50ns

ns

110

mA

-

70

90

(Standby with CBR Refresh)

-

500

uA

(

=31.3us,

<=0.3

O U T =

I

C C 8

mA

1

UCAS, LCAS = V

D

O U T

C C 9

-

300

10

uA

(RAS, UCAS or LCAS<=0.2V

O U T =

I

L(I)

Input Leakage Current

Any Input (0V<=V IN<= 6V)

-10

Output Leakage Current

I

L(O)

-10

10

uA

(DOUT is Disabled, 0V<=V O U T <= 6V)

Note: 1. IC C depends on output load condition when the device is selected.

(max) is specified at the output open condition.

2. Address can be changed once or less while RAS = VI L

3. Address can be changed once or less while LCAS and UCAS = VIH

.

5. L-version.

Rev 0.1 / Apr 01

GM71C16160C

GM71CS16160CL

Capacitance (VCC = 5V+/-10%, TA = 25C)

Symbol

Parameter

Input Capacitance (Address)

Input Capacitance (Clocks)

Output Capacitance (Data-In/Out)

M in

Max

Unit

pF

Note

C

I1

-

5

7

1

I2

pF

I/O

7

pF

1, 2

Note: 1. Capacitance measured with B oonton Meter or effective capacitance measuring method.

2. UCAS and LCAS = VIH to disable DOUT

.

AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ +70C, Vss = 0V, Note 1, 2, 3, 19)

Test Conditions

Input rise and fall times : 5 ns

Output timing reference levels : 0.4V, 2.4V

Output load : 2TTL gate + CL (100 pF)

(Including scope and jig)

Input timing reference levels : 0.8V , 2.4V

R ead, W r ite, Read-Modify-W r ite and Refr esh Cycles (Common Parameters)

GM71C(S)16160 GM71C(S)16160 GM71C(S)16160

C/CL-5

C/CL-6

C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

Random Read or Write Cycle Time

R A S Precharge Time

90

30

-

110

40

-

130

50

-

ns

t

R C

tRP

CAS Precharge Time

7

-

10

60

-

10

70

-

ns

25

t

CP

ns

tR A S

RAS Pulse Width

50 10,000

10,000

tCAS

CAS Pulse Width

13 10,000 15 10,000 18 10,000

tA S R

Row Address Set up Time

Row Address Hold Time

Column Address Set-up Time

0

-

0

10

0

-

0

10

0

-

tRAH

7

tASC

0

ns

22

4

tCAH

Column Address Hold Time

RAS to CAS Delay Time

RAS to Column Address Delay Time

RAS Hold Time

7

-

45

30

-

10

20

15

60

5

-

45

30

-

15

20

15

18

70

5

-

52

35

-

17

12

13

50

5

tRCD

tR A D

5

tRSH

CAS Hold Time

-

tCSH

CAS to RAS Precharge Time

OE to DIN Delay Time

-

23

6

tCRP

tODD

13

0

-

15

0

-

18

0

-

tDZO

OE Delay Time from DIN

CAS Delay Time from DIN

T ransition Time (Rise and Fall)

-

7

0

-

0

-

0

-

7

tDZC

tT

3

50

3

50

3

50

8

Rev 0.1 / Apr’01

GM71C16160C

GM71CS16160CL

R ead Cycle

GM71C(S)16160 GM71C(S)16160 GM71C(S)16160

C/CL-5 C/CL-6 C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

t

RAC

Access Time from RAS

-

50

13

25

13

-

60

15

30

15

-

70

18

35

18

-

ns

9,10

10,11,18

10,26

tCAC

Access Time from CAS

tAA

Access Time from Address

Access Time from OE

-

tOAC

-

tR C S

Read Command Setup Time

Read Command Hold Time to CAS

0

tRCH

-

13,23

13

-

Read Command Hold Time to RAS

Column Address to RAS Lead Time

5

tRRH

tRAL

25

-

30

35

-

tCAL

Column Address to CAS Lead Time

CAS to Output in Low-Z

25

0

30

0

-

35

0

-

tCLZ

3

-

tOH

Output Data Hold Time

3

-

3

-

tOHO

Output Data Hold Time from OE

Output B uffer Turn-off Time

Output B uffer Turn-off Time to OE

CAS to DIN Delay Time

3

-

3

-

tO F F

13

-

15

-

15

-

14

6

-

tOEZ

-

13

15

18

tCDD

W r ite Cycle

GM71C(S)16160 GM71C(S)16160 GM71C(S)16160

C/CL-5 C/CL-6 C/CL-7

Symbol

Parameter

Unit

Note

Min Max Min Max Min Max

Write Command Setup Time

Write Command Hold Time

Write Command Pulse Width

Write Command to RAS Lead Time

Write Command to CAS Lead Time

Data-in Setup Time

15,22

22

0

7

-

0

-

0

-

ns

t

W C S

10

15

0

15

10

18

0

tWCH

7

t

WP

13

0

tR W L

24

tC W L

16,24

tD S

Data-in Hold Time

7

10

15

t

D

H

Rev 0.1 / Apr’01

GM71C16160C

GM71CS16160CL

R ead- Modify-W r ite Cycle

GM71C(S)16160 GM71C(S)16160 GM71C(S)16160

C/CL-5 C/CL-6 C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

t

R W C

Read-Modify-Write Cycle Time

RAS to WE Delay Time

131

73

-

155

85

-

181

98

-

ns

tR W D

15

tC W D

CAS to WE Delay Time

36

40

46

tAWD

Column Address to WE Delay Time

OE Hold Time from WE

48

55

63

t

OEH

13

15

18

R efresh Cycle

GM71C(S)16160 GM71C(S)16160

C/CL-5 C/CL-6

GM71C(S)16160

C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

tC S R

CAS Setup Time

22

5

-

5

-

5

-

ns

(CAS-before-RAS Refresh Cycle)

t

CHR

CAS Hold Time

23

22

7

5

-

10

5

-

10

5

-

ns

(CAS-before-RAS Refresh Cycle)

t

RPC

R A S Precharge to CAS Hold Time

F a st Page Mode Cycle

GM71C(S)16160 GM71C(S)16160 GM71C(S)16160

C/CL-5 C/CL-6 C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

35

-

40

-

45

-

ns

t

PC

Fast Page Mode Cycle Time

100,000

Fast Page Mode RAS Pulse Width

17

tR A S P

Access Time from CAS Precharge

RAS Hold Time from CAS Precharge

-

30

-

35

-

40

-

10,18,23

tACP

30

35

40

tRHCP

Rev 0.1 / Apr’01

GM71C16160C

GM71CS16160CL

F a st Page Mode Read-Modify-W r ite Cycle

GM71C(S)16160 GM71C(S)16160 GM71C(S)16160

C/CL-5 C/CL-6 C/CL-7

Unit

Note

Symbol

Parameter

Min Max Min Max Min Max

t

PRWC

Fast Page Mode Read-Modify-Write

Cycle Time

76

53

-

85

60

-

96

68

-

ns

tCPW

15,23

WE Delay Time from CAS Precharge

Self Refr esh

Mode

GM71CS16160

C L - 5

GM71CS16160

C L - 6

GM71CS16160

C L - 7

Symbol

Parameter

Unit

Note

Min Max Min Max Min Max

t

R A S S

-

us

ns

RAS Pulse Width(Self-Refresh)

100

90

100

110

-50

100

130

-50

27

tR P S

R A S Precharge Time(Self-Refresh)

CAS Hold Time(Self-Refresh)

-50

tCHS

ns

Notes:

1. AC measurements assume t

T

= 5ns.

2. An initial pause of 200us is required after power up followed by a minimum of eight initialization

cycles(any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh).

If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are

required.

3. Only row address is indispensable on address A8, A9, A10, A11.

4. Operation with the tRCD(max)limit insures that tRAC(max)can be met, tRCD(max)is specified as a

reference point only; if tRCD >= tRAD(max) + tAA(max) - tCAC(max), then access time is controlled

exclusively by tCAC

.

5. Operation with the tRAD(max) limit insures that tRAC(max)can be met, tRAD(max)is specified as a

reference point only; if tRAD is greater than the specified tRAD(max)limit, then access time is

controlled exclusively by tAA.

6. Either tODD or tCDD must be satisfied.

7. Either tDZO or tDZC must be satisfied.

8. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,

transition times are measured between VIH(min) and VIL(max).

9. Assumes that tRCD <= tRCD(max) and tRAD <= tRAD(max). If tRCD or tRAD is greater than the

maximum recommended value shown in this table, tRAC exceeds the value shown.

10. Measured with a load circuit equivalent to 2 TTL load and 100pF.

11. Assumes that tRCD >= tRCD(max) and tRCD + tCAC(max) >= tRAD + tAA(max).

12. Assumes that tR A D >= tR A D (max) and tRCD + tCAC(max) <= tRAD + tAA(max).

Rev 0.1 / Apr’01

GM71C16160C

GM71CS16160CL

Either tRCH or tRRH must be satisfied for a read cycles.

14. tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit

condition and are not referred to output voltage levels.

W C S

,

, t

the data sheet as electrical characteristics only; if t

cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle

; if tR W D >= tR W D (min), tCWD >= t >= tAWD(min), or tCWD

t

are not restrictive operating parameters. They are included in

>= tW C S (min), the cycle is an early write

tC W D

t

AWD

t

CPW

contain data read from the selected cell; if neither of the above sets of conditions is satisfied,

the condition of data out (at access time)is indeterminate.

WE leading edge in delayed write or read-modify-write cycles.

17. tRASP

18. Access time is determined by the longest among AA

t

,and tACP

19. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying

data to the device. After RAS is reset, if tOEH >= tCWL, the I/O pin will remain open circuit

(high impedance); if tOEH< tCWL, invalid data will be out at each I/O.

20. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device.

UCAS and LCAS cannot be staggered within the same write/read cycles.

21. All the VCC and VS S pins shall be supplied with the same voltages.

22. tASC, tCAH, tRCS, tW C S ,tWCH,tCSR and tRPC are determined by the earlier falling edge of UCAS

or LCAS.

23. tCRP,tCHR, tRCH, tACP and tCPW are determined by the later rising edge of UCAS or LCAS.

24. tCWL, tDH,tD S and tCSH should be satisfied by both UCAS and LCAS.

25. tCP is determined by that time the both UCAS and LCAS are high.

26. When output buffers are enabled once, sustain the low impedance state until valid data is

obtained.

When output buffer is turned on and off within a very short time, generally it causes large

V

CC/V S S line noise, which causes to degrade VIH min/VIL max level.

27. Please do not use tR A S S timing, 10us <= t

transition state from normal operation mode to self refresh mode. If R A S S >=100us, then

RAS precharge time should use tR P S instead of tRP

.

28. If you use distributed CBR refresh within 15.6us interval in normal read/write cycle, CB R

refresh should be executed within 15.6us immediately after exiting from and before entering

into self refresh mode.

29. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or

1024 cycles of distributed CBR refresh with 15.6us interval should be executed within 64 or

16ms immediately after exiting from and before entering into the self refresh mode.

30. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from

self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode

again.

31. H or L (H: VIH (min) <= V

IH

IL

<= VIN <= VIL (max))

Rev 0.1 / Apr 01

GM71C16160C

GM71CS16160CL

Unit: Inches (mm)

Package Dimension

42 SOJ

0.025(0.64)

MIN

0.093(2.38)

MIN

1.058(26.89) MAX

1.072(27.23) MAX

0.128(3.25) MIN

0.148(3.75) MAX

0.050(1.27)

TYP

0.026(0.66) MIN

0.032(0.81) MAX

0.015(0.38) MIN

0.020(0.50) MAX

44(50) TSOP I

0.016(0.40) MIN

0.024(0.60) MAX

_{0 ~ 5}¡ £

0.004(0.12) MIN

0.008(0.21) MAX

0.820(20.82) MIN

0.830(21.08) MAX

0.037(0.95) MIN

0.041(1.05) MAX

0.047(1.20)

MAX

0.012(0.30) MIN

0.017(0.45) MAX

0.031(0.80)

TYP

0.002(0.05) MIN

0.006(0.15) MAX

Rev 0.1 / Apr’01


型号：	GM71CS16160CLJ-5
厂家：	ETC
描述：	x16 Fast Page Mode DRAM X16快速页模式DRAM\n 动态存储器
文件：	总10页 (文件大小：115K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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