GM71VS65803CLT-5 [ETC]
x8 EDO Page Mode DRAM ; X8 EDO页模式DRAM\n
| 型号： | GM71VS65803CLT-5 |
| 厂家： | 
ETC |
| 描述： | x8 EDO Page Mode DRAM
|
| 文件： | 总11页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
G M 71V 65803C
G M 71V S65803CL
8,388,608 WORDS x 8 BIT
CMOS DYNAMIC RAM
D escription
Pin Configuration
32 SOJ / TSOP II
T h e GM 71V ( S)65803C/ C L i s t h e n e w
generation dynamic RA M organized 8,388,608
w o r d s by 8bits. T h e GM 71V (S)65803C/ CL
utilizes advanced CM O S Silicon Gate Process
Technology as w ell as advanced circuit
techniques for w ide operating margins, both
i n t er n al l y and to the system u ser . Sy st em
oriented features include single pow er supply of
3.3V + / -10% tolerance, d i r ect i n t erfacing
capability w ith high performance logic families
such as Schottky TTL.
1
2
3
32
31
VSS
IO7
VCC
IO0
IO1
IO2
IO3
NC
30
IO6
4
5
6
7
29
28
27
26
IO5
IO4
VSS
VCC
/CAS
The GM 71V (S)65803C/ CL offers Extended
Data Out (EDO) M ode as a high speed access
mode.
8
9
25
/OE
/WE
/RAS
24 NC
10
A0
23 A11
22 A10
Features
* 8,388,608 Words x 8 Bit
* Extended Data Out (EDO) M ode Capability
* Fast A ccess Tim e & Cycle Tim e
11
12
A1
A2
A3
A9
21
A8
A7
20
19
13
14
15
(Unit: ns)
A4
A5
t
RAC
50
t
A A
t
CAC
13
t
RC
t
H PC
18 A6
VSS
84
20
25
25
30
G M 71V (S)65803C/ CL-5
G M 71V (S)65803C/ CL-6
16
17
VCC
15
104
60
(Top View)
*Pow er dissipation
- A ctive : 522m W / 486mW(M A X)
- Standby : 1.8 mW ( CM OS level : M A X )
0.54mW ( L-Version : M A X)
*EDO page mode capability
*A ccess tim e : 50ns/ 60ns (m ax)
*Refresh cycles
- RA S only Refresh
4096 cycles/ 64 m s (GM 71V65803C)
4096 cycles/ 128m s (GM 71V S65803CL)(L_Version)
*CBR & H idden Refresh
4096 cycles/ 64 m s (GM 71V65803C)
4096 cycles/ 128 m s (GM 71VS65803CL)( L-Version )
*4 variations of refresh
-RA S-only refresh
-CA S-before-RA S refresh
-H idden refresh
-Self refresh (L-V ersion)
*Single Pow er Supply of 3.3V+/ -10 % with a built-in VBB generator
*Battery Back Up Operation ( L-Version )
Rev 0.1 / Apr’01
G M 71V 65803C
G M 71V S65803CL
Pin D escription
Pin
Function
Address Inputs
Pin
W E
Function
A 0-A 11
A 0-A 11
RA S
Write Enable
I/ O0 - I/ O7
VCC
Data Input / Output
Pow er (+3.3V)
Ground
Refresh Address Inputs
Row Address Strobe
Column Address Strobe
Output Enable
VSS
CAS
OE
NC
N o Connection
O rdering Information
Type N o.
A ccess Time
Pack age
400 M il
32Pin
Plastic SOJ
GM71V(S)65803C/ CLJ-5
GM71V(S)65803C/ CLJ-6
50ns
60ns
400 M il
32Pin
Plastic TSOP II
GM71V(S)65803C/ CLT-5
GM71V(S)65803C/ CLT-6
50ns
60ns
Ab solute M aximum Ratings*
Symbol
Param eter
Rating
Unit
TSTG
Storage Temperature (Plastic)
-55 to 125
C
-0.5 to VCC + 0.5
(M A X ; 4.6V)
Voltage on any Pin Relative to VSS
VT
V
VCC
IOUT
PT
Voltage on V CC Relative to VSS
Short Circuit Output Current
Pow er Dissipation
-0.5 to 4.6
V
50
m A
W
1.0
*N ote : Operation at or above A bsolute M aximum Ratings can adversely affect device reliability.
Recommended D C O p erating Conditions (TA = 0 ~ 70C)
Symbol
VCC
Param eter
Supply Voltage
Typ
M ax
3.6
0
M in
3.0
0
Unit
N otes
3.3
V
V
1,2
2
VSS
Supply Voltage
0
-
Vcc+0.3
0.8
VIH
VIL
Input H igh Voltage
Input Low V oltage
2.0
V
V
1
1
-0.3
-
TA
A m bient Temperature under Bias
70
C
0
-
Rev 0.1 / Apr’01
G M 71V 65803C
G M 71V S65803CL
D C Electrical Characteristics: (VCC = 3.3V+/ -10%, TA = 0 ~ 70C)
Symbol
Parameter
M in M ax Unit N ote
VO H
Output Level
2.4
0
VCC
V
V
Output Level Voltage (IOUT = -2m A )
VOL
ICC1
Output Level
0.4
Output Level Voltage (IOUT = 2m A )
Operating Current (tRC = tRC min)
50ns
60ns
-
-
145
135
m A
m A
1,2
Standby Current (TTL interface)
Pow er Supply Standby Current
(RA S, CA S= VI H , D OUT = High-Z)
ICC2
ICC3
-
2
50ns
60ns
-
-
145
135
RA S-Only Refresh Current
( tRC = tRC min)
m A
2
50ns
60ns
-
-
-
110
100
0.5
ICC4
ICC5
Extended Data Out page M ode Current
m A 1,3
m A
(RA S = VIL, CAS, A d d r ess Cycling: tHPC = tHPC min)
CM OS interface
(RA S, CA S>=VCC-0.2V , DOUT = High-Z)
Standby Current(L_Version)
-
300
u A
4
145
135
ICC6
CA S-before-RA S Refresh Current
(tRC = tRC min)
50ns
60ns
-
-
m A
Battery Back Up Operating Current(Standby w ith CBR)
(tRC=31.25us,tRA S=300ns,Dout=High-Z)
u A
ICC7
ICC8
-
500
4, 5
Standby Current (CM O S)
Pow er Supply Standby Current
RA S = VI H , CA S = VIL , D OUT = Enable
-
5
m A
u A
1
5
ICC9
II(L)
Self Refresh Current
-
400
5
(RA S, CA S <=0.2V,Dout=High-Z)
Input Leakage Current, Any Input
(0V<=VI N <=V cc)
-5
u A
u A
IO(L)
Output Leakage Current
-5
5
(DOUT is Disabled, 0V<=VOUT<=V cc)
N ote: 1. ICC depends on output load condition w hen the device is selected. ICC(max) is specified at the
output open condition.
2. Address can be changed once or less w hile RA S = VIL.
3. M easured with one sequential address change per EDO cycle, tH PC.
4. V I H >=VCC-0.2V, 0V<=VIL<=0.2V
5. L -Version
Rev 0.1 / Apr’01
G M 71V 65803C
G M 71V S65803CL
Capacitance (VCC = 3.3V+/ -10%, TA = 25C)
Symbol
CI1
Parameter
Typ
M ax
Unit
pF
N ote
1
-
Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-in,Data-Out)
5
7
7
CI2
-
-
pF
1
CI/ O
pF
1, 2
N ote: 1. Capacitance m easured with Boonton M eter or effective capacitance m easuring method.
2. RA S, CAS = VI H to disable DOUT.
AC Characteristics (VCC = 3.3V+/ -10%, TA = 0 ~ 70C, N otes 1, 2,19)
T est Conditions
Input rise and fall times : 2ns
Input level : VIL/ VI H = 0.0/ 3.0V
Output timing reference levels : VOL/ V O H = 0.8/ 2.0V
Output load : 1 TTL gate+CL (100pF)
Input timing reference levels : VIL/ VI H = 0.8/ 2.0V
(Including scope and jig)
Read, W rite, Read-M odify-W rite and Refresh Cycles (Com m on Param eters)
G M 71V (S)65803C/CL-5 G M 71V (S)65803C/CL-6
Symbol
Parameter
N ote
s
Unit
M i
M i
M ax
M ax
n
n
104
84
-
-
ns
ns
ns
ns
ns
ns
ns
ns
t
t
RC
RP
Random Read or Write Cycle Time
RA S Precharge Time
30
40
-
-
8
-
10
60
10
-
CAS Precharge Time
t
CP
50
10000
10000
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RA S
RA S Pulse Width
10000
8
0
10000
-
C A S
A SR
RA H
A SC
C A H
RCD
RA D
RSH
CSH
CRP
ODD
DZO
DZC
CAS Pulse Width
0
10
0
-
-
Row Address Set-up Time
Row Address H old Time
Column Address Set-up Time
Column Address H old Time
RA S to CA S D elay Time
RA S to Column Address Delay Time
RA S H old Time
8
-
-
-
0
-
10
8
-
ns
ns
3
4
14
12
15
12
10
13
35
5
37
25
-
45
30
-
ns
ns
ns
ns
40
5
-
-
-
CAS H old Time
-
CAS to RA S Precharge Time
OE to DI N Delay Time
OE Delay Time from DI N
CAS D elay Time from DI N
15
13
0
-
-
ns
ns
ns
5
6
0
0
-
-
-
-
0
6
7
50
t
T
TransitionTime (Rise and Fall)
Refresh Period
2
-
2
-
50
64
ns
m s
m s
4096
cycles
4096
t
REF
64
-
-
Refresh Period ( L-Version )
128
128
cycles
Rev 0.1 / Apr’01
G M 71V 65803C
G M 71V S65803CL
Read Cycles
G M 71V (S)65803C/CL-6
G M 71V (S)65803C/CL-5
Symbol
Parameter
N otes
Unit
M i
M ax
50
M ax
60
M i
n
n
ns
ns
-
-
A ccess Tim e from RAS
t
RA C
CAC
8,9
-
13
-
15
A ccess Tim e from CAS
9,10,17
t
t
t
ns
ns
-
-
25
13
-
-
30
15
-
A ccess Tim e from Column Address
A ccess Tim e from OE
A A
9,11,17
9
OAC
0
ns
ns
ns
ns
ns
0
Read Command Set-up Time
-
t
t
t
t
t
RCS
RCH
RRH
RA L
12
12
0
0
0
Read Command H old Time to CA S
Read Command H old Time to RA S
Column Address to RA S Lead Time
Column Address to CA S Lead Time
Output Buffer Turn-off Delay Time from CAS
Output Buffer Turn-off Delay Time from OE
-
-
-
-
0
30
18
25
15
-
-
-
-
CAL
ns
ns
ns
-
-
13
13
-
-
15
15
t
OF
F
13,21
13
t
OEZ
13
-
-
-
-
5
CAS to DI N D elay Time
RA S to DI N Delay Time
15
15
t
CDD
ns
13
t
RDD
ns
ns
15
-
-
-
W E to D I N D elay Time
13
-
t
t
W D D
OFR
13,21
13
Output Buffer Turn-off Delay Time from RAS
13
15
15
ns
ns
ns
t
W EZ
-
3
13
-
Output Buffer Turn-off Delay Time from WE
Output Data H old Time
3
3
21
-
-
-
-
-
-
-
-
t
t
O H
Output Data H old Time from RA S
3
OHR
21
50
3
ns
ns
ns
Read Command H old Time from RAS
Output data hold time from OE
CAS to Output in Low - Z
60
3
t
t
t
RCHR
O H O
CLZ
-
-
0
0
Rev 0.1 / Apr’01
G M 71V 65803C
G M 71V S65803CL
W rite Cycles
G M 71V (S)65803C/CL-5
G M 71V (S)65803C/CL-6
N ote
Symbol
Parameter
Unit
M in
M in
0
M ax
M ax
0
8
-
-
-
-
-
14
ns
ns
ns
ns
ns
ns
ns
Write Com m and Set-up Time
Write Com m and Hold Time
t
t
W C S
W C H
10
10
15
10
0
-
-
-
-
-
-
8
Write Com m and Pulse Width
Write Com m and to RA S Lead Time
t
t
W P
13
8
RW L
-
-
Write Com m and to CA S Lead Time
t
CWL
15
15
0
Data-in Set-up Time
Data-in H old Time
t
t
D S
D H
10
8
-
Read-M odify-W rite Cycles
G M 71V (S)65803C/CL-5
G M 71V (S)65803C/CL-6
N ote
Symbol
Parameter
Unit
M in
116
67
M in
M ax
M ax
140
-
-
-
-
-
-
Read-M odify-Write Cycle Tim e
RA S to W E Delay Time
ns
ns
ns
ns
ns
t
t
t
t
RW C
RW D
C W D
79
34
-
-
14
14
30
CAS to W E Delay Time
42
49
15
14
-
-
Column Address to W E Delay Time
A W D
13
t
OEH
OE H old Time from WE
Refresh Cycles
G M 71V (S)65803C/CL-5 G M 71V (S)65803C/CL-6
N ote
Symbol
Unit
Parameter
M in
M in
M ax
M ax
CAS Set-up Time
(CA S-before-RA S Refresh Cycle)
-
ns
-
5
t
CSR
5
CAS H old Time
(CA S-before-RA S Refresh Cycle)
8
0
-
-
-
-
10
0
ns
ns
t
t
CHR
WRP
W E setup time
(CA S-before-RA S Refresh Cycle)
W E hold time
(CA S-before-RA S Refresh Cycle)
8
5
-
-
10
5
-
-
ns
ns
t
t
W R H
RPC
RA S Precharge to CA S H old Time
Rev 0.1 / Apr’01
G M 71V 65803C
G M 71V S65803CL
Extended D ata Out M ode Cycles
G M 71V (S)65803C/CL-5
G M 71V (S)65803C/CL-6
N ote
Symbol
Parameter
Unit
M in
M in
M ax
M ax
25
20
8
-
-
-
t
t
H PC
W PE
EDO Page M ode Cycle Time
ns
-
ns
20
10
-
-
Write pulse width during CAS Precharge
EDO M ode RA S Pulse Width
-
100000
t
t
t
RA SP
100000
16
ns
ns
ns
ns
ns
ns
-
35
-
9,17
28
-
-
ACP
A ccess Tim e from CAS Precharge
RA S H old Time from CA S Precharge
35
RH C P
28
8
10
t
COL
-
-
-
-
CAS H old Time Referred OE
CAS to OE set-up Time
5
-
5
t
COP
35
t
RCH P
28
-
Read Command H old Time from CAS
Precharge
t
t
D O H
OEP
ns
ns
Output Data H old Time from CA S Low
OE Precharge Time
3
8
-
-
-
-
3
9,22
10
ED O Page M ode Read-M odify-W rite cycle
G M 71V (S)65803C/CL-5
G M 71V (S)65803C/CL-6
N ote
Symbol
Parameter
Unit
M in
57
M in
M ax
M ax
EDO Read-M odify-Write Cycle Time
-
-
68
54
-
-
t
t
H PRW C
CPW
ns
ns
EDO Page M ode Read-M odify-W rite Cycle
C A S Precharge to W E D elay Tim e
45
14
Self Refresh Cycles (L_V ersion)
G M 71V (S)65803C/CL-5
G M 71V (S)65803C/CL-6
Symbol
Parameter
N ote
Unit
M in
100
90
M in
100
110
-50
M ax
M ax
us
-
-
-
-
-
-
t
RA SS
26
26
RA S Pulse Width(Self-Refresh)
ns
ns
t
t
RPS
RA S Precharge Time(Self-Refresh)
CAS H old Time(Self-Refresh)
-50
C H S
Rev 0.1 / Apr’01
G M 71V 65803C
G M 71V S65803CL
Notes:
T
AC measurements assume t = 2
ns
.
1.
2.
AC initial pause of 200
is required after power up followed by a minimum of eight
us
initialization cycles ( any combination of cycles containing RAS-only refresh or CAS-before-
RAS refresh)
RCD
RAC
RCD
Operation with the t (max) limit insures that t (max) can be met, t (max) is specified as a
3.
4.
5.
RCD
RCD
reference point only: if t
controlled exclusively by t
is greater than the specified t
(max) limit, then access time is
CAC
.
RAD
RAC
RAD
Operation with the t (max) limit insures that t (max) can be met, t (max) is specified as a
RAD
RAD
reference point only: if t
controlled exclusively by t .
is greater than the specified t
(max) limit, then access time is
AA
OED
CDD
Either t or t must be satisfied.
DZO
DZC
6. Either t or t must be satisfied.
IH
IL
7. V (min) and V (max) are reference levels for measuring timing of input signals. Also,
IH
IL
transition times are measured between V (min) and V (max).
RCD
RCD
RAD
RAD
RCD
RAD
8. Assumes that t
t
(max) and t
t
<=
(max). If t
or t is greater than the maximum
<=
RAC
recommended value shown in this table, t exceeds the value shown.
9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF.
RCD
RAD
RCD
RCD
CAC
RAD
AA
10. Assumes that t
t
(max) and t + t (max)
t
>=
+ t (max).
>=
11.
RAD
RCD
CAC
RAD
t
AA
Assumes that t
t
(max) and t +t (max)
+t (max).
>=
<=
12.
RCH
RRH
Either t or t must be satisfied for a read cycles.
OFF
t
OEZ(
OFR
WEZ
13.
(max), t max), t (max) and t (max) define the time at which the outputs achieve the
open circuit condition and is not referenced to output voltage levels.
WCS
RWD
CWD, AWD,
CPW
14.
t
, t
data sheet as electrical characteristics only: if t
and the data out pin will remain open circuit (high impedance) throughout the entire cycle: if
, t
t
and t
are not restrictive operating parameters. They are included in the
³
WCS
WCS
t
(min), the cycle is an early write cycle
³
³
³
³
RWD
t
RWD
CWD
CWD
AWD
AWD
CPW
CPW
t
t
(min), t
t
(min), t
t
(min) and t
(min), the cycle is a read-
modify-write and the data output will contain data read from the selected cell: if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
DS
DH
15.
t and t are referred to CAS leading edge in early write cycles and to WE leading edge in
delayed write or read-modify-write cycles.
RASP
16.
17.
18.
t
defines RAS pulse width in extended data out mode cycles.
AA, CAC
CPA
and t
Access time is determined by the longest among t
t
.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
19.
When output buffers are enabled once, sustain the low impedance state until valid daa is
obtained. When output buffer is turned on and off within a very short time, generally it causes
CC
SS
IH
IL
large V /V line noise, which causes to degrade V min/V max level.
Rev 0.1 / Apr’01
G M 71V 65803C
G M 71V S65803CL
HPC
t
(min) can be achieved during a series of EDO mode early write cycles or EDO mode read
20.
21.
cycles. If both write and read operation are mixed in a EDO mode, RAS cycle { EDO mode mix
cycle (1),(2) } minimum value of CAS cycle t HPC (t + t + 2t ) becomes greater than the
specified t
CAS
CP
T
HPC
(min) value.
The value of CAS cycle time of mixed EDO page mode is
shown in EDO page mode mix cycle (1) and (2).
Data output turns off and becomes high impedance from later rising edge of RAS and CAS.
Hold time and turn off time are specified by the timing specifications of later rising edge of RAS
and CAS between t and t , and between t and t
OHR
OH
OFR
OFF
.
DOH
OL
OH
t
defines the time at which the output level go cross.
V
= 0.8V, V =2.0V of output timing
22.
23.
reference level.
Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64
ms
period on the condition a and b below.
a. Enter self refresh mode within 15.6 us after either burst refresh or distributed refresh at equal
interval to all refresh addresses are completed.
b. Start burst refresh or distributed refresh at equal interval to all refresh addressed within 15.6us
after exiting from self refresh mode.
In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and
after self refresh mode according as note 23.
For L_Version, it is available to apply each 128 ms and 31.2 us instead of 64ms and 15.6us at
note 23.
24.
25.
RASS
RASS
At t
> 100 us , self refresh mode is activated, and not active at t
< 10us. It is undefined
26.
27.
RASS
RASS
RPS
within the range of 10 us < t
< 100 us . for t
> 10 us , it is necessary to satisfy t
.
IH
IN
IH
IH
IN
IH
XXX: H or L ( H : V (min)<=V <=V (max), L: V (min)<=V <=V (max))
///////: Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must
IH
IL.
be applied V or V
Rev 0.1 / Apr’01
G M 71V 65803C
G M 71V S65803CL
SOJ 32 pin PK G D i m ension
Unit: mm
0.64 M I N
1.16 M A X
2.09 M I N
3.01 M A X
20.95 M I N
21.38 M A X
1.165 M A X
0.33 M I N
0.53 M A X
1.27
0.33 M I N
0.49 M A X
0.10
Rev 0.1 / Apr’01
G M 71V 65803C
G M 71V S65803CL
TSOPII 32 PIN Pack age D imension
0.40 M I N
0.60 M A X
Unit: mm
¡ £
20.95 M I N
21.35 M A X
0 ~ 5
N O R M A L TYPE
0.145
0.125
0.05
0.04
0.80
1.15 M A X
0.42 0.08
0.40 0.06
1.27
0.08 M I N
0.18 M A X
0.10
Dimension including the plating thickness
Base m aterial dimension
Rev 0.1 / Apr’01
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