GS71024T-12IT [ETC]
x24 SRAM ; X24 SRAM\n
| 型号： | GS71024T-12IT |
| 厂家： | 
ETC |
| 描述： | x24 SRAM
|
| 文件： | 总13页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS71024T/U
TQFP, FPBGA
Commercial Temp
Industrial Temp
8, 10, 12, 15 ns
64K x 24
3.3 V V
DD
1.5Mb Asynchronous SRAM
Fine Pitch BGA Bump Configuration
Features
• Fast access time: 8, 10, 12, 15 ns
• CMOS low power operation: 190/160/130/110 mA at
minimum cycle time.
• Single 3.3 V ± 0.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
1
2
3
4
5
6
A
B
C
D
DQ
A3
A2
A1
A0
DQ
DQ DQ CE2 WE DQ DQ
DQ DQ CE1 OE DQ DQ
• Industrial Temperature Option: –40 to 85°C
• Package
VSS
VDD
VDD
VSS
DQ
DQ
A5
A7
A9
A4
A6
A8
DQ
DQ
T: 100-pin TQFP package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array
E
F
DQ DQ
DQ DQ
Description
G
H
DQ DQ A11 A10 DQ DQ
The GS71024 is a high speed CMOS static RAM organized as
65,536 words by 24 bits. Static design eliminates the need for
external clocks or timing strobes. The GS71024 operates on a
single 3.3 V power supply, and all inputs and outputs are TTL-
compatible. The GS71024 is available in a 6 mm x 8 mm Fine
Pitch BGA package, as well as in a 100-pin TQFP package.
DQ A15 A14 A13 A12 DQ
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Pin Descriptions
Symbol
A0 to A15
X/Y
Description
Address input
Symbol
DQ1 to DQ24
Description
Data input/output
Address Multiplexer Control
Output enable input
—
Vector Input
V/S
OE
—
WE
Write enable input
Chip enable input
+3.3 V power supply
CE1, CE2
VDD
VSS
Ground
Block Diagram
A0
Row
Decoder
Memory Array
1024 x 1536
Address
Input
A14
Column
Decoder
A15
X/Y
V/S
0
1
Q
CE1
CE2
I/O Buffer
Control
WE
OE
DQ1
DQ24
Rev: 1.03 11/2000
1/13
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71024T/U
100-Pin TQFP Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
NC
NC
NC
NC
2
3
4
NC
5
DQ13
DQ14
DQ15
DQ16
VSS
VDD
6
DQ12
DQ11
DQ10
DQ9
VSS
VDD
DQ8
DQ7
VSS
NC
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Top View
DQ17
DQ18
NC
VDD
NC
VSS
VDD
NC
DQ19
DQ20
VDD
DQ6
DQ5
VDD
VSS
DQ4
DQ3
DQ2
DQ1
NC
NC
NC
NC
NC
VSS
DQ21
DQ22
DQ23
DQ24
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 1.03 11/2000
2/13
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71024T/U
Truth Table
VDD Current
CE1
H
X
CE2
OE
X
WE
X
V/S
X
Mode
DQ0 to DQ23
High Z
X
L
Not selected
ISB1, ISB2
X
X
X
Not selected
High Z
L
H
H
H
H
H
L
H
H
L
H
L
Read using X/Y
Read using A15
Write using X/Y
Write using A15
Output disable
Data Out
Data Out
Data In
L
L
IDD
L
X
H
L
L
X
L
Data In
L
H
H
X
High Z
X: “H” or “L”
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply Voltage
VDD
–0.5 to +4.6
V
–0.5 to VDD + 0.5
(£ 4.6 V max.)
Input Voltage
VIN
V
–0.5 to VDD + 0.5
(£ 4.6 V max.)
Output Voltage
VOUT
V
Allowable TQFP power dissipation
Allowable FPBGA power dissipation
Storage temperature
PD
PD
1
1
W
W
oC
TSTG
–55 to 150
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec-
ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
Rev: 1.03 11/2000
3/13
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71024T/U
Recommended Operating Conditions
Parameter
Supply Voltage for -10/12/15
Supply Voltage for -8
Input High Voltage
Symbol
Minimum
3.0
Typical
Maximum
3.6
Unit
VDD
VDD
VIH
VIL
3.3
3.3
—
V
V
V
V
3.135
2.0
3.6
VDD + 0.3
Input Low Voltage
–0.3
—
0.8
70
Ambient Temperature,
Commercial Range
oC
oC
TAc
TAi
0
—
—
Ambient Temperature,
Industrial Range
–40
85
Notes:
1. Input overshoot voltage should be less than VDD + 2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Capacitance
Parameter
Input Capacitance
I/O Capacitance
Symbol
CIN
Test Condition
Maximum
Unit
pF
VIN = 0 V
5
7
COUT
VOUT = 0 V
pF
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested
DC I/O Pin Characteristics
Parameter
Symbol
Test Conditions
Minimum
Maximum
IIL
VIN = 0 to VDD
Input Leakage Current
–1uA
1uA
Output High Z, VOUT = 0
to VDD
IOL
Output Leakage Current
–1uA
1uA
VOH
VOL
IOH = –4mA
IOL = +4mA
Output High Voltage
Output Low Voltage
2.4
—
—
0.4 V
Rev: 1.03 11/2000
4/13
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71024T/U
AC Test Conditions
Output Load 1
Parameter
Conditions
VIH = 2.4 V
VIL = 0.4 V
DQ
Input high level
30pF1
50W
Input low level
Input rise time
VT = 1.4 V
tr = 1 V/ns
tf = 1 V/ns
1.4 V
Input fall time
Output Load 2
Input reference level
Output reference level
Output load
3.3 V
1.4 V
Fig. 1& 2
589W
DQ
Notes:
5pF1
434W
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
.
Power Supply Currents
0 to 70°C
-40 to 85°C
Parameter
Symbol
Test Conditions
8 ns
10 ns 12 ns 15 ns 10 ns 12 ns 15 ns
CE £ VIL
All other inputs
³ VIH or £ VIL
Operating
Supply
IDD
190 mA 160 mA 130 mA 110 mA 165 mA 135 mA 115 mA
Current
Min. cycle time
IOUT = 0 mA
CE ³ VIH
Standby
Current
All other inputs
³ VIH or £VIL
Min. cycle time
ISB1
45 mA
40 mA
35 mA
30 mA
45 mA
40 mA
15 mA
35 mA
CE ³ VDD – 0.2 V
All other inputs
³ VDD – 0.2 V or £ 0.2 V
Standby
Current
ISB2
10 mA
Rev: 1.03 11/2000
5/13
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71024T/U
AC Characteristics
Read Cycle
-8
-10
-12
-15
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max
tRC
tAA
tAC
tAV
Read cycle time
8
—
—
—
—
3
—
8
10
—
—
—
—
3
—
10
10
10
5
12
—
—
—
—
3
—
12
12
12
6
15
—
—
—
—
3
—
15
15
15
7
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
Chip enable access time (CE1, CE2)
MUX control to output valid (V/S)
Output enable to output valid (OE)
Output hold from address change
Output hold from MUX controls change
Chip enable to output in low Z (CE1, CE2)
8
8
tOE
tOH
tOH1
4
—
—
—
—
—
—
—
—
—
—
—
—
3
3
3
3
*
3
3
3
3
tLZ
*
Output enable to output in low Z (OE)
Chip disable to output in High Z (CE1, CE2)
Output disable to output in High Z (OE)
0
—
4
0
—
5
0
—
6
0
—
7
ns
ns
ns
tOLZ
*
—
—
—
—
—
—
—
—
tHZ
*
4
5
6
7
tOHZ
* These parameters are sampled and are not 100% tested
Rev: 1.03 11/2000
6/13
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71024T/U
Read Cycle 1: CE = OE = V , WE = V
IL
IH
tRC
Address
tAA
V/S
tOH
Data Out
Previous Data
Data valid
tOH1
tAV
Read Cycle 2: WE = V
IH
tRC
Address
CE1(*1)
tAA
tAC
tHZ
tLZ
tAV
V/S
OE
tOE
tOHZ
tOLZ
Data Out
Data valid
High impedance
*1 CE1 represents both CE1 low and CE2 high.
Rev: 1.03 11/2000
7/13
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71024T/U
Write Cycle
-8
-10
-12
-15
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max
tWC
tAW
tCW
tVW
tDW
tDH
Write cycle time
8
5.5
5.5
5.5
4
—
—
—
—
—
—
—
—
—
—
—
—
10
7
7
7
5
0
7
0
0
0
0
3
—
—
—
—
—
—
—
—
—
—
—
—
12
8
8
8
6
0
8
0
0
0
0
3
—
—
—
—
—
—
—
—
—
—
—
—
15
10
10
10
7
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to end of write
Chip enable to end of write (CE1, CE2)
MUX control to end of write (V/S)
Data set up time
Data hold time
0
0
tWP
tAS
Write pulse width
5.5
0
10
0
Address set up time
tVS
MUX control set up time
Write recovery time (WE)
Write recovery time (V/S, CE1, CE2 )
Output Low Z from end of write
0
0
tWR
tWR1
0
0
0
0
*
2
3
tWLZ
*
Write to output in High Z
—
4
—
5
—
6
—
7
ns
tWHZ
* These parameters are sampled and are not 100% tested
Rev: 1.03 11/2000
8/13
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71024T/U
Write Cycle 1: WE control
tWC
Address
OE
tAW
tWR
tCW
CE1(*1)
tVW
tVS
V/S
WE
tAS
tWP
(*2)
tDW
tDH
Data In
Data valid
tWHZ
tWLZ
Data Out
High impedance
(*3)
(*3)
*1 CE1 represents both CE1 low and CE2 high.
*2 Write is executed when both CE1 and WE are at low simultaneously.
*3 Do not apply the data input voltage to the output while DQ pin is in output condition.
Write Cycle 2: CE control
tWC
Address
OE
tAW
tWR1
tAS
tCW
CE1(*1)
tVW
V/S
WE
tWP
tDW
tDH
Data In
Data valid
Data Out
High impedance
*1 CE1 represents both CE1 low and CE2 high.
Rev: 1.03 11/2000
9/13
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71024T/U
6 mm x 8 mm Fine Pitch BGA
0 1 . 0 ± 0 0 . 8
0.10
5 2 . 5
Rev: 1.03 11/2000
10/13
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71024T/U
TQFP Package Drawing
q
L
c
Symbol
Description
Standoff
Min. Nom. Max
L1
A1
0.05
1.35
0.20
0.09
0.10
1.40
0.30
0.15
1.45
0.40
0.20
22.1
20.1
16.1
14.1
A2
Body Thickness
Lead Width
b
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
D1
e
E
E1
Package Body
Lead Pitch
13.9
e
b
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
0.75
L1
Y
q
0.10
0°
7°
A1
Notes:
A2
E1
E
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion
BPR 1999.05.18
Rev: 1.03 11/2000
11/13
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71024T/U
Ordering Information
Part Number
GS71024T-8
Package
100-Pin TQFP
Access Time
8 ns
Temp. Range
Commercial
Commercial
Commercial
Commercial
Industrial
Status
GS71024T-10
GS71024T-12
GS71024T-15
GS71024T-8I
GS71024T-10I
GS71024T-12I
GS71024T-15I
GS71024U-8
GS71024U-10
GS71024U-12
GS71024U-15
GS71024U-8I
GS71024U-10I
GS71024U-12I
GS71024U-15I
100-Pin TQFP
10 ns
12 ns
15 ns
8 ns
100-Pin TQFP
100-Pin TQFP
100-Pin TQFP
Not Available
100-Pin TQFP
10 ns
12 ns
15 ns
8 ns
Industrial
100-Pin TQFP
Industrial
100-Pin TQFP
Industrial
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
Commercial
Commercial
Commercial
Commercial
Industrial
10 ns
12 ns
15 ns
8 ns
Not Available
10 ns
12 ns
15 ns
Industrial
Industrial
Industrial
* Customers requiring Tape and Reel should add the character “T” to the end of the part number. For example: GS71024T/U-12T.
Rev: 1.03 11/2000
12/13
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71024T/U
Revision History
Rev. Code: Old;
New
Types of Changes
Format or Content
Page/Revisions/Reason
• Document Changed subscripts to small caps.
• 1/Features: Changed TP to T.
Format/Typos
• Document/Replaced “micro” with “fine pitch”.
GS71024Rev 2:17pm, 4/8/
1999;
• Ordering Information/Added Tape and Reel Note/
Enhancement
• Pin Description/Changed A0 - A14 to A0 - A15/Correction
• Page 1/Took out “Byte Control” from Features/Correction
• 3/Changed pin 97 from NC to CE2/Correction
•
1.00a5/1999
Content
1. Pin out/Changed Pin 89 from CK to NC/Correction
GS710241.00a5/1999;
1.01 8/1999B
2. Pin out/Changed Pin 92 from NC to V/S/Correction
3. Pin out/Changed Pin 93 from V/S to X/Y/Correction
4. Pin out/Changed Pin 94 from X/Y to NC/Correction
Content
• Package Diagram/Changed Dimension “D Max” from 20.1 to
22.1/Correction
GS710241.01 8/1999C;
1.02 9/1999C
Content
Format
• GSI Logo
GS71024Rev1.01 8/
1999C;Rev1.02 2/2000D
• Updated format to comply with Technical Publications
standards
• Changed all VSSQ to VSS and all VDDQ to VDD in pinout on
Rev1.02 2/2000D;
71024_r1_03
Format and Content
page 2
• Updated Revision History (revision notes for 8/1999 incorrect)
Rev: 1.03 11/2000
13/13
© 1999, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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