GS71108J [ETC]
128K x 8 1Mb Asynchronous SRAM; 128K ×8 1Mb的SRAM的异步
| 型号： | GS71108J |
| 厂家： | 
ETC |
| 描述： | 128K x 8 1Mb Asynchronous SRAM |
| 文件： | 总14页 (文件大小：398K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GS71108ATP/J/SJ/U
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
7, 8, 10, 12 ns
3.3 V VDD
Center VDD and VSS
128K x 8
1Mb Asynchronous SRAM
SOJ & TSOP-II 128K x 8-Pin Configuration
Features
• Fast access time: 7, 8, 10, 12 ns
• CMOS low power operation: 140/120/95/80 mA at minimum
cycle time
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
A3
A4
2
A2
A5
3
A1
A6
• Single 3.3 V power supply
4
A0
A7
• All inputs and outputs are TTL-compatible
• Fully static operation
5
CE
OE
DQ8
DQ7
VSS
VDD
DQ6
DQ5
A8
32-pin
400 mil SOJ
&
6
DQ1
DQ2
VDD
VSS
DQ3
DQ4
WE
A16
A15
A14
A13
• Industrial Temperature Option: –40° to 85°C
• Package line up
7
8
J: 400 mil, 32-pin SOJ package
9
300 mil SOJ
&
TP: 400 mil, 32-pin TSOP Type II package
SJ: 300 mil, 32-pin SOJ package
U: 6 mm x 8 mm Fine Pitch Ball Grid Array package
10
11
12
13
14
15
16
400 mil TSOP II
A9
Description
A10
A11
A12
The GS71108A is a high speed CMOS Static RAM organized
as 131,072 words by 8 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS71108A is available in a 6 mm x 8 mm
Fine Pitch BGA package, as well as in 300 mil and 400 mil
SOJ and 400 mil TSOP Type-II packages.
Packages J, TP, and SJ
Fine Pitch BGA 128K x 8-Bump Configuration
1
2
3
4
5
6
A
B
C
D
NC
OE
A2
A1
A0
NC
A6
A5
A4
A3
A7
NC
Pin Descriptions
DQ1 NC
DQ2 NC
CE DQ8
NC DQ7
Symbol
A0–A16
DQ1–DQ8
CE
Description
Address input
Data input/output
Chip enable input
Write enable input
Output enable input
+3.3 V power supply
VSS
VDD
VDD
VSS
NC
NC
NC
NC
E
F
NC
A14
A15
A16
NC
WE
DQ3 NC
DQ4 NC
A11 DQ5 DQ6
OE
V
G
H
A12
A13
WE
A9
A8
DD
V
Ground
SS
NC
A10
NC
NC
No connect
Package U
6 mm x 8 mm, 0.75 mm Bump Pitch
Top View
Rev: 1.04a 10/2002
1/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Block Diagram
A0
Row
Decoder
Memory Array
Address
Input
Buffer
Column
Decoder
A16
CE
WE
OE
I/O Buffer
Control
DQ8
DQ1
Truth Table
V
Current
CE
OE
WE
DQ1 to DQ8
DD
H
L
L
L
X
L
X
H
L
Not Selected
Read
ISB1, ISB2
X
H
Write
IDD
H
High Z
Note: X: “H” or “L”
Rev: 1.04a 10/2002
2/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply Voltage
VDD
–0.5 to +4.6
V
–0.5 to V +0.5
DD
Input Voltage
VIN
V
(≤ 4.6 V max.)
–0.5 to V +0.5
DD
Output Voltage
VOUT
V
(≤ 4.6 V max.)
Allowable power dissipation
Storage temperature
PD
0.7
W
o
TSTG
–55 to 150
C
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec-
ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
Recommended Operating Conditions
Parameter
Supply Voltage for -7/-8/-10/-12
Input High Voltage
Symbol
Min
3.0
Typ
3.3
—
Max
Unit
V
3.6
V
V
V
DD
V
+0.3
VIH
VIL
2.0
DD
Input Low Voltage
–0.3
—
0.8
Ambient Temperature,
Commercial Range
o
TAc
TAI
0
—
—
70
85
C
Ambient Temperature,
Industrial Range
o
–40
C
Notes:
1. Input overshoot voltage should be less than V +2 V and not exceed 20 ns.
DD
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Rev: 1.04a 10/2002
3/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Capacitance
Parameter
Symbol
CIN
Test Condition
VIN = 0 V
Max
Unit
pF
Input Capacitance
Output Capacitance
5
7
COUT
VOUT = 0 V
pF
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
DC I/O Pin Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage
Current
VIN = 0 to V
IIL
–1 uA
–1 uA
1 uA
DD
Output High Z
VOUT = 0 to V
Output Leakage
Current
ILO
1 uA
DD
Output High Voltage
Output Low Voltage
VOH
VOL
IOH = –4 mA
2.4
—
ILO = +4 mA
—
0.4 V
Power Supply Currents
0 to 70°C
–40 to 85°C
Parameter
Symbol
Test Conditions
7 ns
8 ns
10 ns 12 ns
7 ns
8 ns
10 ns 12 ns
CE ≤ VIL
Operating
Supply
Current
All other inputs
≥ VIH or ≤ VIL
Min. cycle time
IOUT = 0 mA
IDD
140 mA 120 mA 95 mA 80 mA 145 mA 125 mA 100 mA 85 mA
CE ≥ VIH
Standby
Current
All other inputs
≥ VIH or ≤VIL
Min. cycle time
ISB1
25 mA 20 mA 20 mA 15 mA 30 mA
25 mA 25 mA 20 mA
CE ≥ VDD – 0.2 V
All other inputs
≥ VDD – 0.2 V or ≤ 0.2 V
Standby
Current
ISB2
2 mA
5 mA
Rev: 1.04a 10/2002
4/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
AC Test Conditions
Output Load 1
Parameter
Input high level
Input low level
Conditions
VIH = 2.4 V
VIL = 0.4 V
tr = 1 V/ns
tf = 1 V/ns
1.4 V
DQ
1
30pF
50Ω
Input rise time
VT = 1.4 V
Input fall time
Input reference level
Output reference level
Output load
Output Load 2
1.4 V
3.3 V
Fig. 1& 2
589Ω
DQ
Note:
1
434Ω
1. Include scope and jig capacitance.
5pF
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
AC Characteristics
Read Cycle
-7
-10
-12
-8
Parameter
Symbol
Unit
Min
7
Max
—
7
Min
8
Max
Min
10
—
—
—
3
Max
Min
12
—
—
—
3
Max
Read cycle time
tRC
tAA
—
8
—
10
10
4
—
12
12
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
—
—
—
3
—
—
—
3
Chip enable access time (CE)
Output enable to output valid (OE)
Output hold from address change
Chip enable to output in low Z (CE)
Output enable to output in low Z (OE)
Chip disable to output in High Z (CE)
Output disable to output in High Z (OE)
tAC
7
8
tOE
3
3.5
—
—
—
4
tOH
—
—
—
3.5
3
—
—
—
5
—
—
—
6
tLZ*
tOLZ*
tHZ*
tOHZ*
3
3
3
3
0
0
0
0
—
—
—
—
—
—
—
—
3.5
4
5
* These parameters are sampled and are not 100% tested
Rev: 1.04a 10/2002
5/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Read Cycle 1: CE = OE = V , WE = V
IL
IH
tRC
Address
Data Out
tAA
tOH
Previous Data
Data valid
Read Cycle 2: WE = V
IH
tRC
Address
CE
tAA
tAC
tHZ
tLZ
OE
tOE
tOHZ
tOLZ
DATA VALID
Data Out
High impedance
Rev: 1.04a 10/2002
6/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Write Cycle
-7
-8
-10
-12
Parameter
Symbol
Unit
Min
7
Max
—
—
—
—
—
—
—
—
—
—
Min
8
Max
—
—
—
—
—
—
—
—
—
—
Min
10
7
Max
—
—
—
—
—
—
—
—
—
—
Min
12
8
Max
—
—
—
—
—
—
—
—
—
—
Write cycle time
Address valid to end of write
Chip enable to end of write
Data set up time
tWC
tAW
tCW
tDW
tDH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5.5
5.5
4
5
7
8
3
5
6
Data hold time
0
0
0
0
Write pulse width
tWP
tAS
5
5.5
0
7
8
Address set up time
0
0
0
Write recovery time (WE)
Write recovery time (CE)
Output Low Z from end of write
tWR
tWR1
0
0
0
0
0
0
0
0
*
3
3
3
3
tWLZ
*
Write to output in High Z
—
3
—
3.5
—
4
—
5
ns
tWHZ
* These parameters are sampled and are not 100% tested
Rev: 1.04a 10/2002
7/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Write Cycle 1: WE control
tWC
Address
tAW
tWR
OE
tCW
CE
tAS
tWP
WE
tDW
tDH
DATA VALID
Data In
Data Out
tWHZ
tWLZ
HIGH IMPEDANCE
Write Cycle 2: CE control
tWC
Address
tAW
tWR1
OE
CE
tAS
tCW
tWP
WE
tDW
tDH
DATA VALID
Data In
Data Out
HIGH IMPEDANCE
Rev: 1.04a 10/2002
8/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
32-Pin SOJ, 400 mil
Dimension in inch
Dimension in mm
Symbol
min
nom
—
max
min
—
nom
—
max
3.70
—
L
A
—
0.146
—
D
c
A1
0.026
—
0.66
2.67
—
A2
0.105 0.110 0.115
2.80
0.43
0.71
0.20
2.92
0.53
0.81
0.30
B
0.013 0.017 0.021 0.33
0.024 0.028 0.032 0.61
0.006 0.008 0.012 0.15
B1
1
c
e
A
D
0.820 0.824 0.829 20.83 20.93 21.06
0.395 0.400 0.405 10.04 10.16 10.28
E
e
—
0.05
—
—
1.27
—
B
B1
y
HE
0.430 0.435 0.440 10.93 11.05 11.17
Q
GE
0.354 0.366 0.378 9.00
9.30
—
9.60
—
Detail A
L
y
0.082
—
—
—
—
—
2.08
—
0.004
—
0.10
o
o
o
o
Q
—
0
10
0
10
Notes:
1. Dimension D& E do not include interlead flash.
2. Dimension B1 does not include dambar protrusion/intrusion.
3. Controlling dimension: inches
Rev: 1.04a 10/2002
9/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
32-Pin TSOP-II, 400mil
Dimension in inch
Dimension in mm
D
Symbol
c
32
min
nom
—
max
min
—
nom
—
max
1.27
0.15
1.14
0.45
0.16
A
0.039
0.002
0.037
0.012
0.05
0.006
0.045
0.018
A1
—
0.01
0.90
0.30
—
A
A2
0.040
0.016
1.02
0.40
0.13
b
c
0.0047 0.0051 0.0062 0.12
1
ZD
D
0.820
—
0.825
0.037
0.463
0.400
0.05
0.020
0.031
—
0.830 20.82 20.95 21.08
0.95
e
b
ZD
—
—
—
E
0.455
0.395
—
0.471 11.56 11.76 11.96
0.405 10.03 10.16 10.29
E1
y
e
—
—
1.27
0.50
0.80
—
—
L
L1
0.017
0.024
0.00
0.023
0.039
0.003
0.40
0.60
0.00
0.60
1.00
0.76
Q
y
Detail A
o
o
o
o
Q
—
—
0
5
0
5
Notes:
1.Dimension D includes mold flash, protrusions or gate burrs.
2. Dimension E does not include interlead flash
3. Controlling dimension: mm
Rev: 1.04a 10/2002
10/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
6 mm x 8 mm Fine Pitch BGA
8 . 0 0 ± 0 . 1 0
0.10
5 . 2 5
Rev: 1.04a 10/2002
11/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Ordering Information
*
Package
Access Time
Temp. Range
Status
Part Number
GS71108ATP-7
GS71108ATP-8
GS71108ATP-10
GS71108ATP-12
GS71108ATP-7I
GS71108ATP-8I
GS71108ATP-10I
GS71108ATP-12I
GS71108ASJ-7
GS71108ASJ-8
GS71108ASJ-10
GS71108ASJ-12
GS71108ASJ-7I
GS71108ASJ-8I
GS71108ASJ-10I
GS71108ASJ-12I
GS71108AJ-7
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
400 mil TSOP-II
300 mil SOJ
7 ns
8 ns
Commercial
Commercial
Commercial
Commercial
Industrial
10 ns
12 ns
7 ns
8 ns
Industrial
10 ns
12 ns
7 ns
Industrial
Industrial
Commercial
Commercial
Commercial
Commercial
Industrial
300 mil SOJ
8 ns
300 mil SOJ
10 ns
12 ns
7 ns
300 mil SOJ
300 mil SOJ
300 mil SOJ
8 ns
Industrial
300 mil SOJ
10 ns
12 ns
7 ns
Industrial
300 mil SOJ
Industrial
400 mil SOJ
Commercial
Commercial
Commercial
Commercial
Industrial
GS71108AJ-8
400 mil SOJ
8 ns
GS71108AJ-10
GS71108AJ-12
GS71108AJ-7I
GS71108AJ-8I
GS71108AJ-10I
GS71108AJ-12I
400 mil SOJ
10 ns
12 ns
7 ns
400 mil SOJ
400 mil SOJ
400 mil SOJ
8 ns
Industrial
400 mil SOJ
10 ns
12 ns
Industrial
400 mil SOJ
Industrial
Rev: 1.04a 10/2002
12/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
Ordering Information
*
Package
Access Time
Temp. Range
Status
Part Number
GS71108AU-7
GS71108AU-8
GS71108AU-10
GS71108AU-12
GS71108AU-7I
GS71108AU-8I
GS71108AU-10I
GS71108AU-12I
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
6 mm x 8 mm Fine Pitch BGA
7 ns
8 ns
Commercial
Commercial
Commercial
Commercial
Industrial
10 ns
12 ns
7 ns
8 ns
Industrial
10 ns
12 ns
Industrial
Industrial
*
Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example:
GS71108ATP-8T
Rev: 1.04a 10/2002
13/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS71108ATP/J/SJ/U
1Mb Asynchronous Datasheet Revision History
Rev. Code: Old;
New
Types of Changes
Format or Content
Page #/Revisions/Reason
• Creation of new datasheet
71108A_r1
• Added 6 ns speed bin to entire document
71108A_r1; 71108A_r1_01
Content
Content
• Updated all power numbers
• Changed 6 mm x 10 mm package designator from U to X
71108A_r1_01; 71108A _r1_02
• Updated Recommended Operating Conditions table on page 3
• Updated Power Supply Currents table
• Changed FPBGA package from 6 x 10 to 6 x 8 (package U)
71108A_r1_02; 71108A _r1_03
71108A_r1_03; 71108A _r1_04
Content
Content
• Removed 6 ns speed bin from entire document
• Added 7 ns speed bin to entire document
Rev: 1.04a 10/2002
14/14
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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