GVT71128E36B-9 [ETC]
x36 Fast Synchronous SRAM ; X36高速同步SRAM
| 型号： | GVT71128E36B-9 |
| 厂家： | 
ETC |
| 描述： | x36 Fast Synchronous SRAM
|
| 文件： | 总14页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GVT71128E36
128K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
SYNCHRONOUS
BURST SRAM
FLOW-THROUGH
128K x 36 SRAM
+3.3V CORE SUPPLY, +2.5V I/O SUPPLY
REGISTERED INPUTS, BURST COUNTER
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
Fast access times: 7.5, 8, 8.5, and 10ns
Fast clock speed: 117, 100, 90, and 50 MHz
Provide high performance 2-1-1-1 access rate
Fast OE# access times: 4.0ns
3.3V -5% and +10% core power supply
2.5V or 3.3V I/O supply
The Galvantech Synchronous Burst SRAM family
employs high-speed, low power CMOS designs using
advanced triple-layer polysilicon, double-layer metal
technology. Each memory cell consists of four transistors and
two high valued resistors.
The GVT71128E36 SRAM integrates 131,072x36
SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
chip enable (CE#), depth-expansion chip enables (CE2# and
CE2), burst control inputs (ADSC#, ADSP#, and ADV#),
write enables (BW1#, BW2#, BW3#, BW4#,and BWE#), and
global write (GW#).
Asynchronous inputs include the output enable (OE#),
burst mode control (MODE), and sleep mode control (ZZ).
The data outputs (Q), enabled by OE#, are also asynchronous.
Addresses and chip enables are registered with either
address status processor (ADSP#) or address status controller
(ADSC#) input pins. Subsequent burst addresses can be
internally generated as controlled by the burst advance pin
(ADV#).
5V tolerant inputs except I/O’s
Clamp diodes to VSSQ at all inputs and outputs
Common data inputs and data outputs
BYTE WRITE ENABLE and GLOBAL WRITE control
Three chip enables for depth expansion and address
pipeline
•
•
•
•
•
Address, data and control registers
Internally self-timed WRITE CYCLE
Burst control pins (interleaved or linear burst sequence)
Automatic power-down for portable applications
Low profile 119 lead, 14mm x 22mm BGA (Ball Grid
Array) and 100 pin TQFP packages
OPTIONS
•
MARKING
Timing
7.5ns access/8.5ns cycle
8ns access/10ns cycle
8.5ns access/11ns cycle
10ns access/20ns cycle
-7
-8
-9
-10
Address, data inputs, and write controls are registered on-
chip to initiate self-timed WRITE cycle. WRITE cycles can
be one to four bytes wide as controlled by the write control
inputs. Individual byte write allows individual byte to be
written. BW1# controls DQ1-DQ8 and DQP1. BW2# controls
DQ9-DQ16 and DQP2. BW3# controls DQ17-DQ24 and
DQP3. BW4# controls DQ25-DQ32 and DQP4. BW1#,
BW2# BW3#, and BW4# can be active only with BWE#
being LOW. GW# being LOW causes all bytes to be written.
The GVT71128E36 operates from a +3.3V core power
supply and all outputs operate on a +2.5V supply. All inputs
and outputs are JEDEC standard JESD8-5 compatible. The
•
Packages
119-lead BGA
100-pin TQFP
B
T
TM
device is ideally suited for 486, Pentium , 680x0, and
TM
PowerPC systems and for systems that are benefited from a
wide synchronous data bus.
Pentium is a trademark of Intel Corporation.
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688 Fax (408) 566-0699
Rev. 5/98
PowerPC is a trademark of IBM Corporation.
Galvantech, Inc. reserves the right to change
products or specifications without notice.
GVT71128E36
128K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
FUNCTIONAL BLOCK DIAGRAM
BYTE 1 WRITE
BW1#
BWE#
D
Q
CLK
BYTE 2 WRITE
BW2#
D
Q
GW#
BYTE 3 WRITE
BW3#
D
Q
BYTE 4 WRITE
BW4#
D
Q
ENABLE
CE#
CE2
D
Q
CE2#
ZZ
Power Down Logic
OE#
ADSP#
Input
Register
A16-A2
Address
Register
ADSC#
DQ1-DQ32,
DQP1, DQP2
DQP3, DQP4
CLR
ADV#
A1-A0
MODE
Binary
Counter
& Logic
NOTE: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing
diagrams for detailed information.
May 29, 1998
2
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
GVT71128E36
128K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
PIN ASSIGNMENT (Top View)
1
2
3
4
5
6
7
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VCCQ
NC
ADSP#
ADSC#
VCC
A16
CE2#
A15
VCCQ
NC
A
B
C
D
E
F
A6
A4
A3
A8
A9
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQP3
DQ17
DQ18
VCCQ
VSSQ
DQ19
DQ20
DQ21
DQ22
VSSQ
VCCQ
DQ23
DQ24
NC
DQP2
DQ16
DQ15
VCCQ
VSSQ
DQ14
DQ13
DQ12
DQ11
VSSQ
VCCQ
DQ10
DQ9
2
CE2
3
4
NC
A12
VSS
VSS
VSS
BW2#
VSS
NC
NC
A7
A2
5
6
DQ17
DQ18
VCCQ
DQ21
DQ23
VCCQ
DQ25
DQ26
VCCQ
DQ30
DQ32
NC
DQP3
DQ19
DQ20
DQ22
DQ24
VCC
VSS
VSS
VSS
BW3#
VSS
NC
NC
DQP2
DQ14
DQ13
DQ12
DQ10
VCC
DQ7
DQ5
DQ4
DQ3
DQP1
A13
DQ16
DQ15
VCCQ
DQ11
DQ9
7
CE#
8
9
OE#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
ADV#
G
H
J
GW#
VCC
CLK
VSS
NC
P
100-pin TQFP
VCCQ
DQ8
VCC
NC
VSS
VCC
ZZ
DQ8
DQ7
VCCQ
VSSQ
DQ6
DQ5
DQ4
DQ27
DQ28
DQ29
DQ31
DQP4
VSS
BW4#
VSS
VSS
VSS
MODE
A10
VSS
BW1#
VSS
VSS
VSS
NC
K
L
M
N
P
DQ25
DQ26
VCCQ
VSSQ
DQ27
DQ28
DQ29
DQ30
VSSQ
VCCQ
DQ31
DQ32
DQP4
NC
DQ6
BWE#
VCCQ
DQ2
A1
A0
VCC
A11
NC
DQ1
DQ3
NC
R
T
U
A5
NC
NC
VSSQ
VCCQ
DQ2
DQ1
DQP1
NC
A14
NC
NC
ZZ
VCCQ
NC
NC
VCCQ
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
TOP VIEW 119 LEAD BGA
PIN DESCRIPTIONS
SYMBOL
BGA PINS
QFP PINS
TYPE
DESCRIPTION
4P, 4N, 2A, 3A, 5A, 37, 36, 35, 34, 33,
6A, 3B, 5B, 2C, 3C, 32, 100, 99, 82,
5C, 6C, 2R, 6R, 3T, 81, 44, 45, 46, 47,
A0-A16
Input-
Synchronous
Addresses: These inputs are registered and must meet the setup and hold
times around the rising edge of CLK. The burst counter generates internal
addresses associated with A0 and A1, during burst cycle and wait cycle.
4T, 5T
48, 49,50
5L, 5G, 3G, 3L
93,94,95,96
BW1#,
BW2#,
BW3#,
BW4#
Input-
Synchronous
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ
cycle. BW1# controls DQ1-DQ8 and DQP1. BW2# controls DQ9-DQ16 and
DQP2. BW3# controls DQ17-DQ24 and DQP3. BW4# controls DQ25-DQ32
and DQP4. Data I/O are high impedance if either of these inputs are LOW,
conditioned by BWE# being LOW.
4M
4H
87
88
BWE#
GW#
Input-
Write Enable: This active LOW input gates byte write operations and must
meet the setup and hold times around the rising edge of CLK.
Synchronous
Input-
Synchronous
Global Write: This active LOW input allows a full 36-bit WRITE to occur
independent of the BWE# and BWn# lines and must meet the setup and hold
times around the rising edge of CLK.
4K
89
CLK
Input-
Synchronous
Clock: This signal registers the addresses, data, chip enables, write control
and burst control inputs on its rising edge. All synchronous inputs must meet
setup and hold times around the clock’s rising edge.
4E
6B
98
92
CE#
Input-
Synchronous ADSP#.
Chip Enable: This active LOW input is used to enable the device and to gate
CE2#
Input-
Chip Enable: This active LOW input is used to enable the device.
Synchronous
May 29, 1998
3
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
GVT71128E36
128K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
PIN DESCRIPTIONS (continued)
BGA PINS
QFP PINS
SYMBOL
TYPE
DESCRIPTION
2B
97
CE2
input-
Chip enable: This active HIGH input is used to enable the device.
Synchronous
4F
86
83
OE#
Input
Output Enable: This active LOW asynchronous input enables the data
output drivers.
4G
ADV#
Input-
Address Advance: This active LOW input is used to control the internal
Synchronous burst counter. A HIGH on this pin generates wait cycle (no address
advance).
4A
4B
3R
7T
84
85
31
64
ADSP#
ADSC#
MODE
ZZ
Input-
Address Status Processor: This active LOW input, along with CE# being
Synchronous LOW, causes a new external address to be registered and a READ cycle
is initiated using the new address.
Input-
Address Status Controller: This active LOW input causes device to be
Synchronous de-selected or selected along with new external address to be registered.
A READ or WRITE cycle is initiated depending upon write control inputs.
Input-
Static
Mode: This input selects the burst sequence. A LOW on this pin selects
LINEAR BURST. A NC or HIGH on this pin selects INTERLEAVED
BURST.
Input-
Snooze: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input has to be
either LOW or NC (No Connect).
7P, 7N, 6N, 6M, 6L, 7L, 6K,
7K, 7H, 6H, 7G, 6G, 6F, 6E,
7E, 7D, 1D, 1E, 2E, 2F, 1G,
2G, 1H, 2H, 1K, 1L, 2K, 2L,
2M, 1N, 2N, 1P
52, 53, 56, 57, 58, DQ1-DQ32
59, 62, 63, 68, 69,
72-75, 78, 79, 2, 3,
6-9, 12, 13, 18, 19,
22-25, 28, 29
Input/
Output
Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is DQ9-DQ16.
Third Byte is DQ17-DQ24. Fourth Byte is DQ25-DQ32. Input data must
meet setup and hold times around the rising edge of CLK.
6P, 6D, 2D, 2P
51, 80, 1, 30
DQP1 -
DQP4
Input/
Output
Parity Inputs/Outputs: DQP1 is parity bit for DQ1-DQ8 and DQP2 is
parity bit for DQ9-DQ16. DQP3 is parity bit for DQ17-DQ24 and DQP4 is
parity bit for DQ25-DQ32.
4C, 2J, 4J, 6J, 4R
15, 41,65, 91
17, 40, 67, 90
VCC
VSS
Supply
Core power Supply: +3.3V -5% and +10%
3D, 5D, 3E, 5E, 3F, 5F,
5G, 3H, 5H, 3K, 5K, 3L,
3M, 5M, 3N, 5N, 3P, 5P
Ground Ground: GND.
1A, 7A, 1F, 7F, 1J, 7J,
1M, 7M, 1U, 7U
4, 11, 20, 27, 54,
61, 70, 77
VCCQ
VSSQ
NC
I/O Supply Output Buffer Supply: +2.5V (from 2.375V to VCC)
I/O Ground Output Buffer Ground: GND
5, 10, 21, 26, 55,
60, 71, 76
1B, 7B, 1C, 7C, 4D, 3J, 5J,
4L, 1R, 5R, 7R, 1T, 2T, 6T,
2U, 3U, 4U, 5U, 6U
14, 16, 38, 39, 42,
43, 66
-
No Connect: These signals are not internally connected.
BURST ADDRESS TABLE (MODE = NC/VCCQ)
First Address
(external)
Second Address
(internal)
Third Address
(internal)
Fourth Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
BURST ADDRESS TABLE (MODE = GND)
First Address
(external)
Second Address
(internal)
Third Address
(internal)
Fourth Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
May 29, 1998
4
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
GVT71128E36
128K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
TRUTH TABLE
ADDRESS
USED
OPERATION
CE#
CE2#
CE2
ADSP# ADSC#
ADV#
WRITE#
OE#
CLK
DQ
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
READ Cycle, Begin Burst
None
H
L
X
X
H
X
H
L
X
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
X
X
X
X
X
L
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
High-Z
High-Z
High-Z
High-Z
High-Z
Q
None
None
L
X
L
L
None
L
H
H
L
None
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
External
External
External
External
External
Next
L
X
X
L
READ Cycle, Begin Burst
L
L
L
H
X
L
High-Z
D
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
H
H
H
H
H
H
L
Q
READ Cycle, Begin Burst
L
L
L
H
L
High-Z
Q
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
High-Z
Q
Next
L
Next
L
H
X
X
L
High-Z
D
Next
L
Next
L
L
D
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
Q
H
L
High-Z
Q
H
X
X
High-Z
D
L
D
Note:
1.
X means “don’t care.” H means logic HIGH. L means logic LOW. WRITE# = L means [BWE# +
BW1#*BW2#*BW3#*BW4#]*GW# equals LOW. WRITE# = H means [BWE# + BW1#*BW2#*BW3#*BW4#]*GW# equals
HIGH.
2. BW1# enables write to DQ1-DQ8 and DQP1. BW2# enables write to DQ9-DQ16 and DQP2. BW3# enables write to DQ17-
DQ24 and DQP3. BW4# enables write to DQ25-DQ32 and DQP4.
3. All inputs except OE# must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
4. Suspending burst generates wait cycle.
5. For a write operation following a read operation, OE# must be HIGH before the input data required setup time plus High-Z time
for OE# and staying HIGH throughout the input data hold time.
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
7. ADSP# LOW along with chip being selected always initiates an READ cycle at the L-H edge of CLK. A WRITE cycle can be
performed by setting WRITE# LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for
clarification.
PARTIAL TRUTH TABLE FOR READ/WRITE
FUNCTION
GW#
BWE#
BW1#
BW2#
BW3#
BW4#
READ
H
H
H
H
L
H
L
L
L
X
X
H
L
X
H
H
L
X
H
H
L
X
H
H
L
READ
WRITE one byte
WRITE all bytes
WRITE all bytes
L
X
X
X
X
May 29, 1998
5
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
GVT71128E36
128K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS......-0.5V to +4.6V
V
.........................................................-0.5V to VCC+0.5V
IN
o
o
Storage Temperature (plastic) .......................-55 C to +125
Junction Temperature ...................................................+125
Power Dissipation ..........................................................1.6W
Short Circuit Output Current (per I/O).........................20mA
o
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
o
(0 C £ T £ 70°C; VCC = 3.3V -5% and +10% unless otherwise noted)
a
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage Data Inputs (DQxx)
All Other Inputs
VIHD
VIH
1.7
1.7
-0.3
-2
VCC+0.3
V
V
1,2
1,2
1, 2
14
4.6
0.7
2
Input Low (Logic 0) Voltage
VIl
V
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
0V < VIN < VCC
ILI
uA
uA
V
Output(s) disabled, 0V < VOUT < VCC
IOH = -2.0mA
ILO
-2
2
VOH
VOL
VCC
VCCQ
1.7
1, 11
1, 11
1
IOL = 2.0mA
0.7
3.6
V
3.135
2.375
V
I/O Supply Voltage
VCC
V
1
DESCRIPTION
CONDITIONS
SYM
TYP
-7
-8
-9
-10 UNITS NOTES
Power Supply
Current: Operating
Device selected; all inputs < VILor >
VIH;cycle time > tKC MIN; VCC =MAX;
outputs open
Icc
150
370
320
290
200
mA
mA
mA
mA
3, 12, 13
CMOS Standby
TTL Standby
Device deselected; VCC = MAX;
all inputs < VSS +0.2 or >VCC -0.2;
all inputs static; CLK frequency = 0
ISB2
ISB3
ISB4
5
10
20
80
10
10
20
60
10
12,13
Device deselected; all inputs < VIL
or > VIH; all inputs static;
VCC = MAX; CLK frequency = 0
10
40
20
20
12,13
Clock Running
Device deselected;
70
40
12,13
all inputs < VIL or > VIH; VCC = MAX;
CLK cycle time > tKC MIN
May 29, 1998
6
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
GVT71128E36
128K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
AC ELECTRICAL CHARACTERISTICS
o
o
(Note 5) (0 C £ T £ 70 C; VCC = 3.3V -5% and +10%)
A
- 7
- 8
- 9
- 10
DESCRIPTION
SYM
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNITS NOTES
Clock
Clock cycle time
tKC
tKH
tKL
8.5
3
10
4
11
4.5
4.5
20
4.5
4.5
ns
ns
ns
Clock HIGH time
Clock LOW time
3
4
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE to output valid
OE to output in Low-Z
OE to output in High-Z
Setup Times
tKQ
tKQX
7.5
8
8.5
10
ns
ns
2
0
2
2
0
2
2
0
2
2
0
2
tKQLZ
tKQHZ
tOEQ
tOELZ
tOEHZ
ns
ns
ns
ns
ns
4, 6,7
4, 6,7
9
3.5
4.0
3.5
4.0
3.5
4.0
3.5
4.0
0
0
0
0
4, 6,7
4, 6,7
3.5
3.5
3.5
3.5
Address, Controls and Data In
Hold Times
tS
tH
1.5
0.5
2.0
0.5
2.0
0.5
2.0
0.5
ns
ns
10
10
Address, Controls and Data In
CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
MAX
UNITS
NOTES
Input Capacitance
TA = 25oC; f = 1 MHz
VCC = 3.3V
CI
4
7
5
8
pF
pF
4
4
Input/Output Capacitance (DQ)
CO
THERMAL CONSIDERATION
DESCRIPTION
CONDITIONS
SYMBOL TQFP TYP UNITS
NOTES
Thermal Resistance - Junction to Ambient
Thermal Resistance - Junction to Case
Still air, soldered on 4.25 x
1.125 inch 4-layer PCB
QJA
QJC
25
9
oC/W
oC/W
TYPICAL OUTPUT BUFFER CHARACTERISTICS
OUTPUT HIGH
VOLTAGE
OUTPUT LOW
VOLTAGE
PULL-UP CURRENT
PULL-DOWN CURRENT
VOH (V)
-0.5
0
IOH(mA) Min IOH(mA) Max
VOL (V)
-0.5
0
IOL(mA) Min IOL(mA) Max
-38
-38
-38
-26
-20
0
-105
-105
-105
-83
-70
-30
-10
0
0
0
0
0
0.8
0.4
10
20
31
40
40
40
40
20
40
63
80
80
80
80
1.25
1.5
0.8
1.25
1.6
2.3
2.7
0
2.8
2.9
0
3.2
3.4
0
0
3.4
May 29, 1998
7
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
GVT71128E36
128K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
OUTPUT LOADS
AC TEST CONDITIONS
Input pulse levels
0V to 2.5V
DQ
Input slew rate
1.0V/ns
1.8ns
Z0 = 50W
50W
Vt = 1.25V
Output rise and fall times(max)
Input timing reference levels
Output reference levels
Output load
1.25V
1.25V
Fig. 1 OUTPUT LOAD EQUIVALENT
See Figures 1
15. Capacitance derating applies to capacitance different from the
load capacitance shown in Fig. 1.
NOTES
1. All voltages referenced to VSS (GND).
t
2. Overshoot:
Undershoot:
V
V
£ +6.0V for t £ KC /2.
IH
IL
t
£ -2.0V for t £ KC /2
3.
I is given with no output current. I increases with greater
cc cc
output loading and faster cycle times.
4. This parameter is sampled.
5. Test conditions as specified with the output loading as shown in
Fig. 1 unless otherwise noted.
6. Measured at + 200mV from steady state.
t
7. At any given temperature and voltage condition, KQHZ is less
t
t
t
than KQLZ and OEHZ is less than OELZ.
8. A READ cycle is defined by byte write enables all HIGH or
ADSP# LOW along with chip enables being active for the
required setup and hold times. A WRITE cycle is defined by at
one byte or all byte WRITE per READ/WRITE TRUTH
TABLE.
9. OE# is a “don’t care” when a byte write enable is sampled LOW.
10. This is a synchronous device. All synchronous inputs must meet
specified setup and hold time, except for “don’t care” as defined
in the truth table.
11. AC I/O curves are available upon request.
12. “Device Deselected” means the device is in POWER -DOWN
mode as defined in the truth table. “Device Selected” means the
device is active.
o
13. Typical values are measured at 3.3V, 25 C and 20ns cycle time.
14. MODE pin has an internal pull-up and ZZ pin has an internal
pull-down. These two pins exhibit an input leakage current of
+30 mA.
May 29, 1998
8
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
GVT71128E36
128K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
READ TIMING
t
KC
t
KL
CLK
t
t
S
KH
ADSP#
t
H
ADSC#
t
S
ADDRESS
A1
A2
t
H
BW1#, BW2#,
BW3#, BW4#,
BWE#, GW#
CE#
(See Note)
t
S
ADV#
OE#
DQ
t
H
t
t
t
KQ
KQ
OEQ
t
t
KQLZ
OELZ
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
Q(A2+2)
SINGLE READ
BURST READ
Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active.
May 29, 1998
9
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
GVT71128E36
128K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
WRITE TIMING
CLK
t
S
ADSP#
t
H
ADSC#
t
S
ADDRESS
A1
A2
A3
tH
BW1#, BW2#,
BW3#, BW4#,
BWE#
GW#
CE#
(See Note)
t
S
ADV#
OE#
DQ
t
H
t
OEHZ
t
KQX
Q
D(A1)
D(A2)
D(A2+2)
D(A2+2)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
SINGLE WRITE
BURST WRITE
BURST WRITE
Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active.
May 29, 1998
10
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
GVT71128E36
128K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
READ/WRITE TIMING
CLK
t
S
ADSP#
t
H
ADSC#
t
S
ADDRESS
A2
A3
A4
A5
A1
t
H
BW1#, BW2#,
BW3#, BW4#,
BWE#, GW#
CE#
(See Note)
ADV#
OE#
DQ
Q(A1)
Q(A2)
D(A3)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
D(A5)
D(A5+1)
Single Reads
Single Write
Burst Read
Burst Write
Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active.
May 29, 1998
11
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
GVT71128E36
128K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
100 Pin TQFP Package Dimensions
16.00 + 0.10
14.00 + 0.10
# 1
1.40 + 0.05
1.60 Max
0.65 Basic
0.30 + 0.08
0.60 + 0.15
Note: All dimensions in Millimeters
May 29, 1998
12
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
GVT71128E36
128K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
7 x 17 (119-lead) BGA Dimensions
22.00 + 0.20
20.32
1.27
7
6
5
4
3
2
1
U T R P N M L K J H G F E D C B A
BOTTOM VIEW
o0.75+0.15 (119X)
19.50 + 0.10
PIN 1A CORNER
30 TYP.
TOP VIEW
0.56 REF.
0.60 + 0.10
SIDE VIEW
13
Note: All dimensions in Millimeters
May 29, 1998
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
GVT71128E36
128K X 36 SYNCHRONOUS BURST SRAM
GALVANTECH, INC.
Ordering Information
GVT 71128E36 X - XX
Galvantech Prefix
Part Number
Speed (7 = 7.5ns access/8.5ns cycle
8 = 8.0ns access/10ns cycle
9 = 8.5ns access/11ns cycle
10 = 10ns access/20ns cycle)
Package (B = 119 LEAD BGA,
T = 100 PIN TQFP)
May 29, 1998
14
Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 5/98
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