HB28B064A8HSR_技术文档

Section 1 Flash Memory Cards

1.1

Introduction

As a flash memory card has no internal drive mechanism, it has the advantages of relatively low

power consumption and greater tolerance of vibration when used in portable products in

comparison with devices using hard disks or similar drive systems. This makes it an ideal storage

medium for the age of mobile computing, in which machines are no longer confined to the desk

top or the office. The flash memory card—or rather, various kinds of memory cards—first came to

the attention of the market at virtually the same time as the advent of the early notebook personal

computers.

Notebook PCs, with smaller memory and hard disk capacities than desktop machines, had to

include provisions for the addition of memory and large-capacity auxiliary storage devices. These

expansion slots later evolved into general-purpose slots that could accept fax/modem, LAN, and

other kinds of cards, as well as flash memory cards. This marked the beginning of the PC card, as

it is known in the market, and the electrical specifications, protocol, and mechanical form were

established and standardized by PCMCIA*¹(Personal Computer Memory Card International

Association) and JEIDA*²(Japan Electric Industrial Development Association). The ability to

incorporate the various functions mentioned above in a business-card-sized PC card is the result of

remarkable advances in mounting technology and component miniaturization.

Similar advances were simultaneously being made in digital information devices of all kinds, and

products began to appear of such small size as to make even the incorporation of a business-card-

sized PC card difficult. Digital cameras and WindowsCE*³based handheld PCs are notable

examples of such products.

Against this backdrop, SanDisk Corporation of the USA proposed a new flash memory card

standard—CompactFlash™*⁴. This new standard has two special features: first , a postage-stamp

size of 42.8 mm (H) × 36.4 mm (W) × 3.3 mm (T), giving a cubic capacity approaching 1/4 that of

the PC card, and second, the use of the existing PC-ATA*⁵and True-IDE*⁶interface standards,

providing a high degree of compatibility with notebook PCs and similar systems currently on the

market. This compatibility allows system designers to use existing chip sets*⁷and know-how

when designing new products using CompactFlash™, while the compact size offers a greater

degree of freedom in terms of product design.

Note: * See Appendix C, Glossary.

1

Hitachi has released both cards compatible with the PCMCIA standard and cards compatible with

the CompactFlash™ standard, using Hitachi flash memory. In the following descriptions, “CF” is

used to refer to CompactFlash™, and “PC-ATA cards” to refer to cards compatible with the

PCMCIA standard.

This user’s manual describes CF and PC-ATA card specifications and the use of these cards.

HITACHI

PC-ATA

Card

HITACHI

COMPACT

FLASH

Figure 1.1 PC-ATA Card and CompactFlash™ Outlines

2

1.2

PCMCIA (JEIDA) and CFA

1.2.1

PCMCIA (Personal Computer Memory Card International Association)

The PCMCIA (Personal Computer Memory Card International Association) is the body that

decides the physical and electrical specifications of PC cards.

A PC card is about the size of a business card, and uses a 68-pin two-piece connector. Moves to

establish PC card standards date back to 1985 when JEIDA (Japan Electric Industrial

Development Association) began drawing up standards for SRAM and other memory cards*⁸. The

PCMCIA was established in 1989, with the participation of American personal computer

manufacturers, including IBM and Apple. Since that time, the PCMCIA and JEIDA have worked

jointly toward standardization. The world’s first standard was PCMCIA 1.0/JEIDA 4.0, but this

included areas lacking full compatibility. Also, since this standard was intended for memory cards,

it could not be used for driving fax/modem and other I/O cards. This problem was solved with the

creation of PCMCIA 2.0/JEIDA 4.2 in 1991, when the standard term “PC card” was adopted. At

the present time, various kinds of cards are available, including SCSI, fax/modem, LAN, ISDN,

HDD, and flash memory types.

A major advantage of PC cards is that, as long as a PC card slot is available, the card is basically

independent of the type of machine. In other words, any PC card should work in any type of

machine. In practice, however, this is not necessarily the case, owing to differences in PC card

controllers and driver software.

Further information on PCMCIA standards is available from:

Personal Computer Memory Card International Association

2635 North First Street, Suite 209

San Jose, CA 95134, USA

Note: * See Appendix C, Glossary.

3

1.2.2

CFA (CompactFlash™ Association)

The CFA (CompactFlash™ Association) is a body established for the promotion of the new

CompactFlash™ flash card standard proposed by SanDisk Corporation of the USA. CF is a

trademark of SanDisk Corporation, and is licensed to the CFA. A CF card is of postage-stamp

size, with an area of about 1/3 (and a cubic capacity of close to 1/4) that of a PC card, and also

uses a smaller 50-pin two-piece connector. Electrically, it conforms to PCMCIA PC-ATA

specifications and True-IDE specifications, offering an interface with an extremely high degree of

compatibility that includes existing specifications.

Further information on the CFA is available from:

CompactFlash™ Association

PO Box 51537

Palo Alto, CA 94303

http:www.compactflash.org

4

1.2.3

PC-ATA and True-IDE Specifications

PC-ATA specifications and True-IDE specifications are both standards for handling flash cards

and HDDs. Originally, these specifications all began with the IDE specifications*¹⁰which were

devised as a means of directly connecting an HDD to the PC-AT bus*¹¹(generally known as the

ISA bus) used in the IBM-PC*¹².

The IDE standard, proposed by Western Digital Corporation and Compaq Corporation of the

USA, came into widespread use because of the simplicity of its interface, but there was not always

full compatibility between different companies’ products. ANSI (American National Standards

Institute*¹⁶) therefore drew up detailed standards based on the IDE specifications, covering

virtually all areas from the shape of the connector to the software interface, with the aim of

eliminating the problem of compatibility. These together comprise the ATA standard*¹³. The ATA

standard is reviewed on an ad hoc basis to keep pace with advances in the PC field. The general

enhanced IDE*¹⁴standard is currently designated ATA3. In general, an HDD described as IDE-

compatible conforms to these ATA specifications. The PC-ATA specifications, for handling

memory cards and HDDs, are the result of transporting the ATA standard into the PC card field.

While the PC card standards offer an extremely high degree of general applicability in their

support for cards of all kinds, including SCSI and LAN cards, tasks such as initialization and

acquisition of card attributes have to be carried out by the host. Assuming that, for embedded

applications, only a flash card can be used from the start, these PC card limitations (initialization

and acquisition of card attributes) impose an extremely heavy burden on the system. It would

therefore be useful to have a standard whereby a flash card behaves like an HDD as soon as the

power is turned on. This demand is met by the True-IDE standard. The True-IDE standard thus

falls outside the category of PC card standards. Consequently, although a flash card contains flash

memory, its interface is the same as that for HDD control. To put it another way, a flash card

cannot be controlled by treating it as flash memory.

Note: * See Appendix C, Glossary.

5

HDD interface standard from the early days

of PC-AT compatible machines, proposed

by Western Digital Corporation and

Compaq Corporation of the USA

IDE

Detailed standardization by ANSI, based

on IDE standard

ATA

Standard incorporated

for PC card use

Derivatives

ATA

specifications

ATA

Fast-ATA

PCMCIA

Enhanced-IDE

Extended for CD-ROM use

ATAPI

Figure 1.2 Evolution of ATA Standard

6

Section 2 Flash Memory Card Specifications

2.1

PC-ATA Card Specifications

Basic Specifications: Conformity to PC card specifications

•

Interface

Conformity to PCMCIA PC-ATA specifications

•

External dimensions

Conformity to PCMCIA specifications Type II (54.0 mm × 85.6 mm × 5.0 mm)

5.0 (max)

54.00±0.10

85.60±0.20

10.0 min

3.3±0.1

34 pin

Upper side

1 pin

1.27±0.1

35 pin

68 pin

Lower side

1.27±0.1

41.91

(Reference value)

Unit: mm

Figure 2.1 PC-ATA Specification External Dimensions

7

•

Performance (representative example: HB286075A1)

Transfer speed: 8-Mbyte/second burst

Write speed:

250 kbytes/second

Guaranteed rewrites (per logical sector): 100,000

(for rewriting of a DOS file of about 500 kB)

Error rate:

Max. 10^–14bits

Electrical characteristics, etc. (representative example: HB286075A1)

Power supply voltage:

Sleep/standby current:

3.3 V ±5%/5 V ±10%

2 mA/3 mA max.

Sector read/write current: 75 mA/100 mA max.

Operating temperature:

Storage temperature:

0 to +60°C

–20 to +65°C

8

•

Pin assignment table

Table 2.1 PC Card Specification Pin Assignments

Mode

PCMCIA ATA

Pin No.

1

Memory Card

I/O Card

GND

D3

Pin No.

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

Memory Card

I/O Card

GND

D3

GND

CD1

D11

D12

D13

D14

D15

CE2

VS1

RFU

—

GND

CD1

D11

D12

D13

D14

D15

CE2

VS1

IORD

IOWR

—

2

3

D4

4

D5

5

D6

6

D7

7

CE1

A10

OE

—

CE1

A10

OE

—

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

A9

A8

—

WE

RDY/BUSY

V_CC

—

WE

IREQ

V_CC

—

V_CC

—

V_CC

—

A7

—

A6

VS2

RESET

WAIT

RFU

REG

BVD2

BVD1

D8

VS2

RESET

WAIT

INPACK

REG

SPKR

STSCHG

D8

A5

A4

A3

A2

A1

A0

D0

D1

D9

D2

D10

CD2

GND

D10

CD2

GND

WP

GND

IOIS16

GND

9

2.2

CompactFlash™ Specifications

Basic Specifications: Conformity to CompactFlash™ specifications

•

Interface

Conformity to PCMCIA PC-ATA specifications

Support for memory mode and I/O mode

* Can be mounted in a PC card slot, using an adapter.

Conformity to True-IDE (True-Integrated Device Electronics) specifications

•

External dimensions

Conformity to CompactFlash™ specifications (42.8 mm × 36.4 mm × 3.3 mm)

Unit: mm

26 pin

1 pin

Upper side

Lower side

50 pin

1.60±0.05

3.30±0.10

1.00±0.05

1.27

25 pin

1.27

1.00±0.08

42.80±0.10

3.30±0.10

12.00±0.10

2.40±0.08

3.00±0.08

0.80±0.08

0.60±0.08

41.66±0.13

Figure 2.2 CompactFlash™ External Dimensions

10

•

Performance (representative example: HB286015C2)

Transfer speed: 8 Mbytes/second

Write speed:

400 kbytes/second (8 MB: 250 kbytes/second)

Guaranteed rewrites (per logical sector): 100,000

(for rewriting of a DOS file of about 500 kB)

Error rate:

Max. 10^-14bits

Electrical characteristics, etc. (representative example: HB286015C2)

Power supply voltage:

Sleep/standby current:

3.3 V ±5%/5 V ±10%

0.6 mA/1.0 mA max.

Sector read/write current: 75 mA/100 mA max.

Operating temperature:

Storage temperature:

0 to +60°C

–20 to +65°C

11

•

Pin assignment table

Table 2.2 CompactFlash™ Pin Assignments

Mode

PCMCIA ATA

Memory

Mode

PCMCIA ATA

Memory

Pin No. Card

I/O Card

GND

D3

True-IDE

GND

D3

I/O Card

CD1

D11

True-IDE

CD1

1

GND

D3

D4

D5

D6

D7

CE1

A10

OE

A9

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

CD1

D11

D12

D13

D14

D15

CE2

VS1

IORD

IOWR

WE

2

D11

3

D4

D12

4

D5

D13

5

D6

D14

6

D7

D15

7

CE1

A10

OE

A9

CE1

A10

ATASEL

A9

CE2

8

VS1

9

IORD

IOWR

WE

IORD

IOWR

WE

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

A8

A7

RDY/BUSY IREQ

INTRQ

V_CC

A6

V_CC

A6

V_CC

A6

—

CSEL

VS2

A5

VS2

RESET

WAIT

—

VS2

A4

RESET

WAIT

INPACK

REG

SPKR

RESET

IORDY

INPACK

REG

A3

A2

A1

REG

BVD2

BVD1

D8

A0

DASP

D0

D1

D2

WP

CD2

D0

STSCHG PDIAG

D1

D8

D2

D9

IOIS16

CD2

IOIS16

CD2

D10

GND

D10

GND

D10

GND

12

Section 3 Functions in Each Flash Card Operating Mode

3.1

Introduction

Hitachi flash cards—both PC-ATA cards and CF—conform to PCMCIA PC-ATA specifications.

The PC-ATA specifications are one set of specifications within the PCMCIA standard, comprising

specifications for handling SRAM cards and flash memory cards in the same way as hard disk

drives. This means that, as with hard disks in general, all read/write instructions, etc., are issued as

commands via a register, and the card decodes the instructions and executes the corresponding

operations. A flash card can therefore be thought of as a miniature hard disk drive rather than as

ordinary memory.

When using a flash card...

Flash card

H

ITA

C

om

pact

H

I

F

lash

MPU

50H 50H 1FH 2AH

All read/write instructions are executed by setting the necessary data in registers

within the card.

A flash card is just like a hard disk drive in which flash memory is used instead

of a magnetic disk.

Figure 3.1 Conceptual Diagram of Flash Card Interface

One disadvantage of flash cards, therefore, may be that, unlike ordinary memory, they cannot be

driven by simple interface circuitry and driver software. However, chip sets supporting PC cards

for use in notebook PCs which are already available on the market can be used, and the advantage

of being able to use a card of a different capacity in the future simply by switching cards, with no

need to change the peripheral circuitry, far outweighs this disadvantage. This section covers the

minimum information required when using a card (acquisition of card attribute information, and

access to control registers).

13

When using EP/EEPROM memory...

MPU

Address

Flash

Control

memory

3 or 4 signals:

CS, WE, OE, PGM

Data

Small-scale/specific use, etc.

Systems in which states do not change greatly and

only a few variables have to be stored

Advantage

Data can be written and read simply by setting

the address and controlling the control pins.

Disadvantage

If the capacity or manufacturer is changed, the

peripheral circuitry must be redesigned.

When using a flash card...

Intermediary chip set

may also be used

Intel 82365

compatible product

Flash card

Control

Address

Control

MPU

logic

Flash

memory

Many signals:

CS, WE, OE, IORD,

IOWR, REG, etc.

Registers

Work memory

(Min. 512 bytes)

Data

Sector reads

Large-scale/general use

Systems in which many system state variables have

to be stored and managed

Advantages

Disadvantage

The same interface circuit can be used even if the memory

capacity is changed.

Large-capacity memory can be installed comparatively easily,

and memory capacity can be selected in a scalable fashion.

System configuration

and control programs

are complex.

Figure 3.2 Differences in System Size and Features with Use of a Card and Memory

14

3.2

Card Register Configuration

Flash memory card data is accessed via registers, as in the case of hard disk drives, etc. The actual

operations can be itemized as read/write operations, mode setting, card attribute acquisition, and

so on. Broadly speaking, PC-ATA cards and CF can operate in accordance with (1) PC-ATA

specifications or (2) True-IDE specifications. This section and sections 3.3 and 3.4 are concerned

with the PC-ATA specifications. For use of a PC-ATA card or CF in PC-ATA mode, continue

reading from here. If the card is to be handled in accordance with the True-IDE specifications,

skip forward to section 3.5.

(Switching between PC-ATA mode and the True-IDE specifications depends on how the flash

card input pins are set at power-on. Once the card has been started up in a particular mode, it

cannot be switched unless the power is turned on again. This problem is discussed in section 4.)

When the card is handled in accordance with the True-IDE specifications, the control registers can

be broadly divided into two regions. One is the attribute region, used to set and manage the

operating mode and store the card attributes, and the other is the task file region, used for data

write and read instructions.

Attribute Region: The attribute region consists of a configuration register section for setting and

managing the operation status of the card, and a CIS section for storing card attribute information,

located in the address spaces shown below. The configuration register section is further subdivided

into four registers.

The register names are shown below.

•

Register names

Configuration register section (configuration registers: 200h–206h)

•

Configuration option register (address 200h in attribute memory)

Configuration and status register (address 202h in attribute memory)

Pin replacement register (address 204h in attribute memory)

Socket and copy register (address 206h in attribute memory)

CIS section (card information structure: 000h–168h in attribute memory)

Note: The minimum register requirements are described in section 4. For details, see the

appendices.

When a card is mounted in a system by insertion in a PC card slot, it is first necessary to determine

what the inserted card is. Then settings appropriate to the card must be made.

First, the CIS section must be accessed to find out what kind of card has been inserted. The CIS

section contains essential information concerning the card, such as the settings that should be

made, the operating voltage, and the addresses at which the registers that perform card

15

management and control (the configuration registers) are located. Note that the CIS section is a

ROM area in which only read access is possible, and which cannot be written to by the host.

Next, it is necessary to specify the location of control-related registers and make the appropriate

settings, based on information from the CIS section. These control-related registers are called the

configuration registers.

The CIS section and configuration registers are both in an area called the card attribute region. The

write access sequence for this region is shown in table 3.1, and detailed timing specifications are

given in tables 3.2 and 3.3.

Write-related information applies only to accesses to the configuration registers, since the CIS

section is a read-only area.

As shown in table 3.1, the attribute region is allocated to the even byte (D0–D7) parts of even

addresses in the card., and consists entirely of 8-bit registers. Odd byte (D8–D15) parts are invalid

data. Mapping of the task file region described later is also performed by these registers.

Note: The configuration registers are used to set the operating mode of the card. It might

therefore be supposed that switching between PC-ATA specifications and True-IDE

specifications in a flash card can also be performed by means of these registers, but this is

not the case. These registers can only be used with the PC-ATA specifications. Whether a

flash card is set to the PC-ATA specifications or True-IDE specifications depends on the

input pin settings when the power is turned on; once the card has been started up in a

particular mode, the mode can only be changed by turning on the power again.

16

Table 3.1 Attribute Region Access

•

Attribute region

— Configuration register access

A8–

D15–

Register Name

R/W CE2 CE1 REG OE WE A10 A9 A4 A3 A2 A1 A0 D8

D7–D0

Configuration

Option REG.

Add 200h

R

×*¹

L

H

L

0

1

0

1

0

1

0

High-Z Even

byte data

W

H

Don’t

care

Card Status REG. R

L

H

L

High-Z

Add 202h

W

H

Don’t

care

Pin Replacement

REG. Add 204h

R

L

H

L

High-Z

W

H

Don’t

care

Socket

and

Copy RL

H

0

1

0

1

0

H

REG. Add 206h

W

H

L

Don’t

care

— CIS access

D15–

D8

Register Name

R

CE2 CE1 REG OE WE A10–A0

D7–D0

CIS REG.

Add 000h–0FEh

R*²×*²H*²

L

×

High-Z Even

byte

Corresponds to addresses

000h–0FEh

Notes: 1. In the attribute section, as with accesses to other main memory, even byte/odd byte

switching can be performed using CE1 and CE2. However, in the attribute section, only

even bytes are valid. Therefore, when a word access is executed (16-bit width, CE1

and CE2 low), invalid data is output when the odd byte part (D15–D8) is read, and input

data is ignored when the odd byte part is written.

2. The CIS section is a read-only area that stores card attribute information. It cannot be

written to. Only even bytes are valid, as with other registers in the attribute region.

17

Table 3.2 Attribute Memory Read Timing

Speed Version

300 ns

Max [ns]

No.

1

Item

Symbol

t_CR

Min [ns]

Read cycle time

250

2

Address access time

t_A(Add)

t_A(CE)

t_A(OE)

t_DIS(CE)

t_DIS(OE)

t_SU(Add)

t_EN(CE)

t_EN(OE)

t_V(Add)

250

125

100

3

Card enable access time

Output enable access time

Output disable time from CE

Output disable time from OE

Address setup time

4

5

6

7

30

5

8

Output enable time from CE

Output enable time from OE

Data vaild from address change

9

5

10

0

t_CR

t_A(A)

An

t_SU(A)

REG

CE

t_V(A)

t_A(CE)

t_DIS(CE)

t_DIS(OE)

t_A(CE)

OE

t_EN(OE)

t_EN(CE)

Dout

Figure 3.3 Attribute Memory Read Timing Chart

Note: The attribute memory read access time is stipulated as 300 ns or more. Data placed on

Dout is the data output from the CF and transferred to the host. When a burst read is

performed, either CE or OE must be driven high.

18

Table 3.3 Attribute Memory Write Timing

Speed Version

250 ns

Max [ns]

No.

1

Item

Symbol

t_CW

Min [ns]

250

150

30

Write cycle time

Write pulse width

Address setup time

Write recovery time

Data setup time for WE

Data hold time

2

t_W(WE)

t_SU(Add)

t_REC(WE)

t_SU(D-WEH)

t_H(D)

3

4

30

5

80

6

30

t_CW

REG

An

t_SU(A)

t_REC(WE)

t_W(WE)

WE

CE

OE

Din

t_SU(D-WEH)

t_H(D)

Data in valid

Figure 3.4 Attribute Memory Write Timing Chart

Note: The attribute memory write access time is stipulated as 250 ns or more. Data placed on

Din is the data output from the host and transferred to the card. With a flash card, writes

cannot be performed to the CIS section, so this timing applies only to writes to the

configuration registers.

19

Memo

Aren’t flash cards only used in personal computers and digital cameras?

Flash cards may be thought of as only being used for data storage in notebook PCs and

digital cameras. It is true that PC-ATA cards and CompactFlash™ were designed to be

inserted into a PC card slot, but flash cards are not only used as HD or FD replacements in

PC card slots. Although the control method is different from that used up to now, since the

cards contain flash memory it is natural that they should be able to be used as program ROM.

For example, with a general-purpose sequence that handles a large program, if it is necessary

to change the program according to its intended use, a flash card could be used instead of

writing data in program ROM. Program replacement can be achieved simply by switching

cards. In a system in which the program size and number of variables may increase in the

future, an initial small-capacity card could be replaced when necessary at a later date with a

larger-capacity card.

There is no need for a special device to write data to a card or verify its contents; this can be

done using an ordinary personal computer. By adopting a slightly different perspective and

looking at flash cards as system components, a variety of different uses can be found.

Task File Region: The task file region contains the following registers, and is used for data

exchange (reading/writing) between the card and the host.

•

Register names

Data register

Drive head register

Error register

Status register

Feature register

Alternate status register

Sector count register

Command register

Sector number register

Device control register

Cylinder low register

Cylinder high register

Drive address register

Note: For details of register settings, see the descriptions of task file register contents in the

appendices.

20

The addresses at which these registers are located are changed by settings in the configuration

option register in the attribute region. The operating mode and interface pin functions are also

changed.

There are four operating modes, selected by a setting in the configuration option register.

•

Memory mode

Primary I/O mode

Secondary I/O mode

Contiguous I/O mode

The basic handling is the same in the primary, secondary, and contiguous I/O modes, the only

differences being in the mapping of the task file registers. There are thus basically two operating

modes, memory mode and I/O mode. These are described in sections 3.3 and 3.4.

3.3

Memory Mode

Both PC-ATA cards and CF enter memory mode at power-on or in a hardware reset. Therefore,

while no particular settings are required concerning the operating mode, it is preferable to make

settings in the configuration option register. The configuration option register settings shown in

table 3.4 place the card in memory mode.

In memory mode, read and write operations are performed by controlling WE and OE. At this

time, IORD and IOWR must be held high. This mode is useful when driving a card using a CPU

with no IORD and IOWR signals, a CISC microcomputer, or a RISC microcomputer. When using

a microcomputer that has IORD and IOWR signals and is capable of control by IN/OUT

instructions, it may be more convenient to use I/O mode.

The pin interface in memory mode is shown in tables 3.7 and 3.8.

For the method of accessing the registers, and timing details, see tables 3.4 to 3.6, etc.

21

Table 3.4 Memory Mode

Configuration Option Register (Attribute 200h)

Setting

OPERATION

R/W

D7

D6

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

Register

SRST

LevReg

Note: Normally, the card enters memory mode when powered on.

Allocation: 0–F, 400–7FF

Register

No.

A9–

Register Name R/W CE2 CE1 REG RD WR A10 A4 A3 A2 A1 A0 Offset Attribute

1

0*¹

1*¹

2

Even data

R

*

L

H

L

H

L

0

×

0

7

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

R

/W

W

R

Error REG

Feature REG

Sector

L

H

L

0

R only

W

H

W onry

count

no

RL

H

L

1

R

/W

W

3

Sector

RL

H

L

1

/W

4

Cylinder

Select

low

RL

H

L

0

5

high

RL

H

L

0

6

card/head RL

H

L

1

W

R

H

7

Status

L

H

0

1

R only

Command

Dup.

W

H

L

W only

8*²

9*²

10*²

11

12

8*³

9*³

even

odd

data

R1L 0H 0 0 0

R1L 0H 0 0 1

8

9

D

E

F

8

9

R

/W

W

Dup.

data

R

/W

W

R

H

L

Dup. error REG

H

L

0

1

0

1

0

1

R only

W only

R only

W only

R only

W only

Dup. feature REG W

Alt

H

status

RL

H

L

0

Drive control

Drive

W

address

even

RL

H

L

Reserved

Dup.

data

R×L ×H × 1 0

R×L ×H × 1 1

R

/W

H

L

Dup.

odd

data

R

/W

IORD, IOWR: Fixed high

22

Notes: 1. Note that the meaning of the data differs depending on whether byte access or word

access is used on register 0.

• Byte access

CE1 low, CE2 high: The even byte is accessed first, followed by the odd byte.

CE1 high, CE2 low: Register 1 ErrorREG. or FeaturesREG is accessed.

• Word access

CE1, CE2 low: Operates as a word register via D15–D0. A0 is ignored. In this case,

the format is for EvenRD Data + ErrorREG (when reading) or EvenWR Data +

Features REG. (when writing) to exist in the same word.

2. The contents of registers 8–10 are a duplicate of the data in registers 0 and 1. Thus the

following access methods are possible.

• Byte access

— When consecutive byte accesses are performed on register 0 (8), the even-byte

data is accessed first, followed by the odd-byte data.

— By performing byte access to register 9 and register 8, in that order, the odd-byte

data is accessed first, followed by the even-byte data.

— By performing byte access to register 8 and register 9, in that order, the even-

byte data is accessed first, followed by the odd-byte data.

— When access is performed alternately to register 0 and register 8, the even-byte

data is accessed first, followed by the odd-byte data.

Byte access cannot be performed on register 9, either singly or consecutively. It

must always be paired with register 8, and used only for extracting odd-byte data

from word data.

• Word access

— As in note 1 above. Register 8 can also be handled in the same way as register 0.

3. Data is placed in order in the 1-kbyte memory space from 400 to 7FF, starting at the

selected address.

Of this data, even-address data can be accessed via register 8, and odd-address data

via register 9. Use of this function allows functions such as block transfer to be

implemented between memory areas in the card. However, note that this involves

accessing a FIFO starting with a certain address, and does not mean that the sector

buffer in the CF can be accessed randomly.

23

Table 3.5 Common Memory Read Timing

No.

1

Item

Symbol

t_A(OE)

Min [ns]

Max [ns]

125

Output enable access time

Output disable time from OE

Address setup time

2

t_DIS(OE)

t_SU(Add)

t_H(Add)

t_SU(CE)

t_H(CE)

100

3

30

20

0

4

Address hole time

5

CE setup before OE

6

CE hold following OE

Wait delay falling from OE

Data setup for wait release

Wait width time (default speed)

20

7

t_V(WIT-OE)

t_V(WIT)

t_W(WIT)

35

0

8

9

350

An

t_SU(A)

t_H(A)

REG

CE

t_SU(CE)

t_H(CE)

OE

t_W(WIT)

t_V(WIT-OE)

WAIT

t_DIS(OE)

t_V(WIT)

t_A(OE)

Data transferred

from card to host

Dout

Figure 3.5 Common Memory Read Timing Chart

Note: The WAIT maximum load is one 50 pF LS-TTL in total.

The WAIT maximum width (slowest mode operation) is stipulated by the CIS section.

If the OE cycle-to-cycle time is longer than WAIT signal width, the WAIT signal may be

ignored.

24

Table 3.6 Common Memory Write Timing

No.

1

Item

Symbol

t_SU(D-WEH)

t_H(D)

Min [ns]

80

Max [ns]

Data setup before WE

Data hold following WE

WE pulse Width

2

30

3

t_W(WE)

t_SU(Add)

t_SU(CE)

t_REC(WE)

t_H(Add)

t_H(CE)

150

30

4

Address setup time

CE setup before WE

Write recovery

5

0

6

30

7

Address hold time

CE hold following WE

Wait delay falling from WE

WE high from wait release

Wait width time

20

8

20

9

t_V(WIT-WE)

t_V(WT)

35

10

11

0

t_V(WIT)

350

An

t_H(A)

t_SU(A)

REG

CE

t_SU(CE)

t_W(WE)

t_W(WIT)

t_H(CE)

t_REC(WE)

t_V(WIT)

t_H(D)

Data in valid

WE

t_V(WIT-WE)

WAIT

t

_SU(D-WEH)

Data transferred

from host to card

Dout

Figure 3.6 Common Memory Write Timing Chart

Note: The WAIT maximum load is one 50 pF LS-TTL in total.

The WAIT maximum width (slowest mode operation) is stipulated by the CIS section.

If the WE cycle-to-cycle time is longer than WAIT signal width, the WAIT signal may be

ignored.

25

Table 3.7 Pin Arrangement in Memory Mode

CompactFlash^TM

Pin No.

1

Memory Card

GND

D3

Pin No.

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

Memory Card

CD1

2

D11

3

D4

D12

4

D5

D13

5

D6

D14

6

D7

D15

7

CE1

A10

OE

CE2

8

VS1

9

IORD

IOWR

WE

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

A9

A8

A7

RDY/BUSY

V_CC

A6

—

A5

VS2

A4

RESET

WAIT

—

A3

A2

A1

REG

BVD2

BVD1

D8

A0

D0

D1

D2

D9

WP

CD2

D10

GND

26

Table 3.7 Pin Arrangement in Memory Mode (cont)

PC-ATA Card

Pin No.

1

Memory Card

Pin No.

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

Memory Card

GND

CD1

D11

D12

D13

D14

D15

CE2

VS1

RFU

—

GND

D3

2

3

D4

4

D5

5

D6

6

D7

7

CE1

A10

OE

—

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

A9

A8

—

WE

RED/BUSY

V_CC

—

V_CC

—

A7

—

A6

VS2

RESET

WAIT

RFU

REG

BVD2

BVD1

D8

A5

A4

A3

A2

A1

A0

D0

D1

D9

D2

D10

CD2

GND

WP

GND

27

Table 3.8 Pin Functions in Memory Mode

Pin No.

Abbre-

viation

Compact PC-ATA

Input/

Output Function

Flash

13, 38

1, 50

Card

V_CC

17, 51

Input

Power supply pins

GND pins

GND

1, 34, 35, Input

68

D0–D15

21, 22, 23, 30, 31, 32, Input/ Data bus. D0–D7 comprise the even byte of a word,

2, 3, 4, 5, 2, 3, 4, 5, Output and D8–D15 the odd byte. D0 and D8 are the

6, 47, 48, 6, 64, 65,

49, 27, 28, 66, 37, 38,

29, 30, 31 39, 40, 41

respective LSBs.

A0–A10

20, 19, 18, 29, 28, 27, Input

17, 16, 15, 26, 25, 24,

14, 12, 11, 23, 22, 12,

Address bus. A10 is the MSB, and A0 the LSB.

10, 8

11, 8

CE1, CE2 7, 32

7, 42

Input

CE1 is used for even address control and CE2 for

odd address control. Both are active-low.

OE

9

This pin is used to read the contents of both attribute

and common areas. Active-low.

WE

36

34

35

37

15

44

45

16

This pin is used to write the contents of both attribute

and common areas. Active-low.

IORD

IOWR

Not used in memory mode. It is recommended that

this pin be pulled high.

Not used in memory mode. It is recommended that

this pin be pulled high.

RDY/

Output Goes low during internal initialization operations

performed automatically at power-on and in a reset.

Proceed to the next operation when this pin goes

high.

BUSY

CD1, CD2 26, 25

36, 67

33

Output Used by the host to determine whether a card is

inserted. These pins are connected to GND inside

the card.

WP

24

Output Originally intended to indicate whether the write-

protect state is in effect, but as this card has no

write-protect function, the output of this pin is always

low.

28

Table 3.8 Pin Functions in Memory Mode (cont)

Pin No.

Abbre-

viation

Compact PC-ATA

Input/

Output Function

Flash

Card

REG

44

61

Input

Input pin for switching between common and

attribute area access.

Drive high for common area access, and low for

attribute area access. As the attribute area section is

allocated to even addresses, D8–D15 are invalid in

word access mode. In byte access, odd addresses

are invalid.

BVD1

BVD2

RESET

46

45

41

63

62

58

59

Output Originally intended to indicate the card’s internal

battery voltage level, but as this card has no battery,

the output of this pin is always high.

Output Originally intended to indicate the card’s internal

battery voltage level, but as this card has no battery,

the output of this pin is always high.

Input

All registers in the card can be cleared by high-level

input at this pin. Initialization is then started, and

RDY/BSY output goes high.

WAIT

42

43

Output I/O access or memory access cycle execution is

kept waiting while the output of this pin is low.

INPACK

60

Output Not used in memory card mode.

VS1, VS2 33, 40

43, 57

Output These pins indicate the required input voltage value

for this card (CIS information).

3.4

I/O Mode (Primary/Secondary/Contiguous)

The card enters memory mode immediately after being powered on and in a hardware reset.

Therefore, in order to use the card in I/O mode, the configuration option register in the attribute

region must be set for the card as shown in tables 3.9 to 3.11.

In I/O mode, reading and writing is performed by controlling IORD and IOWR. WE and OE must

be held high.

This mode may be useful when using an MPU that has IORD and IOWR signals.

The pin interface in I/O mode is shown in tables 3.14 and 3.15. For the method of accessing the

registers, and timing details, see tables 3.9 to 3.13, etc.

29

Table 3.9 Primary I/O Mode

Configuration Option Register (Attribute 200h)

Setting

OPERATION

R/W

D7

D6

D5

0

D4

0

D3

0

D2

0

D1

1

D0

0

Register

SRST

LevReg

Allocation: 1F0–1F7, 3F6–3F7

Interrupt: IRQ14

Drive no.: 0 (1 is not supported)

Register Register

No.

Name

R/W CE2 CE1 REG IORD IOWR A9–A4 A3

A2

A1

A0

1

0*²

Even RD data

R

*

L

H

L

1F

0

W

R

1*²

2

Error REG.

Feature REG.

Sector

L

H

L

0

1

0

1

0

1

0

1

0

1

0

W

H

count

no

RL

H

L

W

3

Sector

RL

H

L

4

Cylinder

low

RL

H

L

5

high

card/

RL

H

L

6

Select

head

RL

H

L

W

7

Status

RL

W

H

1

Command

Alt

H

RL

H

L

8

status

H

L

3F

1

0

1

Drive control

Drive

W

9

address RL

H

L

Reserved

WE, OE: Fixed high

30

Note: 1. Note that the meaning of the data differs depending on whether byte access or word

access is used on register 0.

• Byte access

CE1 low, CE2 high: The even byte is accessed first, followed by the odd byte.

CE1 high, CE2 low: Register 1 Error REG. or Features.REG. is accessed.

• Word access

CE1, CE2 low: Operates as a word register via D15–D0. A0 is ignored. In this case,

the format is for Even RD Data + Error REG. (when reading) or Even WR Data +

Features REG. (when writing) to exist in the same word.

31

Table 3.10 Secondary I/O Mode

Configuration Option Register (Attribute 200h)

Setting

OPERATION

R/W

D7

D6

D5

0

D4

0

D3

0

D2

1

D1

1

D0

0

Register

SRST

LevReg

Allocation: 170–177, 376–377

Interrupt: IRQ14

Drive no.: 0 (1 is not supported)

Register Register

No.

Name

R/W CE2 CE1 REG IORD IOWR A9–A4 A3

A2

A1

A0

1

0*²

Even RD data

R

*

L

H

L

17

0

W

R

1*²

2

Error REG.

Feature REG.

Sector

L

H

L

0

1

0

1

0

1

0

1

0

1

0

W

H

count

No

RL

H

L

W

3

Sector

RL

H

L

4

Cylinder

low

RL

H

L

5

high

card/

RL

H

L

6

Select

head

RL

H

L

W

7

Status

RL

W

H

1

Command

Alt

H

RL

H

L

8

Status

H

L

37

1

0

1

Drive control

Drive

W

9

Address RL

H

L

Reserved

WE, OE: Fixed high

32

Note: 1. Note that the meaning of the data differs depending on whether byte access or word

access is used on register 0.

• Byte access

CE1 low, CE2 high: The even byte is accessed first, followed by the odd byte.

CE1 high, CE2 low: Register 1 Error REG. or Features REG. is accessed.

• Word access

CE1, CE2 low: Operates as a word register via D15–D0. A0 is ignored. In this case,

the format is for Even RD Data + Error REG. (when reading) or Even WR Data +

Features REG. (when writing) to exist in the same word.

33

Table 3.11 Contiguous I/O Mode

Configuration Option Register (Attribute 200h)

Setting

OPERATION

R/W

D7

D6

D5

0

D4

0

D3

0

D2

0

D1

0

D0

1

Register

SRST

LevReg

Allocation: Allocated to 16 contiguous bytes starting at any I/O address.

Register Register

Other

No.

Name

R/W CE2 CE1 REG IORD IOWR Add A3 A2 A1 A0 Offset Attribute

1

3

0*¹

Even data

R

*

L

H

L

*

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

R

/W

W

R

H

L

1*¹

2

Error REG.

Feature REG.

Sector

H

L

0

R only

W only

W

H

count RL

H

L

1

R

/W

W

3

Sector

No

RL

H

L

1

/W

4

Cylinder

low

RL

H

L

0

5

high RL

H

L

0

6

Select

head

card/

RL

H

L

1

W

R

7

Status

L

H

0

1

7

R only

0

Command

W

H

RL

H

L

W only

8*²

9*²

10*²

Dup.

data

even

H

L

1

0

8

R

/W

W

Dup.

data

odd

R

L

H

L

0/W

1

R

W

R

H

Dup. error

REG.

L

H

1

0

1

D

R only

Dup. feature

REG.

W

H

L

W only

11

12

Alt

status

RL

H

L

1

0

1

E

F

R only

W only

R only

W only

Drive control

Drive

W

address RL

H

L

Reserved

WE, OE: Fixed high

34

Notes: 1. Note that the meaning of the data differs depending on whether byte access or word

access is used on register 0.

• Byte access

CE1 low, CE2 high: The even byte is accessed first, followed by the odd byte.

CE1 high, CE2 low: Register 1 Error REG. or Features REG. is accessed.

• Word access

CE1, CE2 low: Operates as a word register via D15–D0. A0 is ignored. In this case,

the format is for Even RD Data + Error REG. (when reading) or Even WR Data +

Features REG. (when writing) to exist in the same word.

2. The contents of registers 8–10 are a duplicate of the data in registers 0 and 1. Thus the

following access methods are possible.

• Byte access

— When consecutive byte accesses are performed on register 0 (8), the even-byte

data is accessed first, followed by the odd-byte data.

— By performing byte access to register 9 and register 8, in that order, the odd-byte

data is accessed first, followed by the even-byte data.

— By performing byte access to register 8 and register 9, in that order, the even-

byte data is accessed first, followed by the odd-byte data.

— When access is performed alternately to register 0 and register 8, the even-byte

data is accessed first, followed by the odd-byte data.

Byte access cannot be performed on register 9, either singly or consecutively. It

must always be paired with register 8, and used only for extracting odd-byte data

from word data.

• Word access

— As in note 1 above. Register 8 can also be handled in the same way as register 0.

3. With CompactFlash™, address lines other than A0–A3 are ignored when accessing the

above task file region address space.

35

Note: Although there are three I/O modes—primary, secondary, and contiguous—the only

difference is in the mapping of the task file registers; the access timing is the same for all

three modes.

Specifications Common to Primary, Secondary, and Contiguous Modes

Table 3.12 I/O Read Timing

No.

1

Item

Symbol

Min [ns]

Max [ns]

Data delay after IORD

t_D(IORD)

100

2

Data hold following IORD

IORD width time

t_H(IORD)

0

3

t_WIORD

165

70

20

5

4

Address setup before IORD

Address hold following IORD

CE setup before IORD

t_SUA(IORD)

t_HA(IORD)

t_SUCE(IORD)

t_HCE(IORD)

t_SUREG(IORD)

t_HREG(IORD)

t_DFINPACK(IORD)

t_DRINPACK(IORD)

t_DFIOIS16(Add)

t_DRIOIS16(Add)

t_DWIT(IORD)

t_D(WIT)

5

6

7

CE hold following IORD

REG setup before IORD

REG hold following IORD

INPACK delay falling from IORD

INPACK delay rising from IORD

IOIS16 delay falling from IORD

IOIS16 delay rising from IORD

Wait delay falling from IORD

Data delay from wait rising

Wait width time (default speed)

20

5

8

9

0

10

11

12

13

14

15

16

0

45

35

0

t_W(WIT)

350

36

t_HA(IORD)

t_SUA(IORD)

An

t_SUREG(IORD)

t_SUCE(IORD)

t

_HREG(IORD)

REG

t_HCE(IORD)

CE

t_WIORD

IORD

INPACK

t_DRINPACK(IORD)

t_DRIOIS16(Add)

t_DFINPACK(IORD)

t_DFIOIS16(Add)

IOIS16

t

(WIT)

t_D(WIT)

t_DWIT(IORD)

W

WAIT

t_H(D)

t_D(IORD)

Dout

Figure 3.7 I/O Read Timing Chart

Note: The maximum load for WAIT, INPACK, and IOIS16 is one 50 pF LS-TTL in total. In a

read, the time from the point at which WAIT goes high until IORD goes high is 0 ns or

more.

37

Specifications Common to Primary, Secondary, and Contiguous I/O Modes

Table 3.13 I/O Write Timing

No.

1

Item

Symbol

Min [ns]

60

Max [ns]

IOWRt

Data

setup

hold

_SU(IObWefRo)re

_Hf(oIOlloWwRin)g

t_WIOWR

2

Data

30

IOWRt

3

IOWR pulse width

Address

CE

165

4

setup

hold

setup

hold

setup

hold

delay

_SUb_Ae(IfOorWe R)

70

IOWRt

5

follow(IiOngWR)

20 IOWRt

HA

6

_SUCE(IObWefRor)e

_HCEf(oIOlloWwRin)g

_SUREGb(IeOfoWreR)

5

IOWRt

7

CE

20

5

IOWRt

8

REG

9

REG

follo(IwOiWngR)

0

IOWRt

HREG

10

11

10

11

IOIS16

WAIT

falling _DFIOIS16(Add) from

3IO5WRt

delay

rising_DRIOIS16(Add) from

35IOWRt

35 IOWRt

falling_DWIT(IOWR)

t_DRIOWR(WIT)

t_W(WIT)

from

IOWR high from WAIT high

WAIT width time (default speed)

(Set feature speed < 68 mA)

0

350

700

38

t_SUA(IOWR)

t_HA(IOWR)

An

t_SUREG(IOWR)

t_SUCE(IOWR)

t_HREG(IOWR)

t_HCE(IOWR)

REG

CE

t_WIOWR

IOWR

IOIS16

t_DRIOIS16(Add)

t_DFIOIS16(Add)

t_DWIT(IOWR) t_W(WIT) t_DRIOWR(WIT)

WAIT

t_SU(IORD) t_H(IORD)

Data in valid

Dout

Figure 3.8 I/O Write Timing Chart

Note: The maximum load for WAIT, INPACK, and IOIS16 is one 50 pF LS-TTL in total. In a

write, the time from the point at which WAIT goes high until IOWR goes high is 0 ns or

more.

39

Table 3.14 Pin Arrangement in I/O Mode

CompactFlash^TM

Pin No.

1

Memory Card

GND

D3

Pin No.

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

Memory Card

CD1

2

D11

3

D4

D12

4

D5

D13

5

D6

D14

6

D7

D15

7

CE1

A10

OE

CE2

8

VS1

9

IORD

IOWR

WE

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

A9

A8

A7

IREQ

V_CC

A6

—

A5

VS2

A4

RESET

WAIT

INPACK

REG

SPKR

STSCHG

D8

A3

A2

A1

A0

D0

D1

D2

D9

IOIS16

CD2

D10

GND

40

Table 3.14 Pin Arrangement in I/O Mode (cont)

PC-ATA Card

Pin No.

1

Memory Card

GND

D3

Pin No.

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

Memory Card

GND

CD1

D11

D12

D13

D14

D15

CE2

VS1

IORD

IOWR

—

2

3

D4

4

D5

5

D6

6

D7

7

CE1

A10

OE

—

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

A9

A8

—

WE

IREQ

V_CC

—

V_CC

—

A7

—

A6

VS2

RESET

WAIT

INPACK

REG

SPKR

STSCHG

D8

A5

A4

A3

A2

A1

A0

D0

D1

D9

D2

D10

CD2

GND

IOIS16

GND

41

Table 3.15 Pin Functions in I/O Mode

Pin No.

Abbre-

viation

Compact PC-ATA

Input/

Output Function

Flash

13, 38

1, 50

Card

V_CC

17, 51

Input

Power supply pins

GND pins

GND

1, 34, 35, Input

68

D0–D15

21, 22, 23, 30, 31, 32, Input/ Data bus. D0–D7 comprise the even byte of a word,

2, 3, 4, 5, 2, 3, 4, 5, Output and D8–D15 the odd byte. D0 and D8 are the

6, 47, 48, 6, 64, 65,

49, 27, 28, 66, 37, 38,

29, 30, 31 39, 40, 41

respective LSBs.

A0–A10

20, 19, 18, 29, 28, 27, Input

17, 16, 15, 26, 25, 24,

14, 12, 11, 23, 22, 12,

Address bus. A10 is the MSB, and A0 the LSB.

10, 8

11, 8

CE1, CE2 7, 32

7, 42

Input

CE1 is used for even address control and CE2 for

odd address control. Both are active-low.

OE

9

This pin is used to read the contents of both attribute

and common areas. Active-low.

WE

36

34

15

44

This pin is used to write the contents of both attribute

and common areas. Active-low.

IORD

Used to read data from the I/O task file area. This

pin is only valid when the card is set as an I/O card.

Active-low.

IOWR

IREQ

35

37

45

16

Input

Used to write data to the I/O task file area. This pin

is only valid when the card is set as an I/O card.

Active-low.

Output Interrupt request pin. When output is low, the card is

requesting software service by the host. When

output is high, the card is not requesting anything

from the host.

CD1, CD2 26, 25

36, 67

33

Output Used by the host to determine whether a card is

inserted. These pins are connected to GND inside

the card.

IOIS16

24

Output The output of this pin goes low when a task file

register is accessed in 16-bit access mode.

42

Table 3.15 Pin Functions in I/O Mode (cont)

Pin No.

Abbre-

viation

Compact PC-ATA

Input/

Output Function

Flash

Card

REG

44

61

Input

Input pin for switching between common and

attribute area access.

Drive high for common area access, and low for

attribute area access. As the attribute area section is

allocated to even addresses, D8–D15 are invalid in

word access mode. In byte access, odd addresses

are invalid.

STSCHG 46

63

Output Used to modify the configuration status register in

the attribute memory area.

Only valid in I/O card mode.

SPKR

45

41

62

58

Output As this card has no digital audio output function, the

output of this pin is always high.

RESET

All registers in the card can be cleared by high-level

input at this pin. Initialization is then started, and

RDY/BSY output goes high.

WAIT

42

43

59

60

Output I/O access or memory access cycle execution is

kept waiting while the output of this pin is low.

INPACK

Output Used for input data buffer control. Selects the card

and executes an I/O read cycle for the address pins.

If the card gives an I/O read cycle reaction, a low

level is output from the card.

VS1

33, 40

39

43, 57

39

Output Indicates the required input voltage value for this

card (CIS information).

CSEL

Input

Not used in memory card mode or I/O card mode.

43

3.5

True-IDE Specifications

The following requirements must be met in order to use a flash card in accordance with the True-

IDE specifications. If these requirements are not met, the card will probably start up in memory

mode. Once a card starts up as a PC-ATA card, it will operate as such until its power is turned off.

True-IDE specifications cannot be selected by modifying registers during operation or by a reset.

•

True-IDE setting procedure and precautions

1. Set the flash card OE pin (ATASEL) to GND during the transition from power-off to power-

on.

2. The OE pin (ATASEL) must then be held low during use as a True-IDE specification card.

Notes: 1. When starting up as a True-IDE specification card, only I/O access is enabled.

2. Only the task file region can be accessed.

3. No memory areas can be accessed (including the attribute region); i.e., the WE and OE

input pins cannot be used. It is recommended that WE and OE be pulled high.

4. The card will operate as a PC-ATA specification card if the OE setting is incorrect

(including an incorrect setting due to noise, etc.) when performing hot-line insertion or

removal, and particularly in the power-off → power-on sequence.

5. The selection of PC-ATA or True-IDE specifications is determined only in the power-

on sequence. The state of OE is not checked in a reset.

When the True-IDE specifications are used, the access method is simpler than in other modes. The

necessary peripheral circuitry is also comparatively small in scale, making this mode suitable for

embedded applications. Once a card is used with the PC-ATA specifications, this does not mean

that it can no longer be used as a PC card. For example, a flash card used as a True-IDE

specification card in the user’s own system can be used as a PC card without any problem if

inserted in the PC card slot of a notebook PC.

In this case, however, although identification as hardware is possible, it will not be possible to

read or write data if the actual file formats of the user’s system and the PC are different. It is

therefore advisable to use DOS format or similar file management in one’s own system so that

files can also be read in a PC environment.

The pin interface when using the True-IDE specifications is shown in tables 3.19 and 3.20. For the

method of accessing the registers, and timing details, see tables 3.16 to 3.18, etc.

44

Table 3.16 True-IDE Specification Access

Register Register

No.

Name

R/W CE2

CE1

IORD

IOWR A2

A1

A0

Attribute

0

Even

data

RH

L

H

L

0

1

0

R

/W

W

R

H

L

1

2

3

4

5

6

7

8

9

Error REG.

H

L

0

1

0

1

0

1

0

R only

W only

R

Feature REG.

Sector

W

H

count

RL

H

L

1

/W

W

H

RL

H

Sector

no

H

L

1

R

Cylinder

Select

low

RL

H

L

0

high

RL

H

L

0

card/head RL

H

L

1

W

R

H

Status

L

H

1

R only

Command

W

H

L

W only

R only

W only

R only

W only

Alt

status

RL

H

L

H

L

1

0

1

Drive control

Drive

W

address

RL

H

L

Reserved

Table 3.17 True-IDE Read Timing

No.

1

Item

Symbol

Min [ns]

Max [ns]

Data delay after IORD

Data hold following IORD

IORD width time

t_D(IORD)

t_H(IORD)

t_WIORD

100

2

0

3

165

70

20

5

4

Address setup before IORD

Address hold following IORD

CE setup before IORD

CE hold following IORD

IOIS16 delay falling from IORD

IOIS16 delay rising from IORD

t_SUA(IORD)

5

t_HA(IORD)

6

t_SUCE(IORD)

t_HCE(IORD)

t_DFIOIS16(Add)

t_DRIOIS16(Add)

7

20

8

35

9

45

t_SUA(IORD)

An

t_HA(IORD)

t_SUCE(IOWR)

t_HCE(IORD)

CE

t_WIORD

IORD

t_DRIOIS16(Add)

t_DFIOIS16(Add)

IOIS16

t_H(IORD)

t_D(IORD)

Dout

Figure 3.9 True-IDE Read Timing Chart

Note: The maximum load for WAIT, INPACK, and IOIS16 is one 50 pF LS-TTL in total. In a

read, the time from the point at which WAIT goes high until IORD goes high is 0 ns or

more.

46

Table 3.18 True-IDE Write Timing

No.

1

Item

Symbol

Min [ns]

Max [ns]

Data

setup

hold

_SU(IOWR)before60

IOWR

2

Data

(IOWRfo)lowing 30

IOWRt

H

3

IOWR pulse width

Address

CE

t_WIOWR

165

4

setup

hold

_SUA(IOWbeRfo)re

_HA(IfOolWlowRi)ng

70

20

IOWRt

5

6

setup

hold

_SUCE(IOWR)befor5e

IOW

7

CE

(IOWfRol)lowing20

IOWR

HCE

8

IOIS16

delay

falling (Add)

from 35

IO

I

DFIOIS16

9

delay

rising (Add)

DRIOIS16

t_SUA(IOWR)

An

t_HA(IOWR)

t_HCE(IOWR)

t_SUCE(IOWR)

CE

t_WIOWR

IOWR

t_DFIOIS16(Add)

t_DRIOIS16(Add)

IOIS16

t_SU(IOWR) t_H(IOWR)

Data in valid

Dout

Figure 3.10 True-IDE Write Timing Chart

Note: The maximum load for WAIT, INPACK, and IOIS16 is one 50 pF LS-TTL in total. In a

write, the time from the point at which WAIT goes high until IOWR goes high is 0 ns or

more.

47

Table 3.19 Pin Arrangement when Using True-IDE Specifications

CompactFlash^TM

Pin No.

1

True-IDE

GND

D3

Pin No.

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

True-IDE

CD1

2

D11

3

D4

D12

4

D5

D13

5

D6

D14

6

D7

D15

7

CE1

A10

ATASEL

A9

CE2

8

VS1

9

IORD

IOWR

WE

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

A8

A7

INTRQ

V_CC

A6

CSEL

VS2

A5

A4

RESET

IORDY

INPACK

REG

DASP

PDIAG

D8

A3

A2

A1

A0

D0

D1

D2

D9

IOIS16

CD2

D10

GND

48

Table 3.20 Pin Functions when Using True-IDE Specifications

Pin No.

Abbre-

viation

CompactFlash^TMInput/Output Function

V_CC

13, 38

1, 50

Input

Power supply pins

GND pins

GND

D0–D15

21, 22, 23, 2, 3, Input/Output

4, 5, 6, 47, 48,

49, 27, 28, 29,

Data bus. D0–D7 comprise the even byte of a

word, and D8–D15 the odd byte. D0 and D8 are

the respective LSBs.

30, 31

A0–A10

20, 19, 18, 17,

16, 15, 14, 12,

11, 10, 8

Input

One register in the task file area can be selected

using A0–A2. Other address pins should be

dropped to GND on the host side.

CE1, CE2 7, 32

CE2 is used to select the alternate status register

and device control register in the task file area.

CE1 is used to select other registers in the task file

area.

ATASEL

9

Input

True-IDE mode can be selected by dropping this

pin to GND on the host side.

WE

36

34

Input

Not used. Connect to V_CCon the host side.

IORD

Used to read data from the I/O task file area. This

pin is only valid when the card is set as an I/O

card. Active-low.

IOWR

35

37

Input

Used to write data to the I/O task file area. This pin

is only valid when the card is set as an I/O card.

Active-low.

INTRQ

Output

Pin for interrupt requests to the host. Active when

the output is high.

CD1, CD2 26, 25

Used by the host to determine whether a card is

inserted. These pins are connected to GND inside

the card.

IOIS16

24

Output

A low level at this pin indicates that the card is

requesting a word data transfer cycle.

REG

44

46

Input

Not used. Connect to V_CCon the host side.

PDIAG

Output

The Pass Diagnostic signal in the master-slave

handshake protocol.

DASP

45

41

Output

The Disk Active/Slave Present signal in the

master-slave handshake protocol.

RESET

Low-level input to this pin from the host causes a

hardware reset.

49

Table 3.20 Pin Functions when Using True-IDE Specifications (cont)

Pin No.

Abbre-

viation

CompactFlash^TMInput/Output Function

WAIT

42

Output

I/O access or memory access cycle execution is

kept waiting while the output of this pin is low.

—

43

Output

Not used. Leave open.

VS1

33, 40

Indicates the required input voltage value for this

card (CIS information).

CSEL

39

Input

Pulled up internally. Dropping this pin to GND

selects master mode, while leaving it open selects

slave mode.

50

Section 4 Basic Operation and Method of Use of Flash

Cards

This section describes the tasks that should be performed when a flash card is powered on, and the

basic ATA commands used when actually reading the card.

ATA commands are basically a set of instructions for controlling an ATA-specification hard disk

drive, but as they comprise an extremely rationalized set of instructions, they can also be used for

other storage media devices. These commands are used to execute flash card reads, writes and

other operations.

4.1

Start-Up in Each Mode

The flash cards covered in this manual are the PC-ATA card (a PC card type flash card) and the

postage-stamp sized CF. With both of these cards, either of the following modes can be selected

by a pin setting at power-on.

1. PC-ATA specification mode

2. True-IDE specification mode

The PC-ATA specification mode is further subdivided into four access modes. When the card is

powered on, a transition is made to the respective address mode according to settings made in the

configuration registers.

Figure 4.1 shows an outline flowchart of the access mode setting procedure. The setting

procedures in each access mode are described in the following section.

51

START

Yes

OE pin =

low?

Decision

made at

power-on

No

PC-ATA

True-IDE

Set with lower bits D0–D5

Configuration

option REG.< 00h set

Memory-mode

Set with lower bits D0–D5

Configuration

option REG.< 01h set

Contiguous I/O-mode

Primary I/O-mode

Executed

after mode

is decided

Set with lower bits D0–D5

Configuration

option REG.< 02h set

Set with lower bits D0–D5

Configuration

option REG.< 03h set

Secondary I/O-mode

Configuration option reg. = add 200h in attribute area

Note: The lower 6 bits (D0–D5) of the configuration option register are used for mode setting.

D6 determines whether level or pulse mode is used for the interrupt signal.

D6 < 1: Level-mode interrupts

D6 < 0: Pulse-mode interrupts

D7 is the software reset bit.

D7 < 1: Software reset executed

* All registers are cleared to 0.

D7 < 0: Software reset cleared

Figure 4.1 Flash Card Access Mode Setting Flowchart

52

4.1.1

Switching between True-IDE and PC-ATA Specifications

Switching between True-IDE and PC-ATA specifications is performed at power-on.

Once the card starts up in a particular mode, the mode can only be switched by powering on again.

The mode cannot be switched by means of a hardware or software reset.

Mode switching is performed by confirming the ATASEL (OE pin) potential. ATASEL (OE pin)

checking is only performed at power-on.

Table 4.1 shows the relationship between the ATASEL potential referenced at power-on and

switching between PC-ATA specifications and True-IDE specifications.

Table 4.1 Mode Switching

No.

1

Mode

ATASEL Potential

Notes

PC-ATA

True-IDE

H

L

Subsequently operates as OE

Subsequently must constantly be held low

2

Note: If the ATASEL potential is set to the low level on the host side at power-on, but the card

identifies a high level due to noise, etc., the card will start up in PC-ATA mode. Adequate

noise prevention measures are therefore required for this pin.

53

4.2

Access Mode Switching when Using PC-ATA Specifications

In broad terms, the PC-ATA specifications include two access modes:

1. Memory Mode

2. I/O mode

The I/O mode is further subdivided into the following three access modes:

1. Primary I/O mode

2. Secondary I/O mode

3. Contiguous I/O mode

There are thus four access modes in all. (See section 3 for the access method in each mode, and

timing details.)

The differences between these operating modes are determined by the addresses to which the host

allocates the task file register section with respect to the card.

The register that sets these operating modes is the configuration option register in the attribute

region. The location of the task file region is determined by a setting in this register. Basically, the

task file registers can be allocated to both memory space and I/O space according to the setting in

this register.

The ability to change task file region addresses in this way is essential in order to maintain the

general applicability of the PC card. For example, while a memory card supports the four access

modes listed above, with fax, SCSI, and other cards, there are cases where only I/O mode access is

enabled, or where a task file region address is booked as the address of another I/O device for

reasons related to control on the host side. A flexible approach to register allocation is necessary in

order to avoid problems in such cases.

What, then, is the best access mode to use, as viewed from the system side?

In a system using an MPU with no I/O-related pins such as IOWR and IORD, for example, it may

be easier to use the card in memory mode, since both the attribute region and the task file region

are allocated to memory space in this mode. In other words, control can be performed with the RD

and WR signals, without the need for IOWR and IORD. In I/O mode, on the other hand, the RD

and WR signals are used for read and write accesses to the attribute region, while the IOWR and

IORD signals are used for accesses to the task file region. The number of signals used is thus

greater than in memory mode.

In any case, the access mode should be set for the card according to the system in which it is used.

54

4.2.1

Initialization (Access Mode Setting, Etc.)

After powering on in PC-ATA mode, as described in section 4.1.1, the first requirement is to

acquire card attribute data from the CIS section. The CIS section, as the name Card Information

Structure suggests, is a memory area that holds card attribute information. This information

includes the card’s operating voltage, the address of the configuration register section, and so on.

The CIS section is a ROM area in which only read access can be performed.

At first glance, reading the card information may seem unnecessary when always using a card of

the same model and capacity from the same manufacturer. In some cases, there may be no

problem if reading of the card attribute information is ignored. But with the possibility of future

revisions in the standards, sufficient system flexibility should be provided to enable any

manufacturer’s cards to be used. It is therefore probably advisable to enable a CIS section read to

be performed in terms of hardware, even if a card attribute check is not performed by the driver

software.

The CIS section holds a large amount of card attribute information. Actually reading all of this

data would be a considerable task, but the contents of the six registers shown in table 4.2, at least,

should be acquired.

Table 4.2 CIS Section Data Acquisition

No.

Tuple Identifier

Tuple Code

Description and Comments

1

01h

CISTPL_DEVICE

Device information. This tuple information is not

necessary for memory cards, but is essential

for fax, LAN, and other I/O cards.

2

3

15h

1Ah

CISTPL_VERS_1

CISTPL_CONF

Product information. Includes the product

information string, product name, product

number, and other manufacturer information.

Crucial information. Indicates the locations of

the configuration registers and their presence.

Configuration register allocation should be set

on the basis of this information.

4

1Bh

CISTPL_CE

Configuration table entry. Appropriate

configuration items are specified, including I/O

space, interrupts, memory, etc.

5

6

20h

21h

CISTPL_MANFID

CISTPL_FUNCID

Manufacturer’s identification. Holds the name of

the card manufacturer.

Function identifier. Provides function

information concerning the card. Also includes

system initialization information.

If information other than that shown above is needed, refer to the appendices or the data sheet.

55

The most important information in the above table is item 3, CISTPL_CONF, which holds the

addresses of the configuration registers. In current (June 1997) cards, the configuration registers

are assigned to even addresses starting at 200h in the attribute region, but this allocation may

change in the future. The configuration register address allocation should therefore be determined

on the basis of information read from the CIS section.

The internal arrangement of the configuration registers, and the various settings, are described on

the following pages.

56

Register Name: Configuration Option

Address:

Use:

200h in attribute memory

Card mode setting, interrupt level setting, software reset

Operation

R/W

D7

D6

D5

D4

D3

D2

D1

D0

SRESET LevIREQ Conf5

Conf4

Conf3

Conf2

Conf1

Conf0

Conf0–5:

The host can set the card access mode by making settings as shown in the

following table.

Conf2–5

Conf1

Conf0

Memory

0

1

0

1

0

1

Contiguous I/O

Primary I/O

Secondary I/O

Note: Conf2–5 must always be cleared to 0.

LevelREQ:

SRESET:

This bit is used to switch the interrupt signal mode.

0: Pulse mode interrupts

1: Level mode interrupts

This bit can be used to execute a software reset.

1. Set SRESET bit (D7) to 1:

2. Wait for time required for reset: 250 ms or more

3. Clear SRESET bit (D7) to 0: Reset cleared

Reset executed

The reset is not cleared unless SRESET is cleared to 0.

This differs from the case of hardware reset execution.

A reset clears all configuration register bits.

57

Register Name: Card Configuration & Status

Address:

Use:

202h in attribute memory

Indicates the card status.

Operation

Read

D7

Changed SigChg

SigChg

D6

D5

D4

0

D3

0

D2

D1

Int

0

D0

0

IOis8

PwrDwn

Write

0

Changed:

Indicates that 1 has been set in either the CRdy or CWProt bit in Pin

ReplacementREG.

In I/O mode, the STSCHG pin output is held low if this bit is set when the

SigChg bit is 1.

SigChg:

IOis8

Clearing of this bit to 0 by the host allows the Changed bit and STSCHG bit to

be disabled by the card. In this case, the STSCHG signal output is always “High

level”

When 8-bit I/O access is performed, the host should set this bit to 1.

With CompactFlash™, this bit has no meaning, since whether 8- or 16-bit access

is used is of no particular concern.

PwrDwn:

Setting this bit to 1 switches to power saving mode. Clearing this bit to 0 restores

normal mode.

When this bit changes, the card sets “Busy” and the Busy state is maintained

until the mode changes.

Hitachi cards also have an automatic power saving mode, so there will probably

be few occasions to use this bit.

INT:

This bit indicates the interrupt state. It is set to 1 by the card when the host issues

a read request, etc., to the card, and remains set to 1 until the interrupt source has

been serviced.

This bit can be disabled by the IEN bit in the device control register. In this case,

this bit holds a value of 0.

58

Register Name: Pin Replacement

Address:

Use:

204h in attribute memory

Indicates the card status.

Operation

Read

D7

0

D6

0

D5

D4

D3

0

D2

0

D1

D0

CRdy/-Bsy CWProt

Rdy/-Bsy RWProt

MRdy/-Bsy MWProt

Write

0

Rdy/-Bsy:

The host can identify the Rdy/-Bsy state by reading the state of this bit.

In I/O access mode, in particular, the Rdy/-Bsy bit is replaced by the IREQ pin,

but in this case too, the Rdy/-Bsy state can be identified by means of this bit.

CRdy/-Bsy:

RWProt:

When the Rdy/-Bsy bit changes, the card sets this bit to 1.

This bit can be modified by the host.

Indicates whether the card is in the write-protect state.

Hitachi cards do not support a write-protect function, so this bit is always cleared

to 0. Support for this function is not included in the CompactFlash™ standards,

either.

CWProt:

When the RWProt bit changes, the card sets this bit to 1. Since the RWProt bit is

never used, this bit is always 0.

This bit can be modified by the host.

MRdy/-Bsy:

MWProt:

Functions as a mask for write information to the CRdy/-Bsy bit. See the table

below.

Functions as a mask for write information to the CWProt bit. See the table

below.

Written by Host

Initial Value of (C) Status

“C” Bit

“M” Bit

Final “C” Bit

Command

0

1

×

0

1

0

1

0

1

0

1

Unchanged

Cleared by host

Set by host

59

Register Name: Socket and Copy

Address:

Use:

206h in attribute memory

Used for drive number setting.

Operation

Read

D7

Reserved

0

D6

0

D5

0

D4

D3

0

D2

0

D1

0

D0

0

Drive#

Write

0

×

Reserved:

Drive#:

Reserved for future use. When actually used, cleared to 0.

Indicates the number assigned to the drive in a system with a twin card

configuration.

With CompactFlash™, a twin card configuration is not supported, so this bit

should always be cleared to 0.

60

4.3

Switching Access Modes when Using True-IDE Specifications

Holding ATASEL (the OE pin) low when power is turned on causes the flash card to operate as a

True-IDE specification card. The ATASEL pin must then be held low continuously.

There are not a number of different access modes, as in the case of the PC-ATA specifications.

The task file region is fixed and access is only possible in the I/O space, giving in effect only one

access mode.

The features of these specifications are as follows.

(1) The location of the task file region is fixed, and cannot be varied.

(2) Form (1), it follows that access mode setting and other initialization tasks are not necessary.

(3) Only I/O space can be accessed.

(4) From (3), it follows that access is not possible anywhere in the memory space, including the

attribute region. With the PC-ATA specifications, therefore, its is not possible to access the

configuration registers or the CIS section.

For information on accesses after start-up, see the description of the True-IDE specifications in

section 3.

These specifications comprise a single, independent set of specifications, and are not a part of the

PC card standard, as in the case of the PC-ATA specifications.

The merit of these specifications is precisely that they are exclusively for handling a flash card as

a hard disk drive. Therefore, if the system side is specialized toward these specifications, it cannot

support a variety of different cards as in the case of the PCMCIA standard. These specifications

thus lack general applicability, but on the other hand, enable extremely simple circuitry and driver

software to be used.

Now that PC-ATA specifications and True-IDE specifications have been described, there is the

question of the choice of slot—PC-ATA compatible or True-IDE compatible—considered from

the system side.

True-IDE Specification Compatibility: If the user is prepared to use a card slot exclusively for

dedicated flash memory card use, as long as an auxiliary storage medium can be mounted, use

with the True-IDE specifications is the easiest approach. Actual access is easy, and there are far

fewer control signals than in the case of a PC card, so that peripheral circuitry and driver software

for the card can also be kept simple. This is the best solution if a flash card is to be used simply as

a storage medium.

However, if a card slot supporting only the True-IDE specifications is decided on, it will not be

possible to support cards with different functions, as provided for in the PCMCIA standard, and it

will probably never be possible to insert anything but a True-IDE specification flash card.

61

PC-ATA Specification Compatibility (PCMCIA Standard Compatibility): If the possibility of

using cards with various functions, such as fax/LAN and SCSI cards, in addition to flash cards is

considered, it is obvious that the design should provide for a card slot offering PCMCIA

compatibility. However, the operating circuitry is rather more complex than for the use of a True-

IDE specification card slot, and support must be provided for a variety of driver software, so that

the scale of both hardware and software can be expected to be greater. In this case, hardware

implementation will be made easier by using an MPU already equipped with a PCMCIA interface,

or a commercially available PC card controller chip.

MPUs equipped with a PCMCIA interface include the SH7708 and SH7709 (SH3) in Hitachi’s

SuperH microcomputer series.

4.4

Overview of ATA Commands

ATA commands are codes for controlling actual read/write operations, that are set in the command

register, one of the registers in the task file region. A flash card has approximately 30 commands,

but for the sake of brevity only the following five basic commands are outlined here.

1. Format

2. Erase Sector(s)

3. Stand-By

4. Read Sector(s)

5. Write Sector(s)

These commands are described below.

Table 4.3 lists the registers referenced by each command.

Table 4.3 Basic ATA Commands

No. Class Command Name

Code [Hex]

50

FR

—

SC

Y

SN

—

Y

CY

Y

DH

Y

LBA

Y

1

2

3

4

5

2

1

2

Format track

Erase sector(s)

Stand by

C0

Y

E2 or 96

20 & 21

30 & 31

—

Y

—

Y

—

Y

D

—

Y

Read sector(s)

Write sector(s)

Y

62

The meaning of the abbreviations used in table 4.3 is as follows.

FRFeature

register

SC

SN

CY

DH

LBA

Sector count

Sector number

Cylinder registers

Card/drive/head register

Logical block address mode

“Y” in the table means that the register is referenced when the ATA command is executed. For the

drive/head register, “Y” means that both the “Drive” and “Head” parameters are referenced, while

“D” means that only the “Drive” parameter is referenced.

ATA commands are divided into classes according to the execution mode, as shown below.

Class 1

Class 2

Bsy is set within 400 ns after command execution.

Bsy is set and the sector buffer for receiving write data from the host is prepared

within 400 ns after command execution. DRQ is set within 700 µs, and Bsy is

cleared within 400 ns after this.

Class 3

Bsy is set and the sector buffer for receiving write data from the host is prepared

within 400 ns after command execution. DRQ is set within 20 ms, and Bsy is

cleared within 400 ns after this.

Further details of ATA commands can be found in the specifications issued by the following

organizations:

1. ATA1 or ATA2 standard issued by ANSI (American National Standards Institute)

2. CompactFlash™ standard specification issued by the CFA

3. PCMCIA2.1 issued by the PCMCIA

4. Hitachi flash card data sheet

63

Command Name: Format Track

Bit

7

6

5

1

4

3

2

1

0

Command

C/D/H

7

6

5

4

3

2

1

50

1

LBA

Drive

Head (LBA27–24)

Cyl High

Cyl Low

Sec Num

Set Cnt

Feature

Cylinder High

Cylinder Low

× (LBA7–0)

Count (LBA mode only)

×

When a card receives this command, it writes FF to all 32 sectors for the specified drive, cylinder,

and head. In executing this command, it is assumed that write data is transferred from the host in

the same way as with the WriteSector(s) command, but the received data is not actually written.

The purpose of this is to maintain compatibility with the standard ATA commands.

When operating in LBA mode, the card writes the numeric value specified in the SectorCount

register to the sectors.

Command Name: Erase Sector

Bit

7

1

6

5

1

4

3

2

1

0

Command

C/D/H

7

6

5

4

3

2

1

C0

LBA

Drive

Head (LBA27–24)

Cyl High

Cyl Low

Sec Num

Set Cnt

Feature

Cylinder High (LBA23–16)

Cylinder Low (LBA15–8)

Sector Number (LBA7–0)

Sector Count

×

This command is basically only an erase command, but in fact also handles updating of header

information. Consequently, it is also assumed that errors will occur due to write abnormalities, and

so this must be taken into account when writing programs.

Note: Header information: Corresponds to HDD servo information.

There is individual header information for each sector, containing information such as the

logical address of the sector and the number of times the sector has been rewritten.

64

Command Name: Stand By

Bit

7

6

5

4

3

2

1

0

Command

C/D/H

7

6

5

4

3

2

1

E2 or 96

Drive

×

Cyl High

Cyl Low

Sec Num

Set Cnt

Feature

×

After receiving this command, the card generates an interrupt immediately after (1) Bsy setting →

(2) sleep mode transition* → Bsy clearing processing.

Standby mode can only be cleared by issuance of another command by the host.

When standby is cleared, reset processing can be carried out, but this is not essential.

Note: * Corresponds to standby mode in the ATA standard.

65

Command Name: Read Sector(s)

Bit

7

1

6

5

1

4

3

2

1

0

Command

C/D/H

7

6

5

4

3

2

1

20 & 21

Drive

LBA

Head (LBA27–24)

Cyl High

Cyl Low

Sec Num

Set Cnt

Feature

Cylinder High (LBA23–16)

Cylinder Low (LBA15–8)

Sector Number (LBA7–0)

Sector Count

×

When this command is issued, the number of sectors set in the SectorCount register can be read,

starting at the sector set in the SectorNumber register. A value of 01H to 0FFH can be set in the

SectorCount register. Inputting 00H is equivalent to inputting FFH.

When the card receives this command, it performs the following operations:

1. If there is unprocessed data left in the sector buffer for any reason, the card waits until that data

has been processed.

2. Bsy setting → data setting in sector buffer → DRQ setting → Bsy clearing

3. Interrupt generation

4. Data can then be fetched from the sector buffer.

5. If the processing ends normally, the following data is set in the CommandBlock register:

— Last read cylinder number, head number, and sector number

6. If the processing ends abnormally, the operation in which the error occurred is aborted, and the

following data is set in the CommandBlock register:

— Cylinder number, head number, and sector number at which the error occurred

The data in the sector buffer is the data of the sector in which the error occurred.

66

Command Name: Write Sector(s)

Bit

7

1

6

5

1

4

3

2

1

0

Command

C/D/H

7

6

5

4

3

2

1

30 & 31

Drive

LBA

Head (LBA27–24)

Cyl High

Cyl Low

Sec Num

Set Cnt

Feature

Cylinder High (LBA23–16)

Cylinder Low (LBA15–8)

Sector Number (LBA7–0)

Sector Count

×

When this command is issued, the number of sectors set in the SectorCount register can be written,

starting at the sector set in the SectorNumber register. A value of 01H to FFH can be set in the

SectorCount register. Inputting 00H is equivalent to inputting FFH.

When the card receives this command, it performs the following operations:

1. Bsy setting → data setting in sector buffer → DRQ setting → Bsy clearing

2. Waits for 512 bytes of data to be sent by the host.

An interrupt is not generated at this time, as in the case of a read operation.

The host must not perform data transfer until Bsy is cleared.

3. If the processing ends normally, the following data is set in the CommandBlock register:

— Last read cylinder number, head number, and sector number

4. If the processing ends abnormally, the operation in which the error occurred is aborted, and the

following data is set in the CommandBlock register:

— Cylinder number, head number, and sector number at which the error occurred

The data in the sector buffer is the data of the sector in which the error occurred.

The host can find out what kind of error occurred in which sector by accessing the

CommandBlock register.

67

Section 5 Application Examples for Systems with

Embedded CF

When a flash card is used for an embedded application, the application can be implemented most

easily by using the True-IDE specifications. If the use of PC cards for various purposes is

envisaged, it is probably better to use a PC card controller chip employed in notebook PCs, etc., or

to use an MPU with a PCMCIA interface (such as the SH3, SH7708, or SH7709 in Hitachi’s

SuperH microcomputer series) as the CPU. This is because, while the level of general applicability

is high with the PC-ATA specifications, a large number of conditions have to be satisfied,

resulting in a proportionate increase in the size of both hardware and software. Thus it is

extremely difficult to implement peripheral circuitry using TTL devices, etc.

If the True-IDE specifications are used, on the other hand, an interface circuit can be implemented

very easily, as shown in figure 5.1, Block Diagram, on the next page. The down side is that it is

not possible to use a variety of PC cards. This configuration only provides for the use of a flash

card in the same way as a hard disk drive.

5.1

True-IDE Interface Block Circuit

5.1.1

Outline

Use of this circuit presupposes the following conditions. This circuit should not be used unless

these conditions are accepted.

•

This circuit is subject to the conditions listed in section 5.1.2, Notes, and is only a reference

example.

•

Hitachi, Ltd., accepts no responsibility for any problems arising out of the use of this circuit.

No engineering services have been implemented with regard to the contents of this circuit.

This circuit may be freely used by anybody.

5.1.2

Notes

(1) Hitachi PCMCIA PC-ATA specification card: Use an HB286***AT or later model.

(2) (1) or Hitachi CompactFlash™: Use an HB286***C*.

(3) Use the True-IDE specifications.

(4) The third party below provides support for driver software. Inquiries should be directed to the

address shown.

AI Corporation, Production Department

IIjima Bldg. 6F, Nishi-Gotanda 2-25-2, Shinagawa-ku, Tokyo

Tel: (03) 3493-7981

Fax: (03) 3493-7993

69

Sample Interface Circuit when Using True-IDE Mode

MPU

CF card

A0–A2

A0–A3

Add. bus

A0–A2

A3

CE1

CE2

7

CE1

CE2

IORD

IOWR

CS

WR/RD

Bus CLK

32

Interface

logic

IORD 34

IOWR 35

41

42

37

24

RESET

WAIT

INTRQ

IOIS16

Data bus

D0–D7/15

A3–A10

GND

1 k

1, 50

GND

0.1 µF

1 k

1.0 µF

+

39

9

CSEL

ATASEL

V_CC

13, 38

V_CC

1 k

36

44

WE

REG

Master mode only

Figure 5.1 Block Diagram

70

Host side

A3

Card side

CE2

CE1

D

DFF

Q

D

DFF

Q

CS

CLK

IORD

IOWR

WR/RD

Figure 5.2 Interface Logic

Min 33 ns

CLK

A0–A3

Host side

CS

WR/RD

CE1 or

CE2

1 CLK cycle

Min. 165 ns

Card side

IORD or

IOWR

Max 100 ns

Dout

(Read)

Min 30ns

Min 60 ns

Din

(Write)

Figure 5.3 Interface Logic Timing Waveforms

71

Table 5.1 True-IDE Mode Access

Register

No.

Register Name

R/W

WR/RD A3

RL

A2

A1

A0

Attribute

0

Even

data

0

1

0

R

/W

W

R

H

L

1

2

3

4

5

6

7

8

9

Error REG.

Feature REG.

Sector

0

1

0

1

0

1

0

1

0

1

0

1

0

1

R only

W only

R

W

H

count

no

RL

H

/W

W

Sector

RL

H

R

Cylinder

Select

low

RL

H

high

RL

H

card/head

RL

H

W

Status

RL

W

R only

W only

R only

W only

R only

W only

Command

H

RL

H

Alt

status

Drive control

Drive

W

address

RL

H

Reserved

72

5.2

Connector Information

The products shown below are available as sockets for use when providing a PC card or CF slot.

(The following products are not guaranteed or recommended by Hitachi.)

1. For PC card slot

Manufacturer

Product Code

AXP121121

AXP122121

AXP121122

AXP122122

177961-1

Matsushita Electric Works, Ltd.

AMP

(Header; with ejector; 1 slot)

(Header; with ejector; 2 slot)

(Header; with ejector; 1 slot)

(Header; with ejector; 2 slot)

(Header; with ejector; 1 slot)

AMP

177964-1

2. For CompactFlash™

Manufacturer

Product Code

3M

N7E50-7516VY-20

D7E50-7516-02

JC26-CS20LH

JC26-CS20L

(Header)

3M

(Ejector)

JAE

(Header; with ejector)

(Header; without ejector)

JAE

JST

ICM-MA50H-SS52 (Header)

Hosiden Corporation

CCD3003-010020

CCD3003-010010

CCD3003-010100

(Header)

(Ejector)

Note: CompactFlash™ can also be mounted in a PCMCIA slot (Type II or Type III) by inserting

it in a special adapter. PC card adapters are available from any bulk electrical products

supplier.

73

Appendix A CIS Information

CIS addresses are defined as shown below, starting at address 000H in the attribute region. These

addresses are read-only.

Address Data

7

6

5

4

3

2

1

0

Description of Contents

Device info tuple

CIS Function

Tuple code

000H

002H

004H

01H CISTPL DEVICE

04H TPL_LINK

Link length is 4 byte

Link to next tuple

DFH Device type

WPS Device speed

Device type = DH: I/O device Device type,

WPS = 0: No WP

WPS, speed

Device speed = 7: ext speed

006H

008H

00AH

00CH

4AH EXT Speed mantissa

01H 1x

Speed exponent

2k units

400 ns if no wait

Extended speed

Device size

2 kbyte of address space

End of device

FFH List end marker

1CH CISTPL DEVICE OC

END marker

Tuple code

Other conditions device info

tuple

00EH

010H

04H TPL_LINK

Link length is 4 bytes

Link to next tuple

02H EXT Reserved

V_CC

MWAIT 3 V, wait is used

Other conditions

info field

012H

D9H Device type

WPS Device speed

Device type = DH: I/O device Device type,

WPS = 0: No WP

WPS, speed

Device speed = 1: 250 ns

014H

016H

018H

01AH

01CH

01H 1x

2 k units

2 kbyte of address space

End of device

Device size

END marker

FFH List end marker

18H CISTPL JEDEC C

02H TPL_LINK

JEDEC ID common memory Tuple code

Link length is 2 bytes

Link to next tuple

DFH PCMCIA’s manufacturer’s JEDEC ID code

Manufacturer’s ID code

JEDEC ID of PC

Card ATA

01EH

020H

022H

024H

01H PCMCIA JEDEC device code

20H CISTPL MANFID

2nd byte of JEDEC ID

Manufacturer’s ID code

Link length is 4 bytes

Tuple code

04H TPL_LINK

Link to next tuple

07H Low byte of PCMCIA manufacturer’s code

HITACHI JEDEC

manufacturer’s ID

Low byte of

manufacturer’s ID

code

026H

00H High byte of PCMCIA manufacturer’s code

Code of 0 because other byte High byte of

is JEDEC 1 byte manufac ID manufacturer’s ID

code

028H

02AH

00H Low byte of product code

00H High byte of product code

HITACHI code for PC CARD Low byte of

ATA

product code

High byte of

product code

75

Address Data

7

6

5

4

3

2

1

0

Description of Contents

Level 1 version/product info

Link length is 15h bytes

CIS Function

Tuple code

Link to next tuple

version

02CH

02EH

030H

032H

034H

036H

038H

03AH

03CH

03EH

040H

042H

044H

046H

048H

04AH

04CH

04EH

050H

052H

054H

056H

058H

05AH

05CH

05EH

15H CISTPL_VER_1

15H TPL_LINK

04H TPPLV1_MAJORPCMCIA2.0/JEIDA4.1

Major

Minor

01H TPPLV1_MINORPCMCIA2.0/JEIDA4.1

version

48H

‘ H ’

Info string 1

49H

‘ I ’

54H

‘ T ’

41H

‘ A ’

43H

‘ C ’

48H

‘ H ’

49H

‘ I ’

00H

Null terminator

46H

‘ F ’

Info string 2

4CH

‘ L ’

41H

‘ A ’

53H

‘ S ’

48H

‘ H ’

00H

Null terminator

‘ 2 ’

32H

Vender specific

strings

2EH

‘ . ’

30H

‘ 0 ’

00H

Null terminator

End of device

Function ID tuple

Link length is 2 bytes

FFH List end marker

21H CISTPL MANFID

02H TPL_LINK

04H TPLFID_FUNCTION = 04H

END marker

Tuple code

Link to next tuple

Disk function, may be silicon, PC card function

may be removable

code

060H

01H Reserved

R

P

R = 0: No BIOS ROM

System

initialization byte

P = 1: Configure card at

power on

76

Address Data

7

6

5

4

3

2

1

0

Description of Contents

Function extension tuple

Link length is 2 bytes

Disk interface type

CIS Function

Tuple code

062H

064H

066H

22H CISTPL FUNCE

02H TPL_LINK

Link to next tuple

01H Disk function extension tuple type

Extension tuple

type for disk

068H

06AH

06CH

06EH

01H Disk interface type

22H CISTPL FUNCE

PC card ATA interface

Function extension tuple

Link length is 3 bytes

Single drive

Interface type

Tuple code

03H TPL_LINK

Link to next tuple

02H Disk function extension tuple type

Extension tuple

type for disk

070H

0CH Reserved

D

U

S

V

No V_PP, silicon, single drive

V = 0: No V_PPrequired

S = 1: Silicon

Basic ATA option

parameters byte 1

U = 1: Unique serial #

D = 1: Single drive on card

072H

0FH RI

E

N

P3

P2

P1

P0

P0:

Sleep

mode

suBpapsoicrteAdTA option

P1: Standby mode supported parameters byte 2

P2: Idle mode suppported

P3: Drive auto control

N: Some config excludes

3X7

E: Index bit is emulated

I:

Twin IOIS16# data reg

only

R: Reserved

074H

076H

078H

1AH CISTPL CONF

05H TPL LINK

01H RFS

Configuration tuple

Link length is 5 bytes

RFS: Reserved

Tuple code

Link to next tuple

Size of fields byte

RMS

RAS

RMS:TPCC_RMSK size - 1 = TPCC_SZ

0

RAS: TPCC_RADR size - 1 =

1

1 byte register mask

2 byte config base address

07AH

07CH

03H TPCC_LAST

Entry with config index of 3 is Last entry of

fainal entry in table

config registers

00H TPCC RADR (LSB)

Configuration registers are

located at 200 H in REG

space

Location of config

registers

07EH

080H

02H TPCC RADR (MSB)

0FH Reserved

S

P

C

I

I: CCOR, C: CCSR

P: PRR, S: SCR

Configuration

registers present

mask

TPCC_RMSK

77

Address Data

7

6

5

4

3

2

1

0

Description of Contents

CIS Function

082H

084H

086H

1BH CISTPL_CFTABLE ENTRY

08H TPL_LINK

Configuration table entry tuple Tuple code

Link length is 8 bytes

Link to next tuple

C0H

I

D

Configuration index

Memory mapped I/O

configuration

I = 1: Interface byte follows

D = 1: Default entry

Configuration index = 0

Configuration

table index byte

TPCE_INDX

088H

08AH

W

RP

B

Interface

type

W

=

0:

WInatietrface not

description field

TPCE_IF

used

R = 1:

P = 0:

B = 0:

Ready active

WP not used

BVD1 and BVD2

not used

IF type = 0: Memory interface

A1H

M

MS

IRIO

T

P

M

=

1: Misc

Finefoature seplreecsteionnt

MS = 01: Memory space info byte

single 2-byte length TPCE_FS

IR = 0: No interrupt info

present

IO = 0: No I/O port info

present

T = 0:

No timing info

present

P = 1:

V

_CConly info

08CH

01H RDI

PI

AI

SI

HV

LV

NV

Nominal

voltage

only

Pofwolelorwpsara-

R: Reserved

meters for V_CC

DI: Power down current info

PI: Peak current info

AI: Average current info

SI: Static current info

HV: Max voltage info

LV: Min voltage info

NV: Nominal voltage info

08EH

090H

55H

X

Mantissa

Exponent

Nominal voltage = 5 V

V_CCnominal value

08H Length in 256 bytes pages (LSB)

Length of memory space is

2 kB

Memory space

description

structures (TPCE

MS)

092H

094H

00H Length in 256 bytes pages (MSB)

20H

X

RP

O

RA

T

X

=

0:

No

more Miscmelilsacneous fields

features field

R:

Reserved

P = 1: Power down

supported

TPCE_MI

RO = 0: Not read only mode

A = 0: Audio not supported

T = 0: Single drive

78

Address Data

7

6

5

4

3

2

1

0

Description of Contents

CIS Function

096H

098H

09AH

1BH CISTPL_CFTABLE ENTRY

06H TPL_LINK

Configuration table entry tuple Tuple code

Link length is 6 bytes

Link to next tuple

00H

01H

I

D

Configuration index

Memory mapped I/O

configuration

I = 0: No Interface byte

D = 0: No Default entry

Configuration index = 0

Configuration

table index byte

TPCE_INDX

09CH

M

MS

IRIO

T

P

M

=

0:

No

MFisecature sienlfeoction

MS = 00: No Memory space byte

info

TPCE_FS

IR = 0: No interrupt info

present

IO = 0: No I/O port info

present

T = 0:

No timing info

present

P = 1:

V

_CConly info

09EH

21H RDI

PI

AI

SI

HV

LV

NV

Nominal

voltage

only

Pofwolelorwpsara-

R: Reserved

meters for V_CC

DI: Power down current info

PI: Peak current info

AI: Average current info

SI: Static current info

HV: Max voltage info

LV: Min voltage info

NV: Nominal voltage info

0A0H

0A2H

0A4H

B5H

1EH

4DH

X

Mantissa

Exponent

Nominal voltage = 3.0 V

+0.3 V

V_CCnominal value

Extension byte

Max average current over 10 Max. average

msec is 45 mA current

79

Address Data

7

6

5

4

3

2

1

0

Description of Contents

CIS Function

0A6H

0A8H

0AAH

1BH CISTPL_CFTABLE ENTRY

0AH TPL_LINK

Configuration table entry tuple Tuple code

Link length is 10 bytes

Link to next tuple

C1H

41H

I

D

Configuration INDEX

Contiguous I/O mapped ATA Configuration

registers configuration

table index byte

I = 1: Interface byte follows TPCE_INDX

D = 1: Default entry

Configuration index = 1

0ACH

0AEH

W

RP

B

Interface

type

W

=

0:

WInatietrface not

description field

TPCE_IF

used

R = 1:

P = 0:

B = 0:

Ready active

WP not used

BVS1 and BVD2

not used

IF type = 1: I/O interface

99H

M

MS

IRIO

T

P

M

=

1: Misc

Finefoature seplreecsteionnt

MS = 00: No memory space byte

info

TPCE_FS

IR = 1: Interrupt info

present

IO = 0: No I/O port info

present

T = 0:

No timing info

present

P = 1:

V

_CConly info

0B0H

01H RDI

PI

AI

SI

HV

LV

NV

Nominal

voltage

only

Pofwolelorwpsara-

R: Reserved

meters for V_CC

DI: Power down Current info

PI: Peak current info

AI: Average current info

SI: Static current info

HV: Max voltage info

LV: Min voltage info

NV: Nominal voltage info

0B2H

0B4H

55H

X

Mantissa

E

Exponent

Nominal voltage = 5 V

V_CCnominal value

64H RS

IO

AddrLine

S

=

1:

1I/6O-bsipt ace hosts

description field

TPCE_IO

supported

8-bit hosts

supported

E = 1:

IO AddrLine: 4 lines decoded

0B6H

F0H

S

P

L

M

V

B

I

N

S = 1: Share logic active

P = 1: Pulse mode IRQ

supported

Interrupt request

description

structure

L = 1: Level mode IRQ

supported

TPCE_IR

M = 1: Bit mask of IRQs

present

V = 0: No vender unique IRQ

B = 0: No bus error IRQ

I = 0: No IO check IRQ

N = 0: No NMI

80

Address Data

7

6

5

4

3

2

1

0

Description of Contents

CIS Function

0B8H

0BAH

0BCH

FFH IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 IRQ level to be routed 0 to 15 Mask extension

recommended

byte 1

TPCE_IR

FFH IRQ15 IRQ14 IRQ13 IRQ12 IRQ11 IRQ10 IRQ9 IRQ8 Recommended routing to any Maskextension

“normal, maskable” IRQ.

byte 2

TPCE_IR

20H

X

RP

O

RA

T

X

=

0:

Nomore

reserved

mMisciscellanefioeuldss

features field

TPCE_MI

R:

P = 1: Power down

supported

RO = 0: Not read only mode

A = 0: Audio not supported

T = 0: Single drive

81

Address Data

7

6

5

4

3

2

1

0

Description of Contents

CIS Function

0BEH

0C0H

0C2H

1BH CISTPL_CFTABLE ENTRY

06H TPL_LINK

Configuration table entry tuple Tuple code

Link length is 6 bytes

Link to next tuple

01H

I

D

Configuration index

Contiguous I/O mapped ATA Configuration

registers configuration

I = 0: No Interface byte

D = 0: No Default entry

Configuration index = 1

table index byte

TPCE_INDX

0C4H

M

MS

IRIO

T

P

M

=

0:

No

MFisecature sienlfeoction

byte

TPCE_FS

MS = 00: No Memory

space info

IR = 0: No interrupt info

present

IO = 0: No I/O port info

present

T = 0:

No timing info

present

P = 1:

V

_CConly info

0C6H

21H RDI

PI

AI

SI

HV

LV

NV

Nominal

voltage

only

Pofwolelorwpsara-

R: Reserved

meters for V_CC

DI: Power down current info

PI: Peak current info

AI: Average current info

SI: Static current info

HV: Max voltage info

LV: Min voltage info

NV: Nominal voltage info

0C8H

0CAH

0CCH

B5H

1EH

4DH

X

Mantissa

Exponent

Nominal voltage = 3.0 V

+0.3 V

V_CCnominal value

Extension byte

Max average current over 10 Max. average

msec is 45 mA current

82

Address Data

7

6

5

4

3

2

1

0

Description of Contents

CIS Function

0CEH

0D0H

0D2H

1BH CISTPL_CFTABLE ENTRY

0FH TPL_LINK

Configuration table entry tuple Tuple code

Link length is 15 bytes

Link to next tuple

C2H

41H

I

D

Configuration INDEX

ATA primary I/O mapped

configuration

Configuration

table index byte

I = 1: Interface byte follows TPCE_INDX

D = 1: Default entry follows

Configuration index = 2

0D4H

0D6H

W

RP

B

Interface

type

W

=

0:

WInatietrface not

description field

TPCE_IF

used

R = 1:

P = 0:

B = 0:

Ready active

WP not used

BVS1 and BVD2

not used

IF type = 1: I/O interface

99H

M

MS

IRIO

T

P

M

=

1: Misc

Finefoature seplreecsteionnt

MS = 00: No memory space byte

info

TPCE_FS

IR = 1: Interrupt info

present

IO = 0: No I/O port info

present

T = 0:

No timing info

present

P = 1:

V

_CConly info

0D8H

01H RDI

PI

AI

SI

HV

LV

NV

Nominal

voltage

only

Pofwolelorwpsara-

R: Reserved

meters for V_CC

DI: Power down Current info

PI: Peak current info

AI: Average current info

SI: Static current info

HV: Max voltage info

LV: Min voltage info

NV: Nominal voltage info

0DAH

0DCH

55H

X

R

Mantissa

Exponent

Nominal voltage = 5 V

V_CCnominal value

EAH

S

E

IO AddrLine

R = 1:

S = 1:

Range follows

16-bit hosts

supported

I/O space

description field

TPCE_IO

E = 1:

8-bit hosts

supported

IO AddrLines:10 lines

decoded

0DEH

61H LS

AS

N range

LS = 1:

AS = 2:

Size of lengths I/O range format

is 1 byte

description

Size of address

is 2 byte

N Range = 1: Address

range - 1

83

Address Data

7

6

5

4

3

2

1

0

Description of Contents

CIS Function

0E0H

F0H

1st I/O base address (LSB)

1st I/O range

address

0E2H

0E4H

01H

07H

1st I/O base address (MSB)

1st I/O length - 1

1st I/O range

length

0E6H

F6H

2nd I/O base address (LSB)

2nd I/O range

address

0E8H

0EAH

03H

01H

2nd I/O base address (MSB)

2nd I/O length - 1

2nd I/O range

length

0ECH

EEH

S

P

L

M

IRQ level

S = 1: Share logic active

P = 1: Pulse mode IRQ

supported

Interrupt request

description

structure

L = 1: Level mode IRQ

supported

TPCE_IR

M = 0: Bit mask of IRQs

present

IRQ level is IRQ14

0EEH

20H

X

RP

O

RA

T

X

=

0:

No

reserved

more Miscmelilsacneous fields

features field

R:

P = 1: Power down

supported

TPCE_MI

RO = 0: Not read only mode

A = 0: Audio not supported

T = 0: Single drive

84

Address Data

7

6

5

4

3

2

1

0

Description of Contents

CIS Function

0F0H

0F2H

0F4H

1BH CISTPL_CFTABLE ENTRY

06H TPL_LINK

Configuration table entry tuple Tuple code

Link length is 6 bytes

Link to next tuple

02H

01H

I

D

Configuration index

ATA primary I/O mapped

configuration

I = 0: No Interface byte

D = 0: No Default entry

Configuration index = 2

Configuration

table index byte

TPCE_INDX

0F6H

M

MS

IRIO

T

P

M

=

0:

No

MFisecature sienlfeoction

MS = 00: No Memory space byte

info

TPCE_FS

IR = 0: No interrupt info

present

IO = 0: No I/O port info

present

T = 0:

No timing info

present

P = 1:

V

_CConly info

0F8H

21H RDI

PI

AI

SI

HV

LV

NV

Nominal

voltage

only

Pofwolelorwpsara-

R: Reserved

meters for V_CC

DI: Power down current info

PI: Peak current info

AI: Average current info

SI: Static current info

HV: Max voltage info

LV: Min voltage info

NV: Nominal voltage info

0FAH

0FCH

0FEH

B5H

1EH

4DH

X

Mantissa

Exponent

Nominal voltage = 3.0 V

+0.3 V

V_CCnominal value

Extension byte

Max average current over 10 Max average

msec is 45 mA current

85

Address Data

7

6

5

4

3

2

1

0

Description of Contents

CIS Function

100H

102H

104H

1BH CISTPL_CFTABLE ENTRY

0FH TPL_LINK

Configuration table entry tuple Tuple code

Link length is 15 bytes

Link to next tuple

C3H

41H

I

D

Configuration INDEX

ATA secondary I/O mapped

configuration

Configuration

table index byte

I = 1: Interface byte follows TPCE_INDX

D = 1: default entry

Configuration index = 3

106H

108H

W

RP

B

Interface

type

W

=

0:

WInatietrface not

description field

TPCE_IF

used

R = 1:

P = 0:

B = 0:

Ready active

WP not used

BVS1 and BVD2

not used

IF type = 1: I/O interface

99H

M

MS

IRIO

T

P

M

=

1: misc

Finefoature seplreecsteionnt

MS = 00: No memory space byte

info

TPCE_FS

IR = 1: Onterrupt info

present

IO = 0: No I/O port info

present

T = 0:

No timing info

present

P = 1:

V

_CConly info

10AH

01H RDI

PI

AI

SI

HV

LV

NV

Nominal

voltage

only

Pofwolelorwpsara-

R: Reserved

meters for V_CC

DI: Power down Current info

PI: Peak current info

AI: Average current info

SI: Static current info

HV: Max voltage info

LV: Min voltage info

NV: Nominal voltage info

10CH

10EH

55H

X

R

Mantissa

Exponent

Nominal voltage = 5 V

V_CCnominal value

EAH

S

E

IO AddrLine

R = 1:

S = 1:

Range follows

16-bit hosts

supported

I/O space

description field

TPCE_IO

E = 1:

8-bit hosts

supported

IO AddrLines:10 lines

decoded

110H

61H LS

AS

N range

LS = 1:

AS = 2:

Size of lengths I/O range format

is 1 byte

description

Size of address

is 2 byte

N Range = 1: Address

range - 1

86

Address Data

7

6

5

4

3

2

1

0

Description of Contents

CIS Function

112H

70H

1st I/O base address (LSB)

1st I/O range

address

114H

116H

01H

07H

1st I/O base address (MSB)

1st I/O length - 1

1st I/O range

length

118H

76H

2nd I/O base address (LSB)

2nd I/O range

address

11AH

11CH

03H

01H

2nd I/O base address (MSB)

2nd I/O length - 1

2nd I/O range

length

11EH

EEH

S

P

L

M

IRQ level

S = 1: Share logic active

P = 1: Pulse mode IRQ

supported

Interrupt request

description

structure

L = 1: Level mode IRQ

supported

TPCE_IR

M = 0: Bit mask of IRQs

present

IRQ level isIRQ14

120H

20H

X

RP

O

RA

T

X

=

0:

Nomore

reserved

mMisciscellanefioeuldss

features field

TPCE_MI

R:

P = 1: Power down

supported

RO = 0: Not read only mode

A = 0: Audio not supported

T = 0: Single drive

87

Address Data

7

6

5

4

3

2

1

0

Description of Contents

CIS Function

122H

124H

126H

1BH CISTPL_CFTABLE ENTRY

06H TPL_LINK

Configuration table entry tuple Tuple code

Link length is 6 bytes

Link to next tuple

03H

01H

I

D

Configuration index

ATA secondary I/O mapped

configuration

I = 0: No Interface byte

D = 0: No Default entry

Configuration index = 3

Configuration

table index byte

TPCE_INDX

128H

M

MS

IRIO

T

P

M

=

0:

No

MFisecature sienlfeoction

MS = 00: No Memory space byte

info

TPCE_FS

IR = 0: No interrupt info

present

IO = 0: No I/O port info

present

T = 0:

No timing info

present

P = 1:

V

_CConly info

12AH

21H RDI

PI

AI

SI

HV

LV

NV

Nominal

voltage

only

Pofwolelorwpsara-

R: Reserved

meters for V_CC

DI: Power down current info

PI: Peak current info

AI: Average current info

SI: Static current info

HV: Max voltage info

LV: Min voltage info

NV: Nominal voltage info

12CH

12EH

130H

B5H

1EH

4DH

X

Mantissa

Exponent

Nominal voltage = 3.0 V

+0.3 V

V_CCnominal value

Extension byte

Max average current over 10 Max average

msec is 45 mA

No link control tuple

Link is 0 bytes

current

132H

134H

136H

14H CISTPL_NO_LINK

00H

Tuple code

Link to next tuple

Tuple code

FFH CISTPL_END

End of list tuple

88

Appendix B Descriptions of Task File Registers

Data Register: This is a 16-bit readable/writable register used in sector-unit data transfer between

the host and the card. Word, byte, and odd-byte accesses defined in the PC card standard can all be

used on this register, but part of the address is shared with the error register when reading and the

feature register when writing.

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

D0 to D15

Error Register: This is a read-only register used in the analysis of error contents during card

access. This register is valid when the BSY bit is 0 (“Ready”) in the status register and alternate

status register.

Bit 7

BBK

Bit 6

UNC

Bit 5

“0”

Bit 4

Bit 3

“0”

Bit 2

Bit 1

“0”

Bit 0

IDNF

ABRT

AMNF

Bit

7

Name

Function

This bit is set if a bad block is detected.

BBK (Bad BlocK detected)

UNC (Data ECC error)

IDNF (I D Not Found)

6

This bit is set if an uncorrectable ECC error is detected.

4

This bit is set if there is an error in the access target

sector or if that sector is not present.

2

0

ABRT (ABoRTed command)

This bit is set if a command is aborted due to the card

status (Not ready, Write fault, etc.), or if an unsupported

command is executed.

AMNF (Address Mark Not Found) This bit is set in case of the general error state.

Feature Register: This is a write-only register used when the host sets a specific function for the

card.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Feature byte

Sector Register: The number of sectors for read/write transfer between the host and the card is set

in this register by the host. If a value of 00H is set in this register, the sector count is 256. In the

case of multiple sector transfers, if the command ends abnormally the number of unprocessed

sectors is stored in this register. The initial value of this register is 01H.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Sector count byte

89

Sector Number Register: The sector number at which sector transfer is to start is set in this

register.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Sector number byte

Cylinder Low Register: The lower 8 bits of the cylinder number at which sector transfer is to

start are set in this register.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Cylinder low byte

Cylinder High Register: The upper 8 bits of the cylinder number at which sector transfer is to

start are set in this register.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Cylinder high byte

Drive Head Register: The card drive number and the head number at which sector transfer is to

start are set in this register.

Bit 7

1

Bit 6

LBA

Bit 5

1

Bit 4

DRV

Bit 3

Bit 2

Bit 1

Bit 0

Head number

Bit

7

Name

Function

1

Set this bit to 1.

6

LBA

Used to switch between operation in cylinder/head/sector (CHS) mode

and logical block address (LBA) mode. CHS mode is selected when

LBA = 0, and CHS mode when LBA = 1. In LBA mode, the logical block

addresses correspond to the following register bits.

LBA07-LBA00: Sector Number Register D7–D0.

LBA15-LBA08: Cylinder Low Register D7–D0.

LBA23-LBA16: Cylinder High Register D7–D0.

LBA27-LBA24: Drive/Head Register bits HS3–HS0.

5

4

1

Set this bit to 1.

DRV (DRiVe

select)

This bit is used for selection in a master/slave configuration. When the

DRV# bit in the socket and copy register and this bit match, the card

can be accessed.

3 to 0 Head number

These bits specify the head number at which sector transfer is to start.

Bit 3 is the MSB.

90

Status Register: This is a read-only register that notifies the host of the card status when a

command is executed. If the card is configured in I/O card mode (INDEX = 1, 2, 3) and level

interrupt mode, the IREQ signal pin is negated by reading this register.

Bit 7

BSY

Bit 6

Bit 5

Bit 4

DSC

Bit 3

Bit 2

Bit 1

IDX

Bit 0

ERR

DRDY

DWF

DRQ

CORR

Bit

Name

BSY (BuSY)

Function

7

This bit is set to 1 when internal card processing is being

executed. When this bit is 1, the other bits in this register

are invalid.

6

DRDY (Drive ReaDY)

This bit is set to 1 when internal card processing ends and

access from the host can be accepted.

5

4

3

DWF (Drive Write Fault)

This bit is set to 1 if a write fault occurs in the card.

DSC (Drive Seek Complete) This bit is set to 1 when a drive seek is completed.

DRQ (Data ReQuest)

This bit is set to 1 when preparations are completed for

data transfer between the host and the card.

2

CORR (CORRected data)

This bit is set to 1 when a correctable error has occurred in

internal card processing and the error has been corrected.

1

0

IDX (InDeX)

This bit is always cleared to 0.

ERR (ERRor)

This bit is set to 1 if an error occurs during processing of

the input command. Supplementary error information is set

in the error register. This bit is cleared by input of the next

command.

Alternate Status Register: Physically, this register has the same bit assignments as the status

register. The difference is that the IREQ pin is not negated when this register is read.

91

Command Register: This is a write-only register used for command execution. A command is

executed by writing that command to this register after parameter setting is completed (see table

below).

Used Parameter

Command

Command Code FR

SC

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

SN

N

Y

N

Y

N

Y

N

Y

N

Y

CY

N

Y

N

Y

N

Y

N

Y

N

Y

DR

Y

HD

N

Y

N

Y

N

Y

N

Y

N

Y

N

Y

LBA

N

Y

Check power mode

Execute drive diagnostic

Erase sector

E5H or 98H

90H

N

Y

N

C0H

Format track

50H

Y

Identify Drive

ECH

N

Y

Idle

E3H or 97H

E1H or 95H

91H

Idle immediate

Initialize drive parameters

Read buffer

E4H

Read multiple

Read long sector

Read sector

C4H

22H or 23H

20H or 21H

40H or 41H

1XH

Y

Read verify sector

Recalibrate

Y

N

Y

Request sense

Seek

03H

7XH

Set features

EFH

N

Y

Set multiple mode

Set sleep mode

Stand by

C6H

E6H or 99H

E2H or 96H

E0H or 94H

87H

Stand by immediate

Translate sector

Wear level

F5H

N

Y

Write buffer

E8H

Write long sector

Write multiple

32H or 33H

C5H

Y

Write multiple w/o erase

Write sector

CDH

Y

30H or 31H

38H

Y

Write sector w/o erase

Write verify

Y

3CH

Y

Note: FR: Feature register

SC: Sector Count register

SN: Sector Number register

92

CY: Cylinder register

DR: DRV bit of Drive Head register

HD: Head Number of Drive Head register

LBA: Logical Block Address Mode Supported

Y:

N:

Valid parameter for this command

Invalid parameter for this command

Device Control Register: This is a write-only register that performs internal reset signal control

and ATA software reset issuance.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

1

Bit 2

Bit 1

Bit 0

0

×

SRST

nIEN

Bit

Name

Function

7 to 4

×

don’t care

3

2

1

Set this bit to 1.

SRST (Software ReSeT)

When this bit is set to 1, an ATA software reset is

executed. Unlike a hardware reset, this reset does not

initialize the configuration registers. The reset state is not

cleared until this bit is cleared to 0.

1

0

nIEN (Interrupt ENable)

This bit controls enabling of the IREQ signal. IREQ is

enabled when this bit is cleared to 0, and disabled when

it is set to 1.

0

Clear this bit to 0.

Drive Address Register: This is a read-only register used to provide compatibility with the AT

disk interface. As bit 7 of this register may cause a collision, it is recommended that this register

not be mapped in I/O space.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

×

nWTG

nHS3

nHS2

nHS1

nHS0

nDS1

nDS0

Bit

7

Name

Function

Undefined

×

6

nWTG (WriTing Gate)

5 to 2

nHS3–0 (Head Select 3–0)

These 4 bits are the NOT of the Head Number bits in the

drive/head register.

1

0

nDS1 (Idrive Select 1)

nDS0 (Idrive Select 0)

Undefined

93

Appendix C Glossary

No. Item

Description

1

PCMCIA

Personal Computer Memory Card International Association: an

organization for the standardization of PC card specifications.

PCMCIA*.* /

JEIDA *.*

Standard name and revision number. Standardization of SRAM and

other memory cards was begun in 1985, initially by JEIDA. In 1989,

PCMCIA was established with the participation of IBM, Apple, etc.

Standardization efforts have progressed jointly since then. The current

standard is PCMCIA2.1/JEIDA4.2, covering the use of fax/modem

cards, etc., as well as memory cards.

2

3

4

JEIDA

Japan Electric Industrial Development Association. Promotes PC card

standardization jointly with PCMCIA.

WindowsCE

CompactFlash^TM

An operating system for handheld PCs, developed by Microsoft. The

interface uses a similar GUI to that of Windows95.

A new flash card standard proposed by SanDisk Inc. of the USA.

Physically, 1/3 the area of a PC card, with a 50-pin two-piece

connector, but electrically compliant with existing projects, including

PC-ATA specifications and True-IDE specifications, offering excellent

compatibility.

5

PC-ATA

PC Card AT Attachment. Standard for connecting a PC-ATA

specification memory card to a PC card slot. Can be thought of as

bringing the ATA standard for HDDs into the field of PC cards. A PC-

ATA card is a PC card that conforms to the PCMCIA PC-ATA

standard.

6

7

True-IDE

Chip set

Standard for handling a flash card as an HDD. Standard for flash

cards operated as HDDs immediately after start-up. Totally unrelated

to PC-ATA specifications and the PC card standard.

Generally refers to functional LSIs for implementing certain functions

by being connected to the CPU, bus, etc. In this manual, “chip set”

refers to products called PC card controllers.

8

Memory card

I/O card

A type of PC card, such as an SRAM card or flash card, containing

memory and used for storage, .

9

A type of PC card, such as a SCSI card or fax/modem card, for

connection to another device or computer.

10

IDE specifications

IDE: Integrated Device Electronics, Intelligent Device Electronics.

HDD interface standard developed by US companies Western Digital

and Compaq in 1986. Designed to allow direct connection to the PC-

AT bus (currently generally called the ISA bus) initially used by IBM.

11

94

ISA bus (PC-AT bus) Industrial Standard Architecture bus. Bus used in the days of the IBM-

PC, initially called the PC-AT bus. Provides direct connection to an

Intel X86 CPU. Became an industry standard after IBM stopped

designing machines using this bus standard.

No. Item

Description

12

IBM-PC

Earliest personal computer produced by IBM, from which all today’s

personal computers could be said to derive. The undercurrents of

today’s technologies, including Intel CPUs and Microsoft operating

systems, began here.

13

ATA specifications

HDD standard created by ANSI, basically synonymous with IDE

specifications. The original IDE specifications were established as

ATA1, and currently a general enhanced IDE has been standardized

as ATA3. Note that these specifications are different from the PC-ATA

specifications referred to throughout this manual.

14

15

Enhanced IDE

specifications

Currently the most widely used HDD standard. The former IDE

standard, which provided only for connection of up to two HDDs and a

capacity of up to 504 MB, has been enhanced to support 4 HDDs and

almost 4 GB.

Connection of CD-ROM is also supported. This requires an ATAPI

(ATA Packet Interface) specification CD-ROM.

CFA

CompactFlash™ Association: an organization for the promotion of

CompactFlash™. Currently (June 13, 1997) includes 72 vendors and

user companies working to promote the use of this medium.

16

17

ANSI

American National Standards Institute

PC card

Business-card-sized IC card inserted in a PC card slot in a personal

computer, etc. Fax/modem cards, LAN cards, etc., are available as

well as flash memory cards. These have been standardized by

PCMCIA/JEIDA.

18

19

Microsoft

Intel

Leader of the personal computer OS industry, headed by Bill Gates.

World’s largest software company, holding an overwhelming share of

the PC operating system and application software markets.

World’s largest semiconductor manufacturer. Controls 90% of the

market for personal computer CPUs. Now attempting to make inroads

into other PC-related fields.

20

21

Western Digital

SanDisk

HDD manufacturer

Dedicated flash card manufacturer, originator of the CF standard.

Currently holds the largest share of the world flash card market.

95

Hitachi IC Memory CompactFlash™/PC-ATA Standard

User’s Manual

Publication Date: 1st Edition, November 1997

Published by:

Semiconductor and IC Div.

Hitachi, Ltd.

Edited by:

Technical Documentation Center

Hitachi Microcomputer System Ltd.


型号：	HB28B064A8HSR
厂家：	ETC
描述：	IC Memory CompactFlash /PC-ATA Standard Users Manual/Device IC存储CF卡/ PC - ATA标准的用户手册/设备\n 存储 PC
文件：	总103页 (文件大小：458K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HB28B064A8HSR [ETC]

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