HB28B512IA2SR_技术文档

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April 1, 2003

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Hitachi IDE Card

User’s Manual

ADE-603-011

Rev. 1.0

3/19/2003

Hitachi, Ltd.

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s

patent, copyright, trademark, or other intellectual property rights for information contained in

this document. Hitachi bears no responsibility for problems that may arise with third party’s

rights, including intellectual property rights, in connection with use of the information

contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you

have received the latest product standards or specifications before final design, purchase or

use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.

However, contact Hitachi’s sales office before using the product in an application that

demands especially high quality and reliability or where its failure or malfunction may directly

threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear

power, combustion control, transportation, traffic, safety equipment or medical equipment for

life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi

particularly for maximum rating, operating supply voltage range, heat radiation characteristics,

installation conditions and other characteristics. Hitachi bears no responsibility for failure or

damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,

consider normally foreseeable failure rates or failure modes in semiconductor devices and

employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi

product does not cause bodily injury, fire or other consequential damage due to operation of

the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document

without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi

semiconductor products.

Contents

Section 1 Hitachi IDE Card Overview.........................................................................

1.1 Introduction.......................................................................................................................

1.2 Interface ............................................................................................................................

1.3 IDE Card Features.............................................................................................................

1.4 I/O Pin Arrangement.........................................................................................................

1.5 IDE Card Configuration....................................................................................................

1

2

3

4

5

Section 2 ATA Standards..................................................................................................

2.1 Access Modes ...................................................................................................................

2.2 Description of Transfer Modes .........................................................................................

7

8

Section 3 ATA Signals and Electrical Characteristics.............................................. 11

Section 4 ATA Registers and ATA Commands ......................................................... 17

4.1 ATA Registers .................................................................................................................. 17

4.2 ATA Commands ............................................................................................................... 20

Section 5 IDE Card Access Methods............................................................................. 21

5.1 PIO Mode.......................................................................................................................... 21

5.2 MultiWord/Ultra DMA Mode........................................................................................... 22

Section 6 IDE Card Usage Notes.................................................................................... 25

6.1 Cutting Power ................................................................................................................... 25

6.2 Inadvertent Insertion of an IDE Card into a PC Card Slot................................................ 25

6.3 Damping Resistances between Host and IDE Card .......................................................... 25

Section 7 Reference Information .................................................................................... 27

7.1 HDD Structure and Logical Addressing ........................................................................... 27

7.2 How to Obtain Specifications ........................................................................................... 28

Section 8 Appendices......................................................................................................... 29

8.1 Details of ATA Registers.................................................................................................. 29

8.2 CHS Mode and LBA Mode .............................................................................................. 32

8.3 MBR and PBR .................................................................................................................. 33

Rev. 1.0, 03/03, page iii of iv

Figures

Figure 1-1 Schematic Representation of Host and IDE Devices .............................................

Figure 1-2 Front View of IDE Card Connector .......................................................................

Figure 1-3 IDE Card Configuration.........................................................................................

Figure 2-1 Schematic Representation of PIO Mode Transfer..................................................

Figure 2-2 Schematic Representation of MultiWord DMA Mode Transfer ............................

1

5

8

9

Figure 2-3 Schematic Representation of Ultra DMA Mode Transfer...................................... 10

Figure 5-1 Flowchart of PIO Transfer ..................................................................................... 22

Figure 5-2 Flowchart of MultiWord/Ultra DMA Transfer ...................................................... 23

Figure 6-1 Example of Damping Resistances between Host Interface and IDE Card ............. 26

Figure 7-1 Schematic Representation of HDD Structure and Logical Addressing.................. 27

Figure 8-1 Detailed Diagram of MBR/PBR............................................................................. 34

Tables

Table 1-1

Table 1-2

Table 1-3

Table 2-1

Table 3-1

Table 4-1

Functions Supported by PC-ATA Card, IDE Card, HDD, and CD-ROM .............

Characteristics of IDE Card and HDD ...................................................................

Pin Assignments of IDE Card and PC-ATA Card .................................................

ATA Standards and Flash Card Standards .............................................................

ATA Signals........................................................................................................... 11

ATA Register Assignments.................................................................................... 17

2

3

4

7

Rev. 1.0, 03/03, page iv of iv

Section 1 Hitachi IDE Card Overview

1.1

Introduction

Possible uses of the Hitachi IDE Card are as follows:

(1) replacement for a hard disk

(2) embedding storage in various kinds of devices

This manual is intended for those looking into the IDE Card for such applications for the first

time, and aims to give its readers an understanding of just what a Hitachi IDE Card is. Further

details are available in a Data Sheet and other documentation. The following sections describe the

internal configuration of the card, its operating modes, and data transfer procedures.

Notes on Reading this User's Manual

(1)

IDE Device

Host

Master

Slave

IDE Card

IDE Controller

IDE Device

CD-ROM Drive

Figure 1-1 Schematic Representation of Host and IDE Devices

In this manual the term "host" refers to a computer system that has an IDE controller (so-called

"South Bridge"⁽¹⁾) and same as IDE controller interface system, and devices such as an IDE Card,

hard disk (HDD), and CD-ROM mentioned in this manual fall into the category of "IDE devices".

Terminology (1)

(1) South Bridge

Provided on a chip-set (set of circuits managing data exchange between the CPU, RAM,

extension cards, etc., in the motherboard of a PC), and mainly used to perform control of

peripheral devices. The IDE controller is included in this chip-set.

Rev. 1.0, 03/03, page 1 of 34

(2)

A minus sign ("-") is used in this manual to indicate negative logic. Negative logic means that a

signal is logically enabled when at the low level. In this case, the actual signal is active-low.

Conversely, positive logic means that a signal is logically enabled when at the high level. In this

case, the actual signal is active-high.

1.2

Interface

The IDE Card conforms to the ATA (AT Attachment) -5 standard established by ANSI (American

National Standards Institute). The shape of the card conforms to PMCIA Type-II, and its

dimensions of 85.6 mm (D) × 54.0 mm (W) × 5.0 m (H) are exactly the same as those of Hitachi's

PC-ATA Card. Note, IDE Card does not support the ATAPI-5 interface used for CD-ROM and so

forth.

When a Hitachi IDE Card is used by a PC motherboard, for instance, the card should be connected

to the IDE connector on the motherboard via a cable. As the cable connector and the IDE Card

connector are of different shape, conversion must be carried out by the customer. When designing

a special board, refer to section 1.4 regarding the wiring.

Unlike an HDD, CD-ROM, etc., IDE Card master/slave settings can only be made by means of a

CSEL setting. Refer to the Data Sheet for details of the CSEL pin. Also note that hot swapping⁽¹⁾

is not supported for IDE devices, and must not be carried out.

The information given above is summarized in table 1-1.

Table 1-1 Functions Supported by PC-ATA Card, IDE Card, HDD, and CD-ROM

PC-ATA Card

IDE Card

ATA-5

HDD

ATA-5

CD-ROM

ATAPI-5

Supported interface

Hot swapping

*1

*2

Not supported

Master/slave

setting

Set with CSEL

Set with jumper

Shape

PCMCIA Type-II PCMCIA Type-II 2.5/3.5-inch

standard shape

3.5-inch standard

shape

*1 The PC-ATA Card supports memory card mode, I/O card mode, and True-IDE mode.

*2 Hot swapping is enabled in memory card mode and I/O card mode, but is disabled in True-IDE

mode. (See the Hitachi User's Manual for details of functions supported by the PC-ATA Card.)

Terminology (2)

(1) Hot swapping

A PC card can be recognized even if removed or inserted while the personal computer is

switched on. Such an operation is known as hot swapping.

Rev. 1.0, 03/03, page 2 of 34

1.3

IDE Card Features

As shown in table 1-2, an IDE Card offers a number of advantages compared with an ordinary

HDD, including lower power consumption, a wide operating temperature range, excellent

vibration and environment tolerance, and high-speed random access capability.

Table 1-2 Characteristics of IDE Card and HDD

Characteristic

Power consumption

IDE Card

HDD

○

×

Operating temperature range

Environment tolerance

Vibration tolerance

0 to 70°C

5 to 55°C

○

×

Random sector writes

Sequential sector writes

×

○

Functionally, an IDE Card offers the following features.

•

SMART (Self Monitoring Analysis and Reporting Technology) function

When an IDE Card is approaching the end of its life, the IDE Card returns predictive

information to the host in response to a SMART RETURN STATUS command issued by the

host. Use of this function enables the user to check whether the number of alternate sectors of

a card in operation have fallen below a prescribed value.

•

Wear leveling function (flash memory data rewrite life prolongation function)

When a memory block has been rewritten more than a certain number of times, it is swaped

with another memory block and logical address. This enables leveling of the number of

memory block rewrites to be achieved.

Improved reliability through CRC (Cyclic Redundancy Code: check code for data error

detection) checking during UDMA mode data transfer

In ANSI ATA-5, CRC checks are stipulated as a specification in order to improve data bus

reliability during data transfers in Ultra DMA mode. As the IDE Card supports Ultra DMA,

use of Ultra DMA mode is recommended for users who require reliability of the bus between

the host and a device.

Rev. 1.0, 03/03, page 3 of 34

1.4

I/O Pin Arrangement

Pin assignments and a pin arrangement diagram are shown below for a PC-ATA Card and IDE

Card.

Table 1-3 Pin Assignments of IDE Card and PC-ATA Card

Function Name

PC-ATA

Function Name

PC-ATA

Function Name

PC-ATA

No.

Card True-

IDE Mode

IDE Card

Card True-

IDE Mode

IDE Card

Card True-

IDE Mode

IDE Card

1

2

GND

D[3]

D[4]

D[5]

D[6]

D[7]

-CE1

A10

-ATASEL

―

GND

DD[3]

DD[4]

DD[5]

DD[6]

DD[7]

-CS0

―

24

25

26

27

28

29

30

31

32

33

34

35

36

37

A5

A4

―

47

48

49

50

51

52

53

54

55

56

57

58

59

60

―

3

A3

―

4

A2

DA[2]

DA[1]

DA[0]

DD[0]

DD[1]

DD[2]

-IOIS16

GND

―*

―

5

A1

VCC

―

VCC

―

6

A0

7

D[0]

D[1]

D[2]

-IOIS16

GND

CD[1]

D[11]

―

8

―

9

―

10

11

12

13

14

―

-CSEL

-VS2

-RESET

IORDY

-CSEL

―*

A9

―

A8

―

-RESET

Note 3

DMARQ

―

DD[11]

INPACK

Note 4

15

-WE

―

38

D[12]

DD[12]

61

-REG

Note 5

-DMACK

16

17

18

19

20

21

22

23

INTRQ

VCC

―

INTRQ

VCC

―

39

40

41

42

43

44

45

46

D[13]

D[14]

D[15]

-CE2

-VS1

-IORD

-IOWR

―

DD[13]

DD[14]

DD[15]

-CS1

―*

62

63

64

65

66

67

68

-DASP

-PDIAG

D[8]

-DASP

-PDIAG

DD[8]

DD[9]

DD[10]

―*

―

D[9]

―

D[10]

CD[2]

GND

―

Note 1

Note 2

―

A7

―

GND

A6

―

Note: The -IOIS16 signal was discontinued from ATA-3 onward.

—*: The host must not be connected to these pins.

Rev. 1.0, 03/03, page 4 of 34

Changes in Signal Names with Ultra DMA (Notes 1 to 3)

Signal Name Except in Ultra DMA

Ultra DMA data-in burst

Ultra DMA data-out burst

HSTROBE

Signal Direction

Host → device

Device → host

Note 1

Note 2

Note 3

-DIOR

-DIOW

IORDY

-HDMARDY

STOP

DSTROBE

-DDMARDY

Ultra DMA data-in burst: Indicates device → host data transfer

Ultra DMA data-out burst: Indicates host → device data transfer

Note 4 INPACK Signal: This signal is not used and should not be connected at the host.

Note 5 -REG Signal: This input signal is not used and should be connected to VCC.

34

1

68

35

Figure 1-2 Front View of IDE Card Connector

1.5

IDE Card Configuration

The general configuration of an IDE Card is shown in figure 1-3. The IDE Card contains a

Hitachi controller and Hitachi AND-type flash memory.

HB28B1700IA2 (1.7GB)

Hitachi AND-type

flash memory

Controller

ATA-5

UDMA66

68-pin

Hitachi AND-type

flash memory

Host

14 chips

installed

Interface

Read: 8MB/s

Write: 7MB/s

Hitachi AND-type

flash memory

Figure 1-3 IDE Card Configuration

Rev. 1.0, 03/03, page 5 of 34

Rev. 1.0, 03/03, page 6 of 34

Section 2 ATA Standards

2.1

Access Modes

ATA interfaces include the following standards, and products have been developed for each.

Table 2-1 ATA Standards and Flash Card Standards

IDE

Card

Maximum

Transfer

Rate (MB/s)

ATA Standard

Flash Card

CF

Transfer

Mode

1

*

2

3

ATA-1 ATA-2 ATA-3 ATA-4 ATA-5

Standard

*

PIOMode0 3.33

(MB/s)

○

×

○

×

○

×

○

×

○

×

○

×

○

×

○

×

○

×

○

Mode1 5.22 (MB/s)

Mode2 8.33 (MB/s)

Mode3 11.1 (MB/s)

Mode4 16.6 (MB/s)

Mode0 4.16 (MB/s)

Mode1 13.3 (MB/s)

Mode2 16.6 (MB/s)

Mode0 16.6 (MB/s)

Mode1 25 (MB/s)

Mode2 33.3 (MB/s)

Mode3 44.4 (MB/s)

Mode4 66.6 (MB/s)

Multi

Word

DMA

Ultra

DMA

×

IO interface mode

×

Memory card mode

×

*1 CompactFlash^®standard CFA specification 1.4, PC card standard

*2 IDE Card: HB28BxxxIA2 (xxx = 512, 1000, 1700)

*3 CompactFlash^®: HB28BxxxC8H (xxx = 32 to 512)

As shown in the above table, the ANSI ATA-5 standard includes PIO modes 0 to 4, MultiWord

DMA modes 0 to 2, and Ultra DMA modes 0 to 4. (See 2.2, Description of Transfer Modes, for

details of PIO mode, MultiWord DMA mode, and Ultra DMA mode.)

Rev. 1.0, 03/03, page 7 of 34

2.2

Description of Transfer Modes

(1) PIO Transfer

PIO is an abbreviation of "Programmed I/O". In PIO transfer, the CPU employs the data bus⁽¹⁾to

perform data reading/writing directly between the host and an IDE Card using read/write signals.

While performing access to the IDE Card, the CPU accesses an IDE Card register ⁽²⁾and main

memory. Thus, in order to carry out high-speed transfer, it is necessary for the system bus to

operate at high speed and for a sufficiently high transfer rate to be achieved.

Figure 2-1 Schematic Representation of PIO Mode Transfer

Terminology (3)

(1) Data bus

A bus is a path for exchanging data between the host and a device. The data bus is a bus that

carries data exchanged by devices connected to the bus.

(2) Register

A location that temporarily stores data used by the CPU to execute processing for controlling a

device. This stored data includes parameters, commands, addresses, etc.

Rev. 1.0, 03/03, page 8 of 34

(2) MultiWord DMA Transfer

DMA transfer is an access method in which a DMA controller exchanges data between memory

locations, or between memory and an IDE Card, instead of the CPU. During DMA transfer the

CPU releases the bus, which not only enables data to be transferred at high speed, but also allows

the CPU itself to execute other processing. The MultiWord DMA transfer method conforms to the

specifications of the Intel i8237, which is the DMA controller in the PC/AT architecture. With the

MultiWord DMA transfer method, burst transfer⁽¹⁾of a prescribed number of bytes is carried out

in response to a single DMA request.

Figure 2-2 Schematic Representation of MultiWord DMA Mode Transfer

Terminology (4)

(1) Burst transfer

In burst transfer, data is sent continuously and transfer is not interrupted until the prescribed

number of bytes have been sent.

Rev. 1.0, 03/03, page 9 of 34

(3) Ultra DMA Transfer

Ultra DMA transfer is a kind of DMA transfer in which data is transferred in accordance with a

serial clock. A special feature of Ultra DMA transfer is that data transfer is performed at both the

*

rising and falling edges of the strobe signal . Ultra DMA can achieve a transfer rate twice that of

the conventional method. In Ultra DMA transfer, data transfer is performed by a DMA controller

incorporated in the IDE controller which is the bus master⁽²⁾on the PCI bus.

Figure 2-3 Schematic Representation of Ultra DMA Mode Transfer

Terminology (5)

(1) Strobe

A signal used for transfer timing (latch timing), that is a trigger for a state transition.

(2) Bus master

The device operating as the master on the bus. The CPU and DMA controller on the

motherboard are both "bus" masters, but with a PC, generally speaking, "bus master" denotes

an expansion card or device capable of becoming the master of the bus. The device operating

as the bus master can access memory directly without the intervention of the CPU (i.e., can

perform DMA transfer). Data transfer by the bus master is faster than program transfer by the

CPU or DMA transfer by the DMA controller on the motherboard.

*

"Rising edge" denotes a transition of potential from the low level to the high level in a digital

signal. Conversely, "falling edge" denotes a transition of potential from the high level to the low

level. Generally speaking, the operation of a digital circuit (synchronous circuit) consists of a

repetitive pattern in which the state of a particular signal changes in synchronization with the

rising edge or falling edge of another signal.

Rev. 1.0, 03/03, page 10 of 34

Section 3 ATA Signals and Electrical Characteristics

ATA signals include signals whose signal name and role differ in Ultra DMA transfer and in other

kinds of transfer. First, therefore, the output direction and function of each ATA signal will be

described. ATA signals are listed in table 3-1.

Table 3-1 ATA Signals

Direction

Signal Name

Description

Host

Device

-CSEL

―

→

⇔

―

→

←

→

←

→

―

→

Cable select

Chip select

-CS[1:0]

DD[15:0]

-DASP

16-bit data bus

Device active indicator or slave present

Address

DA[2:0]

-DMACK

DMARQ

INTRQ

DMA acknowledge

DMA request

Interrupt request

-DIOR

I/O read

-HDMARDY

HSTROBE

IORDY

DMA ready during Ultra DMA data-in bursts

DMA strobe during Ultra DMA data-out bursts

I/O ready

-DDMARDY

DSTROBE

-DIOW

DMA ready during Ultra DMA data-out bursts

DMA strobe during Ultra DMA data-out bursts

I/O write

STOP

DMA stop during Ultra DMA data burst

Self-diagnosis bus

-PDIAG

-CBLID

Cable assembly type indicator

Reset

-RESET

Data-out burst:

Data-in burst:

Data burst from host to hard disk

Data burst from hard disk to host

Ultra DMA data-in burst: Transfer burst from device (HDD) to host in Ultra DMA data bursts

Ultra DMA data-out burst: Transfer burst from host to device (HDD) in Ultra DMA data bursts

Next, a description of each ATA signal will be given. (See table 3-1 for the pins corresponding to

the various signals.)

Rev. 1.0, 03/03, page 11 of 34

•

-CS[1:0] (Chip select)

Chip select signals used to address an ATA command block register or control block register.

When -DMACK is asserted⁽¹⁾(L: Low), these signals must be negated⁽¹⁾(H: High).

Terminology (6)

(1) Asserted, negated

States of a control signal indicating validity or cancellation. "Asserted" denotes the state

indicating validity, and "negated" the state indicating cancellation.

•

DA[2:0] (Device address)

Address signals for accessing data or a data port, and different from the address of the memory

like SRAM.

-DASP (Device active or slave [Device 1] present]

Signal in which a signal indicating that a device is active, and a signal indicating that Device 1

is present, are multiplexed

•

DD[15:0] (Device data)

16-bit bidirectional data bus

-DIOR (-HDMARDY; HSTROBE) (Device I/O read, DMA ready during Ultra DMA

data-in bursts, Data strobe during Ultra DMA data-out bursts)

Except in Ultra DMA transfer, this signal operates as -DIOR (signal that becomes active), a

read signal used for a register or data port read from the host to the device.

In Ultra DMA transfer, this signal operates as -HDMARDY or HSTROBE, data transfer flow

control signals⁽¹⁾.

-HDMARDY: Used in case of Ultra DMA data-in bursts (read by Ultra DMA)

Signal informing the device whether the host is ready to capture data. Also

used to temporarily stop transfer by the host.

HSTROBE: Used in case of Ultra DMA data-out bursts (write by Ultra DMA)

Signal used when a device latches data from the host

Rev. 1.0, 03/03, page 12 of 34

Terminology (7)

(1) Flow control signal

In data transfer, some kind of handshaking is necessary between the transmitting side and

receiving side to prevent data from being lost. Flow control is one handshaking⁽²⁾method.

When data is transmitted, the flow of data is adjusted (suppressed) by decreasing the data

transferring speed, or stopping data transmission, mainly in accordance with the situation at the

receiving side, such as whether the receive buffer is full or whether receive data processing

has been completed in time. A flow control signal is a signal sent to the transferred side to

prevent the capacity of the receive buffer on the receiving side from being exceeded.

(2) Handshaking

A control method for ensuring dependable data transfer, in which the data sending side and

input side are linked by means of control signals called Ready and strobe signals. For

example, when the controller is the data sending side, when sending data to a device, it sends

a Ready signal indicating that data has been prepared and sent. When the Ready signal is

input to the device, the device recognizes that data has been sent, and returns a strobe signal

indicating that it has received the data. When the strobe signal is restored to its original state

after a certain interval, the sending side recognizes that the sent data has been transferred

successfully, restores the Ready signal to its original state, and proceeds to send the next data.

•

-DIOW (STOP) (Device I/O write, Stop during Ultra DMA burst)

Except in Ultra DMA transfer, this signal operates as -DIOW, a write signal used to write to a

register or data port.

-DIOW must be negated before an Ultra DMA burst is started. STOP is used as a signal for

stopping an Ultra DMA burst while in progress, and is asserted upon termination.

•

-DMACK (DMA acknowledge)

Reply signal (enabling DMA operation) returned to the device by the host in response to

DMARQ at the start of DMA transfer

DMARQ (DMA request)

Used when performing DMA transfer. This signal indicates a DMA transfer request to the

host when the IDE Card has completed preparations for data transfer, and is asserted by the

device. The data transfer direction is controlled by -DIOR/-DIOW. It performs handshaking

together with -DMACK. The -CS[1:0] signals are not used in DMA transfer.

Rev. 1.0, 03/03, page 13 of 34

•

INTRQ (Device interrupt request)

INTRQ is used to make a request for an interrupt ⁽¹⁾by the selected device to host control.

Driving is possible when device nIEN⁽²⁾= 0 and a device is selected. When this signal is

asserted, the device negates INTRQ within 400 ns after the rise of the -DIOR signal by reading

the ATA Status register. Similarly, when this signal is asserted, the device negates INTRQ

within 400 ns after the rise of the -DIOW signal by writing to the Command register. If the

same device is selected with the Device/Head register while INTRQ is asserted, the device

must negate INTRQ within 400 ns after the rise of the -DIOW signal. Similarly, if another

device is selected with the Device/Head register while INTRQ is asserted, the previously

selected device must release INTRQ and place it in the high-impedance state within 400 ns

after the rise of the -DIOW signal.

Terminology (8)

(1) Interrupt

When the IDE Card requests some kind of control by the CPU, it uses an interrupt signal.

When this is conveyed to the CPU, the CPU temporarily halts the program being executed and

performs the requested processing. This is called an interrupt (interrupt handling). A PC uses

specifications based on Intel's 8259A interrupt control chip. The 8259A includes an interrupt

status register that holds an indication of what the interrupt source is, an interrupt mask register

that enables or disables interrupts, and an interrupt level setting register that is used to set the

degree of importance of an interrupt signal.

(2) nIEN

Indicates INTRQ signal enable/disable switching. When nIEN = 0, both devices are enabled,

and when nIEN = 1, both devices are disabled.

•

IORDY (-DDMARDY; DSTROBE) (I/O channel ready, DMA ready during Ultra DMA

data-out bursts, Data strobe during Ultra DMA data-in bursts)

Except in Ultra DMA transfer, this signal is used as IORDY. At this time, a signal for

extending the register access transfer cycle when the IDE Card has not completed data transfer

preparations is negated, and is used as a wait. This signal can be used when the IDE Card uses

a high-speed transfer cycle of PIO transfer mode 3 or above. (The fact that the IORDY signal

can be used in PIO mode 3 and above is stated in ANSI Information Technology—AT

Attachment with Packet Interface-5 (ATA/ATAPI-5) T13/1321D Revision 3.)

-DDMARDY: Used in case of Ultra DMA data-out bursts (write by Ultra DMA)

Signal informing a device whether or not the device is ready to capture data.

Also used to temporarily stop transfer by a device.

DSTROBE: Used in case of Ultra DMA data-in bursts (read by Ultra DMA)

Signal used when the host latches data from a device

Rev. 1.0, 03/03, page 14 of 34

•

-PDIAG (Passed diagnostics)

-PDIAG is asserted by Device 1, and informs Device 0 that Device 1 has finished self-

diagnosis⁽¹⁾.

Terminology (9)

(1) Self-diagnosis

A function whereby a device itself diagnoses whether or not there is an abnormality of some

kind in its operation, and issues the result.

•

-RESET (Hardware reset)

Hardware reset signal used for a reset of a device by the host

-CSEL (Cable Select)

Signal used when performing device selection as master or slave device

-CBLID (Cable assembly type identifier)

-CBLID is used to detect an 80-core cable at power-on or after a hardware reset.

Rev. 1.0, 03/03, page 15 of 34

Rev. 1.0, 03/03, page 16 of 34

Section 4 ATA Registers and ATA Commands

4.1

ATA Registers

In ATA, the host controls a device, and transfers data, commands, and statuses, via registers.

ATA register address assignments and an overview of each register are given below.

The CPU accesses ATA registers using the -CS[1:0], DA[2:0], -DIOR, and -DIOW signals. This

method is the same one in which the CPU performs data transfer directly. Therefore, ATA register

accesses are categorized as PIO transfers.

Next, ATA register address assignments will be described (see table 4-1). ATA registers can be

broadly divided into command block registers and control block registers.

Table 4-1 ATA Register Assignments

Register Name

CS1#

CS0#

DA2

DA1

DA0

Read

Write

H

L

H

L

X

L

X

L

X

L

Register not selected

Prohibited

L

H

L

―

L

H

L

H

L

H

L

H

L

H

L

H

L

Alternate Status register

Device Control register

L

H

L

―

H

Data register (16 bits)

Error register Feature register

L

H

L

H

L

Sector Count register

Sector Number register

Cylinder Low register

Cylinder High register

Device/Head register

L

H

L

H

L

H

L

H

L

H

Status register

Command register

Note: H: High

L: Low

X: Don't care

Rev. 1.0, 03/03, page 17 of 34

•

Command Block Registers

Registers in the register space accessed with -CS0 low and -CS1 high are called command

block registers. These registers are used to issue a command to a device or read a status, and

include the Cylinder High/Low, Device/Head, Sector Count/Number, Command, Status,

Feature, Error, and Data registers.

Control Block Registers

Registers in the register space accessed with -CS0 high and -CS1 low are called control block

registers. These registers are used to control devices and read an alternate status. They include

the Device Control and Alternate Status registers.

Note: Asserting both -CS0 and -CS1 is prohibited. If, conversely, both -CS0 and -CS1 are

negated, a state is established in which no ATA register is being accessed. In DMA

transfer, both -CS0 and -CS1 are negated and handshaking is performed by means of

DMARQ and -DMACK, so it is possible for data transfer to be performed even though -

CS0 and -CS1 are both negated.

A more detailed description of register contents is given below, referring to the list of ATA

registers in Appendix 8.1.

•

Status register

This is a read-only register that indicates the status of an IDE Card. For IDE Card control,

handshaking must be carried out while referring to this register. The register address is the

same as that of the Command register, and therefore when the host performs a write operation

on this address, a value is written to the Command register.

•

Command register

This is a write-only register. The register address is the same as that of the Status register, and

therefore when the host reads this address, the contents of the Status register are read. Before

writing a command to the Command register, confirm that the BSY bit⁽¹⁾and DRQ bit⁽²⁾are

both 0, and that -DMACK is not asserted.

Terminology (10)

(1) BSY bit

A bit in the Status register that indicates whether the IDE Card is in the busy state (engaged in

processing). Bit 7 is the BSY bit.

(2) DRQ bit

A bit in the Status register that indicates, during data transfer between the IDE Card and the

host, that the IDE Card side can request data. Used in IDE Card PIO reads or PIO writes.

Bit 3 is the DRQ bit.

Rev. 1.0, 03/03, page 18 of 34

•

Cylinder High register

This is a readable/writable register that specifies cylinder number [15:8] when using the CHS

system, or LBA[15:8] when using the LBA system. This register can be written to when the

BSY and DRQ bits are both 0 and -DMACK is not asserted. If this register is read when either

the BSY or DRQ bit is 1, the value will not be valid. This register is invalid when a device is

in sleep mode⁽¹⁾.

Terminology (11)

(1) Sleep mode

State in which power dissipation is minimized, and most drive and control functions are halted.

Reset processing is necessary to exit this state.

•

Cylinder Low register

This is a readable/writable register that specifies cylinder number [7:0] when using the CHS

system, or LBA[7:0] when using the LBA system. This register can be written to when the

BSY and DRQ bits are both 0 and -DMACK is not asserted. If this register is read when either

the BSY or DRQ bit is 1, the value will not be valid. This register is invalid when a device is

in sleep mode.

•

Device Control register

This is a write-only register. The register address is the same as that of the Alternate Status

register, and therefore when the host reads this address, the value in the Alternate Status

register is read. The Device Control register can be written to when -DMACK is negated.

Device/Head register

This is a readable/writable register. It is an ATA register that selects the CHS or LBA system,

and executes a software reset of an IDE Card. This register can be written to when the BSY

and DRQ bits are both 0 and -DMACK is not asserted. If this register is read when the BSY

bit is 1, the data will not be valid.

•

Error register

This is a read-only register. Diagnostic results are reflected in this register on completion of a

power-on operation, a hardware reset, or a software reset. When other commands are

executed, it operates as a register that indicates error contents. The register address is the same

as that of the Feature register, and therefore when the host performs a write operation on this

address, a value is written to the Feature register. A read of this register is valid when the BSY

bit is 0, the DRQ bit is 0, and the Error register value is 1. This register is invalid when a

device is in sleep mode.

Rev. 1.0, 03/03, page 19 of 34

•

Feature register

This is a write-only register that sets the operation of an IDE Card. The register address is the

same as that of the Error register, and therefore when the host reads this address, the contents

of the Error register are read. This register can be written to when the BSY bit and DRQ bit

are both 0 and -DMACK is not asserted.

Sector Count register

This is a readable/writable register that sets the number of sectors accessed when the CHS

system is used for sector addressing. This register can be written to when the BSY and DRQ

bits are both 0 and -DMACK is not asserted. If this register is read when either the BSY or

DRQ bit is 1, the value will not be valid. This register is invalid when a device is in sleep

mode.

•

Sector Number register

This is a readable/writable register that sets the location number of the sector to be accessed

when the CHS system is used for sector addressing. This register can be written to when the

BSY and DRQ bits are both 0 and -DMACK is not asserted. If this register is read when either

the BSY or DRQ bit is 1, the value will not be valid. This register is invalid when a device is

in sleep mode. The value written to this register depends on the ATA command, and therefore

bit assignments and values are defined for each command.

•

Data register

This is the data register used in PIO data transfer. This register is used for data reads and

writes between the host and an IDE Card. It can be accessed when the DRQ bit is 1 and

-DMACK is not asserted. This register is 16 bits wide.

4.2

ATA Commands

Registers are used in the execution of functions such as Hitachi IDE Card reading and writing.

Parameters relating to the command to be executed are set in a maximum of six registers, then the

command is executed by setting the command code in the Command register. The Hitachi IDE

Card supports 41 ATA commands. For details of the commands, see Hitachi's IDE Card Data

Sheet.

Rev. 1.0, 03/03, page 20 of 34

Section 5 IDE Card Access Methods

The following basic procedure is the same for all transfer modes when performing data transfer

from the host to a device or from a device to the host.

(1) The CPU accesses a register using -CS[1:0], DA[2:0], -DIOR, or -DIOW.

(2) The Status register is read.

(3) When the Status register is read, it is confirmed that the BSY bit is 0—that is, 5X (where X is

any value), and a signal is returned to the CPU.

(4) The CPU confirms that the bus is 5X for the device selection protocol (a command cannot be

entered unless the device and bus are both 5X). Then an ATA command is issued to the

desired device.

The exchange of signals and commands between the host and device in each transfer mode is

described below.

(This section is intended for software designers. Readers requiring detailed information on the

hardware should refer to the interface IC Specification of the host side.

5.1

PIO Mode

The procedure is described below taking the example of the READ SECTOR(S)/WRITE

SECTOR(S) commands.

(A flowchart of PIO transfer is shown in figure 5-1.)

(1) First, set the necessary parameters in the respective registers (Feature, Sector Number, Sector

Count, Cylinder Low/High, Device/Head registers).

(2) Issue a READ SECTOR(S) or WRITE SECTOR(S) command.

(3) When data transfer preparations are completed, the device confirms that the Status register

value is 58h, and informs the host that data transfer preparations have been completed.

(4) When the device has completed data transfer preparations, the host reads one sector of data

continuously from the Data register.

(5) If there is a non-transferred sector, the host waits until the Status register value becomes 58h

before starting transfer.

(6) When data transfer is completed for all sectors, the host confirms that the Status register value

is 50h or 51h. A Status register value of 50h indicates normal termination, while a value of

51h indicates abnormal termination. If the value is 51h, check the Error register and take

appropriate action.

Rev. 1.0, 03/03, page 21 of 34

Feature,

Sector Count,

Set parameters

(1)

(2)

(3)

Sector Number,

Cylinder High/Low,

Device/Head Register

Issue READ/WRITE SECTOR(S)

command

Device waits for Status register

value to become 58h

Host reads 1 sector of data from IDE Card Data

register when reading, or writes 1 sector of data

to IDE Card Data register when writing

(4)

(5)

If there is non-transferred sector, host waits

until Status register value is 58h, then starts

transfer. When number of transfers for all

sectors are completed, host confirms that

Status register value is 50h

Read Status register, and check whether

command has been completed normally (50h)

(6)

Figure 5-1 Flowchart of PIO Transfer

5.2

MultiWord/Ultra DMA Mode

The procedure is described below taking the example of the READ DMA/WRITE DMA

commands.

(A flowchart of MultiWord/Ultra DMA transfer is shown in figure 5-2.)

(1) First, set the necessary parameters in the respective registers (Feature, Sector Number, Sector

Count, Cylinder Low/High, Device/Head registers).

(2) Issue a READ DMA or WRITE DMA command.

(3) When DMA transfer preparations are completed, the device confirms that the Status register

value is 58h, and informs the host that data transfer preparations have been completed.

Rev. 1.0, 03/03, page 22 of 34

(4) The device then asserts DMARQ, and performs transfer of all data while carrying out

handshaking with the host's -DMACK signal. However, there are some differences that the

subject of data transfer is different, and so on between MultiWord and ultra DMA.

(5) When transfer of all data is completed, the host confirms that the Status register value is 50h or

51h. When the command ends, the Status register is read to check whether the command has

been completed normally. A Status register value of 50h indicates normal termination, while a

value of 51h indicates abnormal termination.

As many parts of DMA transfer depend on the IDE controller, refer to the interface IC

Specification of the host side for details of DMA transfer.

Feature

Sector Count

Sector Number

Cylinder High/Low

Set parameters

(1)

(2)

(3)

Device/Head Register

Command: PIO transfer

Issue READ DMA or

WRITE DMA command

Device waits for Status register

value to become 58h

After device confirms that data transfer

preparations are completed, host starts DMA

transfer

(4)

(5)

(6)

*

Data: DMA transfer

When number of transfers for all sectors are

completed, confirm that Status register value is

50h or 51h

Command: PIO transfer

Read Status register, and check whether

command has been completed normally (50h)

MultiWord DMA : IORDY, -DIOR, -DIOW

Ultra DMA

: READ

-HDMARDY, DSTORBE, STOP

*

WRITE -DDMARDY, HSTORBE, STOP

Figure 5-2 Flowchart of MultiWord/Ultra DMA Transfer

Rev. 1.0, 03/03, page 23 of 34

Rev. 1.0, 03/03, page 24 of 34

Section 6 IDE Card Usage Notes

6.1

Cutting Power

"Cutting power" refers to an operation that cuts the power supply, lowers the power supply voltage

below the operating range, or removes a card from the card connector (or slot), while the card is

busy. Removing a card from its slot or cutting the power supply while the card is busy may

damage the card. An IDE Card is not a removable medium, and should be used as a hard disk.

Check that the card's Status register has a value of 50h (command wait state), then use the proper

procedure to cut the power supply.

If power is cut, an IDE Card may be permanently damaged. Also, if power is cut while writing,

data in the sector (blocks) being written, and adjacent sectors (blocks) and logical address may be

lost.

6.2

Inadvertent Insertion of an IDE Card into a PC Card Slot

An IDE Card conforms to PC Card Standard Type-II in terms of card size, and is of the same

shape as a PC-ATA card. It is therefore conceivable that an IDE Card could be inserted in a PC

card slot by mistake. However, this must be avoided at all costs. An IDE Card is an ATA-

compliant device, and does not employ the True-IDE mode, IO mode, or PC card ATA mode of a

PC-ATA card. Therefore, inadvertently inserting an IDE Card in a PC card slot will not only

result in failure to recognize the card, but may also cause a fault that adversely affects both the

host and the card. Incorrect insertion is therefore absolutely to be avoided.

6.3

Damping Resistances between Host and IDE Card

Overshoot (when the waveform temporarily exceeds the prescribed level) or undershoot (when the

waveform temporarily falls below the prescribed level) caused by changes in signals between the

host and an IDE Card can result in IDE Card (or flash disk) read/write errors. To prevent this

problem, it is recommended for ANSI also that damping resistances be inserted in signal lines

based on the ATA-5 Specification. Even if Ultra DMA is not used, the insertion of damping

resistances can be expected to be an effective anti-noise measure. The purpose of damping

resistance insertion is to suppress reflected waves of signals. Figure 6-1 shows an example of the

addition of damping resistances to wiring. Note, however, that this example is based on the ANSI

Standard, and the values shown are not guaranteed values. Optimal values should be set by the

user in the design stage.

Rev. 1.0, 03/03, page 25 of 34

Figure 6-1 Example of Damping Resistances between Host Interface and IDE Card

Rev. 1.0, 03/03, page 26 of 34

Section 7 Reference Information

7.1

HDD Structure and Logical Addressing

The structure and logical addressing system of an HDD are illustrated in figure 7-1. Refer also to

the description of HDD structure and logical addressing (CHS system and LBA system) given in

8.2, CHS Mode and LBA Mode.

With the CHS system, a target sector is addressed by specifying HDD cylinder, head, and sector

values. With the LBA system, sectors are assigned sequential serial numbers starting from 0, and

a sector location is specified using this number. This system is independent of the physical

structure. As can be seen from figure 7-1, although the addressing method differs in the CHS

system and the LBA system, the end result is to enable a target address to be accessed. As shown

in the figure, also, sector addressing is performed from the outer periphery toward the center of the

disk.

Address Specification in CHS and LBA Systems

CHS System

LBA System

Cylinder Number Head Number Sector Number Block Number

0

:

0

:

1

2

3

:

0

1

2

:

0

:

0

1

:

62

63

1

:

30

Head (H)

31

32

:

0

:

1

2

:

63

1

:

63

Cylinder (C)

64

:

0

:

2

:

63

:

126

:

Sector (S)

0

1

:

16

0

:

63

1

2

:

1008

1009

1010

:

1

:

0

:

63

:

1071

:

2

:

0

:

1

2

:

2017

2018

:

XX

:

Y

:

ZZ

:

AAAAAA

:

Figure 7-1 Schematic Representation of HDD Structure and Logical Addressing

Rev. 1.0, 03/03, page 27 of 34

7.2

How to Obtain Specifications

The ATA/ATAPI-5 specification (ANSI NCITS 340-2000AT Attachment-5 with Packet Interface)

can be purchased through the Japanese Standards Association, and can also be purchased in PDF

format from the ELECTRONICS STANDARDS STORE within the ANSI Home Page. The

ATA-5 draft specification is available from the following site:

http://www.t13.org

Documentation issued by the SFF Committee (an HDD manufacturers' industry group) can be

purchased from the Small Form Factor Committee.

SFF Committee: A committee that makes decisions on disk drive related matters such as external

dimensions and commands.

Rev. 1.0, 03/03, page 28 of 34

Section 8 Appendices

8.1

Details of ATA Registers

(a) Status Register

Status Register

7

6

5

#

4

#

3

2

1

0

BSY

DRDY

DRQ

obs

ERR

BSY:

Busy

0: Device is idle

1: Device is busy

DRDY: Device Ready

0: Device is not ready

1: Device is ready

DRQ:

ERR:

Data Request

0: No data transfer request

1: Data transfer requested

Error

0: No error

1: Command error

#:

Bit definition differs due to command differences

Obsolete bit

obs:

(b) Device Control Register

Device Control Register

7

r

6

r

5

r

4

r

3

r

2

1

0

SRST

nIEN

r:

Reserved

SRST: Software Reset

0: No action

1: Software reset of both devices executed

nIEN: INTRQ Signal Disable/Enable Switching

0: Both devices enabled

1: Both devices disabled

0:

Always write 0 to this bit

Rev. 1.0, 03/03, page 29 of 34

(c) Error Register

Error Register

7

#

6

#

5

#

4

#

3

#

2

1

#

0

#

ABRT

ABRT: Command Abort

0: No abort source

1: Executed command is undefined command, or parameter is incorrect

#:

Bit definition differs due to command differences

(d) Sector Count Register

Sector Count Register

7

6

5

4

3

2

1

0

Sector Count

(e) Command Register

Command Register

7

6

Command Code

(f)-1 Cylinder High Register

Cylinder High Register

7

6

5

Cylinder High (with CHS system), LBA[15:8] (with LBA system)

(f)-2 Cylinder Low Register

Cylinder Low Register

7

6

5

4

3

Cylinder Low (with CHS system), LBA[7:0] (with LBA system)

Rev. 1.0, 03/03, page 30 of 34

(g) Device/Head Register

Device/Head Register

7

6

#

5

4

3

#

2

#

1

#

0

#

obs

DEV

obs: Obsolete bit

DEV: Selected Device

0: Master

1: Slave

#:

Bit definition differs due to command differences

(h) Feature Register

Feature Register

7

#

6

#

5

#

4

#

3

#

2

#

1

#

0

#

#: Bit definition differs due to command differences

(i) Sector Number Register

Sector Number Register

7

#

6

#

5

#

4

#

3

#

2

#

1

#

0

#

#: Bit definition differs due to command differences

(j) Data Register

Data Register

7

6

5

4

3

2

1

9

0

8

Data[7:0]

Data Register

15

14

13

12

11

10

Data[15:8]

Rev. 1.0, 03/03, page 31 of 34

8.2

CHS Mode and LBA Mode

CHS mode and LBA mode refer to data addressing data methods used by an HDD. Here, the

structure used to determine HDD addresses is first described, followed by a description of CHS

mode and LBA mode.

An HDD is a device that records digital data on disks. Viewed from above, each disk is divided

into concentric circles called tracks. Each track is assigned a track number, running sequentially

from the outer to the inner edge of the disk. Tracks are further divided into arcs called sectors. In

the case of an HDD, the sector size is 512 bytes. (Other multimedia devices have different sector

sizes, such as 1024 or 2048 bytes.) Sector numbers are assigned to sectors in each track. A device

called a head is necessary in order to read or write sector data on a disk. One head is required for

each surface of a disk. If there are a number of disks, there are a number of heads. The

management numbers for these data recording surfaces are conventionally called surface numbers.

As most disks generally have separate heads for reading and writing information on each surface,

these numbers are usually referred to as head numbers. Thus, the location of data on a disk can be

indicated by the track number, head number, and sector number. Tracks with the same track

number on the separate disks, forming a cylindrical shape, are denoted by a cylinder number. The

method whereby data is accessed by specifying a track number, head number, and sector number

is known as the CHS system.

A SCSI type HDD, on the other hand, does not have this kind of logical structure, but uses a SCSI

type HDD LBA (Logical Block Address) system in which logical sector numbers are assigned

sequentially from the start of the disk, regardless of the physical structure of the disk, and this

logical sector number is used to access data. PC card type flash memory, CompactFlash, etc.,

support the CHS system and LBA system. At present, however, ATA devices do not necessarily

support the LBA system.

The following points should be noted concerning sector addressing when using an MS-DOS

system.

A PC uses CHS number based addressing for disk reading and writing using the BIOS.

Traditionally, an ATA disk uses a total of 20 bits for addressing, comprising a 10-bit cylinder

number, 4-bit head number, and 6-bit sector number. This derives from the limitation of having to

use the smaller of each of the following values:

•

ATA hardware specification upper limits (C: 16 bits, H: 4 bits, S: 8 bits)

PC BIOS parameter upper limits (C: 10 bits, H: 8 bits, S: 6 bits)

The maximum disk capacity that can be handled in this case is:

1024 × 16 × 63 = 1,032,192 sectors = approx. 528 MB

Rev. 1.0, 03/03, page 32 of 34

Having the BIOS perform a kind of conversion enables the BIOS limit—that is, 10 + 8 + 6 = 24-

bit space—to be used to the full.

Thus, addressing is performed using the numbers of cylinders, heads, and sectors after conversion,

enabling the following maximum disk capacity to be handled:

1024 × 256 × 63 = 16,515,072 sectors = approx. 8.4 GB

With ATA and CF, on the other hand, there is no disk structure, and therefore addressing is

performed using serial numbers called LBAs. (In the ATA specifications, addressing is

standardized as using 28-bit LBAs.)

Logically, therefore, the maximum disk capacity that can be handled is:

65,536 × 16 × 256 = 268,435,456 sectors = approx. 137 GB

In conclusion, while there is a capacity limit of approximately 8.4 GB for CHS access, up to

approximately 137 GB can be handled with LBA access.

8.3

MBR and PBR

MBR and PBR are described below with reference to figure 8-1. In general, a hard disk is divided

into a number of partitions, and is used logically as a number of drives. The partitioning method

is recorded at the start of the disk, in a Master Boot Record (MBR). The MBR contains code for

reading the OS from the disk. Of this, the 64 bytes starting at byte 446 comprise a partition table.

The next two bytes are a signature attached to the partition table, and if the final values are not

0x55 and 0xAA, the partition table is determined to be missing or corrupted. When partition

formatting is executed, data called a Partition Boot Record (PBR) is written in the first sector of a

partition.

Rev. 1.0, 03/03, page 33 of 34

• File system configuration (when one partition is created)

One partition

Root directory

MBR Unused area

PBR

Number of FATs

Data area

area

When partition formatting is executed, a PBR is

created at the start of the partition.

MBR

Partition table

64 bytes (= 32 words)

"55", "AA" in

succession

Start code

byte510

byte0 - byte445

byte446 - byte509

- byte511

The partition table comprises 16-byte entries.

Here, there is assumed to be only one partition,

but a maximum of four partitions can be created.

16 bytes

.. ..

00 00 00 00 00 00 00

00 00

Boot

indicator

1 byte

CHS start

sector

3 bytes

Partition

type

1 byte

CHS end

sector

3 bytes

LBA start

sector

4 bytes

Partition

size

4 bytes

00 00 00 00 00 00 00

.. ..

00 00

When one partition is created, the ID

data for the remaining three partitions

(= 48 bytes) is all 0s.

Figure 8-1 Detailed Diagram of MBR/PBR

Rev. 1.0, 03/03, page 34 of 34

Hitachi IDE Card User’s Manual

Publication Date: 1st Edition, March 2003

Published by:

Business Operation Division

Semiconductor & Integrated Circuits

Hitachi, Ltd.

Edited by:

Technical Documentation Group

Hitachi Kodaira Semiconductor Co., Ltd.


型号：	HB28B512IA2SR
厂家：	ETC
描述：	IDE Card Users Manual/Device IDE卡用户手册/设备\n
文件：	总41页 (文件大小：353K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HB28B512IA2SR [ETC]

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