HC05K3GRS [ETC]
68HC05K3 General Release Specification ; 68HC05K3常规版本规格\n
| 型号： | HC05K3GRS |
| 厂家： | 
ETC |
| 描述： | 68HC05K3 General Release Specification
|
| 文件： | 总132页 (文件大小：1093K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document by
MC68HC05K3/D
Rev. 4.0
HC 5
MC68HC05K3
HCMOS Mic roc ontrolle r Unit
TECHNICAL DATA
Te c hnic a l Da ta — MC68HC05K3
List of Se c tions
Se c tion 1. Ge ne ra l De sc rip tion . . . . . . . . . . . . . . . . . . . 15
Se c tion 2. Me m ory Ma p . . . . . . . . . . . . . . . . . . . . . . . . . 27
Se c tion 3. Ce ntra l Proc e ssor Unit (CPU) Core . . . . . . . . 35
Se c tion 4. Inte rrup ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Se c tion 5. Re se ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Se c tion 6. Op e ra tiona l Mod e s . . . . . . . . . . . . . . . . . . . . 53
Se c tion 7. Pa ra lle l Inp ut/ Outp ut (I/ O) . . . . . . . . . . . . . . 59
Se c tion 8. 8-Bit Tim e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Se c tion 9. Pe rsona lity EEPROM (PEEPROM) . . . . . . . . . . 79
Se c tion 10. Instruc tion Se t. . . . . . . . . . . . . . . . . . . . . . . . 97
Se c tion 11. Ele c tric a l Sp e c ific a tions . . . . . . . . . . . . . . 115
Se c tion 12. Me c ha nic a l Sp e c ific a tions . . . . . . . . . . . . 123
Se c tion 13. Ord e ring Inform a tion . . . . . . . . . . . . . . . . . 127
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List of Sections
List of Se c tions
Technical Data
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MC68HC05K3 — Revision 4.0
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List of Sections
Te c hnic a l Da ta — MC68HC05K3
Ta b le of Conte nts
Section 1. General Description
1.1
1.2
1.3
1.4
1.5
1.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.7
1.7.1
V
and V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
DD SS
1.7.2
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2-Pin Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . .21
2-Pin Ceramic Resonator Oscillator. . . . . . . . . . . . . . . . .22
2-Pin RC Oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3-Pin RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . .24
PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PB0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PB1/OSC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.7.2.1
1.7.2.2
1.7.2.3
1.7.2.4
1.7.2.5
1.7.3
1.7.4
1.7.5
1.7.6
1.7.7
Section 2. Memory Map
2.1
2.2
2.3
2.4
2.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . .29
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .33
Read-Only Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . . . .33
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Ta b le of Conte nts
Section 3. Central Processor Unit (CPU) Core
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.1
3.2
3.3
3.3.1
3.3.2
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Section 4. Interrupts
4.1
4.2
4.3
4.4
4.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Central Processor Unit (CPU) Interrupt Processing . . . . . . . . .40
Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.6
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
IRQ Status/Control Register. . . . . . . . . . . . . . . . . . . . . . . . .45
Port A Interrupts (PA0–PA3) . . . . . . . . . . . . . . . . . . . . . . . .46
Timer Interrupt (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.6.1
4.6.2
4.6.3
4.6.4
Section 5. Resets
5.1
5.2
5.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5.4
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Computer Operating Properly Reset (COPR) . . . . . . . . . . .51
Illegal Address Reset (ILADR) . . . . . . . . . . . . . . . . . . . . . . .51
5.4.1
5.4.2
5.4.3
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Table of Contents
Section 6. Operational Modes
6.1
6.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6.3
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . .57
6.3.1
6.3.2
6.3.3
6.3.4
6.4
PEEPROM Serial Programming Mode. . . . . . . . . . . . . . . . . . .57
Section 7. Parallel Input/Output (I/O)
7.1
7.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . . .61
Port A Pulldown Inhibit Register. . . . . . . . . . . . . . . . . . . . . .61
Port A Light-Emitting Diode (LED) Drive Capability . . . . . . .62
Port A I/O Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Port B Data Direction Register . . . . . . . . . . . . . . . . . . . . . . .65
Port B Pulldown Inhibit Register. . . . . . . . . . . . . . . . . . . . . .65
Port B with 3-Pin RC Oscillator . . . . . . . . . . . . . . . . . . . . . .66
7.4.1
7.4.2
7.4.3
7.4.4
7.5
I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Pin Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
I/O Pin Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
I/O Pin Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
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Section 8. 8-Bit Timer
8.1
8.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
8.3
8.3.1
8.3.2
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Timer Status/Control Register . . . . . . . . . . . . . . . . . . . . . . .74
8.4
8.5
8.6
COP Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Operating During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .77
Operating During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .77
Section 9. Personality EEPROM (PEEPROM)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.1
9.2
9.3
9.3.1
9.3.2
PEEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
PEEPROM Bit Select Register. . . . . . . . . . . . . . . . . . . . . . .81
PEEPROM Status/Control Register . . . . . . . . . . . . . . . . . . .82
9.4
9.5
PEEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
PEEPROM Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
9.6
PEEPROM Serial Programming. . . . . . . . . . . . . . . . . . . . . . . .87
Serial Programming Connections. . . . . . . . . . . . . . . . . . . . .87
Multiple Devices in Serial Program Mode . . . . . . . . . . . . . .88
PEEPROM Serial Programming Mode Entry . . . . . . . . . . . .89
9.6.1
9.6.2
9.6.3
9.7
9.8
9.9
Serial Programming Sequence. . . . . . . . . . . . . . . . . . . . . . . . .91
Serial Data Readout Sequence . . . . . . . . . . . . . . . . . . . . . . . .95
Serial Bulk Erase Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . .96
Section 10. Instruction Set
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
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10.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
10.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
10.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
10.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
10.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
10.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
10.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
10.3.7 Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
10.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
10.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
10.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .102
10.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .103
10.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .104
10.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .106
10.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
10.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Section 11. Electrical Specifications
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
11.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
11.4 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
11.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
11.6 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .118
11.7 3.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .119
11.8 5.0-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
11.9 3.0-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
11.10 1.8-Volt Control Timing (PEEPROM Read Only) . . . . . . . . . .122
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Section 12. Mechanical Specifications
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
12.3 Dual In-Line Package (Case 648). . . . . . . . . . . . . . . . . . . . . .124
12.4 Small Outline Integrated Circuit (Case 751) . . . . . . . . . . . . . .124
12.5 Super Small Outline Package (Case 940C) . . . . . . . . . . . . . .125
Section 13. Ordering Information
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
13.3 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
13.4 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .128
13.5 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .129
13.6 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
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Te c hnic a l Da ta — MC68HC05K3
List of Fig ure s
Figure
Title
Page
1-1
1-2
Pin Assignments for 16-Pin PDIP. . . . . . . . . . . . . . . . . . . . .18
Pin Assignments for 16-Pin SOIC . . . . . . . . . . . . . . . . . . . .18
1-3
1-4
Pin Assignments for 20-Pin SSOP. . . . . . . . . . . . . . . . . . . .19
MC68HC05K3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . .20
1-5
Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2-1
2-2
2-3
MC68HC05K3 Single-Chip Mode Memory Map. . . . . . . . . .28
MC68HC05K3 I/O Registers Memory Map . . . . . . . . . . . . .29
MC68HC05K3 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . .30
3-1
4-1
M68HC05 Programming Model . . . . . . . . . . . . . . . . . . . . . .36
Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . .41
4-2
4-3
Interrupt Stacking Order. . . . . . . . . . . . . . . . . . . . . . . . . . . .42
IRQ Function Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .43
4-4
5-1
6-1
7-1
IRQ Status/Control Register (ISCR). . . . . . . . . . . . . . . . . . .45
Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Stop/Halt/Wait Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . .55
Port A I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
7-2
7-3
Port A Pulldown Inhibit Register (PDRA) . . . . . . . . . . . . . . .62
Port B I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
7-4
Port B Pulldown Inhibit Register (PDRB) . . . . . . . . . . . . . . .65
8-1
8-2
Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Timer Counter Register (TCNTR) . . . . . . . . . . . . . . . . . . . .73
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List of Fig ure s
Figure
Title
Page
8-3
8-4
Timer Status/Control Register (TSCR). . . . . . . . . . . . . . . . .74
COPR Watchdog Timer Location. . . . . . . . . . . . . . . . . . . . .76
9-1
9-2
Personality EEPROM Block Diagram. . . . . . . . . . . . . . . . . .80
PEEPROM Bit Select Register (PEBSR) . . . . . . . . . . . . . . .81
9-3
9-4
9-5
9-6
9-7
9-8
PEEPROM Status/Control Register (PESCR) . . . . . . . . . . .82
Serial Programming Connections. . . . . . . . . . . . . . . . . . . . .88
PEEPROM Serial Programming Mode Data Format . . . . . .90
PEEPROM Serial Programming Data In Timing . . . . . . . . .92
PEEPROM Serial Read Data Out Timing . . . . . . . . . . . . . .93
Bulk Erase Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Technical Data
12
MC68HC05K3 — Revision 4.0
List of Figures
MOTOROLA
Te c hnic a l Da ta — MC68HC05K3
List of Ta b le s
Table
Title
Page
4-1
Vector Addresses for Interrupts and Reset . . . . . . . . . . . . . .40
7-1
7-2
7-3
Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
PB0 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
PB1/OSC3 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
8-1
RTI Rates and COP Reset Times . . . . . . . . . . . . . . . . . . . . .75
9-1
9-2
9-3
Software to Read PEEPROM. . . . . . . . . . . . . . . . . . . . . . . . .83
PEEPROM Serial Programming Mode Operations . . . . . . . .90
Internal Test Time Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . .94
10-1
10-2
10-3
10-4
10-5
10-6
10-7
Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .102
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .103
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . .105
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . .106
Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
13-1
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
MC68HC05K3 — Revision 4.0
MOTOROLA
Technical Data
List of Tables
13
List of Ta b le s
Technical Data
14
MC68HC05K3 — Revision 4.0
MOTOROLA
List of Tables
Te c hnic a l Da ta — MC68HC05K3
Se c tion 1. Ge ne ra l De sc rip tion
1.1 Conte nts
1.2
1.3
1.4
1.5
1.6
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.7
1.7.1
1.7.2
V
and V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
DD SS
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.7.2.1
1.7.2.2
1.7.2.3
1.7.2.4
1.7.2.5
1.7.3
2-Pin Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . .21
2-Pin Ceramic Resonator Oscillator. . . . . . . . . . . . . . . . .22
2-Pin RC Oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3-Pin RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.7.4
1.7.5
1.7.6
1.7.7
Maskable Interrupt Request (IRQ) . . . . . . . . . . . . . . . . . . . .24
PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PB0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PB1/OSC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.2 Introd uc tion
The low-cost MC68HC05K3 microcontroller (MCU) is a member of the
M68HC05 Family of microprocessors. This device has 64 bytes of user
RAM, 128 bits of personality electronically erasable programmable ROM
(PEEPROM), and 928 bytes of user ROM. This device is available in the
16-pin plastic dual in-line package (PDIP), 16-pin small outline
integrated circuit (SOIC) package, and 20-pin super small outline
MC68HC05K3 — Revision 4.0
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Technical Data
15
General Description
Ge ne ra l De sc rip tion
(SSOP) package. A functional block diagram of the MC68HC05K3 is
shown in Figure 1-4.
1.3 Fe a ture s
• Low-cost HC05 core
• 16-pin PDIP, 16-pin SOIC package, or 20-pin SSOP
• 928 bytes of user ROM, including eight bytes of user vectors
• 64 bytes of user RAM
• Low-power operation at 1.8 V — V minimum (EEPROM read
DD
only)
• 128 bits of personality EEPROM (not memory mapped)
programmed using CPU software or with on-chip serial
programming ROM
• On-chip charge pump for in-circuit programming of the personality
EEPROM at 2.7 to 5.5 Vdc
• 8-bit free-running timer
• 4-stage selectable real-time interrupt generator
• 10 bidirectional input/output (I/O) lines including:
– 8-mA sink capability on four I/O pins (PA7–PA4)
– Mask option for software programmable pulldowns on all I/O
pins
– Mask option for port interrupts on four I/O pins (PA3–PA0)
(keyboard scan feature)
• IRQ interrupt hardware mask, flag bit, and request bit
• Mask option for sensitivity on IRQ interrupt (edge- and
level-sensitive or edge-sensitive only)
• On-chip oscillator (mask options for crystal/ceramic resonator
oscillator with internal 2-MΩ resistor and 2-pin or 3-pin resistor
capacitor (RC) oscillator)
Technical Data
16
MC68HC05K3 — Revision 4.0
General Description
MOTOROLA
General Description
Mask Options
• Mask option for reduced startup delay time with RC oscillator
options
• Mask option for computer operating properly (COP) watchdog
system
• Power-saving stop mode and wait mode instructions
• Mask option to convert STOP instruction to halt mode
• Illegal address reset
• Internal steering diode and pullup resistor on RESET pin to V
DD
• Internal RESET pin pulldown from COP watchdog and ILADR
NOTE: A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low.
Any reference to voltage, current, or frequency specified in the following
sections refers to the nominal values. The exact values and their
tolerance or limits are specified in Section 11. Electrical
Specifications.
1.4 Ma sk Op tions
The MC68HC05K3 contains these eight mask options:
1. COP watchdog timer (enable or disable)
2. IRQ triggering (edge-sensitive or edge- and level-sensitive)
3. Port A interrupts (enable or disable)
4. Port software programmable pulldowns (enable or disable)
5. STOP instruction (enable or disable)
6. Oscillator type (crystal/ceramic resonator or RC)
7. RC oscillator type (2-pin or 3-pin)
8. RC oscillator startup delay (4064 or 16 fOP cycles)
NOTE: The startup delay of 16 fOP cycles and the crystal/ceramic resonator
oscillator should not be selected together.
MC68HC05K3 — Revision 4.0
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TechnicalData
17
General Description
Ge ne ra l De sc rip tion
1.5 Pin Assig nm e nts
The MC68HC05K3 is available in 16-pin PDIP, 16-pin SOIC, and 20-pin
SSOP packages. The pin assignments for these packages are shown in
Figure 1-1, Figure 1-2, and Figure 1-3.
RESET
PB1/OSC3
PB0
OSC1
OSC2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
SS
IRQ
V
DD
PA0
PA7
PA6
PA5
PA4
PA1
PA2
PA3
Figure 1-1. Pin Assignments for 16-Pin PDIP
RESET
PB1/OCS3
PB0
OSC1
OSC2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
V
SS
IRQ
V
DD
PA0
PA7
PA6
PA5
PA4
PA1
PA2
PA3
Figure 1-2. Pin Assignments for 16-Pin SOIC
Technical Data
18
MC68HC05K3 — Revision 4.0
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General Description
General Description
MCU Structure
OSC1
OSC2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RESET
PB1/OSC3
PB0
V
SS
V
IRQ
DD
N/C
N/C
PA7
PA6
PA5
PA4
N/C
N/C
PA0
PA1
PA2
PA3
Figure 1-3. Pin Assignments for 20-Pin SSOP
1.6 MCU Struc ture
The overall block diagram of the MC68HC05K3 is shown in Figure 1-4.
1.7 Func tiona l Pin De sc rip tion
The following paragraphs give a description of the general function of
each pin.
1.7.1 V a nd V
DD
SS
Power is supplied to the MCU through V and V . V is the positive
DD
SS DD
supply and V is ground. The MCU operates from a single power
SS
supply.
Rapid signal transitions occur on the MCU pins. The short rise and fall
times place very high short-duration current demands on the power
supply. To prevent noise problems, special care should be taken to
provide good power supply bypassing at the MCU by using bypass
capacitors with high-frequency characteristics that are positioned as
close to the MCU as possible.
MC68HC05K3 — Revision 4.0
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TechnicalData
19
General Description
Ge ne ra l De sc rip tion
OSC 1
SELECTABLE
OSCILLATOR
÷2
8-BIT
TIMER SYSTEM
OSC 2
V
SS
WATCHDOG &
ILLEGAL ADDRESS
DETECT
V
DD
CPU CONTROL
CPU REGISTERS
ALU
RESET
IRQ
68HC05 CPU
PB1/OSC3
PB0
ACCUM
INDEX REGISTER
0 0 0 0 0 0 0 0 1 1
SP
1
PROGRAM COUNTER
PA7 *
PA6 *
PA5 *
PA4 *
PA3 **
PA2 **
PA1 **
PA0 **
COND CODE REGISTER 1 1 1 H I N Z C
SRAM — 64 BYTES
USER ROM — 928 BYTES
SERIAL PROGRAM AND INTERNAL
TEST ROM — 256 BYTES
ON-CHIP
CHARGE
PUMP
PERSONALITY EEPROM — 128 BITS
*
8-mA sink capability
** IRQ interrupt capability
Figure 1-4. MC68HC05K3 Block Diagram
Technical Data
20
MC68HC05K3 — Revision 4.0
MOTOROLA
General Description
General Description
Functional Pin Description
1.7.2 OSC1 a nd OSC2
The OSC1 and OSC2 pins are the connections for the 2-pin on-chip
oscillator. The OSC1 and OSC2 pins also can be used in conjunction
with the PB1/OSC3 pin to create a more stable 3-pin RC oscillator.
The OSC1, OSC2, and PB1/OSC3 pins can accept these sets of
components:
1. A crystal, as shown in Figure 1-5(a)
2. A ceramic resonator, as shown in Figure 1-5(a)
3. An external resistor and capacitor using two pins, as shown in
Figure 1-5(b)
4. An external resistor and capacitor using three pins, as shown in
Figure 1-5(c)
5. An external clock signal, as shown in Figure 1-5(d)
The frequency, f
, of the oscillator or external clock source is divided
OSC
by two to produce the internal operating frequency, f . The oscillator
OP
type is selected by two mask options.
1.7.2.1 2-Pin Crysta l Osc illa to r
The circuit in Figure 1-5(a) shows a typical 2-pin oscillator circuit for an
AT-cut, parallel resonant crystal. The crystal manufacturer’s
recommendations should be followed, since the crystal parameters
determine the external component values required to provide maximum
stability and reliable startup. The load capacitance values used in the
oscillator circuit design should include all stray capacitances. The crystal
and components should be mounted as close as possible to the pins for
startup stabilization and to minimize output distortion. An internal startup
resistor of approximately 2 MΩ is provided between OSC1 and OSC2
when the crystal/ceramic resonator oscillator option is used.
MC68HC05K3 — Revision 4.0
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TechnicalData
21
General Description
Ge ne ra l De sc rip tion
MCU
MCU
2 MΩ (MASK OPTION)
OSC1
OSC2
OSC1
C
OSC2
*Starting value only. Follow crystal
supplier’s recommendations
regarding component values that
will provide reliable startup and
maximum stability.
R
36
36 pF*
(a) 2-Pin Crystal or
Ceramic Resonator
Connections
(b) 2-Pin
RC Oscillator
Connections
MCU
MCU
OSC1
OSC2
PB1/OSC3
OSC1
OSC2
C
R
UNCONNECTED
EXTERNAL CLOCK
(c) 3-Pin
RC Oscillator
Connections
(d) External
Clock Source
Connection
Figure 1-5. Oscillator Connections
1.7.2.2 2-Pin Ce ra m ic Re so na to r Osc illa to r
In cost-sensitive applications, a ceramic resonator can be used instead
of the crystal. The circuit in Figure 1-5(a) is designed for either a crystal
or a ceramic resonator. The resonator manufacturer’s recommendations
should be followed, since the resonator parameters determine the
external component values required for maximum stability and reliable
starting. The load capacitance values used in the oscillator circuit design
should include all stray capacitances. The ceramic resonator and
components should be mounted as close as possible to the pins for
startup stabilization and to minimize output distortion. An internal startup
resistor of approximately 2 MΩ is provided between OSC1 and OSC2 for
the crystal/ceramic resonator oscillator mask option.
Technical Data
22
MC68HC05K3 — Revision 4.0
General Description
MOTOROLA
General Description
Functional Pin Description
1.7.2.3 2-Pin RC Osc illa to rs
The 2-pin RC oscillator configuration can be used for very low-cost
applications. With this option, a resistor must be connected between the
two oscillator pins and a capacitor must be connected from the OSC1 pin
to V , as shown in Figure 1-5(b). The signal on the OSC2 pin is a
SS
square wave and the signal on the OSC1 pin approximates a triangular
wave.
The 2-pin RC oscillator is optimized for operation at 500 kHz. This
oscillator can be used at higher or lower frequencies with degraded
accuracy over temperature, supply voltage, and/or device processing
variations. The internal startup resistor of approximately 2 MΩ is not
connected between OSC1 and OSC2 when the 2-pin RC oscillator mask
option is selected.
1.7.2.4 3-Pin RC Osc illa to r
Another low cost, but more accurate, type of RC oscillator is the 3-pin
configuration utilizing the PB1/OSC3 pin. With this option, a resistor
must be connected between the OSC1 and OSC2 pins and a capacitor
must be connected between the OSC1 and PB1/OSC3 pins, as shown
in Figure 1-5(c). This 3-pin RC oscillator is more accurate than the 2-pin
RC oscillator with respect to temperature, supply voltage, and/or device
processing variations. The signal on the OSC2 and PB1/OSC3 pins is a
square wave and the signal on the OSC1 pin approximates a triangular
wave.
The 3-pin RC oscillator is optimized for operation at 500 kHz. This
oscillator can be used at higher or lower frequencies with degraded
accuracy over temperature, supply voltage, and/or device processing
variations. The internal startup resistor of approximately 2 MΩ is not
connected between OSC1 and OSC2 when the 3-pin RC oscillator mask
option is selected. The typical external components for a 500-kHz
oscillator are a 20-kΩ resistor and a 25- to 30-pF capacitor.
NOTE: Capacitors used with the RC oscillators should have minimal leakage.
Electrolytic or tantalum capacitors should not be used because they
degrade the temperature performance of the oscillator due to excessive
variation in their leakage.
MC68HC05K3 — Revision 4.0
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TechnicalData
23
General Description
Ge ne ra l De sc rip tion
1.7.2.5 Exte rna l Clo c k
An external clock from another CMOS-compatible device can be
connected to the OSC1 input, with the OSC2 input not connected, as
shown in Figure 1-5(d). This configuration is possible regardless of
whether the oscillator is set up for crystal/ceramic resonator, 2-pin RC,
or 3-pin RC operation. However, if the 3-pin RC oscillator is selected, the
PB1/OSC3 pin also must be left unconnected.
1.7.3 Re se t (RESET)
This pin can be used as an input to reset the MCU to a known startup
state by pulling the pin to the low state. The RESET pin contains a
steering diode to discharge any voltage on the pin to V when the
DD
power is removed. The RESET pin contains an internal pullup resistor to
V
of approximately 100 kΩ to allow the RESET pin to be left
DD
unconnected for low-power applications. The RESET pin contains an
internal Schmitt trigger to improve its noise immunity as an input.
The RESET pin has an internal pulldown device that pulls the RESET
pin low when there is an internal COP watchdog or an illegal address
reset. Refer to Section 5. Resets.
1.7.4 Ma ska b le Inte rrup t Re q ue st (IRQ)
The IRQ input pin drives the asynchronous IRQ interrupt function of the
CPU. The IRQ interrupt function has a mask option to select either
negative edge-sensitive triggering or both negative edge-sensitive and
low level-sensitive triggering. If the option is selected to include
level-sensitive triggering, the IRQ pin requires an external resistor to
V
if “wired-OR” operation is desired. If the IRQ pin is not used, it must
DD
be tied to the V supply.
DD
NOTE: Each of the PA0–PA3 I/O pins can be connected through an OR gate to
the IRQ interrupt function by a common mask option. This capability
allows keyboard scan applications where the transitions or levels on the
I/O pins behave the same as the IRQ pin, except that the logic level is
Technical Data
24
MC68HC05K3 — Revision 4.0
General Description
MOTOROLA
General Description
Functional Pin Description
inverted. The edge or level sensitivity selected by the mask option for the
IRQ pin also applies to the I/O pins ORed to create an IRQ signal.
The IRQ pin contains an internal Schmitt trigger to improve noise
immunity. For more details, see Section 4. Interrupts.
1.7.5 PA0–PA7
These eight I/O lines comprise port A. The state of any pin is software
programmable and all port A lines are configured as inputs during
power-on or reset, except in serial program mode. The four upper-order
I/O pins (PA4–PA7) are capable of sinking higher currents. The four
lower-order I/O pins (PA0–PA3) can be connected via an internal OR
gate to the IRQ interrupt function by a mask option. All the port A pins
can have software programmable pulldown devices provided by another
mask option. See Section 7. Parallel Input/Output (I/O) for more
details on the I/O ports.
1.7.6 PB0
The state of the PB0 pin is software programmable and is configured as
an input during power-on or reset, except in serial program mode. This
pin can have a software programmable pulldown device provided by a
mask option. See Section 7. Parallel Input/Output (I/O) for more
details on the I/O ports.
1.7.7 PB1/ OSC3
The state of the PB1/OSC3 pin is software programmable and is
configured as an input during power-on or reset, except in serial program
mode or when the 3-pin RC oscillator configuration is selected by mask
option. This pin can have a software programmable pulldown device
provided by a mask option. See Section 7. Parallel Input/Output (I/O)
for more details on the I/O ports.
MC68HC05K3 — Revision 4.0
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25
General Description
Ge ne ra l De sc rip tion
Technical Data
26
MC68HC05K3 — Revision 4.0
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General Description
Te c hnic a l Da ta — MC68HC05K3
Se c tion 2. Me m ory Ma p
2.1 Conte nts
2.2
2.3
2.4
2.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Input/Output and Control Registers . . . . . . . . . . . . . . . . . . . . .29
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .33
Read-Only Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . . . .33
MC68HC05K3 — Revision 4.0
MOTOROLA
Technical Data
Memory Map
27
Me m ory Ma p
2.2 Introd uc tion
The MC68HC05K3 has several input/output (I/O) features, 64 bytes of
user random-access memory (RAM), 128 bits of user personality
electronically erasable programmable read-only memory (PEEPROM),
and 928 bytes of user read-only memory (ROM), which are all active in
the single-chip mode as shown in Figure 2-1.
$0000
0000
I/O
32 BYTES
(SEE Figure 2-2)
$001F
$0020
0031
0032
USER ROM
160 BYTES
$00BF
$00C0
0191
0192
USER RAM
64 BYTES
$00DF
$00E0
0223
0224
STACK
32 BYTES
$00FF
$0100
0255
0256
USER ROM
760 BYTES
TIMER VECTOR (HIGH BYTE)
TIMER VECTOR (LOW BYTE)
IRQ VECTOR (HIGH BYTE)
IRQ VECTOR (LOW BYTE)
SWI VECTOR (HIGH BYTE)
SWI VECTOR (LOW BYTE)
RESET VECTOR (HIGH BYTE)
RESET VECTOR (LOW BYTE)
$03F8
$03F9
$03FA
$03FB
$03FC
$03FD
$03FE
$03FF
$03F0
COP WATCHDOG TIMER
1008
1016
$03F7
$03F8
USER VECTORS ROM
8 BYTES
$03FF
1023
Figure 2-1. MC68HC05K3 Single-Chip Mode Memory Map
Technical Data
28
MC68HC05K3 — Revision 4.0
MOTOROLA
Memory Map
Memory Map
Input/Output and Control Registers
2.3 Inp ut/ Outp ut a nd Control Re g iste rs
The input/output (I/O) and status/control registers reside in locations
$0000–$001F. The overall organization of these registers is shown in
Figure 2-2.
The bit assignments for each register are shown in Figure 2-3. Reading
unimplemented bits returns unknown states, and writing to
unimplemented bits has no effect.
PORT A DATA REGISTER
PORT B DATA REGISTER
$0000
$0001
UNIMPLEMENTED (2)
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
$0004
$0005
UNIMPLEMENTED (2)
TIMER STATUS & CONTROL REGISTER
TIMER COUNTER REGISTER
$0008
$0009
$000A
IRQ STATUS & CONTROL REGISTER
UNIMPLEMENTED (3)
PEEPROM BIT SELECT REGISTER
PEEPROM CONTROL & STATUS REGISTER
PORT A PULLDOWN REGISTER
$000E
$000F
$0010
$0011
PORT B PULLDOWN REGISTER
UNIMPLEMENTED (13)
RESERVED
$001F
Figure 2-2. MC68HC05K3 I/O Registers Memory Map
MC68HC05K3 — Revision 4.0
MOTOROLA
TechnicalData
29
Memory Map
Me m ory Ma p
Addr.
Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port A Data
(PORTA)
$0000
Unaffected by reset
0
0
0
0
0
0
PB1
PB0
Port B Data
(PORTB)
$0001
$0002
$0003
Unaffected by reset
Unimplemented
Unimplemented
Read:
Write:
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Port A Data Direction
(DDRA)
$0004
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DDRB1 DDRB0
Port B Data Direction
(DDRB)
$0005
$0006
$0007
0
0
0
0
0
0
0
0
Unimplemented
Unimplemented
Read:
Write:
Read: TOF
Write:
RTIF
0
0
TOFR
0
0
RTIFR
0
TOIE
0
RTIE
0
RT1
1
RT0
1
Timer Status/Control
(TSCR)
$0008
Reset:
0
R
= Unimplemented
= Reserved
Figure 2-3. MC68HC05K3 I/O Registers (Sheet 1 of 4)
Technical Data
30
MC68HC05K3 — Revision 4.0
MOTOROLA
Memory Map
Memory Map
Input/Output and Control Registers
Addr.
Name
Bit 7
Read: TCR7
Write:
6
5
4
3
2
1
Bit 0
TCR6
TCR5
TCR4
TCR3
TCR2
TCR1
TCR0
Timer Counter
$0009
(TCNTR)
Reset:
Read:
Write:
Reset:
Read:
Write:
0
IRQE
1
0
0
0
0
0
0
0
0
0
0
0
0
0
IRQF
IRQ Status/Control
(ISCR)
$000A
$000B
$000C
$000D
R
0
IRQR
0
0
0
0
0
0
Unimplemented
Unimplemented
Unimplemented
Read:
Write:
Read:
Write:
Read:
Write:
Reset:
PEB7
0
PEB6
0
PEB5
0
PEB4
0
PEB3
0
PEB2
0
PDB1
PDB0
Personality EEPROM
Bit Select (PEBSR)
$000E
$000F
$0010
$0011
0
0
0
Read: PEDATA
Write:
PEPCZF
PEBULK PEPGM PEBYTE CPEN CPCLK
Personality EEPROM
Status/Control (PESCR)
Reset:
Read:
1
0
0
0
0
0
0
1
Port A Pulldown Inhibit
(PDRA)
Write: PDIA7
PDIA6
0
PDIA5
0
PDIA4
0
PDIA3
0
PDIA2
0
PDIA1
0
PDIA0
0
Reset:
Read:
Write:
Reset:
0
Port B Pulldown Inhibit
(PDRB)
PDIB1
0
PDIB0
0
R
= Unimplemented
= Reserved
Figure 2-3. MC68HC05K3 I/O Registers (Sheet 2 of 4)
MC68HC05K3 — Revision 4.0
MOTOROLA
TechnicalData
31
Memory Map
Me m ory Ma p
Addr.
Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
$0012
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Read:
Write:
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
R
= Unimplemented
= Reserved
Figure 2-3. MC68HC05K3 I/O Registers (Sheet 3 of 4)
Technical Data
32
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MOTOROLA
Memory Map
Memory Map
Random-Access Memory (RAM)
Addr.
Name
Unimplemented
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
$001C
Read:
Write:
$001D
$001E
$001F
Unimplemented
Unimplemented
Reserved
Read:
Write:
Read:
Write:
R
R
R
R
R
R
R
R
R
= Unimplemented
= Reserved
Figure 2-3. MC68HC05K3 I/O Registers (Sheet 4 of 4)
2.4 Ra nd om -Ac c e ss Me m ory (RAM)
The total RAM consists of 64 bytes (including the stack) at locations
$00C0–$00FF. The stack pointer can access 32 locations from $00E0
to $00FF. The stack begins at address $00FF and proceeds down to
$00E0. Using the stack area for data storage or temporary work
locations requires care to prevent it from being overwritten due to
stacking from an interrupt or subroutine call.
2.5 Re a d -Only Me m ory (ROM)
There are a total of 928 bytes of user ROM on the chip. This includes
160 bytes in page zero from $0020–$00BF, 760 bytes of user ROM with
locations $0100–$03F7 for user program storage, and 8 bytes of user
vectors at locations $03F8–$03FF.
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33
Memory Map
Me m ory Ma p
Technical Data
34
MC68HC05K3 — Revision 4.0
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Memory Map
Te c hnic a l Da ta — MC68HC05K3
Se c tion 3. Ce ntra l Proc e ssor Unit (CPU) Core
3.1 Conte nts
3.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.3
3.3.1
3.3.2
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.2 Introd uc tion
The MC68HC05K3 has a 1024-byte memory map. Therefore, it uses
only the lower 10 bits of the address bus. In the following discussion, the
upper six bits of the address bus can be ignored. Also, by using a mask
option, the STOP instruction can be converted from acting as the normal
STOP instruction. The stack area also is reduced to 32 bytes due to the
limited amount of RAM. Therefore, the stack pointer is reduced to only
five bits, only decrements down to $00E0, and then wraps around to
$00FF. All other instructions and registers behave as described in
M6805 HMOS/M146805 CMOS Family User’s Manual, Motorola
document order number M6805UM/AD3.
MC68HC05K3 — Revision 4.0
MOTOROLA
Technical Data
35
Central Processor Unit (CPU) Core
Ce ntra l Proc e ssor Unit (CPU) Core
3.3 Re g iste rs
The MCU contains five registers that are hard-wired within the CPU and
are not part of the memory map. These five registers are shown in
Figure 3-1.
7
6
5
4
3
2
1
0
ACCUMULATOR
INDEX REGISTER
A
X
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
1
1
1
1
SP
PC
CC
STACK POINTER
0
0
0
0
0
0
PROGRAM COUNTER
CONDITION CODE REGISTER
1
1
H
I
N
Z
C
HALF-CARRY BIT (FROM BIT 3)
INTERRUPT MASK
NEGATIVE BIT
ZERO BIT
CARRY BIT
Figure 3-1. M68HC05 Programming Model
For a more complete description of the M68HC05 CPU functions, refer
to:
•
•
•
M6805 HMOS, M146805 CMOS Family User’s Manual, Motorola
order number M6805UM(AD3)
HC05 Applications Guide, Motorola order number
M68HC05AG/AD
Understanding Small Microcontrollers, Motorola order number
M68HC05TB/D
Any specific differences in the operation of all CPU registers or bits is
described in the following sections.
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Central Processor Unit (CPU) Core
MOTOROLA
Central Processor Unit (CPU) Core
Registers
3.3.1 Sta c k Pointe r (SP)
The stack pointer shown in Figure 3-1 is a 16-bit register internally. In
devices with memory maps less than 64 Kbytes, the unimplemented
upper address lines are ignored. The stack pointer contains the address
of the next free location on the stack. When accessing memory, the 11
most significant bits are permanently set to 00000000111. The five least
significant register bits are appended to these 11 fixed bits to produce an
address within the range of $00FF to $00E0. Subroutines and interrupts
may use up to 32 ($20) locations. If 32 locations are exceeded, the stack
pointer wraps around to $00FF and writes over the previously stored
information.
3.3.2 Prog ra m Counte r (PC)
The program counter shown in Figure 3-1 is a 16-bit register internally.
The program counter contains the address of the next instruction or
operand to be fetched. The six most significant bits of the program
counter are ignored internally and appear as 000000 when stacked onto
the RAM.
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Central Processor Unit (CPU) Core
Ce ntra l Proc e ssor Unit (CPU) Core
Technical Data
MC68HC05K3 — Revision 4.0
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38
Central Processor Unit (CPU) Core
Te c hnic a l Da ta — MC68HC05K3
Se c tion 4. Inte rrup ts
4.1 Conte nts
4.2
4.3
4.4
4.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Central Processor Unit (CPU) Interrupt Processing . . . . . . . . .40
Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.6
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
IRQ Status/Control Register. . . . . . . . . . . . . . . . . . . . . . . . .45
Port A Interrupts (PA0–PA3) . . . . . . . . . . . . . . . . . . . . . . . .46
Timer Interrupt (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.6.1
4.6.2
4.6.3
4.6.4
4.2 Introd uc tion
The MCU can be interrupted four different ways:
1. Non-maskable software interrupt instruction (SWI)
2. External asynchronous interrupt (IRQ)
3. External interrupt via IRQ on PA0–PA3 (enabled by a mask
option)
4. Internal timer interrupt (TIMER)
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Technical Data
39
Interrupts
Inte rrup ts
4.3 Ce ntra l Proc e ssor Unit (CPU) Inte rrup t Proc e ssing
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete.
If interrupts are not masked (I bit in the CCR is clear) and the
corresponding interrupt enable bit is set, the processor proceeds with
interrupt processing. Otherwise, the next instruction is fetched and
executed. If an interrupt occurs, the processor completes the current
instruction, stacks the current CPU register states, sets the I bit to inhibit
further interrupts, and finally checks the pending hardware interrupts. If
more than one interrupt is pending following the stacking operation, the
interrupt with the highest vector location, shown in Table 4-1, is serviced
first. The software interrupt (SWI) is executed the same as any other
instruction, regardless of the I-bit state.
When an interrupt is to be processed, the CPU fetches the address of
the appropriate interrupt software service routine from the vector table at
locations $03F8–$03FF as defined in Table 4-1.
Table 4-1. Vector Addresses for Interrupts and Reset
CPU
Interrupts
Vector
Addresses
Register
Flag Name
Interrupts
N/A
N/A
N/A
N/A
Reset
RESET
SWI
$03FE–$03FF
$03FC–$03FD
$03FA–$03FB
$03F8–$03F9
$03F8–$03F9
Software
ISCR
TSCR
TSCR
IRQF
TOF
RTIF
External interrupt
Timer overflow
Real-time interrupt
IRQ
TIMER
TIMER
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MOTOROLA
Interrupts
Interrupts
Central Processor Unit (CPU) Interrupt Processing
A return-from-interrupt (RTI) instruction is used to signify when the
interrupt software service routine is complete. The RTI instruction
causes the register contents to be recovered from the stack and normal
processing to resume at the next instruction that was to be executed
when the interrupt took place. Figure 4-1 shows the sequence of events
that occurs during interrupt processing. Figure 4-2 shows the stacking
and unstacking order into the RAM that is associated with an interrupt
service routine.
FROM
RESET
IS
I BIT
Y
SET?
N
IRQ
EXTERNAL
INTERRUPT?
CLEAR IRQ
REQUEST
LATCH
Y
Y
N
TIMER
INTERNAL
INTERRUPT?
N
STACK PCL, PCH, X, A, CC
SET I BIT IN CCR
FETCH NEXT
INSTRUCTION
LOAD PC FROM:
SWI: $03FC, $03FD
IRQ: $03FA–$03FB
TIMER: $03F8–$03F9
SWI
INSTRUCTION
?
Y
Y
N
RTI
INSTRUCTION
?
RESTORE REGISTERS
FROM STACK
CC, A, X, PCH, PCL
N
EXECUTE
INSTRUCTION
Figure 4-1. Interrupt Processing Flowchart
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Interrupts
Inte rrup ts
STACK
I
1
0
1
0
1
0
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
N
R
E
T
U
R
N
T
E
R
R
U
P
DECREASING
MEMORY
ADDRESSES
INCREASING
MEMORY
ADDRESSES
0
0
0
PCH
T
PCL
UNSTACK
Figure 4-2. Interrupt Stacking Order
4.4 Re se t Inte rrup t Se q ue nc e
The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner. A low-level input on the RESET pin or
an internally generated reset (RST) signal causes the program to vector
to its starting address, which is specified by the contents of memory
locations $03FE and $03FF. The I bit in the condition code register also
is set. The MCU is configured to a known state during this type of reset,
as described in Section 5. Resets.
4.5 Softwa re Inte rrup t (SWI)
The SWI is an executable instruction and a non-maskable interrupt since
it is executed regardless of the state of the I bit in the CCR. If the I bit
is 0 (interrupts enabled), the SWI instruction executes after interrupts
that were pending before the SWI was fetched or before interrupts
generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of memory locations $03FC and
$03FD.
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Interrupts
MOTOROLA
Interrupts
Hardware Interrupts
4.6 Ha rd wa re Inte rrup ts
All hardware interrupts except RESET are maskable by the I bit in the
CCR. If the I bit is set, all hardware interrupts (internal and external) are
disabled. Clearing the I bit enables the hardware interrupts. The two
types of hardware interrupts are explained here.
4.6.1 Exte rna l Inte rrup t (IRQ)
The IRQ pin provides an asynchronous interrupt to the CPU. A block
diagram of the IRQ function is shown in Figure 4-3.
The IRQ pin is one source of an IRQ interrupt, and a mask option is
available to enable the four lower order port A pins (PA0–PA3) to act as
other IRQ interrupt sources. All of these sources are combined into a
single ORing function that is latched by the IRQ latch.
The IRQ latch is set on the falling edge of the IRQ pin or on the rising
edge of a PA0–PA3 pin, if port A interrupts have been enabled by the
mask option.
TO BIH & BIL
INSTRUCTION
SENSING
IRQ PIN
PA0
V
DD
PA1
LATCH
PA2
PA3
IRQF
PORT A IRQ
R
MASK OPTION
RST
IRQR
IRQ VECTOR FETCH
TO IRQ
PROCESSING
IN CPU
IRQE
IRQ SENSITIVITY
MASK OPTION
Figure 4-3. IRQ Function Block Diagram
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Interrupts
Inte rrup ts
If the mask option for edge-sensitive only IRQ is used, only the IRQ
latch output can activate an IRQF flag which creates a request to the
CPU to generate the IRQ interrupt sequence. This makes the IRQ
interrupt sensitive to these cases:
• If the port A interrupts are disabled by a mask option, only a falling
edge on the IRQ pin initiates an IRQ interrupt.
• If the port A interrupts are enabled by a mask option, these
conditions initiate an IRQ interrupt:
– A falling edge on the IRQ pin with all the PA0–PA3 pins at a
low level
– A rising edge on one PA0–PA3 pin with all other PA0–PA3 pins
at a low level and the IRQ pin at a high level
If the mask option for edge- and level-sensitive IRQ is used, the active
high state of the IRQ latch input also can activate an IRQF flag, which
creates a request to the CPU to generate the IRQ interrupt sequence.
This makes the IRQ interrupt sensitive to these cases:
• If the port A interrupts are disabled by a mask option, only these
conditions initiate an IRQ interrupt:
– A low level on the IRQ pin
– Falling edge on the IRQ pin
• If the port A interrupts are enabled by a mask option, these
conditions initiate an IRQ interrupt:
– A low level on the IRQ pin with all the PA0–PA3 pins at a low
level
– Falling edge on the IRQ pin with all the PA0–PA3 pins at a low
level
– High level on any one of the PA0–PA3 pins with the IRQ pin at
a high level
– Rising edge on any PA0–PA3 pin with all other PA0–PA3 pins
at a low level and the IRQ pin at a high level
The IRQE enable bit controls whether an active IRQF flag can generate
an IRQ interrupt sequence. This interrupt is serviced by the interrupt
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Interrupts
MOTOROLA
Interrupts
Hardware Interrupts
service routine located at the address specified by the contents of $03FA
and $03FB.
Entering the interrupt service routine automatically clears the IRQ latch.
The IRQ interrupt service routine also may clear the IRQ latch by writing
a logic 1 to the IRQR acknowledge bit in the ISCR. As long as the output
state of the IRQF flag bit is active, the CPU continuously re-enters the
IRQ interrupt sequence following an RTI instruction until the active state
is removed or the IRQE enable bit is cleared.
4.6.2 IRQ Sta tus/ Control Re g iste r
The IRQ interrupt function is controlled by the IRQ status/control register
(ISCR) located at $000A as shown in Figure 4-4. All unused bits in the
ISCR read as logic 0s. A reset clears the IRQF bit and sets the IRQE
bit.
Address: $000A
Bit 7
IRQE
1
6
0
5
0
4
0
3
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
IRQF
R
0
IRQR
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 4-4. IRQ Status/Control Register (ISCR)
IRQR — IRQ Interrupt Acknowledge Bit
The IRQR acknowledge bit clears an IRQ interrupt request by
clearing the IRQ latch. If the IRQ latch is set again while in the IRQ
service routine (before an RTI instruction is executed), the CPU
re-enters the IRQ interrupt service routine unless the IRQ latch is
cleared. Writing a logic 1 to the IRQR acknowledge bit clears the IRQ
latch. Writing a logic 0 to the IRQR acknowledge bit has no effect on
the IRQ latch. The IRQR acknowledge bit always reads as a logic 0.
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Interrupts
45
Inte rrup ts
IRQF — IRQ Interrupt Request Bit
The IRQF flag bit indicates that an IRQ request is pending. Writing to
the IRQF flag bit has no effect on it. The IRQF flag bit is cleared
automatically when the IRQ vector is fetched and the service routine
is entered. The IRQF flag bit also can be cleared by writing a logic 1
to the IRQR acknowledge bit to clear the IRQ latch and also condition
the external IRQ sources to be inactive if the edge- and level-sensitive
mask option is selected. In this way, any additional setting of the IRQF
flag bit while in the service routine can be ignored by clearing the
IRQF flag bit just before exiting the service routine. If the IRQF flag bit
is set again while in the IRQ service routine, the CPU re-enters the
IRQ interrupt sequence unless the IRQF flag bit is cleared. The IRQF
flag bit is cleared by reset.
IRQE — IRQ Interrupt Enable Bit
The IRQE bit enables or disables the IRQF flag bit to initiate an IRQ
interrupt sequence. If the IRQE enable bit is set, the IRQF flag bit can
generate an interrupt sequence. If the IRQE enable bit is cleared, the
IRQF flag bit cannot generate an interrupt sequence. Reset sets the
IRQE enable bit, thereby enabling IRQ interrupts once the I bit is
cleared. Execution of the STOP or WAIT instructions causes the
IRQE bit to be set to allow the external IRQ to exit these modes. In
addition, reset also sets the I bit, which masks all interrupt sources.
NOTE: If the I bit is cleared, any instruction that sets the IRQE enable bit when
the IRQF flag bit is already set initiates an IRQ interrupt sequence
immediately after that instruction.
4.6.3 Port A Inte rrup ts (PA0–PA3)
The IRQ interrupt also can be triggered by inputs to PA0–PA3 port pins
as described in 4.6.1 External Interrupt (IRQ) if the port interrupts mask
option is used. If enabled, the lower four bits of port A can activate the
IRQ interrupt function and the interrupt operation is the same as the
input to the IRQ pin. The mask option allows all of these input pins to be
ORed with the input present on the IRQ pin. All PA0–PA3 pins must be
selected as a group and as an additional IRQ interrupt source. All the
port A interrupt sources also are controlled by the IRQE enable bit.
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Interrupts
MOTOROLA
Interrupts
Hardware Interrupts
NOTE: The BIH and BIL instructions apply only to the level on the IRQ pin itself
and not to the output of the logic OR gate with PA0–PA3 pins. The state
of the individual port A pins can be checked by reading the appropriate
port A pins as inputs.
NOTE: If port A interrupts are enabled, the state of PA0–PA3 pins may cause
an IRQ interrupt regardless of whether these pins are configured as
inputs or outputs. (See Section 7. Parallel Input/Output (I/O).)
4.6.4 Tim e r Inte rrup t (TIMER)
The timer interrupt is generated by the 8-bit timer when either a timer
overflow or a real-time interrupt has occurred, as described in
Section 8. 8-Bit Timer. The interrupt flags and enable bits for the timer
interrupts are in the timer status/control register (TSCR) located at
$0008. The I bit in the CCR must be clear for the timer interrupt to be
enabled. Either of these two interrupts vector to the same interrupt
service routine located at the address specified by the contents of
memory locations $03F8 and $03F9.
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Interrupts
Inte rrup ts
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Interrupts
Te c hnic a l Da ta — MC68HC05K3
Se c tion 5. Re se ts
5.1 Conte nts
5.2
5.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
5.4
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Computer Operating Properly Reset (COPR) . . . . . . . . . . .51
Illegal Address Reset (ILADR) . . . . . . . . . . . . . . . . . . . . . . .51
5.4.1
5.4.2
5.4.3
5.2 Introd uc tion
The MCU can be reset from four sources: one external input and three
internal restart conditions. The RESET pin is an input with a Schmitt
trigger, as shown in Figure 5-1. All the internal peripheral modules that
drive external pins are reset by the synchronous reset signal (RST)
coming from a latch, which is synchronized to the PH2 bus clock and set
by any of the four reset sources.
NOTE: Activation of the RST signal generally is referred to as a reset of the
device, unless otherwise specified.
MC68HC05K3 — Revision 4.0
MOTOROLA
Technical Data
49
Resets
Re se ts
V
DD
RESET
CPU
OSC
DATA
ADDRESS
COP WATCHDOG
RESET (COPR)
S
TO OTHER
PERIPHERALS
LATCH
POWER-ON RESET
(POR)
RST
V
DD
PH2
ILLEGAL ADDRESS
(ILADR)
ADDRESS
Figure 5-1. Reset Block Diagram
5.3 Exte rna l Re se t (RESET)
The RESET pin is the only external source of a reset. This pin is
connected to a Schmitt trigger input gate to provide noise immunity. This
external reset occurs whenever the RESET pin is pulled low and
remains in reset until the RESET pin rises to a logic 1. This active low
input generates the RST signal and resets the CPU and peripherals.
5.4 Inte rna l Re se ts
The three internally generated resets are:
• Initial power-on reset (POR) function
• Computer operating properly (COP) watchdog timer reset
• Illegal address detector reset (ILADR)
5.4.1 Powe r-On Re se t (POR)
The internal POR is generated on power-up of the internal CPU to allow
the clock oscillator to stabilize. The POR is strictly for power turn-on
conditions and is not able to detect a drop in the power supply voltage (a
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Resets
MOTOROLA
Resets
Internal Resets
“brown-out” condition). After the oscillator becomes active, a mask
option selects an oscillator stabilization delay of 16 or 4064 cycles of the
internal processor bus clock (PH2).
The POR generates the RST signal that resets the CPU. If any other
reset function is active at the end of this stabilization delay, the RST
signal remains in the reset condition until the other reset condition(s)
end(s).
5.4.2 Com p ute r Op e ra ting Prop e rly Re se t (COPR)
A COP watchdog timer can be enabled by a mask option. The internal
COP reset (COPR) is generated automatically by a timeout of the COP
watchdog timer. This timeout occurs if the counter in the COP watchdog
timer is not reset (cleared) within a specific time by a user program reset
sequence. Refer to 8.4 COP Watchdog Timer for more information on
this timeout feature.
The COPR generates the RST signal that resets the CPU and other
peripherals. If any other reset function is active at the end of the COPR
reset signal, the RST signal remains in the reset condition until the other
reset condition(s) end(s).
The COP watchdog reset activates the internal pulldown device
connected to the RESET pin for one cycle of the internal processor bus
clock, PH2.
5.4.3 Ille g a l Ad d re ss Re se t (ILADR)
The internal ILADR reset is generated when an instruction opcode fetch
occurs from an address in the I/O address area ($0000–$001F). The
ILADR generates the RST signal that resets the CPU and other
peripherals. If any other reset function is active at the end of the ILADR
reset signal, the RST signal remains in the reset condition until the other
reset condition(s) end(s). The ILADR reset activates the internal
pulldown device connected to the RESET pin for one cycle of the
internal processor bus clock, PH2.
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Resets
Re se ts
Technical Data
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Resets
Te c hnic a l Da ta — MC68HC05K3
Se c tion 6. Op e ra tiona l Mod e s
6.1 Conte nts
6.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6.3
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . .57
6.3.1
6.3.2
6.3.3
6.3.4
6.4
PEEPROM Serial Programming Mode. . . . . . . . . . . . . . . . . . .57
6.2 Introd uc tion
The MC68HC05K3 is capable of running in one of several operational
modes. These modes include:
• Low-power operational modes
– Stop mode
– Wait mode
– Halt mode
• Serial program mode
6.3 Low-Powe r Mod e s
The WAIT and STOP/HALT instructions provide two low-power
operational modes that reduce the power required for the MCU by
stopping various internal clocks and/or the on-chip oscillator. The flow of
the stop, halt, and wait modes is shown in Figure 6-1.
MC68HC05K3 — Revision 4.0
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Technical Data
53
Operational Modes
Op e ra tiona l Mod e s
6.3.1 Stop Mod e
The STOP instruction can result in one of two modes of operation
depending on its mask option. The mask option can make the STOP
instruction operate the same as the STOP instruction in other M68HC05
Family members and place the device in stop mode. Or the mask option
can make the STOP instruction behave like a WAIT instruction (except
that the restart time involves a delay) and place the device in halt mode.
The mask option enabling the execution of the STOP instruction places
the MCU in its lowest power consumption mode. In stop mode, the
internal oscillator is turned off, halting all internal processing, including
the COP watchdog timer.
When the CPU enters stop mode, the interrupt flags (TOF and RTIF) and
the interrupt enable bits (TOFE and RTIE) in the TSCR are cleared by
internal hardware to remove any pending timer interrupt requests and to
disable any further timer interrupts. Execution of the STOP instruction
automatically clears the I bit in the condition code register and sets the
IRQE enable bit in the IRQ status/control register so that the IRQ
external interrupt is enabled. All other memory and registers, including
the other bits in the TSCR, remain unaltered.
The MCU can be brought out of stop mode only by an IRQ external
interrupt, an IRQ from port A (if mask option is enabled), or an externally
generated RESET. When exiting stop mode, the internal oscillator
resumes after an oscillator stabilization delay of either 16 or 4064 cycles
(depending on mask option state) of the internal processor clock.
NOTE: If enabled by a mask option, the STOP instruction causes the oscillator
to stop and, therefore, disable the COP watchdog timer. If the COP
watchdog timer is used and the part is never intended to enter stop
mode, the mask option that should be used is the one that disables the
STOP instruction and changes the stop mode to the halt mode. See
6.3.4 COP Watchdog Timer Considerations for more details.
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MOTOROLA
Operational Modes
Low-Power Modes
STOP
WAIT
MASK
OPTION TO
HALT?
Y
HALT
N
STOP EXTERNAL OSCILLATOR,
STOP INTERNAL TIMER CLOCK,
AND RESET STARTUP DELAY
EXTERNAL OSCILLATOR ACTIVE
AND INTERNAL TIMER CLOCK
ACTIVE
EXTERNAL OSCILLATOR ACTIVE
AND INTERNAL TIMER CLOCK
ACTIVE
STOP INTERNAL PROCESSOR
CLOCK, CLEAR I BIT IN CCR, AND
SET IRQE IN ISCR
STOP INTERNAL PROCESSOR
CLOCK, CLEAR I BIT IN CCR,
AND SET IRQE IN ISCR
STOP INTERNAL PROCESSOR
CLOCK, CLEAR I BIT IN CCR,
AND SET IRQE IN ISCR
Y
Y
Y
Y
Y
EXTERNAL
RESET?
EXTERNAL
RESET?
EXTERNAL
RESET?
N
N
N
IRQ
EXTERNAL
INTERRUPT?
IRQ
EXTERNAL
INTERRUPT?
IRQ
EXTERNAL
INTERRUPT?
Y
Y
Y
RESTART EXTERNAL OSCILLATOR
AND BEGIN STABILIZATION DELAY
N
N
N
TIMER
INTERNAL
INTERRUPT?
TIMER
INTERNAL
INTERRUPT?
END
OF STARTUP
N
N
Y
DELAY?
N
RESTART INTERNAL
PROCESSOR CLOCK
1. FETCH RESET VECTOR OR
2. SERVICE INTERRUPT
a. STACK CPU STATE
b. SET I BIT
C. VECTOR TO INTERRUPT ROUTINE
Figure 6-1. Stop/Halt/Wait Flowcharts
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Operational Modes
Op e ra tiona l Mod e s
6.3.2 Ha lt Mod e
Execution of the STOP instruction with a mask option to disable the stop
mode places the MCU in a low-power halt mode, which consumes more
power than stop mode. In halt mode, the internal processor clock is
halted, suspending all processor and internal bus activity. Internal timer
clocks remain active, permitting interrupts to be generated from the timer
or a reset to be generated from the COP watchdog timer. Execution of
the STOP instruction in the halt mode automatically clears the I bit in the
condition code register and sets the IRQE enable bit in the IRQ
status/control register so that the IRQ external interrupt is enabled. All
other registers, memory, and input/output lines remain in their previous
states.
If timer interrupts are enabled, a timer interrupt causes the processor to
exit halt mode and resume normal operation. Halt mode also can be
exited when an external IRQ or external RESET occurs. When exiting
halt mode, the internal processor clock resumes after a variable delay.
Depending on the mask option state, the maximum oscillator
stabilization delay is 16 or 4064 cycles of the internal processor clock.
Using the mask option to disable the STOP instruction prevents the
STOP instruction from halting the oscillator or affecting the COP
watchdog timer similar to wait mode. However, the recovery method
introduces some startup delay in the processor clock.
NOTE: Halt mode is not intended for normal use, but is provided to keep the
COP watchdog timer active if the STOP instruction opcode is executed
inadvertently.
6.3.3 Wa it Mod e
The WAIT instruction places the MCU in a low-power wait mode, which
consumes more power than stop mode. In wait mode, the internal
processor clock is halted, suspending all processor and internal bus
activity. Internal timer clocks remain active, permitting interrupts to be
generated from the timer or a reset to be generated from the COP
watchdog timer. Execution of the WAIT instruction automatically clears
the I bit in the condition code register and sets the IRQE enable bit in the
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Operational Modes
MOTOROLA
Operational Modes
PEEPROM Serial Programming Mode
IRQ status/control register so that the IRQ external interrupt is enabled.
All other registers, memory, and input/output lines remain in their
previous states.
If timer interrupts are enabled, a timer interrupt causes the processor to
exit wait mode and resume normal operation. Thus, the timer can be
used to generate a periodic exit from wait mode. Wait mode also is
exited when an external IRQ or RESET occurs.
6.3.4 COP Wa tc hd og Tim e r Consid e ra tions
If the COP watchdog timer is enabled by the mask option, any execution
of the STOP instruction (either intentional or inadvertent due to the CPU
being disturbed) causes the oscillator to halt and prevent the COP
watchdog timer from timing out unless the STOP instruction is disabled
by a mask option.
If the mask option is selected to enable the COP watchdog timer, the
COP resets the MCU when it times out. Therefore, it is recommended
that the mask option be selected to disable the COP watchdog for a
system that must have intentional uses of the wait mode for periods
longer than the COP timeout period.
6.4 PEEPROM Se ria l Prog ra m m ing Mod e
The internal personality EEPROM (PEEPROM) can be erased, read, or
programmed through the application of serial data patterns to the IRQ
and PB0 pins, if the PEEPROM serial programming mode is selected
following reset. Refer to 9.6 PEEPROM Serial Programming for details.
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Op e ra tiona l Mod e s
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Operational Modes
Te c hnic a l Da ta — MC68HC05K3
Se c tion 7. Pa ra lle l Inp ut/ Outp ut (I/ O)
7.1 Conte nts
7.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Port A Data Direction Register . . . . . . . . . . . . . . . . . . . . . . .61
Port A Pulldown Inhibit Register. . . . . . . . . . . . . . . . . . . . . .61
Port A Light-Emitting Diode (LED) Drive Capability . . . . . . .62
Port A I/O Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Port B Data Direction Register . . . . . . . . . . . . . . . . . . . . . . .65
Port B Pulldown Inhibit Register. . . . . . . . . . . . . . . . . . . . . .65
Port B with 3-Pin RC Oscillator . . . . . . . . . . . . . . . . . . . . . .66
7.4.1
7.4.2
7.4.3
7.4.4
7.5
I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Pin Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
I/O Pin Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
I/O Pin Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
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Parallel Input/Output (I/O)
59
Pa ra lle l Inp ut/ Outp ut (I/ O)
7.2 Introd uc tion
In single-chip mode, 10 bidirectional input/output (I/O) lines are arranged
as one 8-bit I/O port (port A) and one 2-bit I/O port (port B). The individual
bits in these ports are programmable as either inputs or outputs under
software control by the data direction registers (DDRs). All port A and
port B I/O pins have individual software programmable pulldown devices
which can be enabled by a mask option. Some port A pins also have the
additional properties of sinking higher current or acting as additional IRQ
interrupt input sources. One of the port B pins also may be used as an
output for a 3-pin resistor capacitor (RC) oscillator option.
7.3 Port A
Port A is an 8-bit bidirectional port that shares four of its pins with the IRQ
interrupt system, as shown in Figure 7-1. Each port A pin is controlled
by the corresponding bits in a data direction register, a data register, and
a pulldown register.
READ $0004
V
DD
WRITE $0004
DATA DIRECTION
REGISTER BIT
I/O
PIN
WRITE $0000
OUTPUT
DATA
REGISTER BIT
READ $0000
WRITE $0010
PULLDOWN
REGISTER BIT
INTERNAL HC05
DATA BUS
RESET
(RST)
MASK OPTION TO INHIBIT
SOFTWARE PULLDOWNS
TO IRQ INTERRUPT SYSTEM
(BITS 0-3 ONLY)
Figure 7-1. Port A I/O Circuitry
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MC68HC05K3 — Revision 4.0
MOTOROLA
Parallel Input/Output (I/O)
Parallel Input/Output (I/O)
Port A
The port A data register is located at address $0000. The port A data
direction register (DDRA) is located at address $0004. The port A
pulldown register (PDRA) is located at address $0010. Reset clears both
the DDRA and the PDRA. The port A data register is unaffected by reset.
7.3.1 Port A Da ta Re g iste r
Each port A I/O pin has a corresponding bit in the port A data register.
When a port A pin is programmed as an output, the state of the
corresponding data register bit determines the state of the output pin.
When a port A pin is programmed as an input, any read of the port A data
register returns the logic state of the corresponding I/O pin, and any write
to the port A data register is saved in the data register, but is not applied
to the corresponding I/O pin. The port A data register is unaffected by
reset. The port A data register is indeterminant after initial power-up.
7.3.2 Port A Da ta Dire c tion Re g iste r
Each port A I/O pin may be programmed as an input by clearing the
corresponding bit in the DDRA or programmed as an output by setting
the corresponding bit in the DDRA. When a DDRA bit is set, the
corresponding pulldown device is disabled. The DDRA can be accessed
at address $0004. The DDRA is cleared by reset.
7.3.3 Port A Pulld own Inhib it Re g iste r
All port A I/O pins have software programmable pulldown devices which
may be enabled by a mask option. If enabled by mask option, the
software programmable pulldowns are activated by clearing their
corresponding bit in the PDRA or disabled by setting the corresponding
bit in the PDRA. If disabled by a mask option, all pulldowns are disabled.
A pulldown on an I/O pin can be activated only if the I/O pin is
programmed as an input.
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Parallel Input/Output (I/O)
Pa ra lle l Inp ut/ Outp ut (I/ O)
The PDRA is a write-only register and any reads of location $0010 return
undefined results. Since reset clears both the DDRA and the PDRA, all
pins initialize as inputs with the pulldown devices active (if enabled by
mask option).
Address: $0010
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write: PDIA7
Reset:
PDIA6
0
PDIA5
0
PDIA4
0
PDIA3
0
PDIA2
0
PDIA1
0
PDIA0
0
0
= Unimplemented
Figure 7-2. Port A Pulldown Inhibit Register (PDRA)
7.3.4 Port A Lig ht-Em itting Diod e (LED) Drive Ca p a b ility
The outputs of port A pins 4–7 are capable of sinking high current for
light-emitting diode (LED) drive capability.
7.3.5 Port A I/ O Pin Inte rrup ts
The inputs for the lower four bits of port A can be connected through an
OR gate to the IRQ latched input to the CPU by a mask option. When
connected as an alternate source of an IRQ interrupt, the port A input
pins behave the same as the IRQ pin itself, except that their active state
is a logic 1 or a rising edge. The normal IRQ pin has an active state that
is a logic 0 or a falling edge depending on the mask option.
If the mask option for edge- and level-sensitive interrupts and the mask
option for port A interrupts are both used, the presence of a logic 1 on
any one of the lower four port A pins causes an IRQ interrupt request. If
the mask option for edge-sensitive-only interrupts and the mask option
for port A interrupts are both used, the occurrence of a rising edge on
any one of the PA0–PA3 pins causes an IRQ interrupt request, as long
as the other PA0–PA3 pins are at a low level. As long as any one of the
PA0–PA3 IRQ inputs remains at a logic 1 level, or the IRQ remains at a
logic 0 level, the other PA0–PA3 IRQ inputs are effectively ignored. Port
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Parallel Input/Output (I/O)
MOTOROLA
Parallel Input/Output (I/O)
Port B
interrupts will be generated with the above PA0–PA3 I/O state
regardless of whether the port is configured as an input or output.
NOTE: The BIH and BIL instructions apply only to the level on the IRQ pin itself
and not to the internal IRQ input to the CPU. Therefore, BIH and BIL
cannot be used to test the state of the lower four port A input pins as a
group. Each port A interrupt pin can be tested by reading the port A data
register at $0000.
7.4 Port B
Port B is a 2-bit bidirectional port that shares one of its pins with the RC
oscillator as shown in Figure 7-3. Each port B pin is controlled by the
corresponding bits in a data direction register, a data register, and a
pulldown register.
The port B data register is located at address $0001. The port B data
direction register (DDRB) is located at address $0005, and the port B
pulldown register (PDRB) is located at address $0011. Reset clears both
the DDRB and the PDRB. The port B data register is unaffected by reset.
The port B data register is indeterminant after initial powerup.
7.4.1 Port B Da ta Re g iste r
Each port B I/O pin has a corresponding bit in the port B data register.
When a port B pin is programmed as an output, the state of the
corresponding data register bit determines the state of the output pin.
When a port B pin is programmed as an input, any read of the port B data
register returns the logic state of the corresponding I/O pin, and any write
to the port B data register is saved in the data register, but is not applied
to the corresponding I/O pin. Unused bits 2–7 are always read as logic
0s, and any write to these bits is ignored. The port B data register is
unaffected by reset. The port B data register is indeterminant after initial
power-up.
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Parallel Input/Output (I/O)
Pa ra lle l Inp ut/ Outp ut (I/ O)
READ $0005
WRITE $0005
V
DD
DATA DIRECTION
REGISTER B
FROM 3-PIN
RC OSCILLATOR
PB1
OSC3
I/O PIN
WRITE $0001
OUTPUT
DATA
REGISTER BIT
READ $0001
WRITE $0011
PULLDOWN
REGISTER BIT
MASK OPTION
FOR RC OSCILLATOR
MASK OPTION FOR
3-PIN RC OSCILLATOR
READ $0005
WRITE $0005
DATA DIRECTION
REGISTER BIT
PB0
PIN
WRITE $0001
OUTPUT
DATA
REGISTER BIT
READ $0001
WRITE $0011
PULLDOWN
REGISTER BIT
INTERNAL
HC05 DATA BUS
RESET
(RST)
MASK OPTION TO
INHIBIT SOFTWARE PULLDOWNS
Figure 7-3. Port B I/O Circuitry
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Parallel Input/Output (I/O)
Parallel Input/Output (I/O)
Port B
7.4.2 Port B Da ta Dire c tion Re g iste r
Each port B I/O pin may be programmed as an input by clearing the
corresponding bit in the DDRB or programmed as an output by setting
the corresponding bit in the DDRB. When a DDRB bit is set, the
corresponding pulldown device is disabled. The DDRB can be accessed
at address $0005. Unused bits 2–7 are always read as logic 0s, and any
write to these bits is ignored. The DDRB is cleared by reset.
7.4.3 Port B Pulld own Inhib it Re g iste r
Each port B I/O pin has a software programmable pulldown device which
can be enabled by a mask option. If enabled by a mask option, the
software programmable pulldowns are activated by clearing the
corresponding bit in the PDRB or disabled by setting the corresponding
bit in the PDRB. If disabled by a mask option, all pulldowns are disabled.
A pulldown on an I/O pin can be activated only if the I/O pin is
programmed as an input.
The PDRB is a write-only register and any reads of location $0011 return
undefined results. Since reset clears both the DDRB and the PDRB, all
pins initialize as inputs with the pulldown devices active (if enabled by
mask option).
Address: $0011
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PDIB1
0
PDIB0
0
= Unimplemented
Figure 7-4. Port B Pulldown Inhibit Register (PDRB)
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Parallel Input/Output (I/O)
Pa ra lle l Inp ut/ Outp ut (I/ O)
7.4.4 Port B with 3-Pin RC Osc illa tor
The PB1/OSC3 pin may be used as an output from a 3-pin RC oscillator
when the mask option for a 3-pin RC oscillator is used. In this case, the
following conditions apply:
• The PB1 data register bit can be used as a read/write storage
location without affecting the oscillator. PB1 is unaffected by reset.
• The DDRB1 data direction bit can be used as a read/write storage
location without affecting the oscillator. DDRB1 is cleared by
reset.
• The software programmable pulldown on PB1/OSC3 is disabled,
regardless of the mask option selection for the software
programmable pulldowns or the state of PDRB1.
7.5 I/ O Port Prog ra m m ing
All I/O pins can be programmed as inputs or outputs, with or without
pulldown devices.
7.5.1 Pin Da ta Dire c tion
The direction of a pin is determined by the state of its corresponding bit
in the associated port data direction register (DDR). A pin is configured
as an output if its corresponding DDR bit is set to a logic 1. A pin is
configured as an input if its corresponding DDR bit is cleared to a logic 0.
The data direction bits DDRB0, DDRB1, and DDRA0–DDRA7 are
read/write bits that can be manipulated with read-modify-write
instructions. At power-on or reset, all DDRs are cleared, which
configures all port pins as inputs. If the mask option for software
programmable pulldowns is selected, all pins initially power-up with their
software programmable pulldowns enabled.
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Parallel Input/Output (I/O)
MOTOROLA
Parallel Input/Output (I/O)
I/O Port Programming
7.5.2 Outp ut Pin
When an I/O pin is programmed as an output pin, the state of the
corresponding data register bit determines the state of the pin. The state
of the data register bits can be altered by writing to address $0000 for
port A and address $0001 for port B. Reads of the corresponding data
register bit at address $0000 or $0001 return the state of the data
register bit, not the state of the I/O pin itself. Therefore, bit manipulation
is possible on all pins programmed as outputs.
All pins programmed as outputs have their pulldown devices disabled
regardless of the selected mask option for software programmable
pulldowns or the state of their PDR bits.
7.5.3 Inp ut Pin
When an I/O pin is programmed as an input pin, the state of the pin can
be determined by reading the corresponding data register bit. Any writes
to the corresponding data register bit for an input pin is saved by the
register bit, but not applied to the corresponding I/O pin until the pin is
later programmed to be an output.
If the corresponding bit in the pulldown register is clear (and the mask
option for software programmable pulldowns is selected), the input pin
also has an activated pulldown device.
Read-modify-write instructions, such as bit manipulation, should not be
used on the pulldown registers, since they are write-only.
7.5.4 I/ O Pin Tra nsitions
A “glitch” can be generated on an I/O pin when changing it from an input
to an output unless the data register is first pre-conditioned to the
desired state before changing the corresponding DDR bit from a 0 to a 1.
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Parallel Input/Output (I/O)
Pa ra lle l Inp ut/ Outp ut (I/ O)
If the mask option for software programmable pulldowns is selected, a
floating input can be avoided by first clearing the pulldown register bit
before changing the corresponding DDR from a 1 to a 0. This ensures
that the pulldown device is activated on the pin as the I/O pin changes
from a driven output to a pulled low input.
7.5.5 I/ O Pin Truth Ta b le s
Every pin on port A and PB0 on port B may be programmed as an input
or an output under software control, as shown in Table 7-1 and
Table 7-2. All port I/O pins also may have software programmable
pulldown devices selected by a mask option. The PB1/OSC3 pin on port
B also can be programmed as an input or an output under software
control, but it has special considerations when selected by a mask option
as an output for the 3-pin RC oscillator, as shown in Table 7-3.
Otherwise, PB1/OSC3 behaves the same as PB0.
Table 7-1. Port A Pin Functions
Software
Access to PDRA
at $0010
Access to DDRA
at $0004
Access to Data
Prog.
Register at $0000
I/O Pin
Mode
Pulldown PDIAx DDRAx
Mask
Option*
Read
Write
Read/Write
Read
Write
1
1
X
X
0
1
In, Hi-Z
OUT
U
U
PDIA0–PDIA7
PDIA0–PDIA7
DDRA0–DDRA7
I/O pin
X
DDRA0–DDRA7 PA0–PA7 PA0–PA7
DDRA0–DDRA7 I/O pin
In,
Pulldown
0
0
0
U
PDIA0–PDIA7
X
0
0
0
1
1
1
0
1
Out
In, Hi-Z
Out
U
U
U
PDIA0–PDIA7
PDIA0–PDIA7
PDIA0–PDIA7
DDRA0–DDRA7 PA0–PA7 PA0–PA7
DDRA0–DDRA7 I/O pin
X
0
DDRA0–DDRA7 PA0–PA7 PA0–PA7
Notes:
X is don’t care state
U is an undefined state
*1 = pulldowns disabled, 0 = pulldowns enabled
Technical Data
68
MC68HC05K3 — Revision 4.0
MOTOROLA
Parallel Input/Output (I/O)
Parallel Input/Output (I/O)
I/O Port Programming
Table 7-2. PB0 Pin Functions
Software
Prog.
Access to PDRB Access to DDRB
Access to Data
at $0011
at $0005
Register at $0001
I/O Pin
Mode
Pulldown
Mask
PDIB0 DDRB0
Read
Write
Read/Write
Read
Write
Option*
1
X
X
0
0
1
1
0
1
0
1
0
1
In, Hi-Z
Out
U
U
U
U
U
U
PDIB0
PDIB0
PDIB0
PDIB0
PDIB0
PDIB0
DDRB0
DDRB0
DDRB0
DDRB0
DDRB0
DDRB0
I/O pin
PB0
X
PB0
X
1
0
In, pulldown
Out
I/O pin
PB0
0
0
PB0
X
In, Hi-Z
Out
I/O pin
PB0
0
PB0
Notes:
X is don’t care state
U is an undefined state
*1 = pulldowns disabled, 0 = pulldowns enabled
Table 7-3. PB1/OSC3 Pin Functions
Software
Prog.
Access to
DDRB at
$0005
Access to
Access to
Mask
Option
(3-Pin)
Data Register
at $0001
I/O Pin
Mode
PDRB at $0011
Pulldown
Mask
PDIB1 DDRB1
Option*
Read
U
Write
PDIB1
PDIB1
Read/Write
DDRB1
Read
I/O pin
PB1
Write
X
0
0
0
0
1
1
0
1
In, Hi-Z
Out
U
DDRB1
PB1
In,
Pulldown
0
0
0
0
U
PDIB1
DDRB1
I/O pin
X
0
0
0
0
0
0
0
0
0
1
0
1
Out
In, Hi-Z
Out
U
U
U
PDIB1
PDIB1
PDIB1
DDRB1
DDRB1
DDRB1
PB1
I/O pin
PB1
PB1
X
PB1
RC
OSCOUT
1
X
X
X
U
PDIB1
DDRB1
PB1
PB1
Notes:
X is don’t care state
U is an undefined state
*1 = pulldowns disabled, 0 = pulldowns enabled
MC68HC05K3 — Revision 4.0
TechnicalData
69
MOTOROLA
Parallel Input/Output (I/O)
Pa ra lle l Inp ut/ Outp ut (I/ O)
Technical Data
70
MC68HC05K3 — Revision 4.0
MOTOROLA
Parallel Input/Output (I/O)
Te c hnic a l Da ta — MC68HC05K3
Se c tion 8. 8-Bit Tim e r
8.1 Conte nts
8.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
8.3
8.3.1
8.3.2
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Timer Status/Control Register . . . . . . . . . . . . . . . . . . . . . . .74
8.4
8.5
8.6
COP Watchdog Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Operating During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .77
Operating During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .77
8.2 Introd uc tion
The timer for this device is an 8-bit ripple counter. The features include
timer overflow (TOF), power-on reset (POR), real-time interrupt (RTI),
and computer operating properly (COP) watchdog timer. This timer is
powered down in the stop mode to reduce STOP I .
DD
As shown in Figure 8-1, the timer is driven by the timer clock, NTF1,
divided by four (4). NTF1 has the same phase and frequency as the
processor bus clock, PH2, but is not stopped by the wait or halt modes.
This signal drives an 8-bit ripple counter. The value of this 8-bit ripple
counter can be read by the CPU at any time by accessing the timer
counter register (TCNTR) at address $09. A timer overflow function is
implemented on the last stage of this counter, giving a possible interrupt
at the rate of f /1024. Two additional stages produce the POR function
OP
at f /4064 or f /16, followed by two more stages, with the resulting
OP
OP
clock (f /16,384) driving the real-time interrupt (RTI) circuit.
OP
The RTI circuit consists of three divider stages with a one-of-four
selector. The output of the RTI circuit is further divided by eight to drive
MC68HC05K3 — Revision 4.0
MOTOROLA
Technical Data
71
8-Bit Timer
8-Bit Tim e r
the optional COP watchdog timer circuit, which can be enabled by a
mask option. The RTI rate selector bits and the RTI and TOF enable bits
and flags are located in the timer control and status register at location
14
$08. The clock frequency that drives the RTI circuit is f /2 (or
OP
f /16,384) with three additional divider stages giving a maximum
OP
17
interrupt period of f /2 (or f /131,072).
OP
OP
The power-on cycle clears the entire counter chain and begins clocking
the counter. After 4064 or 16 cycles (depending on mask option), the
power-on reset circuit is released, which again clears the counter chain
and allows the device to come out of reset. At this point, if RESET is not
asserted, the timer starts counting up from 0 and normal device
operation begins. If RESET is asserted at any time during operation, the
counter chain is cleared.
MC68HC05 INTERNAL BUS
COPR
CLEAR
8
8
$09 TCNTR
TIMER COUNTER REGISTER (TCNTR)
2
NTF1 INTERNAL
TIMER CLOCK
f
/2
OP
÷4
TCNTR
(f
)
OP
10
f
/2
OP
7-BIT COUNTER
RESET
POR
MOR1,2
REFRESH
TCBP
OVERFLOW
DETECT
CIRCUIT
RTI SELECT CIRCUIT
÷8
$08 TSCR
TIMER STATUS/CONTROL REGISTER
TSCR
TOF
RTIF TOFE RTIE TOFR RTIFR RT1
RT0
COP WATCHDOG
TIMER
INTERRUPT CIRCUIT
TO INTERRUPT
LOGIC
TO RESET
LOGIC
Figure 8-1. Timer Block Diagram
Technical Data
72
MC68HC05K3 — Revision 4.0
MOTOROLA
8-Bit Timer
8-Bit Timer
Timer Registers
8.3 Tim e r Re g iste rs
The 8-bit timer contains two registers:
• Timer counter register
• Timer status/control register
8.3.1 Tim e r Counte r Re g iste r
The timer counter register is a read-only register that contains the
current value of the 8-bit ripple counter at the beginning of the timer
chain. This counter is clocked at f divided by 4 and can be used for
OP
various functions including a software input capture. Extended time
periods can be attained using the TOF function to increment a temporary
RAM storage location thereby simulating a 16-bit (or more) counter. The
value of each bit of the TCNTR is shown in Figure 8-2. This register is
cleared by reset.
Address: $0009
Bit 7
Read: TCR7
Write:
6
5
4
3
2
1
Bit 0
TCR6
TCR5
TCR4
TCR3
TCR2
TCR1
TCR0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-2. Timer Counter Register (TCNTR)
MC68HC05K3 — Revision 4.0
MOTOROLA
TechnicalData
73
8-Bit Timer
8-Bit Tim e r
8.3.2 Tim e r Sta tus/ Control Re g iste r
The TSCR contains the timer interrupt flag, the timer interrupt enable
bits, and the real-time interrupt rate select bits. Bit 2 and bit 3 are
write-only bits that read as logical 0s. Figure 8-3 shows the value of
each bit in the TSCR following reset.
Address: $0008
Bit 7
TOF
6
5
TOIE
0
4
RTIE
0
3
0
2
1
RT1
1
Bit 0
RT0
1
Read:
Write:
Reset:
RTIF
0
RTIFR
0
TOFR
0
0
0
= Unimplemented
Figure 8-3. Timer Status/Control Register (TSCR)
TOF — Timer Overflow Bit
The TOF is a read-only flag bit that is set when the 8-bit ripple counter
rolls over from $FF to $00. A timer interrupt request is generated if
TOF is set when TOIE is also set. The TOF flag bit is reset by writing
a logical 1 to the TOFR acknowledge bit. Writing to the TOF flag bit
has no effect on its value. This bit is cleared by reset.
RTIF — Real-Time Interrupt Flag Bit
The RTIF is a read-only flag bit that is set when the output of the
chosen (one-of-four selection) real-time interrupt stage goes active. A
timer interrupt request is generated if RTIF is set when RTIE is also
set. The RTIF flag bit is reset by writing a logical 1 to the RTIFR
acknowledge bit. Writing to the RTIF flag bit has no effect on its value.
This bit is cleared by reset.
TOIE — Timer Overflow Interrupt Enable Bit
The TOIE is an enable bit that allows generation of a timer interrupt.
When the TOIE enable bit is set, the TIMER Interrupt is generated
when the TOF flag bit is set. This bit is cleared by reset.
Technical Data
74
MC68HC05K3 — Revision 4.0
8-Bit Timer
MOTOROLA
8-Bit Timer
Timer Registers
RTIE — Real-Time Interrupt Enable Bit
The RTIE is an enable bit that allows the generation of a timer
interrupt. When the RTIE enable bit is set and the RTIF flag bit is set,
the timer interrupt is generated. The RTIE bit is cleared by reset.
TOFR — Timer Overflow Acknowledge Bit
The TOFR is an acknowledge bit that resets the TOF flag bit. Writing
a logical 1 to the TOFR clears the TOF flag bit. Reading the TOFR
always returns a logical 0. This bit is unaffected by reset.
RTIFR — Real-Time Interrupt Acknowledge Bit
The RTIFR is an acknowledge bit that resets the RTIF flag bit. Writing
a logical 1 to the RTIFR clears the RTIF flag bit. Reading the RTIFR
always returns a logical 0. This bit is unaffected by reset.
RT1:RT0 — Real-Time Interrupt Rate Select Bit
The RT0 and RT1 control bits select one-of-four taps for the real-time
interrupt circuit. Table 8-1 shows the available interrupt rates with
several f values. Both the RT0 and RT1 control bits are set by
OP
reset, selecting the lowest periodic rate and therefore the maximum
time in which to alter these bits if necessary. Care should be taken
when altering RT0 and RT1 if the time-out period is imminent or
uncertain. If the selected tap is modified during a cycle in which the
counter is switching, an RTIF can be missed or an additional RTIF can
be generated. To avoid problems, the COP should be cleared just
prior to changing RTI taps.
Table 8-1. RTI Rates and COP Reset Times
Minimum COP
Timeout Period
(fOP = 2 MHz)
COP Timeout
Period
(± 1 RTI Period)
RTI Period
(fOP = 2 MHz)
RT1
and RT0
RTI
Rate
14
0
0
1
1
0
1
0
1
8.2 ms
16.4 ms
32.8 ms
65.5 ms
8 x RTI period
8 x RTI period
8 x RTI period
8 x RTI period
57.3 ms
114.7 ms
229.4 ms
458.8 ms
f
f
f
f
OP ÷ 2
OP ÷ 2
OP ÷ 2
OP ÷ 2
15
16
17
MC68HC05K3 — Revision 4.0
MOTOROLA
TechnicalData
75
8-Bit Timer
8-Bit Tim e r
8.4 COP Wa tc hd og Tim e r
The computer operating properly (COP) watchdog timer function is
implemented on this device by using the output of the RTI circuit and
further dividing it by eight. The minimum COP reset times are listed in
Table 8-1.
If the COP circuit times out, an internal reset is generated and the reset
vector is fetched. Preventing a COP timeout is done by writing a logical 0
to the COPC bit at address $03F0 as shown in Figure 8-4. The COPR
register is shared with a user EEPROM byte. This address location is not
affected by any reset signals. Reading this location returns the user
EEPROM byte. When the COPC is cleared, only the final four bits used
to count eight RTI cycles are cleared. The COP watchdog timer can be
enabled/disabled by a mask option.
Address: $03F0
Bit 7
—
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Reading $03F0 returns the contents of user EEPROM
COPC
0
—
—
—
—
—
—
= Unimplemented
Figure 8-4. COPR Watchdog Timer Location
Technical Data
76
MC68HC05K3 — Revision 4.0
MOTOROLA
8-Bit Timer
8-Bit Timer
Operating During Stop Mode
8.5 Op e ra ting During Stop Mod e
The timer system is cleared when going into stop mode. When STOP is
exited by an external interrupt or an external RESET, the internal
oscillator resumes, followed by a 16- or 4064-cycle internal processor
oscillator stabilization delay. The timer system counter is then cleared
and operation resumes. If the STOP instruction is disabled by mask
option to create the halt mode, the effects on the timer are as described
in 8.6 Operating During Wait Mode.
8.6 Op e ra ting During Wa it Mod e
The CPU clock halts during wait mode, but the timer remains active. If
interrupts are enabled, a timer interrupt or custom periodic interrupt
causes the processor to exit wait mode.
MC68HC05K3 — Revision 4.0
MOTOROLA
TechnicalData
77
8-Bit Timer
8-Bit Tim e r
Technical Data
78
MC68HC05K3 — Revision 4.0
MOTOROLA
8-Bit Timer
Te c hnic a l Da ta — MC68HC05K3
Se c tion 9. Pe rsona lity EEPROM (PEEPROM)
9.1 Conte nts
9.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.3
9.3.1
9.3.2
PEEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
PEEPROM Bit Select Register. . . . . . . . . . . . . . . . . . . . . . .81
PEEPROM Status/Control Register . . . . . . . . . . . . . . . . . . .82
9.4
9.5
PEEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
PEEPROM Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
9.6
PEEPROM Serial Programming. . . . . . . . . . . . . . . . . . . . . . . .87
Serial Programming Connections. . . . . . . . . . . . . . . . . . . . .87
Multiple Devices in Serial Program Mode . . . . . . . . . . . . . .88
PEEPROM Serial Programming Mode Entry . . . . . . . . . . . .89
9.6.1
9.6.2
9.6.3
9.7
9.8
9.9
Serial Programming Sequence. . . . . . . . . . . . . . . . . . . . . . . . .91
Serial Data Readout Sequence . . . . . . . . . . . . . . . . . . . . . . . .95
Serial Bulk Erase Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . .96
9.2 Introd uc tion
The MC68HC05K3 contains a 128-bit personality EEPROM
(PEEPROM) for storage of variables or user data. These 128 bits are
provided as a simple EEPROM array and control logic that requires
serial reading of the data. The PEEPROM may be accessed via software
programmed into the user ROM through two registers that directly
interface with the PEEPROM array. The actual implementation of the
software varies depending on customer requirements. The PEEPROM
array is arranged as 16 bytes (rows) with a separate column select for
each bit (column) in a byte. The column select connects the bit to a
MC68HC05K3 — Revision 4.0
MOTOROLA
Technical Data
79
Personality EEPROM (PEEPROM)
Pe rsona lity EEPROM (PEEPROM)
single sense amplifier as shown in the block diagram of the PEEPROM
module in Figure 9-1.
An on-chip charge pump is provided to allow programming and erasure
of the personality EEPROM if the supply voltage to the V pin is at least
DD
2.7 Vdc.
NOTE: Programming and erasure of the personality EEPROM may only be
performed if V greater than or equal to 2.7 Vdc.
DD
HC05
V
DD
DATA BUS
BUS
CLOCK
(PH2)
CPCLK
CPEN
ON-CHIP
CHARGE
PUMP
MUX
INTERNAL
RING
OSCILLATOR
PEPCZF
PEDATA
8
SINGLE
SENSE
AMP
PEPGM/PEBYTE/PEBULK
V
SWITCH
V SWITCH
PP
PP
0-2
8-TO-1
DECODE & MUX
EACH ROW
IS A BYTE
8
3-6
16 x 8
EEPROM
ARRAY
Figure 9-1. Personality EEPROM Block Diagram
Technical Data
80
MC68HC05K3 — Revision 4.0
MOTOROLA
Personality EEPROM (PEEPROM)
Personality EEPROM (PEEPROM)
PEEPROM Registers
9.3 PEEPROM Re g iste rs
Two register locations are used to support the EEPROM array. These
are the bit select and status/control registers.
9.3.1 PEEPROM Bit Se le c t Re g iste r
The PEEPROM bit select register (PEBSR) is located at $000E and
contains the enable signals for the rows and columns to access the bits
in the EEPROM array. Figure 9-2 shows the placement of these bits.
The output of this register is connected to two decoders, one for the
array column and one for the array row.
A byte in the PEEPROM is defined by the upper four bits in the 7-bit
address in the PEBSR (PEB3–PEB6) and the bit within that byte is
defined by the lower three bits in the 7-bit address in the PEBSR
(PEB0–PEB2). The upper bit in the PEBSR (PEB7) may be used as a
storage location. All of the bits in the PEBSR register are cleared by
reset.
$000E
Address:
Bit (Column in Byte (Row)
of PEEPROM
Byte (Row) of PEEPROM
3
6
2
5
1
4
0
3
2
2
1
1
0
Bit 7
PEB7
0
Bit 0
Read:
Write:
Reset:
PEB6
PEB5
PEB4
PEB3
PEB2
PEB1
PEB0
0
0
0
0
0
0
0
Figure 9-2. PEEPROM Bit Select Register (PEBSR)
MC68HC05K3 — Revision 4.0
MOTOROLA
TechnicalData
81
Personality EEPROM (PEEPROM)
Pe rsona lity EEPROM (PEEPROM)
9.3.2 PEEPROM Sta tus/ Control Re g iste r
The PEEPROM status/control register (PESCR) is located at $000F and
contains five user bits, as shown in Figure 9-3. Bit 1 is unimplemented
and always reads as a logic 0. The states of all bits except PEPCZF and
PEDATA are cleared by reset. The PEPCZF is set by reset; and the state
of the PEDATA bit following reset is dependent on the stored data in
bit 0 of the PEEPROM array.
Address: $000F
Bit 7
Read: PEDATA
Write:
6
PEBULK
0
5
4
3
2
CPCLK
0
1
0
Bit 0
PEPCZF
PEPGM
(DATA IN)
PEBYTE CPEN
Reset:
1
0
0
0
0
1
= Unimplemented
Figure 9-3. PEEPROM Status/Control Register (PESCR)
PEPCZF — PEEPROM Column Zero Flag Bit
The PEPCZF is a flag bit that is set to a logical 1 when the first column
(COL0) of the EEPROM array is selected. If any other column is
selected, the PEPCZF flag bit is cleared. This flag bit can be used to
reduce the software code required to access one byte of the
PEEPROM. The PEPCZF is set following a reset, since the first
column is selected by the reset of the PEBSR. The software code
given in Table 9-1 is suggested for reading one byte from the
PEEPROM.
Technical Data
82
MC68HC05K3 — Revision 4.0
Personality EEPROM (PEEPROM)
MOTOROLA
Personality EEPROM (PEEPROM)
PEEPROM Registers
Table 9-1. Software to Read PEEPROM
pebsr
pescr
ram
equ
equ
equ
$000e
$000f
$000c
lda
sta
clr
#$xy
pebsr
ram
; xy is base addresses and should start on
; a first column (i.e., $00, $08, $10, $18, etc).
; clear ram location used for final result
peep_rd rol
pescr
ram
pebsr
; c = pedata (c = carry bit)
; ram = c
; go to next bit in array.
ror
inc
brclr 0,pescr,peep_rd
; care data here, loop until all bytes read
; peep_rd loop ends when PEPCZF = 1.
; At end of loop, ram contains one row of PEEP data.
CPCLK — Charge Pump Clock Source Bit
The CPCLK bit is a read/write bit that controls the source of the clock
for the charge pump. When the CPCLK bit is set, the charge pump is
driven by the PH2 bus clock. When the CPCLK bit is cleared, the
charge pump is driven from an internal ring oscillator. The CPCLK bit
is cleared when the device is in reset.
In systems where the desired PH2 clock rate is below 1 MHz, the
CPCLK bit should be cleared to enable the internal ring oscillator.
Otherwise, the charge pump does not attain sufficient program/erase
voltage because the clock source is too slow.
CPEN — Charge Pump Enable Bit
The CPEN bit is a read/write bit to control the on-chip charge pump
for programming and erasure of the personality EEPROM. This
charge pump is only intended for use at V supply voltages
DD
greater than or equal to 2.7 Vdc. The charge pump is activated
when both the CPEN bit is set and one of the program or erase bits is
also set (PEPGM, PEBYTE, or PBULK). The charge pump supplies
the required programming voltage to the personality EEPROM array.
Once activated, and after startup time t , the charge pump continues
CP
to operate until all the program and erase bits are cleared.
NOTE: If the personality EEPROM is read while the CPEN bit is set, the data is
unknown.
MC68HC05K3 — Revision 4.0
MOTOROLA
TechnicalData
83
Personality EEPROM (PEEPROM)
Pe rsona lity EEPROM (PEEPROM)
The charge pump must always be used to program or erase bits in the
personality EEPROM. The CPEN bit is cleared when the device is in
reset.
NOTE: Setting the CPEN bit can activate the charge pump. However, all the
PEPGM, PEBYTE, PEBULK, and CPEN bits must be cleared to
de-activate the charge pump. If the charge pump is left running, the
overall device I current increases.
DD
PEBYTE — PEEPROM Byte Erase Bit
The PEBYTE bit is a read/write bit to control the switches that apply
the internally provided charge pump programming voltage to a row in
the PEEPROM array that is to be erased. When the PEBYTE bit is set
to a logical 1, a logical 0 is stored to all bits in the same row of the
PEEPROM array, as specified by the upper four bits of the 7-bit
address in the PEBSR.
The PEBYTE bit should only be set if the PEPGM and PEBULK bits
are cleared. If both the PEBYTE and PEBULK bits are set, the
PEEPROM is bulk erased. The PEBYTE bit is cleared when the
device is reset.
PEPGM — PEEPROM Program Control Bit
The PEPGM bit is a read/write bit to control the switches that apply
the internally provided charge pump programming voltage to the
device in the PEEPROM array that is to be programmed. When the
PEPGM bit is set to a logical 1, a logical 1 is stored to the PEEPROM
array element specified by the address in the PEBSR. Since the state
of the PEPGM bit determines the state of the programmed bit in the
PEEPROM array, the PEPGM bit is similar to a DATA IN bit.
The PEPGM bit should be set only if the PEBYTE and PEBULK bits
are cleared. The PEPGM bit is cleared when the device is reset.
NOTE: Only one of the PEPGM, PEBYTE, or PEBULK bits should be set at any
one time.
Always clear the PEPGM bit before altering the addressing bits in the
PEBSR. Otherwise, intermediate locations may be affected if the
programming voltage is present.
Technical Data
84
MC68HC05K3 — Revision 4.0
Personality EEPROM (PEEPROM)
MOTOROLA
Personality EEPROM (PEEPROM)
PEEPROM Programming
PEBULK — PEEPROM Bulk Erase Bit
The PEBULK bit is a read/write bit to control the switches that apply
an internally provided programming voltage to all the bits in the
PEEPROM array that are to be erased. When the PEBULK bit is set
to a logical 1, a logical 0 is stored to all bits of the PEEPROM array
regardless of the bit address specified in the PEBSR.
The PEBULK bit should only be set if the PEBYTE and PEPGM bits
are cleared. If both the PEBYTE and PEBULK bits are set, the
personality EEPROM is bulk erased. The PEBULK bit is cleared when
the device is reset.
PEDATA — PEEPROM Data Bit
The PEDATA bit is a read-only bit that reflects the state of the
PEEPROM sense amplifier. The state of the PEDATA bit is only
meaningful when the PEBYTE, PEPGM, PEBULK, and CPEN control
bits are all 0. The state of the PEDATA bit following a reset is
dependent on the stored data in bit 0 of the PEEPROM array.
9.4 PEEPROM Prog ra m m ing
The PEEPROM can be programmed using a Motorola programmer or in
the user application if the V supply source is at least 2.7 Vdc. In the
DD
latter case, the programming software must be provided in the user
ROM and use some external pins in either a serial or parallel method for
data transfer and/or access. Each bit of the PEEPROM can be
programmed using this step-by-step procedure:
1. Write the desired bit location to be programmed into the PEBSR
located at $000E.
2. Set the PEPGM and CPEN bits in the PESCR located at $000F.
3. Wait for a t
time delay.
EPGM
4. Clear the PEPGM and CPEN bits.
The PEEPROM is then ready to be set up for another bit of data for
programming.
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Personality EEPROM (PEEPROM)
Pe rsona lity EEPROM (PEEPROM)
The programming of a PEEPROM bit only requires access of that bit
through the PEBSR followed by setting the PEPGM and CPEN bits in
the PESCR. Do not access any bits that are to be left unprogrammed
(erased) until all the PEPGM, PEBYTE, PEBULK, and CPEN bits in the
PESCR are cleared. Always clear the PEPGM, PEBYTE, PEBULK, and
CPEN bits before altering the PEBSR.
9.5 PEEPROM Re a d Ac c e ss
The contents of the PEEPROM are read in this sequence:
1. Write the desired bit location to be read into the PEBSR located at
$000E.
2. Read the state of the PEDATA bit in the PESCR located at $000F.
3. Store the state of the PEDATA bit into RAM or a register.
4. Select another bit by changing the PEBSR.
5. Continue reading and storing the PEDATA bit states until all the
required PEEPROM data has been accessed.
Reading the PEEPROM is easiest when each row in the PEEPROM
array is mapped to contain one byte of data. Selecting a column zero bit
selects the first bit in the row; and incrementing the PEEPROM bit select
register (PEBSR) selects the next (column 1) bit from the same row.
Incrementing the PEBSR seven more times selects the remaining bits of
the row and carries over to select column zero of the next row, thereby
setting the column zero flag, PEPCZF in the PESCR. The number of
increments per row can be controlled by looping on a test of the PEPCZF
flag bit.
The complete array can be easily accessed by starting with $007F for
the PEBSR and decrementing the PEBSR after each access of the
PEDATA bit. The decrement sequence can end when the contents of the
PEBSR are 0.
NOTE: One byte of data from the PEEPROM can be re-created in the PEBSR
itself. This can be done if the read routine builds the 8-bit data byte in the
index register or the accumulator and then transfers that result to the
PEBSR when completed. Subsequent reads of the PEBSR quickly yield
that retrieved data byte.
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Personality EEPROM (PEEPROM)
MOTOROLA
Personality EEPROM (PEEPROM)
PEEPROM Serial Programming
9.6 PEEPROM Se ria l Prog ra m m ing
The MC68HC05K3 can be programmed, read, or bulk erased in a serial
fashion using the RESET, PB0 and IRQ pins in PEEPROM serial
programming mode.
• The RESET pin is used to begin and end sequences and must be
able to toggle from 0 Vdc to V .
DD
• PB0 serves as the data pin and must be able to toggle from 0 Vdc
to V .
DD
• IRQ is used as the clock/select line and must be able to toggle
from 0 Vdc to 2 x V .
DD
NOTE: When not in serial programming mode, do not operate the device with
more than V on the IRQ pin.
DD
9.6.1 Se ria l Prog ra m m ing Conne c tions
The required schematic considerations are shown in Figure 9-4. The
serial programming connections can be shared with the application if
certain considerations are met.
1. The application circuitry connected to the PB0 pin must allow this
pin to be used as an input and not driven from some active source
within the application other than the MC68HC05K3. This pin is
driven to a logic high or low level by either an external source or
by the MC68HC05K3 itself.
2. The application circuitry connected to the IRQ pin must be capable
of being driven from an external source to a voltage, V
.
SELCKH
3. The application circuitry connected to the RESET pin must allow
this pin to be used as an input and not driven from some active
source within the application other than the MC68HC05K3.
4. To use the on-chip charge pump for programming/erasure, the
application circuitry must be capable of being supplied with a V
source of at least 2.7 Vdc.
DD
5. The diagram in Figure 9-4 shows the 3-pin RC oscillator
connections. This circuit also works with the 2-pin crystal and RC
oscillators and the PB1/OSC3 pin can be left unconnected in
those cases.
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87
Pe rsona lity EEPROM (PEEPROM)
V
DD
V
SS
C
RESET
PB1/OSC3
PB0
OSC1
OSC2
VSS
VDD
PA7
RESET
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R
DATA
IRQ
SEL/CLK
PA0
PA1
PA6
INPUT SOURCES
USED IN
USED IN
USED IN
APPLICATION
AS REQUIRED
APPLICATION
AS REQUIRED
PA2
PA5
APPLICATION
PA3
PA4
Figure 9-4. Serial Programming Connections
9.6.2 Multip le De vic e s in Se ria l Prog ra m Mod e
If the preceding rules in 9.6.1 Serial Programming Connections are
met, multiple MC68HC05K3 devices can be connected in parallel during
serial programming. All the parallel devices can share the same power
supplies for the V and V ; and they may all share the same DATA
DD
SS
and RESET signals. The only signal that must be routed individually to
each device is the SEL/CLK signal. Programming time can be reduced
by setting the data for each unit and then clocking its SEL/CLK low and
remaining low until the data has been received by all other devices. Then
raise the SEL/CLK line high for all units after the required programming
time.
NOTE: Direct connection of the RESET pin to the V supply should be avoided
DD
because as an internal reset source, such as a COP watchdog reset or
an illegal address, reset turns on an internal pulldown device connected
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Personality EEPROM (PEEPROM)
MOTOROLA
Personality EEPROM (PEEPROM)
PEEPROM Serial Programming
to the RESET pin. This device may be capable of heavily loading the
V
supply source.
DD
9.6.3 PEEPROM Se ria l Prog ra m m ing Mod e Entry
The sequence for entry into the personality EEPROM serial
programming mode to program, erase, or read data is:
1. Connect all parallel device modules.
2. Apply 0 Vdc to the DATA, RESET, and SEL/CLK signal lines.
3. Apply a voltage V
to the VDD suppy line.
DDS
4. Apply V
to the SEL/CLK signal line.
SELCKH
5. Wait for the initial startup delay (16 or 4064 internal PH2 processor
clock cycles, depending on mask option). Then raise the RESET
signal line to V
.
DDS
6. Do not raise the DATA signal line to V
until after a time, t
.
RDH
DDS
7. During the select sequence, the SEL/CLK signal is toggled
between 0 Vdc and V . The duration between transitions is
SELCKH
specified by t
and t
.
CLKLO
CLKHI
The device is now monitoring the IRQ and PB0 pins to determine the
type of procedure to execute. The state of the PB0 pin is examined
following each high-to-low transition of the IRQ pin, as shown in
Figure 9-5.
The state of the PB0 pin during the second and third falling edges of
SEL/CLK determines the type of operation. If the operation is to program
or verify the contents of the personality EEPROM, an additional 128
falling edges are required to store or retrieve data. The type of internal
operation to be executed is defined in Table 9-2. The state of PB0 on the
first falling edge of SEL/CLK is of no consequence; however, PB0 must
remain low for a minimum of 10 internal clock cycles, t
negation of RESET.
, following
RDH
The time delays required for various PEEPROM serial program mode
operations are given in Table 9-3.
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Personality EEPROM (PEEPROM)
Pe rsona lity EEPROM (PEEPROM)
V
DD
RESET DELAYED 16 OR 4064 PH2 CLOCKS
FROM POWER UP OF DEVICE
RESET
2 x V APPLIED
(RESET PIN)
DD
FALLING EDGE OF IRQ
IS BOTH SELECT AND CLOCK
SEL/CLK
(IRQ PIN)
DELAY AT LEAST t
BEFORE DATA PIN IS DRIVEN HIGH
RDH
DATA
(PB0 PIN)
TEST SELECT
(3 BITS)
PEEPROM DATA
(128 BITS)
Figure 9-5. PEEPROM Serial Programming Mode Data Format
Table 9-2. PEEPROM Serial Programming Mode Operations
First Bit Second Bit Third Bit
Internal Test Operation
Serial program personality EEPROM contents
Serial retrieval of personality EEPROM contents
Unassigned
X
X
X
X
0
0
1
1
0
1
0
1
Bulk erasure of EEPROM contents
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Personality EEPROM (PEEPROM)
Personality EEPROM (PEEPROM)
Serial Programming Sequence
9.7 Se ria l Prog ra m m ing Se q ue nc e
The programming of the internal personality EEPROM always begins at
bit address 00 of the 128-bit array. The signal timing on the IRQ and PB0
pins is shown in Figure 9-6, Figure 9-7, and Figure 9-8. The personality
EEPROM is serially programmed by using this sequence:
1. Follow the serial programming mode entry routine as specified in
9.6.3 PEEPROM Serial Programming Mode Entry.
2. Keep the DATA signal at 0 Vdc throughout the select sequence.
3. Clock the SEL/CLK signal line to 0 Vdc and back to V
select bit).
(first
SELCKH
4. Clock the SEL/CLK signal line to 0 Vdc and back to V
(second select bit).
SELCKH
5. Clock the SEL/CLK signal line to 0 Vdc and back to V
select bit).
(third
SELCKH
6. The device is now ready to receive the data to be programmed into
the 128 bits of the personality EEPROM. During the next 128
clocks of the SEL/CLK signal line, the data to be stored into each
bit (starting with location $00) must be present on the DATA signal
line prior to the falling edge of the SEL/CLK signal line to 0 Vdc.
The time that the SEL/CLK signal line stays at 0 Vdc is determined
by the EEPROM programming time (t
).
EPGM
7. On the 128th data bit, rather than drive the SEL/CLK signal high
to complete the programming sequence, drive the RESET pin to
0 V after a time, t
. This must be done to prevent the part from
EPGM
entering an unknown state. If all 128 bits do not need to be
programmed, the RESET pin may be driven to 0 V after the last bit
has been programmed. This will complete the programming
sequence.
8. While RESET is held low, the pins can be conditioned for the next
sequence.
This completes the serial programming sequence. The device can now
be verified by going to the serial data readout sequence or bulk erased
by going to the bulk erase sequence.
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Personality EEPROM (PEEPROM)
Pe rsona lity EEPROM (PEEPROM)
t
CLKHI
SEL/CLK
(IRQ)
t
RSU
t
t
EPGM
RHD
DATA
(PB0)
VALID
DATA IN
VALID
DATA IN
SERIAL PROGRAMMING DATA IN TIMING
t t
128th BIT
EPGM
SEL/CLK
(IRQ)
DATA
(PB0)
VALID
DATA IN
RESET
END OF PROGRAMMING SEQUENCE
Figure 9-6. PEEPROM Serial Programming Data In Timing
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Personality EEPROM (PEEPROM)
Personality EEPROM (PEEPROM)
Serial Programming Sequence
t
t
CLKHI
CLKLO
SEL/CLK
(IRQ)
t
t
DRV
HIZ
DATA
VALID
VALID
(PB0)
DATA IN
DATA OUT
t
PBZ
SERIAL READ DATA OUT TIMING
128th BIT
SEL/CLK
(IRQ)
DATA
(PB0)
VALID
DATA OUT
RESET
END OF READ SEQUENCE
Figure 9-7. PEEPROM Serial Read Data Out Timing
t t
ERBK
SEL/CLK
(IRQ)
DATA
(PB0)
RESET
Figure 9-8. Bulk Erase Sequence
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Personality EEPROM (PEEPROM)
Pe rsona lity EEPROM (PEEPROM)
Table 9-3. Internal Test Time Delays
Symbol
Description
Min
2.7
Max
5.5
Time
V
V
Serial mode V voltage
DD
DDS
V
1.5 x V
2.0 x V
DD
SEL/CLK high voltage
V
SELCKH
DD
t
f
f
f
f
f
cycles
RESET rising edge to 1st rising edge of data
SEL/CLK active high time
10
32
32
0
—
—
RDH
OP
OP
OP
OP
OP
t
cycles
cycles
cycles
cycles
CLKHI
t
SEL/CLK active low time (non-programming/erasing)
Read data in setup before falling edge of SEL/CLK
Read data in hold after falling edge of SEL/CLK
Programming time for EEPROM cell
See Note
CLKLO
t
—
—
15
—
8
RSU
t
16
10
5
RHD
t
ms
EPGM
t
f
f
f
cycles
cycles
cycles
cycles
RESET rising edge to falling edge of SEL/CLK
Data output drive after rising edge of SEL/CLK
Data output hi-Z after rising edge of SEL/CLK
Data hi-Z before rising edge of SEL/CLK
Bulk erase time for EEPROM array
RCLK
OP
OP
OP
t
4
DRV
t
—
0
8
HIZ
t
f
OP
—
30
PBZ
t
30
ms
ERBK
Note:
If computer operating properly (COP) watchdog timer is enabled through mask option, the maximum allowable
interval between any two successive high-to-low transitions of SEL/CLK is 7 x 217 fOP cycles.
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Personality EEPROM (PEEPROM)
Personality EEPROM (PEEPROM)
Serial Data Readout Sequence
9.8 Se ria l Da ta Re a d out Se q ue nc e
The read sequence of the internal personality EEPROM always begins
at bit address 00 of the 128-bit array. The signal timing on the IRQ and
PB0 pins is shown in Figure 9-7. The personality EEPROM can be
serially read out by using this sequence:
1. Follow the serial programming mode entry routine as specified in
9.6.3 PEEPROM Serial Programming Mode Entry.
2. Keep the DATA signal at 0 Vdc.
3. Clock the SEL/CLK signal line to 0 Vdc and back to V
select bit).
(first
SELCKH
4. Clock the SEL/CLK signal line to 0 Vdc and back to V
(second select bit).
SELCKH
5. Raise the DATA signal line to V
.
DDS
6. Clock the SEL/CLK signal line to 0 Vdc and back to V
select bit).
(third
SELCKH
7. The device is now ready to transmit the data that has been
programmed or erased into the 128 bits of the personality
EEPROM. During the next 128 clocks of the SEL/CLK signal line,
the stored data for each bit (starting with location $00) is
presented on the DATA signal line prior to the falling edge of the
SEL/CLK signal line to 0 Vdc. The data is valid within t
internal
DRV
cycles after the rising edge of SEL/CLK and is valid when the
SEL/CLK signal line falls for a time, t
.
HIZ
8. On the 128th data bit, rather than drive the SEL/CLK signal low to
complete the read sequence, drive the RESET pin to 0 V. This
must be done to prevent the part from entering an unknown state.
If all 128 bits do not need to be verified, the RESET pin may be
driven to 0 V after the last bit has been verified.
9. While RESET is held low, the pins can be conditioned for the next
sequence.
This completes the serial data readout sequence, and the device can
now be completely erased by going to the bulk erase sequence if the
verification sequence fails to read the desired data.
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Personality EEPROM (PEEPROM)
Pe rsona lity EEPROM (PEEPROM)
9.9 Se ria l Bulk Era se Se q ue nc e
The signal timing on the IRQ and PB0 pins is shown in Figure 9-8. The
personality EEPROM can be bulk erased by using this sequence:
1. Follow the serial programming mode entry routine as specified in
9.6.3 PEEPROM Serial Programming Mode Entry.
2. Keep the DATA signal at 0 Vdc.
3. Clock the SEL/CLK signal line to 0 Vdc and back to V
select bit).
(first
SELCKH
4. Raise the DATA signal to V
.
DDS
5. Clock the SEL/CLK signal line to 0 Vdc and back to V
(second select bit).
SELCKH
6. Clock the SEl/CLK signal line to 0 Vdc. Do not bring the SEL/CLK
signal line back to V as in other select sequences (third
SELCKH
select bit). This starts the bulk erase sequence.
7. After a time, t , drive the RESET pin to 0 V to complete the
ERBK
bulk erase sequence. This must be done to prevent the part from
entering an unkown state.
8. While RESET is held low, the pins can be conditioned for the next
sequence.
This completes the bulk erase sequence. The device can now be
programmed by going to the serial programming sequence or verified by
going to the serial verification sequence.
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MOTOROLA
Te c hnic a l Da ta — MC68HC05K3
Se c tion 10. Instruc tion Se t
10.1 Conte nts
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
10.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
10.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
10.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
10.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
10.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
10.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
10.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
10.3.7 Indexed,16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
10.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
10.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
10.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .102
10.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .103
10.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .104
10.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .106
10.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
10.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
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Technical Data
97
Instruction Set
Instruc tion Se t
10.2 Introd uc tion
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
10.3 Ad d re ssing Mod e s
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative
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Instruction Set
MOTOROLA
Instruction Set
Addressing Modes
10.3.1 Inhe re nt
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
10.3.2 Im m e d ia te
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
10.3.3 Dire c t
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
10.3.4 Exte nd e d
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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Instruction Set
Instruc tion Se t
10.3.5 Ind e xe d , No Offse t
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
10.3.6 Ind e xe d , 8-Bit Offse t
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
10.3.7 Ind e xe d ,16-Bit Offse t
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
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Instruction Set
MOTOROLA
Instruction Set
Instruction Types
10.3.8 Re la tive
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
10.4 Instruc tion Typ e s
The MCU instructions fall into the following five categories:
• Register/memory instructions
• Read-modify-write instructions
• Jump/branch instructions
• Bit manipulation instructions
• Control instructions
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Instruction Set
Instruc tion Se t
10.4.1 Re g iste r/ Me m ory Instruc tions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 10-1. Register/Memory Instructions
Instruction
Add Memory Byte and Carry Bit to Accumulator
Add Memory Byte to Accumulator
AND Memory Byte with Accumulator
Bit Test Accumulator
Mnemonic
ADC
ADD
AND
BIT
Compare Accumulator
CMP
CPX
EOR
LDA
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory Byte
Load Accumulator with Memory Byte
Load Index Register with Memory Byte
Multiply
LDX
MUL
ORA
SBC
STA
OR Accumulator with Memory Byte
Subtract Memory Byte and Carry Bit from Accumulator
Store Accumulator in Memory
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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Instruction Set
Instruction Set
Instruction Types
10.4.2 Re a d -Mod ify-Write Instruc tions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE: Do not use read-modify-write operations on write-only registers.
Table 10-2. Read-Modify-Write Instructions
Instruction
Arithmetic Shift Left (Same as LSL)
Arithmetic Shift Right
Bit Clear
Mnemonic
ASL
ASR
(1)
BCLR
(1)
Bit Set
BSET
Clear Register
CLR
COM
DEC
INC
Complement (One’s Complement)
Decrement
Increment
Logical Shift Left (Same as ASL)
Logical Shift Right
LSL
LSR
NEG
ROL
ROR
Negate (Two’s Complement)
Rotate Left through Carry Bit
Rotate Right through Carry Bit
Test for Negative or Zero
Notes:
(2)
TST
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence
because it does not write a replacement value.
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Instruction Set
Instruc tion Se t
10.4.3 Jum p / Bra nc h Instruc tions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
Technical Data
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Instruction Set
MOTOROLA
Instruction Set
Instruction Types
Table 10-3. Jump and Branch Instructions
Instruction
Branch if Carry Bit Clear
Branch if Carry Bit Set
Branch if Equal
Mnemonic
BCC
BCS
BEQ
BHCC
BHCS
BHI
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
Branch if Higher or Same
Branch if IRQ Pin High
Branch if IRQ Pin Low
Branch if Lower
BHS
BIH
BIL
BLO
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
BLS
BMC
BMI
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
BMS
BNE
BPL
Branch Always
BRA
Branch if Bit Clear
BRCLR
BRN
BRSET
BSR
Branch Never
Branch if Bit Set
Branch to Subroutine
Unconditional Jump
Jump to Subroutine
JMP
JSR
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Instruction Set
Instruc tion Se t
10.4.4 Bit Ma nip ula tion Instruc tions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 10-4. Bit Manipulation Instructions
Instruction
Mnemonic
BCLR
Bit Clear
Branch if Bit Clear
Branch if Bit Set
Bit Set
BRCLR
BRSET
BSET
Technical Data
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MOTOROLA
Instruction Set
Instruction Set
Instruction Types
10.4.5 Control Instruc tions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 10-5. Control Instructions
Instruction
Clear Carry Bit
Mnemonic
CLC
CLI
Clear Interrupt Mask
No Operation
NOP
RSP
RTI
Reset Stack Pointer
Return from Interrupt
Return from Subroutine
Set Carry Bit
RTS
SEC
SEI
Set Interrupt Mask
Stop Oscillator and Enable IRQ Pin
Software Interrupt
STOP
SWI
Transfer Accumulator to Index Register
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
TAX
TXA
WAIT
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Instruction Set
Instruc tion Se t
10.5 Instruc tion Se t Sum m a ry
Table 10-6. Instruction Set Summary (Sheet 1 of 6)
Effect on
CCR
Source
Form
Operation
Description
H I N Z C
ii
dd
hh ll
ee ff
ff
ADC #opr
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
2
3
4
5
4
3
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Carry
A ← (A) + (M) + (C)
↕ — ↕ ↕ ↕
ii
dd
hh ll
ee ff
ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
2
3
4
5
4
3
Add without Carry
A ← (A) + (M)
↕ — ↕ ↕ ↕
ii
dd
hh ll
ee ff
ff
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
2
3
4
5
4
3
Logical AND
A ← (A) (M)
— — ↕ ↕ —
dd
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
DIR
INH
INH
IX1
IX
38
48
58
68
78
5
3
3
6
5
Arithmetic Shift Left (Same as LSL)
C
0
— — ↕ ↕ ↕
b7
b7
b0
b0
ff
dd
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
DIR
INH
INH
IX1
IX
37
47
57
67
77
5
3
3
6
5
C
Arithmetic Shift Right
— — ↕ ↕ ↕
ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? C = 0
— — — — — REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
5
5
5
5
5
5
5
5
BCLR n opr
Clear Bit n
Mn ← 0
— — — — —
BCS rel
BEQ rel
BHCC rel
BHCS rel
BHI rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Z = 1
PC ← (PC) + 2 + rel ? H = 0
PC ← (PC) + 2 + rel ? H = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
25 rr
27 rr
28 rr
29 rr
22 rr
24 rr
3
3
3
3
3
3
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? C Z = 0 — — — — — REL
PC ← (PC) + 2 + rel ? C = 0 — — — — — REL
BHS rel
Branch if Higher or Same
Technical Data
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Instruction Set
Instruction Set
Instruction Set Summary
Table 10-6. Instruction Set Summary (Sheet 2 of 6)
Effect on
CCR
Source
Form
Operation
Description
H I N Z C
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1 — — — — — REL
PC ← (PC) + 2 + rel ? IRQ = 0 — — — — — REL
2F rr
2E rr
3
3
BIL rel
Branch if IRQ Pin Low
ii
dd
hh ll
ee ff
ff
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
IMM
DIR
EXT
IX2
IX1
IX
A5
B5
C5
D5
E5
F5
2
3
4
5
4
3
Bit Test Accumulator with Memory Byte
(A) (M)
— — ↕ ↕ —
BLO rel
BLS rel
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
PC ← (PC) + 2 + rel ? C = 1
— — — — — REL
25 rr
23 rr
2C rr
2B rr
2D rr
26 rr
2A rr
20 rr
3
3
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? C Z = 1 — — — — — REL
PC ← (PC) + 2 + rel ? I = 0
PC ← (PC) + 2 + rel ? N = 1
PC ← (PC) + 2 + rel ? I = 1
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
PC ← (PC) + 2 + rel ? 1 = 1
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
— — — — — REL
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if Bit n Clear
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
PC ← (PC) + 2 + rel ? Mn = 1
— — — — ↕
BRN rel
Branch Never
— — — — — REL
21 rr
3
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n opr rel Branch if Bit n Set
— — — — ↕
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
5
5
5
5
5
5
5
5
BSET n opr
Set Bit n
Mn ← 1
— — — — —
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
BSR rel
Branch to Subroutine
— — — — — REL
AD rr
6
PC ← (PC) + rel
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
— — — — 0
— 0 — — —
INH
INH
98
9A
2
2
Clear Interrupt Mask
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Instruction Set
Instruc tion Se t
Table 10-6. Instruction Set Summary (Sheet 3 of 6)
Effect on
Source
Form
CCR
Operation
Description
H I N Z C
dd
ff
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
5
3
3
6
5
Clear Byte
— — 0 1 —
ii
dd
hh ll
ee ff
ff
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
2
3
4
5
4
3
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
(A) – (M)
— — ↕ ↕ ↕
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
dd
ff
COM opr
COMA
COMX
COM opr,X
COM ,X
DIR
INH
INH
IX1
IX
33
43
53
63
73
5
3
3
6
5
— — ↕ ↕
1
ii
dd
hh ll
ee ff
ff
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
2
3
4
5
4
3
Compare Index Register with Memory Byte
(X) – (M)
— — ↕ ↕ ↕
dd
ff
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
5
3
3
6
5
Decrement Byte
— — ↕ ↕ —
ii
dd
hh ll
ee ff
ff
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
IMM
DIR
EXT
IX2
IX1
IX
A8
B8
C8
D8
E8
F8
2
3
4
5
4
3
EXCLUSIVE OR Accumulator with Memory
Byte
A ← (A) (M)
— —
↕
—
↕
dd
ff
INC opr
INCA
INCX
INC opr,X
INC ,X
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
5
3
3
6
5
Increment Byte
— — ↕ ↕ —
dd
hh ll
ee ff
ff
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
2
3
4
3
2
Unconditional Jump
PC ← Jump Address
— — — — —
Technical Data
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MOTOROLA
Instruction Set
Instruction Set
Instruction Set Summary
Table 10-6. Instruction Set Summary (Sheet 4 of 6)
Effect on
CCR
Source
Form
Operation
Description
H I N Z C
dd
hh ll
ee ff
ff
JSR opr
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
5
6
7
6
5
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Jump to Subroutine
— — — — —
ii
dd
hh ll
ee ff
ff
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
2
3
4
5
4
3
Load Accumulator with Memory Byte
A ← (M)
X ← (M)
— —
↕
—
↕
ii
dd
hh ll
ee ff
ff
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
2
3
4
5
4
3
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
— — ↕ ↕ —
dd
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
DIR
INH
INH
IX1
IX
38
48
58
68
78
5
3
3
6
5
C
0
— —
↕
↕
↕
↕
↕
b7
b0
ff
dd
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
INH
IX1
IX
34
44
54
64
74
5
3
3
6
5
0
C
Logical Shift Right
— — 0
b7
b0
ff
MUL
Unsigned Multiply
X : A ← (X) × (A)
0 — — — 0
— — ↕ ↕ ↕
— — — — —
INH
42
11
dd
ff
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
INH
IX1
IX
30
40
50
60
70
5
3
3
6
5
Negate Byte (Two’s Complement)
No Operation
NOP
INH
9D
2
ii
dd
hh ll
ee ff
ff
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
2
3
4
5
4
3
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
A ← (A) (M)
— — ↕ ↕ —
dd
ff
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
INH
INH
IX1
IX
39
49
59
69
79
5
3
3
6
5
C
— —
↕
↕
↕
b7
b0
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Instruction Set
Instruc tion Se t
Table 10-6. Instruction Set Summary (Sheet 5 of 6)
Effect on
Source
Form
CCR
Operation
Description
H I N Z C
dd
ff
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
DIR
INH
INH
IX1
IX
36
46
56
66
76
5
3
3
6
5
C
Rotate Byte Right through Carry Bit
— —
↕
↕
↕
b7
b0
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $00FF
— — — — —
INH
9C
2
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
↕
↕ ↕ ↕
INH
80
9
↕
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from Subroutine
— — — — —
INH
81
6
ii
dd
hh ll
ee ff
ff
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
2
3
4
5
4
3
Subtract Memory Byte and Carry Bit from
Accumulator
A ← (A) – (M) – (C)
— —
↕
↕
↕
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
— — — — 1
— 1 — — —
INH
INH
99
9B
2
2
Set Interrupt Mask
dd
hh ll
ee ff
ff
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
4
5
6
5
4
Store Accumulator in Memory
Stop Oscillator and Enable IRQ Pin
Store Index Register In Memory
M ← (A)
— —
↕
—
↕
STOP
— 0 — — —
INH
8E
2
dd
hh ll
ee ff
ff
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
4
5
6
5
4
M ← (X)
— —
— —
↕
↕
—
↕
ii
dd
hh ll
ee ff
ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
2
3
4
5
4
3
Subtract Memory Byte from Accumulator
A ← (A) – (M)
↕ ↕
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
SWI
TAX
Software Interrupt
— 1 — — —
— — — — —
INH
INH
83
97
10
2
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Transfer Accumulator to Index Register
X ← (A)
Technical Data
112
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MOTOROLA
Instruction Set
Instruction Set
Instruction Set Summary
Table 10-6. Instruction Set Summary (Sheet 6 of 6)
Effect on
CCR
Source
Form
Operation
Description
H I N Z C
dd
ff
TST opr
TSTA
TSTX
TST opr,X
TST ,X
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
4
3
3
5
4
Test Memory Byte for Negative or Zero
(M) – $00
— —
↕ —
↕
TXA
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
A ← (X)
— — — — —
— 0 — — —
INH
INH
9F
8F
2
2
WAIT
A
C
Accumulator
Carry/borrow flag
opr
PC
Operand (one or two bytes)
Program counter
CCR
dd
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
PCH Program counter high byte
PCL
REL
rel
rr
SP
X
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
dd rr
DIR
ee ff
EXT
ff
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
Index register
H
Z
Zero flag
hh ll
I
High and low bytes of operand address in extended addressing
Interrupt mask
#
Immediate value
Logical AND
ii
Immediate operand byte
Logical OR
IMM
INH
IX
IX1
IX2
M
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
( )
–( )
←
?
:
↕
—
If
Concatenated with
Set or cleared
Not affected
N
n
Negative flag
Any bit
MC68HC05K3 — Revision 4.0
MOTOROLA
TechnicalData
113
Instruction Set
Table 10-7. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
3
INH
INH
IX1
IX
7
INH
INH
IMM
A
DIR
B
EXT
IX2
IX1
E
IX
F
MSB
LSB
MSB
LSB
0
1
2
4
5
6
8
9
C
D
5
5
BSET0
DIR
5
BCLR0
DIR
5
BSET1
DIR
5
BCLR1
DIR
3
5
3
3
6
5
NEG
IX
9
2
3
4
5
4
3
SUB
IX
3
CMP
IX
3
SBC
IX
3
CPX
IX
3
AND
IX
3
BIT
IX
3
LDA
IX
4
STA
IX
3
EOR
IX
3
ADC
IX
3
ORA
IX
3
ADD
IX
2
JMP
IX
5
JSR
IX
3
LDX
IX
4
STX
IX
BRSET0
BRA
NEG
NEGA
INH
NEGX
INH
NEG
RTI
INH
SUB
SUB
SUB
SUB
SUB
0
1
0
3
DIR
5
BRCLR0
DIR
5
BRSET1
DIR
5
BRCLR1
DIR
5
BRSET2
DIR
5
BRCLR2
DIR
5
BRSET3
DIR
5
BRCLR3
DIR
5
BRSET4
DIR
5
BRCLR4
DIR
5
BRSET5
DIR
5
BRCLR5
DIR
5
BRSET6
DIR
5
BRCLR6
DIR
5
BRSET7
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
REL
2
DIR
1
1
1
2
IX1
1
1
1
2
2
2
2
2
2
2
IMM
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
DIR
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
EXT
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IX2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IX1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
6
2
3
4
5
4
BRN
RTS
CMP
CMP
CMP
CMP
CMP
1
2
3
REL
INH
IMM
DIR
EXT
IX2
IX1
3
BHI
REL
11
MUL
INH
3
COMA
INH
2
3
4
5
4
SBC
SBC
SBC
SBC
SBC
2
3
IMM
DIR
EXT
IX2
IX1
3
5
3
COMX
INH
6
COM
IX1
6
LSR
IX1
5
COM
IX
5
LSR
IX
10
2
3
4
5
4
BLS
COM
SWI
CPX
CPX
CPX
CPX
CPX
3
3
3
REL
2
2
DIR 1
1
1
2
2
1
1
1
INH
IMM
DIR
EXT
IX2
IX1
5
BSET2
DIR
3
5
3
3
2
3
4
5
4
BCC
LSR
DIR
LSRA
INH
LSRX
INH
AND
AND
AND
AND
AND
4
4
3
REL
1
IMM
DIR
EXT
IX2
IX1
5
3
2
BIT
IMM
3
BIT
DIR
4
BIT
EXT
5
4
BCLR2 BCS/BLO
BIT
BIT
5
5
3
DIR
2
2
2
2
2
2
2
2
2
2
2
REL
3
BNE
REL
3
BEQ
REL
3
BHCC
REL
3
BHCS
REL
3
BPL
REL
3
BMI
REL
3
BMC
REL
3
BMS
IX2
IX1
5
BSET3
DIR
5
BCLR3
DIR
5
BSET4
DIR
5
BCLR4
DIR
5
BSET5
DIR
5
BCLR5
DIR
5
BSET6
DIR
5
BCLR6
DIR
5
3
3
6
ROR
IX1
6
ASR
IX1
5
ROR
IX
5
ASR
IX
2
3
4
5
4
ROR
RORA
INH
RORX
INH
LDA
LDA
LDA
LDA
LDA
6
6
3
2
2
DIR
1
1
1
1
2
2
1
1
IMM
DIR
EXT
IX2
IX1
5
3
3
2
4
5
STA
EXT
6
5
ASR
ASRA
INH
ASRX
INH
TAX
STA
STA
STA
7
7
3
DIR
1
1
1
1
1
1
1
INH
DIR
IX2
IX1
5
3
3
6
5
2
2
3
4
5
4
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
CLC
EOR
EOR
EOR
EOR
EOR
8
8
3
2
2
2
DIR
5
ROL
DIR
5
DEC
DIR
1
1
1
INH
3
ROLA
INH
1
1
1
INH
3
ROLX
INH
2
2
2
IX1
6
ROL
IX1
6
DEC
IX1
1
1
1
IX
INH
2
2
2
2
IMM
DIR
EXT
IX2
IX1
5
ROL
IX
5
DEC
IX
2
2
3
4
5
4
SEC
ADC
ADC
ADC
ADC
ADC
9
9
3
INH
IMM
DIR
EXT
IX2
IX1
3
3
2
CLI
INH
2
SEI
INH
2
3
4
5
4
DECA
INH
DECX
INH
ORA
ORA
ORA
ORA
ORA
A
B
C
D
E
F
A
B
C
D
E
F
3
IMM
DIR
EXT
IX2
IX1
2
3
4
5
4
ADD
ADD
ADD
ADD
ADD
3
IMM
DIR
EXT
IX2
IX1
5
INC
3
3
6
INC
5
INC
IX
4
TST
IX
2
2
3
4
3
INCA
INH
INCX
INH
RSP
JMP
JMP
JMP
JMP
3
2
2
DIR
4
1
1
1
1
2
2
IX1
5
1
1
INH
DIR
EXT
IX2
IX1
3
3
2
6
5
6
7
6
TST
DIR
TSTA
INH
TSTX
INH
TST
IX1
NOP
BSR
JSR
JSR
JSR
JSR
3
REL
3
BIL
REL
3
BIH
REL
INH
2
2
REL
DIR
EXT
IX2
IX1
5
BSET7
DIR
5
BCLR7
DIR
2
2
3
4
5
4
STOP
INH
LDX
LDX
LDX
LDX
LDX
3
DIR
5
1
1
IMM
DIR
EXT
IX2
IX1
5
3
3
6
5
CLR
IX
2
2
4
5
6
5
BRCLR7
CLR
DIR
CLRA
INH
CLRX
INH
CLR
IX1
WAIT
INH
TXA
STX
STX
STX
STX
3
DIR
2
1
1
2
1
1
INH
DIR
EXT
IX2
IX1
MSB
INH = InherentREL = Relative
IMM = ImmediateIX = Indexed, No Offset
DIR = DirectIX1 = Indexed, 8-Bit Offset
MSB of Opcode in
Hexadecimal
Number of Cycles
BRSET0 Opcode Mnemonic
DIR Number of Bytes/Addressing Mode
0
LSB
5
0
LSB of Opcode in Hexadecimal
3
EXT = ExtendedIX2 = Indexed, 16-Bit Offset
Te c hnic a l Da ta — MC68HC05K3
Se c tion 11. Ele c tric a l Sp e c ific a tions
11.1 Conte nts
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
11.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
11.4 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
11.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
11.6 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .118
11.7 3.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .119
11.8 5.0-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
11.9 3.0-Volt Control Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
11.10 1.8-Volt Control Timing (PEEPROM Read Only) . . . . . . . . . .122
11.2 Introd uc tion
This section contains electrical and timing specifications.
MC68HC05K3 — Revision 4.0
MOTOROLA
Technical Data
115
Electrical Specifications
Ele c tric a l Sp e c ific a tions
11.3 Ma xim um Ra ting s
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep VIN and VOUT within the range
VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD
Rating
Symbol
Value
Unit
V
Supply voltage
–0.3 to + 7.0
V
DD
V
–0.3 to
+ –0.3
SS
V
Input voltage
V
V
IN
V
DD
V
2 x V
25
Input voltage (IRQ pin only)
Current drain per pin
IN
DD
I
mA
°C
excluding V and V
DD
SS
T
Storage temperature range
–65 to + 150
STG
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 11.6 5.0-Volt DC Electrical Characteristics and
11.7 3.0-Volt DC Electrical Characteristics for guaranteed operating
conditions.
Technical Data
116
MC68HC05K3 — Revision 4.0
Electrical Specifications
MOTOROLA
Electrical Specifications
Operating Range
11.4 Op e ra ting Ra ng e
Characteristic
Symbol
Value
Unit
T to T
Operating temperature range
MC68HC05K3 (standard)
MC68HC05K3 (extended)
L
H
T
°C
0 to +70
–40 to +85
A
Supply voltage range for internal charge
pump operation
V
2.7 to 5.5
V
DDCP
11.5 The rm a l Cha ra c te ristic s
Characteristic
Thermal resistance
Symbol
Value
Unit
θ
PDIP
SOIC
100
140
°C/W
JA
MC68HC05K3 — Revision 4.0
MOTOROLA
TechnicalData
117
Electrical Specifications
Ele c tric a l Sp e c ific a tions
11.6 5.0-Volt DC Ele c tric a l Cha ra c te ristic s
(1)
(2)
(3)
Symbol
Max
Unit
Characteristic
Min
Typ
Output high voltage (I
= –0.8 mA)
Load
V
VDD –0.8
—
—
V
OH
PA7–PA0, PB1/OSC3, PB0
Output low voltage
PA3–PA0, PB1/OSC3, PB0 (I
= 1.6 mA)
V
—
—
—
—
0.4
0.4
V
Load
OL
PA7–PA4 (I
= 8.0 mA)
Load
Input high voltage
V
0.7 x VDD
VSS
VDD
—
—
V
V
IH
PA0–PA7, PB0, PB1/OSC3, IRQ, RESET, OSC1
Input low voltage
V
0.2 x VDD
IL
PA0–PA7, PB0, PB1/OSC3, IRQ, RESET, OSC1
(4), (5), (6), (7), (8)
Supply current (fOP = 2 MHz)
—
—
—
—
5.0
3.0
mA
mA
Run
Wait
Stop
I
DD
—
—
—
100
—
—
200
400
500
nA
nA
nA
25 °C
0 °C to +70 °C (standard)
–40 °C to +85 °C (extended)
I/O ports hi-Z leakage current
I
I
—
0.2
1
µA
µA
IL
IL
PA0–PA7, PB0–PB1 (without pulldowns activated)
Input pulldown current
PA0–PA7, PB0–PB1
50
100
200
Input current IRQ and OSC1
RESET (V = V )
—
—
—
—
15
50
1
—
—
I
I
µA
In
IH
In
In
RESET (V = V )
In
IL
RESET, internal pulldown device
1.0
4.0
8.0
mA
pF
Capacitance
Ports (as input or output)
RESET, IRQ, OSC1, OSC2
C
—
—
—
—
12
8
Out
C
In
Crystal/ceramic resonator
Oscillator mode internal resistor OSC1 to OSC2
R
1.0
2.0
3.0
MΩ
OSC
Notes:
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted.
2. All values shown reflect average measurements.
3. Typical values at midpoint of voltage range, 25 °C only
4. Wait IDD: Only timer system active
5. Run (operating) IDD, wait IDD: Measured using external square wave clock source to OSC1, all inputs 0.2 Vdc from rail;
no DC loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
6. Wait, stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc
7. Stop IDD measured with OSC1 = VDD, RESET open
8. Wait IDD is affected linearly by the OSC2 capacitance.
Technical Data
118
MC68HC05K3 — Revision 4.0
MOTOROLA
Electrical Specifications
Electrical Specifications
3.0-Volt DC Electrical Characteristics
11.7 3.0-Volt DC Ele c tric a l Cha ra c te ristic s
(1)
(2)
(3)
Symbol
Max
Unit
Characteristic
Min
Typ
Output high voltage (I
= –0.4 mA)
Load
V
VDD –0.3
—
—
V
OH
PA7–PA0, PB1/OSC3, PB0
Output low voltage
PA3–PA0, PB1/OSC3, PB0 (I
= 0.4 mA)
V
—
—
—
—
0.3
0.3
V
Load
OL
PA7–PA4 (I
= 4.0 mA)
Load
Input high voltage
V
0.7 x VDD
VSS
VDD
—
—
V
V
IH
PA0–PA7, PB0, PB1/OSC3, IRQ, RESET, OSC1
Input low voltage
V
0.2 x VDD
IL
PA0–PA7, PB0, PB1/OSC3, IRQ, RESET, OSC1
(4), (5), (6), (7), (8)
Supply current (fOP = 1 MHz)
—
—
—
—
2.0
0.75
mA
mA
Run
Wait
Stop
I
DD
—
—
—
50
—
—
100
175
200
nA
nA
nA
25 °C
0 °C to +70 °C (standard)
–40 °C to +85 °C (extended)
I/O ports hi-Z leakage current
PA0–PA7, PB0–PB1 (without individual pulldown
activated)
I
I
—
0.1
50
1
µA
µA
IL
IL
Input pulldown current
PA0–PA7, PB0–PB1
25
100
Input current
IRQ, OSC1
—
—
—
—
10
30
1
—
—
I
I
µA
In
In
RESET (V = V )
In
IH
RESET (V = V )
In
IL
RESET, internal pulldown device
0.2
2.0
4.0
mA
pF
Capacitance
Ports (as input or output)
RESET, IRQ, OSC1, OSC2
C
—
—
—
—
12
8
Out
C
In
Crystal/ceramic resonator
Oscillator mode internal resistor OSC1 to OSC2
R
1.0
2.0
3.0
MΩ
OSC
Notes:
1. VDD = 3.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted
2. All values shown reflect average measurements
3. Typical values at midpoint of voltage range, 25 °C only
4. Wait IDD: Only timer system active
5. Run (operating) IDD, wait IDD: Measured using external square wave clock source to OSC1, all inputs 0.2 Vdc from rail;
no DC loads, less than 50 pF on all outputs, CL = 20 pF on OSC2
6. Wait, stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc
7. Stop IDD measured with OSC1 = VDD, RESET open
8. Wait IDD is affected linearly by the OSC2 capacitance
MC68HC05K3 — Revision 4.0
MOTOROLA
TechnicalData
119
Electrical Specifications
Ele c tric a l Sp e c ific a tions
11.8 5.0-Volt Control Tim ing
(1)
Symbol
Min
Max
Unit
Characteristic
Frequency of operation
3-pin RC oscillator option
2-pin RC oscillator option
Crystal oscillator option
External clock source
0.1
0.1
0.5
DC
1.25
2.7
4.0
4.0
f
MHz
OSC
Internal operating frequency
RC oscillator (fOSC ÷ 2)
0.5
1.0
DC
1.0
2.0
2.0
f
MHz
OP
Crystal oscillator (fOSC ÷ 2)
External clock (fOSC ÷ 2)
Cycle time (1 ÷ fOP)
t
500
—
—
1
νs
ms
ms
ms
cyc
t
RC oscillator stabilization time
RCON
t
Crystal oscillator startup time (crystal oscillator option)
Stop recovery startup time (crystal oscillator option)
RESET pulse width low
—
100
100
—
OXON
t
—
ILCH
t
t
1.5
4.0
RL
cyc
(2)
t
t
—
Timer resolution
RESL
cyc
t
IRQ interrupt pulse width low (edge-triggered)
IRQ interrupt pulse period
125
—
ns
ILIH
(3)
t
t
—
ILIL
cyc
t
PA0–PA3 interrupt pulse width high (edge-triggered)
PA0–PA3 interrupt pulse period
125
(3)
—
ns
IHIL
t
t
—
IHIH
cyc
OSC1 pulse width
t
90
—
ns
%
(4)
2-pin RC oscillator frequency combined stability
∆f
—
—
±35
±25
OSC
fOSC = 500 kHz
(4)
3-pin RC oscillator frequency combined stability
∆f
%
OSC
fOSC = 500 kHz
t
PEEPROM bit programming time
PEEPROM byte erase time
PEEPROM bulk erase time
—
—
—
—
10
10
30
1
ms
ms
ms
ms
EPGM
t
ERBT
t
ERBK
t
PEEPROM charge pump startup time
Notes:
CP
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted
2. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
3. The minimum period, tILIL or tIHIH, should not be less than the number of cycles it takes to execute the interrupt service
routine plus 19 tcyc
4. Effects of processing, temperature, and supply voltage (including tolerances of external 1% R and 2% C)
.
Technical Data
120
MC68HC05K3 — Revision 4.0
MOTOROLA
Electrical Specifications
Electrical Specifications
3.0-Volt Control Timing
11.9 3.0-Volt Control Tim ing
(1)
Symbol
Min
Max
Unit
Characteristic
Frequency of operation
3-pin RC oscillator option
2-pin RC oscillator option
Crystal oscillator option
External clock source
0.1
0.1
0.4
DC
0.6
0.7
2.0
2.0
f
MHz
OSC
Internal operating frequency
RC oscillator (fOSC ÷ 2)
—
—
DC
0.35
1.0
1.0
f
MHz
OP
Crystal oscillator (fOSC ÷ 2)
External clock (fOSC ÷ 2)
Cycle time (1 ÷ fOP)
t
1.0
—
—
1
µs
ms
ms
ms
cyc
t
RC oscillator stabilization time
RCON
t
Crystal oscillator startup time (crystal oscillator option)
Stop recovery startup time (crystal oscillator option)
RESET pulse width low
—
100
100
—
OXON
t
—
ILCH
t
t
1.5
4.0
RL
cyc
(2)
t
t
—
Timer resolution
RESL
cyc
t
IRQ interrupt pulse width low (edge-triggered)
IRQ interrupt pulse period
125
—
ns
ILIH
(3)
t
t
—
ILIL
cyc
t
PA0–PA3 interrupt pulse width high (edge-triggered)
PA0–PA3 interrupt pulse period
125
(3)
—
ns
IHIL
t
t
—
IHIH
cyc
OSC1 pulse width
t
180
—
ns
%
(4)
2-pin RC oscillator frequency combined stability
∆f
—
—
±35
±15
OSC
fOSC = 500 kHz
(4)
3-pin RC oscillator frequency combined stability
∆f
%
OSC
fOSC = 500 kHz
t
PEEPROM bit programming time
PEEPROM byte erase time
PEEPROM bulk erase time
—
—
—
—
15
15
30
1
ms
ms
ms
ms
EPGM
t
ERBT
t
ERBK
t
PEEPROM charge pump startup time
Notes:
CP
1. VDD = 3.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted
2. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
3. The minimum period, tILIL or tIHIH, should not be less than the number of cycles it takes to execute the interrupt service
routine plus 19 tcyc
4. Effects of processing, temperature, and supply voltage (including tolerances of external 1% R and 2% C)
.
MC68HC05K3 — Revision 4.0
MOTOROLA
TechnicalData
121
Electrical Specifications
Ele c tric a l Sp e c ific a tions
11.10 1.8-Volt Control Tim ing (PEEPROM Re a d Only)
(1)
Symbol
Min
Max
Unit
Characteristic
Frequency of operation
3-pin RC oscillator option
2-pin RC oscillator option
Crystal oscillator option
External clock source
0.1
0.1
0.4
DC
0.6
0.7
1.0
1.0
f
MHz
OSC
Internal operating frequency
RC oscillator (fOSC ÷ 2)
—
—
DC
350
500
500
f
kHz
OP
Crystal oscillator (fOSC ÷ 2)
External clock (fOSC ÷ 2)
Cycle time (1 ÷ fOP)
t
2.0
—
—
1
µs
ms
ms
ms
cyc
t
RC oscillator stabilization time
RCON
t
Crystal oscillator startup time (crystal oscillator option)
Stop recovery startup time (crystal oscillator option)
RESET pulse width low
—
100
100
—
OXON
t
—
ILCH
t
t
1.5
4.0
RL
cyc
(2)
t
t
—
Timer resolution
RESL
cyc
t
IRQ interrupt pulse width low (edge-triggered)
IRQ interrupt pulse period
125
—
ns
ILIH
(3)
t
t
—
ILIL
cyc
t
PA0–PA3 interrupt pulse width high (edge-triggered)
PA0–PA3 interrupt pulse period
125
(3)
—
ns
IHIL
t
t
—
IHIH
cyc
OSC1 pulse width
t
360
—
ns
%
(4)
2-pin RC oscillator frequency combined stability
∆f
—
—
±35
±15
OSC
fOSC = 500 kHz
(4)
3-pin RC oscillator frequency combined stability
∆f
%
OSC
fOSC = 500 kHz
Notes:
1. VDD = 1.8 Vdc minimum, VSS = 0 Vdc, TA = –40 °C to +85 °C, unless otherwise noted
2. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
3. The minimum period, tILIL or tIHIH, should not be less than the number of cycles it takes to execute the interrupt service
routine plus 19 tcyc
4. Effects of processing, temperature, and supply voltage (including tolerances of external 1% R and 2% C)
.
Technical Data
122
MC68HC05K3 — Revision 4.0
MOTOROLA
Electrical Specifications
Te c hnic a l Da ta — MC68HC05K3
Se c tion 12. Me c ha nic a l Sp e c ific a tions
12.1 Conte nts
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
12.3 Dual In-Line Package (Case 648). . . . . . . . . . . . . . . . . . . . . .124
12.4 Small Outline Integrated Circuit (Case 751) . . . . . . . . . . . . . .124
12.5 Super Small Outline Package (Case 940C) . . . . . . . . . . . . . .125
12.2 Introd uc tion
The MC68HC05K3 is available in these packages:
• Plastic dual in-line package (PDIP)
• Small outline integrated circuit (SOIC)
• Super small outline package (SSOP)
The following figures show the latest packages at the time of this
publication. To make sure that you have the latest package
specifications, contact one of the following:
• Local Motorola Sales Office
• Motorola Mfax
– Phone 602-244-6609
– EMAIL rmfax0@email.sps.mot.com
• Worldwide Web (wwweb) at http://design-net.com
Follow Mfax or wwweb on-line instructions to retrieve the current
mechanical specifications.
MC68HC05K3 — Revision 4.0
MOTOROLA
Technical Data
123
Mechanical Specifications
Me c ha nic a l Sp e c ific a tions
12.3 Dua l In-Line Pa c ka g e (Ca se 648)
-A-
16
1
9
8
B
S
INCHES
MILLIMETERS
MIN MAX
18.80 19.55
DIM
MIN
MAX
F
A
B
C
D
F
0.740
0.250
0.145
0.015
0.040
0.770
0.270
0.175
0.021
0.70
C
L
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
SEATING
PLANE
-T-
G
H
J
0.100 BSC
0.050 BSC
0.008
2.54 BSC
1.27 BSC
0.21
K
M
0.015
0.130
0.305
10°
0.38
3.30
7.74
10°
H
J
K
L
M
S
0.110
0.295
0°
2.80
7.50
0°
G
D
16 PL
0.020
0.040
0.51
1.01
M
M
0.25 (0.010)
T A
12.4 Sm a ll Outline Inte g ra te d Circ uit (Ca se 751)
-A-
16
9
-B-
8X P
M
M
B
0.010 (0.25)
1
8
J
D 16X
M
S
S
B
0.010 (0.25)
T
A
F
MILLIMETERS
INCHES
MAX
0.411
DIM
MIN
10.15
7.40
2.35
0.35
0.50
MAX
10.45
7.60
2.65
0.49
0.90
MIN
A
B
C
D
F
0.400
0.292
0.093
0.014
0.020
R X 45
0.299
0.104
0.019
0.035
C
G
J
1.27 BSC
0.050 BSC
-T-
0.25
0.10
0°
0.32
0.25
7°
0.010
0.004
0°
0.012
0.009
7°
M
SEATING
PLANE
G14X
K
K
M
P
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
R
Technical Data
124
MC68HC05K3 — Revision 4.0
MOTOROLA
Mechanical Specifications
Mechanical Specifications
Super Small Outline Package (Case 940C)
12.5 Sup e r Sm a ll Outline Pa c ka g e (Ca se 940C)
20X K REF
NOTES:
M
S
S
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
0.12 (0.005)
T U
V
0.25 (0.010)
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
N
20
11
L/2
M
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
B
N
L
F
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION/INTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13 (0.005)
TOTAL IN EXCESS OF K DIMENSION AT
MAXIMUM MATERIAL CONDITION. DAMBAR
INTRUSION SHALL NOT REDUCE DIMENSION K
BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL
CONDITION.
PIN 1
1
10
IDENT
DETAIL E
±U±
A
±V±
K
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
M
S
J
0.20 (0.008)
T U
J1
MILLIMETERS
DIM MIN MAX
INCHES
K1
MIN
MAX
0.288
0.212
0.078
0.008
0.037
A
B
C
D
F
7.07
5.20
1.73
0.05
0.63
7.33 0.278
5.38 0.205
1.99 0.068
0.21 0.002
0.95 0.024
SECTION N±N
±W±
C
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.076 (0.003)
0.59
0.09
0.09
0.25
0.25
7.65
0
0.75 0.023
0.20 0.003
0.16 0.003
0.38 0.010
0.33 0.010
7.90 0.301
0.030
0.008
0.006
0.015
0.013
0.311
8
SEATING
PLANE
±T±
D
G
DETAIL E
H
M
8
0
MC68HC05K3 — Revision 4.0
MOTOROLA
TechnicalData
125
Mechanical Specifications
Me c ha nic a l Sp e c ific a tions
Technical Data
126
MC68HC05K3 — Revision 4.0
MOTOROLA
Mechanical Specifications
Te c hnic a l Da ta — MC68HC05K3
Se c tion 13. Ord e ring Inform a tion
13.1 Conte nts
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
13.3 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
13.4 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .128
13.5 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .129
13.6 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
13.2 Introd uc tion
This section contains instructions for ordering custom-masked ROM
MCUs.
13.3 MCU Ord e ring Form s
To initiate an order for a ROM-based MCU, first obtain the current
ordering form for the MCU from a Motorola representative. Submit the
following items when ordering MCUs:
• A current MCU ordering form that is completely filled out
(Contact your Motorola sales office for assistance.)
• A copy of the customer specification if the customer specification
deviates from the Motorola specification for the MCU
• Customer’s application program on one of the media listed in
13.4 Application Program Media
MC68HC05K3 — Revision 4.0
MOTOROLA
Technical Data
127
Ordering Information
Ord e ring Inform a tion
The current MCU ordering form is also available through the Motorola
Freeware Bulletin Board Service (BBS). The telephone number is (512)
891-FREE. After making the connection, type bbs in lowercase letters.
Then press the return key to start the BBS software.
13.4 Ap p lic a tion Prog ra m Me d ia
Deliver the application program to Motorola in one of the following
media:
®1
• Macintosh 3 1/2-inch diskette (double-sided 800 K or
double-sided high-density 1.4 M)
®2
• MS-DOS or PC-DOSTM3 3 1/2-inch diskette (double-sided 720
K or double-sided high-density 1.44 M)
®
• MS-DOS or PC-DOSTM 5 1/4-inch diskette (double-sided
double-density 360 K or double-sided high-density 1.2 M)
Use positive logic for data and addresses.
When submitting the application program on a diskette, clearly label the
diskette with the following information:
• Customer name
• Customer part number
• Project or product name
• File name of object code
• Date
• Name of operating system that formatted diskette
• Formatted capacity of diskette
On diskettes, the application program must be in Motorola’s S-record
format (S1 and S9 records), a character-based object file format
generated by M6805 cross assemblers and linkers.
1. Macintosh is a registered trademark of Apple Computer, Inc.
2. MS-DOS is a registered trademark of Microsoft Corporation in the United States and/or
other countries..
3. PC-DOS is a trademark of International Business Machines Corporation.
Technical Data
128
MC68HC05K3 — Revision 4.0
Ordering Information
MOTOROLA
Ordering Information
ROM Program Verification
Begin the application program at the first user ROM location. Program
addresses must correspond exactly to the available on-chip user ROM
addresses as shown in the memory map. Write $00 in all non-user
ROM locations or leave all non-user ROM locations blank. Refer to
the current MCU ordering form for additional requirements. Motorola
may request pattern re-submission if non-user areas contain any
non-zero code.
If the memory map has two user ROM areas with the same addresses,
then write the two areas in separate files on the diskette. Label the
diskette with both filenames.
In addition to the object code, a file containing the source code can be
included. Motorola keeps this code confidential and uses it only to
expedite ROM pattern generation in case of any difficulty with the object
code. Label the diskette with the filename of the source code.
13.5 ROM Prog ra m Ve rific a tion
The primary use for the on-chip ROM is to hold the customer’s
application program. The customer develops and debugs the application
program and then submits the MCU order along with the application
program.
Motorola inputs the customer’s application program code into a
computer program that generates a listing verify file. The listing verify file
represents the memory map of the MCU. The listing verify file contains
the user ROM code and may also contain non-user ROM code, such as
self-check code. Motorola sends the customer a computer printout of the
listing verify file along with a listing verify form.
To aid the customer in checking the listing verify file, Motorola will
program the listing verify file into customer-supplied blank preformatted
Macintosh or DOS disks. All original pattern media are filed for
contractual purposes and are not returned.
Check the listing verify file thoroughly, then complete and sign the listing
verify form and return the listing verify form to Motorola. The signed
MC68HC05K3 — Revision 4.0
MOTOROLA
TechnicalData
129
Ordering Information
Ord e ring Inform a tion
listing verify form constitutes the contractual agreement for the creation
of the custom mask.
13.6 MC Ord e r Num b e rs
Table 13-1 shows the MC order numbers for the available package
types.
Table 13-1. MC Order Numbers
Operating
Temperature Range
MC Order Number
MC68HC05K3P (standard)
MC68HC05K3CP (extended)
MC68HC05K3DW (standard)
MC68HC05K3CDW (extended)
MC68HC05K3CSD
–0 °C to 70 °C
–40 °C to 85 °C
–0 °C to 70 °C
–40 °C to 85 °C
–40 °C to 85 °C
Notes:
P = Plastic dual in-line package
DW = Small outline integrated circuit (SOIC) package
SD = Super small outline package (SSOP)
Technical Data
130
MC68HC05K3 — Revision 4.0
MOTOROLA
Ordering Information
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its
products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts.
Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the
design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution, P.O. Box 5405, Denver, Colorado 80217, 1-800-441-2447 or
1-303-675-2140. Customer Focus Center, 1-800-521-6274
JAPAN: Motorola Japan Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 03-5487-8488
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd., 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
Mfax™, Motorola Fax Back System: RMFAX0@email.sps.mot.com; http://sps.motorola.com/mfax/;
TOUCHTONE, 1-602-244-6609; US and Canada ONLY, 1-800-774-1848
HOME PAGE: http://motorola.com/sps/
Mfax is a trademark of Motorola, Inc.
© Motorola, Inc., 1998
MC68HC05K3/D
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