HD6435368U [ETC]
Application Notes Single-Chip Microcomputer Technical Questions and Answers H8/500 Series ; 应用笔记单片机技术问答H8 / 500系列\n
| 型号： | HD6435368U |
| 厂家： | 
ETC |
| 描述： | Application Notes Single-Chip Microcomputer Technical Questions and Answers H8/500 Series
|
| 文件： | 总53页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Application Notes
Hitachi Single-Chip Microcomputer
Technical Questions and Answers
H8/500 Series
Preface
The H8/500 Series is a series of highly integrated single-chip microcontrollers. Their CPU core
has an internal 16-bit architecture, and each chip includes diverse high-performance peripheral
hardware.
These technical questions and answers relate to the H8/510, H8/520, H8/532, H8/534, and
H8/536.
H8/500 Family
Item
H8/510
H8/500
—
H8/520
H8/532
H8/534
H8/536
CPU
H8/500
H8/500
H8/500
H8/500
Memory ROM Masked ROM
ZTAT®*2
16 kbytes 32 kbytes 32 kbytes 62 kbytes
×
❍
❍
❍
❍
RAM
—
512 bytes 1 kbyte
2 kbytes
1 M
8
2 kbytes
1 M
8
Address space (bytes)
External data bus width (bits)
16 M
8/16
1 M
8
1 M
8
Timers 16-bit free-running timer 2 ch
2 ch
1 ch
1 ch
—
3 ch
1 ch
1 ch
3 ch
1 ch
3 ch
1 ch
1 ch
3 ch
2 ch
3 ch
1 ch
1 ch
3 ch
2 ch
8-bit timer
1 ch
1 ch
—
Watchdog timer
PWM timer
Serial communication interface
(async/sync)
2 ch
2 ch
A/D
External
10 bits,
10 bits, 4 or 10 bits,
10 bits,
10 bits,
converter
trigger input
4 channels, 8* channels, 8 channels, 8 channels, 8 channels,
trigger
trigger
no trigger no trigger no trigger
Interrupts
External interrupts 5
Internal interrupts 18
60
9
3
7
7
18
19
65
23
23
I/O ports
50/54*1
65
65
Packages
QFP-112
DILC-64S LCC-84
LCC-84
LCC-84
(windowed) (windowed) (windowed) (windowed)
DILP-64S PLCC-84 PLCC-84 PLCC-84
PLCC-68*1 QFP-80
QFP-64
QFP-80
QFP-80
Notes: 1. PLCC-68 package
2. ZTAT is a registered trademark of Hitachi, Ltd.
How to Use These Technical Questions and Answers
Technical Questions and Answers has been created by arranging technical questions actually
asked by users of Hitachi microcomputers in a question-and-answer format. It should be read for
technical reference in conjunction with the User’s Manual.
Technical Questions and Answers can be read before beginning a microcomputer application
design project to gain a more thorough understanding of the microcomputer, or during the design
process to check up on difficult points.
(For questions and answers about the H8/500 CPU, see H8/500 CPU Microcomputer Technical
Questions and Answers.)
4
Contents
Q&A No.
Page
On-chip ROM
(1) Address bus, data bus, and control line states during access
to on-chip address space
(2) Programming the H8/536 ZTAT
QA500 - 001B
QA500 - 046A
1
2
Clock
(1) EXTAL and system clock output line
(2) External clock specifications
(3) External clock input
(4) External clock input (2)
QA500 - 002B
QA500 - 047A
QA500 - 003B
QA500 - 048A
3
4
5
6
Timers
(1) External clock input to 16-bit FRT
(2) Input capture signal for 16-bit FRT
(3) Access timing to FRC in 16-bit FRT
QA500 - 006B
QA500 - 007B
QA500 - 009B – 1
7
8
9
QA500 - 009B – 2 10
(4) TCNT of 8-bit timer
(5) WDT when system clock stops
(6) NMI requested by WDT
QA500 - 011B
QA500 - 012B
QA500 - 013B
11
12
13
Serial communication interface (SCI)
(1) Input/output designation of SCI clock pin
(2) Serial I/O line status
QA500 - 018B
QA500 - 019B
14
15
(3) RDRF bit set timing
QA500 - 021B – 1 16
QA500 - 021B – 2 17
QA500 - 022B – 1 18
QA500 - 022B – 2 19
(4) TDRE bit set timing
(5) RDR and DTR utilization when SCI is not used
(6) RDRF bit in SCI
(7) SCI receive error 1
(8) SCI receive error 2 (clocked synchronous mode)
(9) SCI RxD input example (asynchronous mode)
(10) SCI transmit start (asynchronous mode)
(11) Simultaneous transmit/receive in clocked synchronous mode
(12) Clearing the SCI’s TDRE bit
QA500 - 023B
QA500 - 049A
QA500 - 050A
QA500 - 051A
QA500 - 052A
QA500 - 053A
QA500 - 054A
QA500 - 055A
20
21
22
23
24
25
26
27
5
Q&A No.
Page
A/D converter
(1) Start of A/D conversion
(2) Non-use of A/D converter reference voltage lines (AV , AV
(3) Changing A/D conversion mode or channels during conversion
(4) Resistor ladder in A/D converter
QA500 - 024B
QA500 - 025B
QA500 - 027B
QA500 - 028B
QA500 - 029B
QA500 - 056A
28
29
30
31
32
33
)
CC
SS
(5) Rise time of power supplies (AV , V
(6) Allowable impedance of A/D signal sources
)
CC
CC
PWM timer
(1) DTR of PWM timer
(2) PWM pin assignments
QA500 - 031B
QA500 - 057A
34
35
Data transfer controller (DTC)
(1) Interrupts during DTC operation
(2) DTC usage
QA500 - 032B
QA500 - 033B
36
37
I/O ports
(1) Analog input part data register during A/D conversion
(2) Port output after reset
(3) AS and RD signal timing
(4) Unused I/O lines
QA500 - 035B
QA500 - 037B
QA500 - 039B
QA500 - 040B
38
39
40
41
Power-down modes
(1) Power dissipation in hardware and software standby modes
QA500 - 041B
QA500 - 058A
QA500 - 059A
QA500 - 060A
42
43
44
45
Bus controller
(1) State of D to D with 8-bit data bus
0
7
Bus interface
(1) State of D to D during byte access in 16-bit data bus mode
0
7
Miscellaneous
(1) RAM standby voltage
6
Technical Question and Answer
Product
Topic
H8/500
Q&A No. QA500 - 001B
Address bus, data bus, and control line states during access to on-chip address space
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Timers
Serial I/O
A/D
Question
1. What values are output on the following lines when on-
chip memory or the on-chip register field is accessed?
❍
❍
(1) Address bus
(2) Data bus
PWM
(3) Bus control signals
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
(1) The address bus carries the address data, regardless of
whether the access is to an on-chip or off-chip address.
(2) The data bus is in the high-impedance state for both read
and write access by the CPU to an on-chip address.
Other Technical
Documentation
Document Name:
(3) The R/W signal is low for write access and high for read
access. The other control signals (AS, DS, RD, WR) are
high.
Related Microcomputer
Technical Q&A
Title:
Additional Information
1
Technical Question and Answer
Product
Topic
H8/536
Programming the H8/536 ZTAT
Q&A No. QA500 - 046A
Classification—H8/536
Software
On-chip ROM
On-chip RAM
Clock
Question
1. We are having trouble programming the ZTAT version of
the H8/536. Are there any precautions we may be missing?
❍
Timers
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. When programming the H8/536, you must set your PROM
writer to memory type HN27C101 and either write H'FF
data in addresses H'F680 to H'1FFFF or set H'F67F as the
end address.
Other Technical
Documentation
Document Name:
Be sure to use byte programming mode. The H8/536 does
not support page programming.
Related Microcomputer
Technical Q&A
Title:
Additional Information
Some PROM writers do not support byte programming for the HN27C101.
2
Technical Question and Answer
Product
Topic
H8/500
Q&A No. QA500 - 002B
EXTAL and system clock output line
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. During external clock input, what is the phase relationship
between EXTAL and the system clock output line
(ø output)?
❍
Timers
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. During external clock input, the phase relationship
between EXTAL and the system clock output line is as
shown below.
Other Technical
Documentation
EXTAL
Document Name:
ø output
Related Microcomputer
Technical Q&A
Title:
Approx. 40 ns internal delay
Additional Information
The internal delay value is not guaranteed.
3
Technical Question and Answer
Product
Topic
H8/500
External clock specifications
Q&A No. QA500 - 047A
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. When an external clock is supplied to the EXTAL pin,
what are the rise-time and fall-time requirements?
❍
Timers
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. For a 20-MHz clock, the rise time (t ) and fall time (t )
Cr
Cf
should both be approximately 5 ns.
External clock
(EXTAL)
Other Technical
Documentation
Document Name:
tCf
tCr
Related Microcomputer
Technical Q&A
Title:
Additional Information
4
Technical Question and Answer
Product
Topic
H8/520, 532, 534, 536
External clock input
Q&A No. QA500 - 003B
Classification—H8/532
Software
On-chip ROM
On-chip RAM
Clock
Question
1. For external clock input, the Hardware Manual shows an
example of a circuit using a 74HC04 (see below). Why is
the 74HC04 necessary?
❍
Timers
Serial I/O
A/D
PWM
External clock input
EXTAL
74HC04
XTAL
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. If the XTAL pin open is left open, operation may become
unstable.
The 74HC04 is necessary to assure stable operation at high
clock rates.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
Note: The XTAL pin can be left open if the external clock rate is 16 MHz or less. For masked-
ROM versions and the H8/510, the XTAL pin can be left open for external clock rates up
to 20 MHz.
5
Technical Question and Answer
Product
Topic
H8/520, 532, 534, 536
External clock input (2)
Q&A No. QA500 - 048A
Classification—H8/532
Software
On-chip ROM
On-chip RAM
Clock
Question
1. The H8/500 Series User’s Manuals (except H8/510) show
a circuit using a 74HC04 for external clock input. (See
diagram on previous page.) Can an ALS-TTL, for
example, be used instead?
❍
Timers
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. An ALS-TTL device can be used if its propagation delay
time and drivability are equivalent to the 74HC04.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
6
Technical Question and Answer
Product
Topic
H8/500
External clock input to 16-bit FRT
Q&A No. QA500 - 006B
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. When the external clock source is selected for the 16-bit
free-running timer, what is the minimum pulse width of the
external clock (FTCI)?
❍
Timers
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. The minimum pulse width of the external clock is 1.5
system clock cycles.
ø
Other Technical
Documentation
Document Name:
FTCI input
Related Microcomputer
Technical Q&A
Title:
1.5 system clocks
Additional Information
7
Technical Question and Answer
Product
Topic
H8/500
Input capture signal for 16-bit FRT
Q&A No. QA500 - 007B
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. If an FRT input capture line (FTI) is multiplexed with a
general-purpose input/output port that is used for output,
will the rise and fall of the output data update the input
capture register?
❍
Timers
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. Yes. The input capture register will be updated by output
on the input/output line, on the edge selected by the input
edge select bit (IEDG) in the timer control/status register
(TCSR).
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
8
Technical Question and Answer
Product
Topic
H8/500
Q&A No. QA500 - 009B – 1
Access timing to FRC in 16-bit FRT
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. What is the read and write timing of the free-running
counter (FRC) in the 16-bit free-running timer (FRT)?
❍
Timers
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. The access timing of the 16-bit timer’s FRC is shown on
the next page.
Word access (or two successive byte accesses) should be
used. The upper byte has to be accessed first.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
9
Technical Question and Answer
Product
Topic
H8/500
Q&A No. QA500 - 009B – 2
Access timing to FRC in 16-bit FRT
Answer
One bus cycle
T2
One bus cycle
T2 T3
T1
T3
T1
ø
Internal address bus
Internal read signal
Internal data bus
H8/500 CPU read
FRCH
H8/500 CPU read
TEMP
→
(FRCL TEMP)
N
N + 1
FRC
FRC Access Timing (read)
Operation when register is read
When the upper byte is read, the upper byte value is passed to the CPU and the lower byte value
is transferred to TEMP. Next, when the lower byte is read, the lower byte value in TEMP is
passed to the CPU.
One bus cycle
T2
One bus cycle
T2 T3
T1
T3
T1
ø
Internal address bus
Internal write signal
Internal data bus
FRC
H8/500 CPU write
High data
H8/500 CPU write
Low data
→
→
→
(High data TEMP) (Low data FRCL, TEMP FRCH)
Write data
N
FRC Access Timing (write)
Operation when register is written
When the upper byte is written, the upper byte value is stored in TEMP. Next, when the lower
byte is written, it is combined with the upper byte value in TEMP and all 16 data bits are written
in the register.
10
Technical Question and Answer
Product
Topic
H8/500
TCNT of 8-bit timer
Q&A No. QA500 - 011B
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. When a compare-match signal clears the timer counter
(TCNT) to H'00, does TCNT remain at H'00, or does it
start counting up from H'00?
❍
Timers
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. TCNT starts counting up from H'00.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
11
Technical Question and Answer
Product
Topic
H8/500
WDT when system clock stops
Q&A No. QA500 - 012B
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. If the system clock stops, will the watchdog timer (WDT)
detect anything wrong?
❍
Timers
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. If the system clock for the whole chip stops, the WDT
count also stops, so the WDT cannot detect the failure.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
12
Technical Question and Answer
Product
Topic
H8/532
NMI requested by WDT
Q&A No. QA500 - 013B
Classification—H8/532
Software
On-chip ROM
On-chip RAM
Clock
Question
1. How can you distinguish between an NMI interrupt
requested from the NMI pin and an NMI interrupt
requested by the watchdog timer (WDT)?
❍
Timers
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. When the WDT requests an NMI interrupt, it sets the
overflow bit (OVF) in the WDT timer status/control
register (TCSR) to 1. You can detect this by software.
Other Technical
Documentation
Document Name:
OVF Bit in TCSR
NMI requested by input signal from pin
NMI requested by WDT
0
1
Related Microcomputer
Technical Q&A
Title:
Additional Information
When the WDT is used in interval timer mode, IRQ interrupts can be discriminated in the same
0
way. (H8/520, H8/532)
13
Technical Question and Answer
Product
Topic
H8/500
Q&A No. QA500 - 018B
Input/output designation of SCI clock pin
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. When the SCI is used, is the serial clock pin designated for
input or output by writing a 0 or 1 in the data direction
register (DDR) of the corresponding port?
Timers
❍
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. When you use the SCI, the input or output setting of the
clock line depends on the communication mode bit (C/A.)
in the serial mode register (SMR) and the clock enable 1
and 0 bits (CKE1 and CKE0) in the serial control register
(SCR). You don’t have to set the DDR.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
14
Technical Question and Answer
Product
Topic
H8/500
Serial I/O line status
Q&A No. QA500 - 019B
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Timers
Serial I/O
A/D
Question
1. After input/output ports multiplexed with TxD, RxD, and
SCK lines have been used for serial communication,
suppose they are redesignated as I/O ports by settings
made in the serial control register (SCR) or serial mode
register (SMR).
❍
PWM
DTC
I/O ports
What values will the corresponding data direction register
(DDR) contain?
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. SCI operations do not affect the contents of the DDR bits
of input/output ports. Given the conditions you describe,
the DDR bits will retain the values they had before the pins
were used for serial communication.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
15
Technical Question and Answer
Product
Topic
H8/500
RDRF bit set timing
Q&A No. QA500 - 021B – 1
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. When data reception is completed, the receive data register
full bit (RDRF) in the serial status register (SSR) is set to
1. At what timing does this occur in asynchronous mode?
Timers
2. At what timing does this occur in clocked synchronous
mode?
❍
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
See the next page.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
16
Technical Question and Answer
Product
Topic
H8/500
RDRF bit set timing
Q&A No. QA500 - 021B – 2
Answer
1. The RDRF bit is set to 1 after the fall of the next data sampling clock after the MSB of the
data is received. (See the diagram below.)
1 2 3 4 5 6 7 8 9 10 111213 14 15 16 1 2 3 4 5 6 7 8 9 10 111213 14 15 16
Basic clock
Receive data
Data sampling
D7
STOP
0.5 to 1.5ø
RDRF
8-Bit Data, 1 Stop Bit, Internal Clock
2. The RDRF bit is set to 1 after the rising edge of the serial clock cycle in which the MSB of
the data is received. (See the diagram below.)
Serial clock
Receive data
Bit 6
Bit 7
0.5 to 1.5ø
RDRF
8-Bit Data
17
Technical Question and Answer
Product
Topic
H8/500
TDRE bit set timing
Q&A No. QA500 - 022B – 1
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. When eight data bits have been transmitted, the transmit
data register empty bit (TDRE) in the serial status register
(SSR) is set to 1. At what timing does this occur in
asynchronous mode?
Timers
❍
Serial I/O
A/D
PWM
DTC
2. At what timing does this occur in clocked synchronous
mode?
I/O ports
Power-down modes
Elec. characteristics
Exception handling
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Answer
Related Manuals
Manual Title:
The TDRE bit is set to 1 at different times depending on
whether the transmit shift register (TSR) contains transmit data
or not.
1. Asynchronous mode
Other Technical
Documentation
Document Name:
1.1 Transmit data present in TSR (see diagram below)
1
2 3 4 5 6 7 8 9 10 111213 14 15 16 1 2 3 4 5 6 7 8 9 10 111213 14 15 16
Basic clock
Related Microcomputer
Technical Q&A
Title:
Receive data
TDRE
Stop bit
Start bit
0.5 to 1.5ø
The timing of the start of transmission after the transmit
enable bit (TE) is set is similar.
Additional Information
Continued on next page.
18
Technical Question and Answer
Product
Topic
H8/500
TDRE bit set timing
Q&A No. QA500 - 022B – 2
Answer
1.2 No transmit data in TSR (see diagram below)
T1
T2
T3
ø
Internal
write signal
8 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516
Basic clock
TDRE
0.5ø
1.5ø
TDRE is set in interval from 8 basic clocks + 0.5ø to 24 basic clocks + 1.5ø
2. Clocked synchronous mode
2.1 Transmit data present in TSR (see diagram below)
Serial clock
Transmit data
Bit 6
Bit 7
0.5 to 1.5ø
TDRE
2.2 No transmit data in TSR (see diagram below)
T1
T2
T3
ø
Internal write signal
TDRE
TDRE is set in interval from 2ø to 0.5 basic clock + 1.5ø
19
Technical Question and Answer
Product
Topic
H8/500
Q&A No. QA500 - 023B
RDR and DTR utilization when SCI is not used
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Timers
Serial I/O
A/D
Question
1. When the serial communication interface is not used, can
the following be utilized as data registers?
(1) RDR (receive data register)
(2) TDR (transmit data register)
❍
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
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Answer
Related Manuals
Manual Title:
1. The answer is as follows:
(1) RDR is a read-only register, so it cannot be used as a
data register.
Other Technical
Documentation
(2) TDR can be used as a data register.
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
20
Technical Question and Answer
Product
Topic
H8/500
RDRF bit in SCI
Q&A No. QA500 - 049A
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. To receive serial data, the receive data register full bit
(RDRF) in the serial status register (SSR) must be cleared
to 0. What happens if 0 is written in the bit directly,
without first reading 1?
Timers
❍
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
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Answer
Related Manuals
Manual Title:
1. The RDRF bit retains its 1 value and is not cleared to 0. An
overrun error occurs at completion of receiving the next
data.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
Similar considerations apply to the transmit data register empty bit (TDRE).
21
Technical Question and Answer
Product
Topic
H8/500
SCI receive error 1
Q&A No. QA500 - 050A
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Timers
Serial I/O
A/D
Question
1. If the receive-error interrupt handler returns to the main
program without clearing the overrun flag (ORER),
framing error flag (FER), or parity error flag (PER) in the
serial status register (SSR) to 0, will a receive error occur
again?
❍
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. After one more instruction is executed in the main program
the receive error will occur again, because the error flag
itself is the interrupt source.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
This holds for all on-chip supporting modules, excluding only the external interrupts.
22
Technical Question and Answer
Product
Topic
H8/500
Q&A No. QA500 - 051A
SCI receive error 2 (clocked synchronous mode)
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. When the SCI is used in clocked synchronous mode, at
what time is an overrun error detected?
Timers
❍
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
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Miscellaneous
Answer
Related Manuals
Manual Title:
1. The overrun error bit (ORER) is set to 1 after the rise of
the serial clock when the most significant data bit (bit 7) is
received.
Other Technical
Documentation
Serial clock
Document Name:
Receive data
ORER
Bit 6
Bit 7
Related Microcomputer
Technical Q&A
Title:
0.5 to 1.5ø
Reception of 8-Bit Data
Additional Information
23
Technical Question and Answer
Product
Topic
H8/500
Q&A No. QA500 - 052A
SCI RxD input example (asynchronous mode)
Classification—H8/532
Software
On-chip ROM
On-chip RAM
Clock
Question
1. Suppose the RxD pin is being used as an input port and is
now low. Do any precautions have to be taken in order to
switch this pin over to its RxD function and receive serial
data correctly?
Timers
❍
Serial I/O
A/D
PWM
DTC
2. Do any precautions have to be taken in order to receive
data correctly after detecting the break condition?
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
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Miscellaneous
Answer
Related Manuals
Manual Title:
1. Change the RxD input to high before setting the SCI’s
receive enable bit (RE) to 1.
2. Before reception of the first data, supply high input to the
RxD line for at least one frame.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
24
Technical Question and Answer
Product
Topic
H8/500
Q&A No. QA500 - 053A
SCI transmit start (asynchronous mode)
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Timers
Serial I/O
A/D
PWM
Question
1. In the SCI transmitting sequence, following the transfer of
data from TDR to TSR, the transmit data register empty bit
(TDRE) in the serial status register (SSR) is set to 1, then
the SCI starts transmitting data. How much delay is there
from the time when the TDRE bit is set to 1 until output of
the start bit?
❍
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. The delay time is eight basic clock cycles (0.5ø to 1.5ø).
See the diagram below.
1 2 3 4 5 6 7 8 9 10111213141516 1 2 3 4 5 6 7 8 9 10111213141516
Other Technical
Documentation
Basic clock
Document Name:
0.5 to 1.5ø
TDRE
Transmit
data
Stop bit
Start bit
Related Microcomputer
Technical Q&A
8 basic clock cycles (0.5ø to 1.5ø)
Title:
Additional Information
The same timing applies when transmission starts from the setting of the transmit enable bit (TE).
25
Technical Question and Answer
Product
Topic
H8/500
Q&A No. QA500 - 054A
Simultaneous transmit/receive in clocked synchronous mode
Classification—H8/500
Question
Software
1. During simultaneous transmitting and receiving in clocked
synchronous mode, can data be transferred in the state
when an overrun error has occurred?
On-chip ROM
On-chip RAM
Clock
Timers
❍
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. Data cannot be transferred.
In simultaneous transmitting and receiving in clocked
synchronous mode, transmitting or receiving cannot
proceed independently before the ORER and TDRE bits
are both cleared to 0.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
26
Technical Question and Answer
Product
Topic
H8/500
Clearing the SCI’s TDRE bit
Q&A No. QA500 - 055A
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. When transmitting data, will there be any data transfer
problem if we wait until after writing transmit data in the
transmit data register (TDR) to read the 1 value of the
TDRE bit, then clear this bit to 0?
Timers
❍
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
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Answer
Related Manuals
Manual Title:
1. No problem will occur.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
If you write in TDR while the TDRE bit is 0, however, you will destroy the previous TDR data.
27
Technical Question and Answer
Product
Topic
H8/500
Start of A/D conversion
Q&A No. QA500 - 024B
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. Software can select the start of A/D conversion by setting
the A/D start bit (ADST) in the A/D control/status register
(ADCSR) to 1. What happens if 1 is written in the ADST
bit again while A/D conversion is in progress?
Timers
Serial I/O
❍
A/D
PWM
DTC
I/O ports
2. What happens if A/D conversion starts by detection of the
falling edge of the external trigger signal (ADTRG), then
ADTRG goes high while A/D conversion is in progress?
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
(H8/510, H8/520, H8/534, H8/536)
Answer
Related Manuals
Manual Title:
1. If the ADST bit is set to 1 again during A/D conversion, it
will be ignored and A/D conversion will continue.
2. Operation will be normal if the ADTRG signal is low for at
least 1.5 cycles. After that, if the ADTRG signal goes high
again during A/D conversion, it will be ignored and A/D
conversion will continue.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
28
Technical Question and Answer
Product H8/500
Q&A No. QA500 - 025B
Topic
Non-use of A/D converter reference voltage lines (AVCC, AVSS
)
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. When the A/D converter is not used, what should be done
with the AV and AV pins?
CC
SS
Timers
Serial I/O
❍
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. Even when the A/D converter is not used, AV should be
CC
connected to V and AV to V .
SS
CC
SS
10 bit D/A
(Reference)
AVCC
AVCC
Comparator
Other Technical
Documentation
Document Name:
AVSS
VSS
AVSS
Related Microcomputer
Technical Q&A
(1) If AV is left open, voltage potentials in the interface to
CC
the digital circuits in the A/D converter will be unstable.
Title:
(2) AV and V are shorted inside the chip. Any potential
SS
SS
difference between them will cause excessive current
drain.
Additional Information
29
Technical Question and Answer
Product
Topic
H8/500
Q&A No. QA500 - 027B
Changing A/D conversion mode or channels during conversion
Classification—H8/500
Question
Software
During A/D conversion, what happens if you:
On-chip ROM
On-chip RAM
Clock
Timers
Serial I/O
1. Change the A/D conversion mode?
2. Change the channel selection?
❍
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. Avoid changing the A/D conversion mode during A/D
conversion. Conversion accuracy will be degraded.
2. Avoid changing the channel selection during A/D
conversion. The same problem will occur as in 1.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
Note: Check the A/D end flag (ADF) in the A/D control/status register (ADCSR), then:
1. Change the A/D conversion mode.
2. Select the channel(s).
30
Technical Question and Answer
Product
Topic
H8/500
Resistor ladder in A/D converter
Q&A No. QA500 - 028B
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. Are the analog power supplies of the A/D converter
connected only to the resistor ladder?
Timers
Serial I/O
❍
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. The analog power supplies are connected not only to the
resistor ladder but also to analog circuits in the comparator
etc. They also power the interface to digital circuits in the
A/D converter.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
31
Technical Question and Answer
Product
Topic
H8/500
Q&A No. QA500 - 029B
Rise time of power supplies (AVCC, VCC
)
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. Will any problems occur if there is a difference in rise
times between the analog power supply (AV ) and digital
power supply (V )?
CC
CC
Timers
Serial I/O
❍
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. There is no restriction on the order in which AV and
CC
V
are powered up.
CC
During the interval marked A in the diagram below,
voltage potentials in the interface to digital circuits in the
A/D converter are unstable, which may cause fluctuations
in current drain.
Other Technical
Documentation
Document Name:
A
Related Microcomputer
Technical Q&A
VCC
Title:
AVCC
Additional Information
32
Technical Question and Answer
Product
Topic
H8/500
Q&A No. QA500 - 056A
Allowable impedance of A/D signal sources
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. Does the allowable signal source impedance remain 10 kΩ
even if the A/D conversion time is changed?
Timers
Serial I/O
❍
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. The low-speed conversion mode should operate even at
20 kΩ, but this is not guaranteed.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
33
Technical Question and Answer
Product
Topic
H8/532, H8/534, H8/536
DTR of PWM timer
Q&A No. QA500 - 031B
Classification—H8/532
Software
On-chip ROM
On-chip RAM
Clock
Question
1. The duty register (DTR) of the PWM timer is set to H'00
for pulses with 0% duty cycle, H'7D for pulses with 50%
duty cycle, and H'FA for pulses with 100% duty cycle, but
what if a value from H'FB to H'FF is written in DTR?
Timers
Serial I/O
A/D
❍
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. If a value from H'FB to H'FF is written in DTR, pulses are
output with a 100% duty cycle.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
34
Technical Question and Answer
Product
Topic
H8/534, H8/536
PWM pin assignments
Q&A No. QA500 - 057A
Classification—H8/534
Software
On-chip ROM
On-chip RAM
Clock
Question
1. The PWM timer outputs (PW to PW ) are can be assigned
1
3
to P6 to P6 (multiplexed with IRQ to IRQ ) or P9 to
1
3
3
5
2
P9 (multiplexed with SCK , RxD , and TxD ). Can all six
4
2
2
2
Timers
pins be used for PWM output?
Serial I/O
A/D
❍
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. Yes, they can.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
P6 to P6 can be used for both PWM output and IRQ input. P9 to P9 can be used for either
1
3
2
4
PWM output or SCI functions, but not both.
35
Technical Question and Answer
Product
Topic
H8/500
Interrupts during DTC operation
Q&A No. QA500 - 032B
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. During operation of the data transfer controller (DTC),
what happens if an interrupt is requested with a priority
higher than the interrupt the DTC is serving?
Timers
Serial I/O
A/D
PWM
❍
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. While the DTC is operating the CPU halts, so no other
interrupts can be accepted.
The DTC therefore completes its interrupt service, after
which one instruction is executed; then the pending
interrupt-handling sequence begins.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
If the instruction executed after the conclusion of DTC operations is LDC or another instruction
that inhibits interrupts, the interrupt-handling sequence will not start until the next instruction
after that has been executed (and if that next instruction also inhibits interrupts, another
instruction will be executed).
36
Technical Question and Answer
Product
Topic
H8/500
DTC usage
Q&A No. QA500 - 033B
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. Can DTC register information be located on ROM?
2. After a DTC data transfer, the data transfer count register
(DTCR) is decremented by 1, and if the result is 0, the
DTC will no longer be activated. If DTC register
Timers
Serial I/O
A/D
PWM
DTC
information is stored on ROM with the DTCR value set to
1, will an interrupt occur after the DTC data transfer?
❍
I/O ports
Power-down modes
Elec. characteristics
Exception handling
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. DTC register information can be located on ROM.
2. An interrupt will be generated. The decision as to whether
DTCR = 0 is made when the DTCR value is decremented.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
37
Technical Question and Answer
Product
Topic
H8/500
Q&A No. QA500 - 035B
Analog input port data register during A/D conversion
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. During A/D conversion, what happens to the values in the
data register (DR) of the input port that is also used for
analog input?
Timers
Serial I/O
A/D
PWM
DTC
❍
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. Pins used for analog input return the value 1 if read during
A/D conversion, regardless of the actual input voltage.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
38
Technical Question and Answer
Product
Topic
H8/500
Port output after reset
Q&A No. QA500 - 037B
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. To use an input/output port line to output data after a reset,
which should be set first: the port’s data register (DR) or its
data direction register (DDR)?
Timers
Serial I/O
A/D
PWM
DTC
❍
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. Set these registers in the following order.
(1) Set the output data in the output port’s data register.
(2) Set the DDR bit of the output line to 1.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
Note: A reset initializes the port data registers to 0.
39
Technical Question and Answer
Product
Topic
H8/500
AS and RD signal timing
Q&A No. QA500 - 039B
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. Are the AS and RD signals synchronized with the falling
edge of the system clock (ø), or with output on the address
lines?
Timers
Serial I/O
A/D
PWM
DTC
❍
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. The AS and RD signals are synchronized with the falling
edge of the system clock in the T state.
1
The AS and RD signals never go low before the falling
Other Technical
Documentation
Document Name:
edge in the T state. Case A in the diagram below cannot
1
occur.
T1
T2
T3
ø
tAD
Related Microcomputer
Technical Q&A
A0 to A15
Title:
tDSD1
tAS1
AS, RD
Case A
Additional Information
40
Technical Question and Answer
Product
Topic
H8/500
Unused I/O lines
Q&A No. QA500 - 040B
Classification—H8/500
Software
On-chip ROM
On-chip RAM
Clock
Question
1. What should be done with unused I/O port lines?
Timers
Serial I/O
A/D
PWM
DTC
❍
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. (1) Pull unused input/output port lines up or down
through an approximately 10-kΩ resistor.
(2) Do the same for input-only port lines.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
Connect a separate pull-up or pull-down resistor to each line.
41
Technical Question and Answer
Product
Topic
H8/520, 532, 534, 536
Q&A No. QA500 - 041B
Power dissipation in hardware and software standby modes
Classification—H8/532
Software
On-chip ROM
On-chip RAM
Clock
Question
1. Is there any difference in current dissipation between
hardware standby and software standby?
Timers
Serial I/O
A/D
PWM
DTC
I/O ports
❍
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
Answer
Related Manuals
Manual Title:
1. Current dissipation satisfies the relationship:
hardware standby ≤ software standby.
Other Technical
Documentation
Document Name:
In hardware standby mode, all lines are placed in the high-
impedance state, which reduces current dissipation. In
software standby mode I/O ports hold their previous states,
so current dissipation varies depending on the state of the
port.
Related Microcomputer
Technical Q&A
Title:
Additional Information
42
Technical Question and Answer
Product
Topic
H8/510
Q&A No. QA500 - 058A
State of D0 to D7 with 8-bit data bus
Classification—H8/510
Software
On-chip ROM
On-chip RAM
Clock
Question
1. In 16-bit data bus mode (mode 2 or 4), during access to the
area accessed via an eight-bit bus, what are the states of the
unused data bus lines (D to D ) and control signals?
0
7
Timers
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
Development tools
Bus controller
Miscellaneous
❍
Answer
Related Manuals
Manual Title:
1. D to D are in the high-impedance state, and LWR is
0
7
always 1.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
43
Technical Question and Answer
Product
Topic
H8/510
Q&A No. QA500 - 059A
State of D0 to D7 during byte access in 16-bit data bus mode
Classification—H8/500
Question
Software
1. What are the pin states during access to byte data in 16-bit
data bus mode (mode 2 or 4)?
On-chip ROM
On-chip RAM
Clock
Timers
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
❍
Answer
Related Manuals
Manual Title:
1. (1) In write access, the upper data bus (D to D ) and
15
8
lower data bus (D to D ) both output the same data.
7
0
Control signal states are as follows:
Other Technical
Documentation
Document Name:
Access to even address
LWR = 1
Access to odd address
LWR = 0
HWR = 1
HWR = 0
(2) In read access, the states differ depending on the
external circuit configuration.
Related Microcomputer
Technical Q&A
Title:
Control signal states are as follows:
RD = 0
Additional Information
1. The minimum RAM standby voltage (VRAM) is specified at 2.0 V. What voltage should be
supplied to AV
?
CC
44
Technical Question and Answer
Product
Topic
H8/520, 532, 534, 536
RAM standby voltage
Q&A No. QA500 - 060A
Classification—H8/532
Software
Question
On-chip ROM
On-chip RAM
Clock
Timers
Serial I/O
A/D
PWM
DTC
I/O ports
Power-down modes
Elec. characteristics
Exception handling
Bus interface
External expansion
Development tools
Miscellaneous
❍
Answer
Related Manuals
Manual Title:
1. AV should be the same as the RAM standby voltage:
CC
2 V. Setting AV to 5 V or VSS will cause excessive
CC
current drain.
Other Technical
Documentation
Document Name:
Related Microcomputer
Technical Q&A
Title:
Additional Information
45
相关型号：
HD6435378
Description Notes on Using LAN Adapter for E6000/E8000 Emulator (HS6000ELN01H) User＇s Manual/Emulator
ETC
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