HD74LV74ARP [ETC]

FLIP-FLOP|DUAL|D TYPE|LV-CMOS|SOP|14PIN|PLASTIC ; 触发器|双| D型| LV- CMOS |专科| 14PIN |塑料\n


型号：	HD74LV74ARP
厂家：	ETC
描述：	FLIP-FLOP\|DUAL\|D TYPE\|LV-CMOS\|SOP\|14PIN\|PLASTIC 触发器\|双\| D型\| LV- CMOS \|专科\| 14PIN \|塑料\n 触发器逻辑集成电路光电二极管
文件：	总11页 (文件大小：364K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HD74LV74A

Dual D–type Flip Flops with Preset and Clear

ADE-205-244 (Z)

1st Edition

March 1999

Description

The HD74LV74A has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package.

The input data is transferred to the output at the rising edge of clock pulse CLK. Low-voltage and high-speed

operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power con-

sumption extends the battery life.

Features

•

V_CC= 2.0 V to 5.5 V operation

All inputs V_IH(Max.) = 5.5 V (@V_CC= 0 V to 5.5 V)

All outputs V_O(Max.) = 5.5 V (@V_CC= 0 V)

Typical V_OLground bounce < 0.8 V (@V_CC= 3.3 V, Ta = 25°C)

Typical V_OHundershoot > 2.3 V (@V_CC= 3.3 V, Ta = 25°C)

Output current ±6 mA (@V_CC= 3.0 V to 3.6 V), ±12 mA (@V_CC= 4.5 V to 5.5 V)

Function Table

Inputs

Outputs

PRE

CLR

CLK

H*¹

↑

↓

Q₀

Note: H:High level

L:Low level

X:Immaterial

↑:Low to high transition

↓:High to low transition

Q₀:The level of Q immediately before the input conditions shown in the above table are determined.

1.:Q and Q will remain HIGH as long as Preset and Clear are Low, but Q and Q are unpredictable, if

Preset and Clear go HIGH simultaneously.

HD74LV74A

Pin Arrangement

14 V_CC

1CLR

13 2CLR

1CLK

1PRE

2CLK

2PRE

GND

(Top view)

Absolute Maximum Ratings

Item

Symbol

V_CC

V_I

Ratings

–0.5 to 7.0

–0.5 to V_CC+ 0.5

–0.5 to 7.0

–20

Unit

Conditions

Supply voltage range

Input voltage range*¹

Output voltage range*^{1, 2}

V_O

Output: H or L

V_CC: OFF

Input clamp current

I_IK

I_OK

I_O

V_I< 0

Output clamp current

Continuous output current

±50

V_O< 0 or V_O> V_CC

V_O= 0 to V_CC

±25

Continuous current through

V_CCor GND

_CCor I_GND

±50

Maximum powerdissipation at P_T

785

500

SOP

Ta = 25°C (in still air)*³

TSSOP

Storage temperature

Tstg

–65 to 150

°C

Notes:The absolute maximum ratings are values which must not individually be exceeded, and furthermore,

no two of which may be realized at the same time.

1.The input and output voltage ratings may be exceeded if the input and output clamp-current

ratings are observed.

2.This value is limited to 5.5 V maximum.

3.The maximum package power dissipation was calculated using a junction temperature of 150°C.

HD74LV74A

Recommended Operating Conditions

Item

Symbol

V_CC

V_I

Min

2.0

Max

5.5

V_CC

–50

–2

Unit

Conditions

Supply voltage range

Input voltage range

Output voltage range

Output current

V_O

I_OH

—

µA

V_CC= 2.0 V

_CC= 2.3 to 2.7 V

–6

V_CC= 3.0 to 3.6 V

V_CC= 4.5 to 5.5 V

V_CC= 2.0 V

–12

I_OL

µA

V_CC= 2.3 to 2.7 V

V_CC= 3.0 to 3.6 V

V_CC= 4.5 to 5.5 V

Input transition rise or fall rate ∆t /∆v

200

100

ns/V

V_CC= 2.3 to 2.7 V

V_CC= 3.0 to 3.6 V

V_CC= 4.5 to 5.5 V

Operating free-air temperature Ta

–40

°C

Note: Unused or floating inputs must be held high or low.

Logic Diagram

PRE

CLK

CLR

DC Electrical Characteristics

•

Ta = –40 to 85°C

•

Item

Symbol

_CC(V)* Min

Typ

—

Max

—

Unit Test Conditions

Input voltage V_IH

2.0 1.5

2.3 to 2.7 V_CC× 0.8

3.0 to 3.6 V_CC× 0.8

—

HD74LV74A

Item

Symbol V_CC(V)* Min

4.5 to 5.5 V_CC× 0.8

2.0

Typ

—

Max

—

Unit Test Conditions

V_IL

—

0.3

2.3 to 2.7 —

3.0 to 3.6 —

4.5 to 5.5 —

—

_CC× 0.2

—

_CC× 0.2

—

Output

voltage

V_OH

Min to

Max

V_CC– 0.1

—

I_OL= –50 µA

2.3

3.0

4.5

2.0

2.48

3.8

—

0.1

I_OL= –2 mA

I_OL= –6 mA

_OL= –12 mA

V_OL

Min to

Max

I_OL= 50 µA

2.3

—

0.4

0.44

0.55

±1

I_OL= 2 mA

3.0

I_OL= 6 mA

4.5

I_OL= 12 mA

Input current I_IN

0 to 5.5

5.5

µA

V_IN= 5.5 V or GND

V_IN= V_CCor GND, I_O= 0

Quiescent

supply

I_CC

current

Output

leakage

current

I_OFF

—

µA

V_O= 5.5 V

Input

C_IN

3.3

2.0

—

V_I= V_CCor GND

capacitance

•

Note:For conditions shown as Min or Max, use the appropriate values under recommended operating

conditions.

Switching Characteristics

•

V_CC= 2.5 ± 0.2 V

Ta = 25°C

Ta = –40 to 85°C

FROM (In- TO (Out-

Item

Symbol Min Typ Max Min

Max

—

Unit Test Conditions put)

put)

Maximum

clock

frequency

t_max

100

—

MHz C_L= 15 pF

C_L= 50 pF

—

Propagation t_PLH

delay time t_PHL

—

9.8

14.8 1.0

17.0

19.0

20.0

23.0

C_L= 15 pF

C_L= 50 pF

PRE/CLR Q or Q

CLK

11.1 16.4 1.0

13.0 17.4 1.0

14.2 20.0 1.0

PRE/CLR Q or Q

CLK

Setup time t_su

8.0

7.0

—

9.0

7.0

—

Data

PRE or CLR inactive

HD74LV74A

Ta = 25°C

Ta = –40 to 85°C

FROM (In- TO (Out-

Item

Symbol Min Typ Max Min

Max

—

Unit Test Conditions put)

put)

Hold time

t_h

0.5

8.0

—

0.5

9.0

Pulse width t_w

—

PRE or CLR “L”

CLK “H” or “L”

—

Switching Characteristics (cont)

•

V_CC= 3.3 ± 0.3 V

Ta = 25°C

Ta = –40 to 85°C

FRO

M (In- TO (Out-

Item

Symbol Min Typ Max Min

Max

—

Unit

Test Conditions put) put)

Maximum

clock

frequency

t_max

140

—

MHz

C_L= 15 pF

C_L= 50 pF

—

Propagation t_PLH

delay time t_PHL

—

6.9

12.3 1.0

14.5

C_L= 15 pF

C_L= 50 pF

PRE/ Q or Q

CLR

—

7.9

9.2

11.9 1.0

15.8 1.0

14.0

18.0

CLK

PRE/ Q or Q

CLR

—

10.2 15.4 1.0

17.5

CLK

Data

Setup time t_su

6.0

5.0

—

7.0

5.0

—

PRE or CLR

inactive

Hold time

t_h

0.5

6.0

—

0.5

7.0

—

Pulse width t_w

PRE or CLR “L”

CLK “H” or “L”

Switching Characteristics (cont)

•

V_CC= 5.0 ± 0.5 V

Ta = 25°C

Ta = –40 to 85°C

FRO

M (In- TO (Out-

Item

Symbol Min Typ Max Min

Max

—

Unit

Test Conditions put) put)

Maximum

clock

frequency

t_max

130 180

—

110

MHz

C_L= 15 pF

140

—

C_L= 50 pF

Propagation t_PLH

delay time t_PHL

—

5.0

5.6

7.7

7.3

1.0

9.0

8.5

C_L= 15 pF

PRE/ Q or Q

CLR

CLK

HD74LV74A

Ta = 25°C

Ta = –40 to 85°C

FRO

M (In- TO (Out-

Item

Symbol Min Typ Max Min

Max

Unit

Test Conditions put) put)

—

6.6

9.7

1.0

11.0

C_L= 50 pF

PRE/ Q or Q

CLR

—

7.2

—

9.3

—

1.0

5.0

3.0

0.5

10.5

—

CLK

Data

Setup time t_su

5.0

3.0

0.5

—

PRE or CLR

inactive

Hold time

t_h

—

Pulse width t_w

5.0

—

5.0

—

PRE or CLR “L”

CLK “H” or “L”

Operating Characteristics

•

C_L= 50 pF

•

Ta = 25°C

Item

Symbol

_CC(V)

Min

—

Typ

21.0

23.0

Max

Unit

Test Conditions

Power

dissipation

capacitance

C_PD

3.3

5.0

—

f = 10 MHz

—

Noise Characteristics

•

C_L= 50 pF

Ta = 25°C

Min

Item

Symbol V_CC(V)

Typ

Max

Unit

Test Conditions

Quiet output, V_{OL (P)}

maximum

dynamic V_OL

3.3

—

0.1

0.8

Quiet output, V_{OL (V)}

minimum

dynamic V_OL

—

–0.8

—

Quiet output, V_{OH (V)}

minimum

dynamic V_OH

—

3.2

—

High-level

dynamicinput

voltage

V_{IH (D)}

2.31

—

Low-level

dynamicinout

voltage

V_{IL (D)}

0.99

HD74LV74A

Test Circuit

Measurement point

C _L

Note: C_Lincludes the probe and jig capacitance.

HD74LV74A

• Waveform – 1

Timming input

t_r

t_f

V_CC

0 V

V_CC

0 V

90%

50% VCC

90%

50% VCC

10%

t_su

10%

t_h

Data input

50% VCC

t_w

V_CC

0 V

Input

50% VCC

• Waveform – 2

Input

t_r

t_f

V_CC

0 V

90%

50% VCC

90%

50% VCC

10%

t_PHL

t_PLH

V_OH

Same-phase output

50% VCC

t_PLH

V_OL

t_PHL

V_OH

50% VCC

Opposite-phase output

V_OL

Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t_r≤ 3 ns, t_f≤ 3 ns

2. The output are measured one at a time with one transition per measurement.

HD74LV74A

Package Dimensions

Unit: mm

10.06

10.5 Max

+ 0.20

7.80

– 0.30

1.42 Max

1.15

0° – 8°

1.27

0.70 ± 0.20

0.42 ± 0.08

0.40 ± 0.06

0.15

0.12

Hitachi Code

JEDEC

FP-14DA

—

EIAJ

Conforms

Dimension including the plating thickness

Base material dimension

Weight (reference value) 0.23 g

Unit: mm

8.65

9.05 Max

+ 0.10

6.10

– 0.30

0.635 Max

1.08

0° – 8°

+ 0.67

1.27

0.60

– 0.20

*0.42 ± 0.08

0.40 ± 0.06

0.15

0.25

Hitachi Code

JEDEC

EIAJ

FP-14DN

Conforms

*Dimension including the plating thickness

Base material dimension

Weight (reference value) 0.13 g

HD74LV74A

Unit: mm

5.00

5.30 Max

0.65

1.0

+0.08

–0.07

0.22

0.13 M

0.20 ± 0.06

6.40 ± 0.20

0.83 Max

0° – 8°

0.50 ± 0.10

0.10

Hitachi Code

JEDEC

EIAJ

TTP-14D

—

Dimension including the plating thickness

Base material dimension

Weight (reference value) 0.05 g

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copy-

right, trademark, or other intellectual property rights for information contained in this document. Hitachi

bears no responsibility for problems that may arise with third party’s rights, including intellectual property

rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have re-

ceived the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, con-

tact Hitachi’s sales office before using the product in an application that demands especially high quality

and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily

injury, such as in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety

equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions

and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the

guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or fail-

ure modes in semiconductor devices and employ systemic measures such as fail-safe devices, so that the

equipment incorporating the Hitachi product does not cause bodily injury, fire or other consequential

damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor prod-

ucts.

HD74LV74A

Hitachi, Ltd.

Semiconductor & IC Div.

Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan

Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109

URL

NorthAmerica

Europe

: http:semiconductor.hitachi.com/

: http://www.hitachi-eu.com/hel/ecg

Asia (Singapore)

Asia (Taiwan)

: http://www.has.hitachi.com.sg/grp3/sicd/index.htm

: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm

Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm

Japan

: http://www.hitachi.co.jp/Sicd/indx.htm

For further information write to:

Hitachi Semiconductor

(America) Inc.

Hitachi Europe GmbH

Hitachi Asia (Hong Kong) Ltd.

Hitachi Asia Pte. Ltd.

16 Collyer Quay #20-00

Hitachi Tower

Singapore 049318

Tel: 535-2100

Electronic components Group

Dornacher Straße 3

D-85622 Feldkirchen, Munich

Germany

Tel: <49> (89) 9 9180-0

Fax: <49> (89) 9 29 30 00

Group III (Electronic Components)

7/F., North Tower, World Finance Centre,

Harbour City, Canton Road, Tsim Sha Tsui,

Kowloon, Hong Kong

Tel: <852> (2) 735 9218

Fax: <852> (2) 730 0281

179 East Tasman Drive,

San Jose,CA 95134

Tel: <1> (408) 433-1990

Fax: <1>(408) 433-0223

Fax: 535-1533

Hitachi Asia Ltd.

Taipei Branch Office

3F, Hung Kuo Building. No.167,

Tun-Hwa North Road, Taipei (105)

Tel: <886> (2) 2718-3666

Fax: <886> (2) 2718-8180

Telex: 40815 HITEC HX

Hitachi Europe Ltd.

Electronic Components Group.

Whitebrook Park

Lower Cookham Road

Maidenhead

Berkshire SL6 8YA, United Kingdom

Tel: <44> (1628) 585000

Fax: <44> (1628) 778322

HD74LV74ARP [ETC]

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