HDE74ALVC16836 [ETC]
;
| 型号： | HDE74ALVC16836 |
| 厂家： | 
ETC |
| 描述： |
|
| 文件： | 总13页 (文件大小：55K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HD74ALVC16836
20-bit Universal Bus Driver with 3-state Outputs
ADE-205-209 (Z)
Preliminary
1st. Edition
January 1998
Description
This 20-bit universal bus driver is designed for 2.3 V to 3.6 V VCC operation.
Data flow from A to Y is controlled by the output enable (OE) input. The device operates in the
transparent mode when the latch enable (LE) input is low. When LE is high, the A data is latched if the
clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch flip
flop on the low to high transition of CLK. When OE is high, the outputs are in the high impedance state.
To ensure the high impedance state during power up or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the
driver.
Features
•
•
•
•
VCC = 2.3 V to 3.6 V
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High output current ±24 mA (@VCC = 3.0 V)
HD74ALVC16836
Function Table
Inputs
Output Y
OE
H
L
LE
X
CLK
X
A
X
L
Z
L
L
X
L
L
X
H
L
H
L
L
H
H
H
H
↑
L
↑
H
X
X
H
*1
L
H
L
Y0
*2
L
Y0
H : High level
L : Low level
X : Immaterial
Z : High impedance
↑ : Low to high transition
Notes: 1. Output level before the indicated steady state input conditions were established, provided that
CLK is high before LE goes low.
2. Output level before the indicated steady state input conditions were established.
2
HD74ALVC16836
Pin Arrangement
CLK
OE 1
56
Y1 2
55 A1
54
53
52
51
50
A2
Y2
GND
Y3
3
4
GND
A3
5
6
A4
Y4
7
VCC
VCC
8
Y5
Y6
49 A5
A6
9
48
47
46
10
11
12
Y7
A7
GND
GND
Y8
45 A8
A9
44
43
42
Y9 13
Y10 14
A10
A11
Y11
Y12
Y13
15
41 A12
A13
16
17
40
39 GND
38 A14
37 A15
GND
Y14
18
19
20
Y15
Y16 21
A16
VCC
A17
A18
GND
A19
A20
LE
36
35
34
33
32
31
30
29
VCC
Y17
Y18
GND
Y19
Y20
NC
22
23
24
25
26
27
28
(Top view)
3
HD74ALVC16836
Absolute Maximum Ratings
Item
Symbol
Ratings
–0.5 to 4.6
–0.5 to 4.6
–0.5 to VCC +0.5
–50
Unit
V
Conditions
Supply voltage
Input voltage *1
VCC
VI
V
Output voltage *1, 2
Input clamp current
Output clamp current
Continuous output current
VCC, GND current / pin
VO
V
IIK
mA
mA
mA
mA
W
VI < 0
IOK
±50
VO < 0 or VO > VCC
VO = 0 to VCC
IO
±50
ICC or IGND
PT
±100
Maximum power dissipation
1
TSSOP
at Ta = 55°C (in still air) *3
Storage temperature
Tstg
–65 to 150
°C
Notes:
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Symbol
VCC
Min
2.3
0
Max
3.6
VCC
VCC
–12
–12
–24
12
Unit
V
Conditions
Supply voltage
Input voltage
VI
V
Output voltage
High level output current
VO
0
V
IOH
—
—
—
—
—
—
0
mA
VCC = 2.3 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3.0 V
Low level output current
IOL
mA
12
24
Input transition rise or fall rate
Operating temperature
∆t / ∆v
10
ns / V
Ta
–40
85
°C
Note: Unused control inputs must be held high or low to prevent them from floating.
4
HD74ALVC16836
Logic Diagram
1
56
29
55
OE
CLK
LE
1D
C1
A1
2
Y1
CLK
To nineteen other channels
5
HD74ALVC16836
Electrical Characteristics (Ta = –40 to 85°C)
Item
Symbol VCC (V)
Min
Max
—
Unit Test Conditions
Input voltage
VIH
2.3 to 2.7 1.7
2.7 to 3.6 2.0
V
—
VIL
2.3 to 2.7
2.7 to 3.6
—
—
0.7
0.8
—
Output voltage
VOH
2.3 to 3.6 VCC–0.2
V
IOH = –100 µA
2.3
2.0
1.7
2.2
2.4
2.0
—
—
IOH = –6 mA, VIH = 1.7 V
IOH = –12 mA, VIH = 1.7 V
IOH = –12 mA, VIH = 2.0 V
IOH = –12 mA, VIH = 2.0 V
IOH = –24 mA, VIH = 2.0 V
IOL = 100 µA
2.3
—
2.7
—
3.0
—
3.0
—
VOL
2.3 to 3.6
2.3
0.2
0.4
0.7
0.4
0.55
±5
—
IOL = 6 mA, VIL = 0.7 V
IOL = 12 mA, VIL = 0.7 V
IOL = 12 mA, VIL = 0.8 V
IOL = 24 mA, VIL = 0.8 V
VIN = VCC or GND
2.3
—
2.7
—
3.0
—
Input current
IIN
3.6
—
µA
µA
µA
µA
Off state output current
IOZ
3.6
—
±10
40
VOUT = VCC or GND
Quiescent supply current ICC
∆ICC
3.6
—
VIN = VCC or GND
3.0 to 3.6
—
750
VIN = one input at (VCC–0.6) V,
other inputs at VCC or GND
6
HD74ALVC16836
Switching Characteristics (Ta = –40 to 85°C)
Item
Symbol VCC (V) Min
Typ
Max
Unit FROM
TO
(Input)
(Output)
Maximum clock frequency fmax
2.5±0.2 150
2.7 150
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3.5
6.0
7.0
—
MHz
—
3.3±0.3 150
2.5±0.2 1.0
—
Propagation delay time
tPLH
tPHL
4.2
4.2
3.6
5.0
4.9
4.2
5.5
5.2
4.5
5.5
5.6
4.6
4.5
4.3
3.9
—
ns
A
Y
Y
Y
Y
Y
2.7
—
3.3±0.3 1.0
2.5±0.2 1.3
LE
CLK
OE
OE
2.7
—
3.3±0.3 1.3
2.5±0.2 1.4
2.7
—
3.3±0.3 1.4
2.5±0.2 1.4
Output enable time
Output disable time
tZH
tZL
ns
ns
2.7
—
3.3±0.3 1.1
2.5±0.2 1.0
tHZ
tLZ
2.7
—
3.3±0.3 1.3
Input capacitance
Output capacitance
CIN
CO
3.3
3.3
3.3
—
—
—
pF
pF
Control inputs
Data inputs
Outputs
—
—
7
HD74ALVC16836
Switching Characteristics (Ta = –40 to 85°C) (cont)
Item
Symbol VCC (V)
Min
2.5±0.2 1.4
2.7 1.7
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
FROM (Input)
Setup time
tsu
ns
Data before CLK↑
3.3±0.3 1.5
2.5±0.2 1.2
Data before LE↑
2.7
1.6
CLK “H”
3.3±0.3 1.3
2.5±0.2 1.4
Data before LE↑
2.7
1.5
CLK “L”
3.3±0.3 1.2
2.5±0.2 0.9
Hold time
th
ns
Data after CLK↑
2.7
0.9
3.3±0.3 0.9
2.5±0.2 1.1
Data after LE↑
2.7
1.1
CLK “H” or “L”
3.3±0.3 1.1
2.5±0.2 3.3
Pulse width
tw
ns
LE “L”
2.7
3.3
3.3±0.3 3.3
2.5±0.2 3.3
CLK “H” or “L”
2.7
3.3
3.3±0.3 3.3
8
HD74ALVC16836
Test Circuit
See under table
OPEN
GND
500 Ω
S1
*1
CL= 50 pF
500 Ω
Load Circuit for Outputs
Vcc=2.7V,
Vcc=2.5±0.2V
Symbol
3.3±0.3V
tPLH/ tPHL
tsu / th / tw
OPEN
OPEN
tZH/ tHZ
tZL / tLZ
GND
GND
6.0 V
2 × VCC
Note:
1. CL includes probe and jig capacitance.
9
HD74ALVC16836
Waveforms – 1
tr
tf
V
IH
90 %
Vref
90 %
Vref
Input
10 %
10 %
GND
tPHL
tPLH
VOH
Output
Vref
Vref
VOL
Waveforms – 2
tr
V
IH
90 %
Vref
Timing Input
Data Input
10 %
tsu
GND
th
V
IH
Vref
Vref
GND
tw
V
IH
Vref
Vref
Input
GND
10
HD74ALVC16836
Waveforms – 3
tf
tr
V
IH
90 %
Vref
90 %
Vref
Output
Control
10 %
tZL
10 %
GND
tLZ
≈VOH1
Vref
Waveform - A
Waveform - B
V
ref1
VOL
VOH
tZH
tHZ
V
ref2
Vref
≈VOL1
Vcc=2.7V,
Vcc=2.5±0.2V
TEST
3.3±0.3V
VIH
VCC
2.7 V
Vref
1/2 VCC
1.5 V
Vref1
Vref2
VOH1
VOL1
VOL +0.15 V VOL +0.3 V
VOH–0.15 V VOH–0.3 V
VCC
3.0 V
GND
GND
Notes:
1. All input pulses are supplied by generators having the following characteristics :
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.0 ns, tf ≤ 2.0 ns. (VCC = 2.5±0.2 V)
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. (VCC = 2.7 V, 3.3±0.3 V)
2. Waveform – A is for an output with internal conditions such that the output is low except
when disabled by the output control.
3. Waveform – B is for an output with internal conditions such that the output is high except
when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
11
HD74ALVC16836
Package Dimensions
Unit : mm
+0.3
–0.1
14.00
56
29
28
1
0.50
+0.1
–0.05
M
0.08
0.20
8.10 ± 0.3
0.40 Max
10° Max
0.50 ± 0.1
0.10
Hitachi code
EIAJ code
JEDEC code
TTP-56D
—
—
12
HD74ALVC16836
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Hitachi Europe GmbH
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 01628-585000
Fax: 01628-585160
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Tel: 415-589-8300
Fax: 415-583-4207
Tel: 089-9 91 80-0
Fax: 089-9 29 30-00
Fax: 535-1533
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Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
13
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