HM62256BLFP10 [ETC]
IC-SM-256K CMOS SRAM ; IC- SM- 256K CMOS SRAM\n
| 型号： | HM62256BLFP10 |
| 厂家： | 
ETC |
| 描述： | IC-SM-256K CMOS SRAM
|
| 文件： | 总15页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM62256B Series
32,768-word × 8-bit High Speed CMOS Static RAM
ADE-203-135D (Z)
Rev. 4.0
Nov. 29, 1995
Description
The Hitachi HM62256B is a CMOS static RAM organized 32-kword × 8-bit. It realizes higher
performance and low power consumption by employing 0.8 µm Hi-CMOS process technology. The
device, packaged in 8 × 14 mm TSOP, 8 × 13.4 mm TSOP with thickness of 1.2 mm, 450-mil SOP (foot
print pitch width), 600-mil plastic DIP, or 300-mil plastic DIP, is available for high density mounting. It
offers low power standby power dissipation; therefore, it is suitable for battery back-up systems.
Features
•
•
High speed
Fast access time: 45/55/70/85 ns (max)
Low power
Standby: 1.0 µW (typ)
Operation: 25 mW (typ) (f = 1 MHz)
Single 5 V supply
•
•
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Common data input and output
Three state output
•
•
•
•
Directly TTL compatible
All inputs and outputs
Capability of battery back up operation
HM62256B Series
Ordering Information
Type No.
Access Time Package
HM62256BLP-7
HM62256BLP-7SL
HM62256BLSP-7
HM62256BLSP-7SL
HM62256BLFP-7T
70 ns
70 ns
70 ns
70 ns
70 ns
600-mil 28-pin plastic DIP (DP-28)
300-mil 28-pin plastic DIP (DP-28NA)
450-mil 28-pin plastic SOP (FP-28DA)
HM62256BLFP-4SLT*1
HM62256BLFP-5SLT
HM62256BLFP-7SLT
45 ns
55 ns
70 ns
HM62256BLFP-7ULT
HM62256BLT-8
70 ns
85 ns
70 ns
85 ns
8 mm × 14 mm 32-pin TSOP (TFP-32DA)
8 mm × 13.4 mm 28-pin TSOP (TFP-28DA)
HM62256BLT-7SL
HM62256BLTM-8
HM62256BLTM-4SL*1
HM62256BLTM-5SL
HM62256BLTM-7SL
45 ns
55 ns
70 ns
HM62256BLTM-7UL
70 ns
Note: 1. Under development
2
HM62256B Series
Pin Arrangement
HM62256BLP/BLFP/BLSP Series
HM62256BLT Series
OE
A11
NC
A9
A10
CS
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A14
A12
A7
2
2
NC
3
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
4
3
A8
5
4
A6
A13
WE
VCC
A14
A12
A7
6
7
5
A9
A5
8
6
A11
OE
A4
9
10
11
12
13
14
15
16
7
A3
8
A6
A5
A10
CS
A2
9
A1
NC
A4
NC
10
11
12
13
14
A1
I/O7
I/O6
I/O5
I/O4
I/O3
A0
A3
A2
I/O0
I/O1
I/O2
VSS
(Top View)
HM62256BLTM Series
A10
CS
OE
A11
A9
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
(Top View)
I/O7
I/O6
I/O5
I/O4
I/O3
A8
A13
WE
V
CC
V
A14
A12
A7
SS
I/O2
I/O1
I/O0
A0
2
3
A6
4
A5
5
A1
A2
A4
6
A3
7
8
(Top View)
Pin Description
Symbol
A0 – A14
I/O0 – I/O7
CS
Function
Address
Input/output
Chip select
Write enable
Output enable
No connection
Power supply
Ground
WE
OE
NC
VCC
VSS
3
HM62256B Series
Block Diagram
V CC
V SS
(MSB) A12
A5
•
•
•
•
•
•
•
A7
•
•
•
Memory Matrix
A6
Row
Decoder
×
512 512
A8
A13
A14
A4
(LSB) A3
I/O0
•
•
•
•
Column I/O
•
•
•
•
•
•
Input
Data
Control
Column Decoder
•
•
•
•
•
•
•
•
•
I/O7
A1 A0 A10 A9 A11
A2
(LSB)
(MSB)
•
•
Timing Pulse Generator
Read/Write Control
CS
WE
OE
Function Table
WE
X
CS
H
L
OE
X
Mode
VCC Current
I/O Pin
High-Z
High-Z
Dout
Ref. Cycle
—
Not selected
Output disable
Read
ISB, ISB1
ICC
H
H
L
—
H
L
ICC
Read cycle (1)–(3)
Write cycle (1)
Write cycle (2)
L
L
H
L
Write
ICC
Din
L
L
Write
ICC
Din
Note: X: H or L
4
HM62256B Series
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
Power supply voltage*1
Terminal voltage*1
–0.5 to +7.0
–0.5*2 to VCC + 0.3*3
V
VT
V
Power dissipation
PT
1.0
W
°C
°C
°C
Operating temperature
Storage temperature
Storage temperature under bias
Notes: 1. Relative to VSS
Topr
Tstg
Tbias
0 to + 70
–55 to +125
–10 to +85
2. VT min: –3.0 V for pulse half-width ≤ 50 ns
3. Maximum voltage is 7.0 V
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
4.5
Typ
5.0
0
Max
5.5
Unit
Supply voltage
V
V
V
V
VSS
0
0
Input high (logic 1) voltage
Input low (logic 0) voltage
VIH
2.2
–0.5 *1
—
VCC+0.3
0.8
VIL
—
Note: 1. VIL min: –3.0 V for pulse half-width ≤ 50 ns
5
HM62256B Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V)
Parameter
Symbol Min Typ*1 Max Unit Test Conditions
Input leakage current
|ILI|
|ILO|
—
—
—
—
1
1
µA
µA
Vin = VSS to VCC
Output leakage
current
CS = VIH or OE = VIH or WE = VIL,
VSS ≤ VI/O ≤ VCC
Operating power
supply current
ICC
—
—
6
15
70
mA CS = VIL, others = VIH/VIL
II/O = 0 mA
Average operating
power supply current
HM62256B-4 ICC1
—
mA min cycle, duty = 100 %, II/O = 0
mA
CS = VIL, others = VIH/VIL
HM62256B-5 ICC1
HM62256B-7 ICC1
HM62256B-8 ICC1
ICC2
—
—
—
—
—
33
29
5
60
60
50
15
mA Cycle time = 1 µs, II/O = 0 mA
CS = VIL, VIH = VCC, VIL = 0
Standby power
supply current
ISB
—
0.3
0.2
0.2*2 50*2
0.2*3 10*3
2
mA CS = VIH
ISB1
—
—
100 µA
Vin ≥ 0 V, CS ≥ VCC – 0.2 V,
Output low voltage
Output high voltage
VOL
VOH
—
—
—
0.4
V
V
IOL = 2.1 mA
2.4
—
IOH = –1.0 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.
2. This characteristics is guaranteed only for L-SL version.
3. This characteristics is guaranteed only for L-UL version.
Capacitance (Ta = 25°C, f = 1.0 MHz)*1
Parameter
Symbol Min
Typ
—
Max
8
Unit
pF
Test Conditions
Vin = 0 V
Input capacitance*1
Input/output capacitance*1
Cin
CI/O
—
—
—
10
pF
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
6
HM62256B Series
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 0.8 V to 2.4 V
Input rise and fall times: 5 ns
Input and output timing reference level: 1.5 V
Output load: HM62256B-4: 1 TTL Gate + CL (30 pF)(Including scope & jig)
HM62256B-5: 1 TTL Gate + CL (50 pF)(Including scope & jig)
HM62256B-7/8: 1 TTL Gate + CL (100 pF)(Including scope & jig)
Read Cycle
HM62256B
-4 -5
Symbol Min Max Min Max Min Max Min Max Unit
-7
-8
Parameter
Notes
Read cycle time
tRC
45
—
—
—
45
45
30
—
—
20
55
—
—
—
5
—
55
55
35
—
—
20
70
—
—
—
10
5
—
70
70
40
—
—
25
85
—
—
—
10
5
—
85
85
45
—
—
30
ns
ns
ns
ns
ns
ns
ns
Address access time
tAA
Chip select access time
Output enable to output valid
Chip selection to output in low-Z
Output enable to output in low-Z
tACS
tOE
tCLZ
tOLZ
tCHZ
5
5
0
2
5
2
Chip deselection in to output in
high-Z
0
0
0
1, 2
Output disable to output in high-Z
Output hold from address change
tOHZ
tOH
0
5
20
0
5
20
0
5
25
0
30
ns
ns
1, 2
—
—
—
10
—
Notes: 1. tCHZ and tOHZ defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
7
HM62256B Series
Read Timing Waveform (1) (WE=VIH)
t RC
Address
CS
Valid address
tAA
tACS
tOH
t OE
t OLZ
OE
tOHZ
tCHZ
High impedance
Dout
Valid data
Read Timing Waveform (2) (WE=VIH, CS=VIL, OE=VIL)
t
RC
Valid address
Address
Dout
t
t
AA
OH
t
OH
Valid data
8
HM62256B Series
Read Timing Waveform (3) (WE=VIH, OE=VIL)*1
t
ACS
CS
t
CLZ
t
CHZ
High impedance
Valid data
Dout
Note: 1. Address must be valid prior to or simultaneously with CS going low.
9
HM62256B Series
Write Cycle
HM62256B
-4
-5
-7
-8
Parameter
Symbol Min Max Min Max Min Max Min Max Unit Notes
Write cycle time
tWC
tCW
tAS
45
35
0
—
—
—
—
—
—
20
—
—
—
20
55
40
0
—
—
—
—
—
—
20
—
—
—
20
70
60
0
—
—
—
—
—
—
25
—
—
—
25
85
75
0
—
—
—
—
—
—
40
—
—
—
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip selection to end of write
Address setup time
4
5
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
35
30
0
40
35
0
60
50
0
75
55
0
3, 8
6
Write recovery time
WE to output in high-Z
Data to write time overlap
Data hold from write time
Output active from end of write
0
0
0
0
1, 2, 7
20
0
25
0
30
0
35
0
tOW
5
5
5
5
2
Output disable to output in high-Z tOHZ
0
0
0
0
1, 2, 7
Notes: 1. tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later
transition of CS going low or WE going low. A write ends at the earlier transition of CS going
high or WE going high. tWP is measured from the beginning of write to the end of write.
4. tCW is measured from CS going low to the end of write.
5. tAS is measured from the address valid to the beginning of write.
6. tWR is measured from the earlier of WE or CS going high to the end of write cycle.
7. Durng this period, I/O pins are in the output state so that the input signals of the opposite
phase to the outputs must not be applied.
8. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem
of data bus contention, tWP ≥ tWHZ max + tDW min.
10
HM62256B Series
Write Timing Waveform (1) (OE Clock)
tWC
Address
OE
Valid address
tAW
tWR
tCW
CS
*1
tWP
tAS
WE
tOHZ
High impedance
tDW
Dout
tDH
High impedance
Din
Valid data
Note: 1. If CS goes low simultaneously with WE going low or after WE going low,
the outputs remain in the high impedance state.
11
HM62256B Series
Write Timing Waveform (2) (OE Low Fixed) (OE = V )
IL
tWC
Address
CS
Valid address
tCW
tWR
*1
tAW
tOH
tWP
WE
tAS
tWHZ
tOW
*3
*2
Dout
Din
tDW
tDH
*4
High impedance
Valid data
Notes: 1. If CS goes low simultaneously with WE going low or after WE going low,
the outputs remain in the high impedance state.
2. Dout is the same phase of the write data of this write cycle.
3. Dout is the read data of next address.
4. If CS is low during this period, I/O pins are in the output state. Therefore, the input
signals of the opposite phase to the output must not be applied to them.
12
HM62256B Series
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
Parameter
Symbol Min
Typ*1
Max
Unit
Test Conditions*6
VCC for data retention
VDR
2.0
—
5.5
V
CS ≥ VCC –0.2 V,
Vin ≥ 0 V
Data retention current
ICCDR
—
—
—
0
0.05
0.05
0.05
—
30*2
10*3
3*4
µA
VCC = 3.0 V, Vin ≥ 0 V
CS ≥ VCC –0.2 V,
Chip deselect to data retention time tCDR
Operation recovery time tR
—
ns
ns
See retention waveform
*5
tRC
—
—
Notes: 1. Typical values are at VCC = 3.0 V, Ta = 25°C and not guaranteed.
2. 10 µA max at Ta = 0 to + 40°C.
3. This characteristics guaranteed for only L-SL version. 3 µA max at Ta = 0 to +40°C.
4. This characteristics guaranteed for only L-UL version. 0.6 µA max at Ta = 0 to +40°C.
5. tRC = read cycle time.
6. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data
retention mode, other input levels (address, WE, OE, I/O) can be in the high impedance state.
Low VCC Data Retention Timing Waveform
Data retention mode
V
CC
4.5V
tCDR
t R
2.2V
V
DR
CS
CS > VCC - 0.2V
0V
13
HM62256B Series
Package Dimensions
HM62256BLP Series (DP-28)
Unit: mm
35.60
36.50 Max
28
15
14
1
1.20
15.24
0.25
1.90 Max
+ 0.11
– 0.05
2.54 ± 0.25
0.48 ± 0.10
0° – 15°
HM62256BLSP Series (DP-28NA)
Unit: mm
36.0
37.32 Max
28
1
15
14
1.3
2.2 Max
7.62
+ 0.11
– 0.05
0.25
0.48 ± 0.10
2.54 ± 0.25
0° – 15°
14
HM62256B Series
HM62256BLFP Series (FP-28DA)
Unit: mm
18.00
18.75 Max
15
28
1
14
11.80 ± 0.30
1.27 Max
1.70
0 – 10 °
+ 0.10
– 0.05
0.40
1.27 ± 0.10
1.00 ± 0.20
HM62256BLT Series (TFP-32DA)
Unit: mm
8.00
8.20 Max
17
32
1
16
0.50
0.20 ± 0.10
0.08
M
0.80
14.00 ± 0.20
0.45 Max
0 – 5 °
0.50 ± 0.10
0.10
15
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