HM62V8512CTSSERIES [ETC]
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| 型号： | HM62V8512CTSSERIES |
| 厂家： | 
ETC |
| 描述： |
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| 文件： | 总14页 (文件大小：64K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM62V8512CTS Series
4 M SRAM (512-kword × 8-bit)
ADE-203-1258A (Z)
Rev. 1.0
Jul. 23, 2001
Description
The Hitachi HM62V8512CTS Series is a 4-Mbit static RAM organized 512-kword × 8-bit. HM62V8512CTS
Series has realized higher density, higher performance and low power consumption by employing CMOS
process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is
suitable for battery backup system. It is packaged in TSOP I is available for high density surface mounting.
Features
•
•
•
Single 3.0 V supply: 2.7 V to 3.6 V
Access time: 55/70 ns (max)
Power dissipation
Active: 6.0 mW/MHz (typ)
Standby: 2.4 µW (typ)
•
•
•
•
•
Completely static memory. No clock or timing strobe required
Equal access and cycle times
Common data input and output: Three state output
Directly LV-TTL compatible: All inputs
Battery backup operation
HM62V8512CTS Series
Ordering Information
Type No.
Access time
Package
HM62V8512CLTS-5
HM62V8512CLTS-7
55 ns
70 ns
8 × 13.4 mm 32-pin plastic TSOPI (TFP-32DC)
HM62V8512CLTS-5SL 55 ns
HM62V8512CLTS-7SL 70 ns
2
HM62V8512CTS Series
Pin Arrangement
32-pin TSOP (Normal Type TSOP)
1
A11
A9
32
OE
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A10
CS
3
A8
4
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
5
6
7
8
9
10
11
12
13
14
15
16
A6
A1
A5
A2
A4
A3
(Top view)
Pin Description
Pin name
A0 to A18
I/O0 to I/O7
CS
Function
Address input
Data input/output
Chip select
OE
Output enable
Write enable
Power supply
Ground
WE
VCC
VSS
NC
No connection
3
HM62V8512CTS Series
Block Diagram
LSB
A11
V CC
V SS
A9
A8
•
•
•
•
•
A15
A18
A10
A13
A17
A16
A14
Memory Matrix
Row
Decoder
×
2,048 2,048
A12
MSB
I/O0
I/O7
•
•
•
Column I/O
•
Input
Data
Control
Column Decoder
LSB
MSB
A3A2A1A0 A4A5A6A7
•
•
CS
Timing Pulse Generator
Read/Write Control
WE
OE
4
HM62V8512CTS Series
Function Table
WE
×
CS
H
L
OE
×
Mode
VCC current
Dout pin
Ref. cycle
—
Not selected
Output disable
Read
ISB, ISB1
ICC
High-Z
High-Z
Dout
Din
H
H
L
H
L
—
L
ICC
Read cycle
Write cycle (1)
Write cycle (2)
L
H
L
Write
ICC
L
L
Write
ICC
Din
Note: ×: H or L
Absolute Maximum Ratings
Parameter
Symbol
VCC
Value
Unit
V
Power supply voltage
Voltage on any pin relative to VSS
Power dissipation
–0.5 to +4.6
–0.5*1 to VCC + 0.5*2
1.0
VT
V
PT
W
Operating temperature
Storage temperature
Storage temperature under bias
Topr
Tstg
Tbias
–20 to +70
–55 to +125
–20 to +85
°C
°C
°C
Notes: 1. VT min: –3.0 V for pulse half-width ≤ 30 ns.
2. Maximum voltage is 4.6 V.
Recommended DC Operating Conditions (Ta = –20 to +70°C)
Parameter
Symbol
VCC
Min
2.7
Typ
3.0
0
Max
3.6
0
Unit
V
Supply voltage
VSS
0
V
Input high voltage
Input low voltage
VIH
2.0
–0.3*1
—
VCC + 0.3
0.8
V
V
VIL
—
Note: 1. VIL min: –3.0 V for pulse half-width ≤ 30 ns.
5
HM62V8512CTS Series
DC Characteristics
Parameter
Symbol Min
Typ*1 Max Unit Test conditions
Input leakage current
Output leakage current
|ILI|
—
—
—
—
1
1
µA Vin = VSS to VCC
|ILO|
µA CS = VIH or OE = VIH or
WE = VIL, VI/O = VSS to VCC
Operating power supply current: DC
ICC
—
—
5
8
10
25
mA CS = VIL,
others = VIH/VIL, II/O = 0
mA
Operating power supply HM62V8512CTS-5 ICC1
current
mA Min cycle, duty = 100%
CS = VIL, others = VIH/VIL
II/O = 0 mA
HM62V8512CTS-7 ICC1
ICC2
—
—
7
2
25
5
mA
mA Cycle time = 1 µs,
duty = 100%
II/O = 0 mA, CS ≤ 0.2 V
VIH ≥ VCC – 0.2 V,
VIL ≤ 0.2 V
Standby power supply current: DC
Standby power supply current (1): DC
ISB
—
—
0.1
0.3 mA CS = VIH
ISB1
0.8*2 20*2 µA Vin ≥ 0 V,
CS ≥ VCC – 0.2 V
—
—
—
0.8*3 10*3 µA
Output low voltage
Output high voltage
VOL
VOH
—
—
0.4
0.2
—
V
V
V
V
IOL = 2.1 mA
IOL = 100 µA
IOH = –100 µA
IOH = –1.0 mA
VCC – 0.2 —
2.4
—
—
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
2. This characteristics is guaranteed only for L version.
3. This characteristics is guaranteed only for L-SL version.
Capacitance (Ta = +25°C, f = 1 MHz)
Parameter
Symbol
Cin
Typ
—
Max
8
Unit
pF
Test conditions
Vin = 0 V
Input capacitance*1
Input/output capacitance*1
CI/O
—
10
pF
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
6
HM62V8512CTS Series
AC Characteristics (Ta = –20 to +70°C, VCC = 2.7 V to 3.6 V, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 0.4 V to 2.4 V
Input rise and fall time: 5 ns
Input timing reference levels: 1.4 V
Output timing reference level: 1.4 V/1.4 V(HM62V8512CTS-5)
0.8 V/2.0 V(HM62V8512CTS-7)
•
Output load: See figure (Including scope & jig)
Ω
500
Dout
1.4 V
50 pF
Read Cycle
HM62V8512CTS
-5
-7
Min
70
—
—
—
10
5
Parameter
Symbol
tRC
Min
55
—
—
—
10
5
Max
—
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read cycle time
Address access time
tAA
55
55
30
—
70
70
35
—
Chip select access time
Output enable to output valid
Chip selection to output in low-Z
Output enable to output in low-Z
tCO
tOE
tLZ
2
tOLZ
—
—
2
Chip deselection to output in high-Z tHZ
0
20
20
—
0
30
30
—
1, 2
1, 2
Output disable to output in high-Z
Output hold from address change
tOHZ
tOH
0
0
10
10
7
HM62V8512CTS Series
Write Cycle
HM62V8512CTS
-5
-7
Min
70
60
0
Parameter
Symbol
tWC
Min
55
50
0
Max
—
—
—
—
—
—
20
—
—
—
20
Max
—
—
—
—
—
—
30
—
—
—
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Write cycle time
Chip selection to end of write
Address setup time
tCW
4
5
tAS
Address valid to end of write
Write pulse width
tAW
50
40
0
60
50
0
tWP
3, 12
6
Write recovery time
WE to output in high-Z
Data to write time overlap
Data hold from write time
tWR
tWHZ
tDW
0
0
1, 2, 7
25
0
30
0
tDH
Output active from output in high-Z tOW
Output disable to output in high-Z tOHZ
5
5
2
0
0
1, 2, 7
Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later
transition of CS going low or WE going low. A write ends at the earlier transition of CS going high
or WE going high. tWP is measured from the beginning of write to the end of write.
4. tCW is measured from CS going low to the end of write.
5. tAS is measured from the address valid to the beginning of write.
6. tWR is measured from the earlier of WE or CS going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to
the outputs must not be applied.
8. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition,
the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the
opposite phase to the outputs must not be applied to them.
12. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of
data bus contention. tWP ≥ tDW min + tWHZ max
8
HM62V8512CTS Series
Timing Waveforms
Read Timing Waveform (WE = VIH)
tRC
Address
tAA
tCO
CS
tLZ
tHZ
tOE
tOLZ
OE
tOHZ
Dout
Valid Data
tOH
9
HM62V8512CTS Series
Write Timing Waveform (1) (OE Clock)
tWC
Address
tAW
tWR
OE
tCW
CS
*8
tWP
tAS
WE
tOHZ
Dout
Din
tDW
tDH
Valid Data
10
HM62V8512CTS Series
Write Timing Waveform (2) (OE Low Fixed)
tWC
Address
tCW
tWR
CS
*8
tAW
tWP
tOH
WE
tAS
tOW
tWHZ
*10
*9
Dout
Din
tDW
tDH
*11
Valid Data
11
HM62V8512CTS Series
Low VCC Data Retention Characteristics (Ta = –20 to +70°C)
Parameter
Symbol Min
Typ
—
0.8*4
Max Unit
Test conditions*3
VCC for data retention
Data retention current
VDR
2
—
V
CS ≥ VCC – 0.2 V, Vin ≥ 0 V
ICCDR
—
20*1
µA
VCC = 3.0 V, Vin ≥ 0 V
CS ≥ VCC – 0.2 V
—
0.8*4
—
10*2
—
µA
ns
ns
Chip deselect to data retention time tCDR
Operation recovery time tR
0
tRC*5
See retention waveform
—
—
Notes: 1. For L-version and 10 µA (max.) at Ta = –20 to +40°C.
2. For L-SL-version and 3 µA (max.) at Ta = –20 to +40°C.
3. CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin
levels (address, WE, OE, I/O) can be in the high impedance state.
4. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed.
5. tRC = read cycle time.
Low VCC Data Retention Timing Waveform (CS Controlled)
Data retention mode
tCDR
tR
VCC
2.7 V
VDR
2.0 V
CS
0 V
≥
CS VCC – 0.2 V
12
HM62V8512CTS Series
Package Dimensions
HM62V8512CLTS Series (TFP-32DC)
As of January, 2001
8.00
Unit: mm
8.20 Max
17
32
1
16
0.50
*0.22 ± 0.08
0.20 ± 0.06
0.08
M
0.80
13.40 ± 0.30
0.43 Max
0° – 5°
0.50 ± 0.10
0.10
Hitachi Code
TFP-32DC
JEDEC
EIAJ
Mass (reference value)
—
—
0.23 g
*Dimension including the plating thickness
Base material dimension
13
HM62V8512CTS Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: (03) 3270-2111 Fax: (03) 3270-5109
URL
http://www.hitachisemiconductor.com/
For further information write to:
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive Whitebrook Park
Hitachi Europe Ltd.
Electronic Components Group
Hitachi Asia Ltd.
Hitachi Tower
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Singapore 049318
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Group III (Electronic Components)
7/F., North Tower
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Tel: <1> (408) 433-1990 Maidenhead
Fax: <1>(408) 433-0223 Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Tel : <65>-538-6533/538-8577
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Tel : <852>-(2)-735-9218
Fax : <852>-(2)-730-0281
URL : http://semiconductor.hitachi.com.hk
Fax: <44> (1628) 585200
Hitachi Asia Ltd.
(Taipei Branch Office)
4/F, No. 167, Tun Hwa North Road
Hung-Kuo Building
Hitachi Europe GmbH
Electronic Components Group
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Tel : <886>-(2)-2718-3666
Fax : <886>-(2)-2718-8180
Telex : 23222 HAS-TP
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Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.
Colophon 5.0
14
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