HM62W1400HJP-12 [ETC]
x1 SRAM ; X1 SRAM\n
| 型号： | HM62W1400HJP-12 |
| 厂家： | 
ETC |
| 描述： | x1 SRAM
|
| 文件： | 总16页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM62W1400H Series
4M High Speed SRAM (4-Mword × 1-bit)
ADE-203-773E (Z)
Rev. 2.0
Nov. 11, 1998
Description
The HM62W1400H is a 4-Mbit high speed static RAM organized 4-Mword × 1-bit. It has realized high
speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell)and high speed
circuit designing technology. It is most appropriate for the application which requires high speed and high
density memory, such as cache and buffer memory in system. The HM62W1400H is packaged in 400-mil
32-pin SOJ and 400-mil 32-pin TSOP II for high density surface mounting.
Features
•
•
•
Single 3.3 V supply : 3.3 V ± 0.3 V
Access time 12/15 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
Directly TTL compatible
•
•
All inputs and outputs
•
•
•
Operating current: 180/160 mA (max)
TTL standby current: 60/50 mA (max)
CMOS standby current: 5 mA (max)
: 1 mA (max) (L-version)
•
•
•
Data retension current: 0.6 mA (max) (L-version)
Data retension voltage: 2 V (min) (L-version)
Center VCC and VSS type pinout
HM62W1400H Series
Ordering Information
Type No.
Access time
Package
HM62W1400HJP-12
HM62W1400HJP-15
12 ns
15 ns
400-mil 32-pin plastic SOJ (CP-32DB)
HM62W1400HLJP-12
HM62W1400HLJP-15
12 ns
15 ns
HM62W1400HTT-12
HM62W1400HTT-15
12 ns
15 ns
400-mil 32-pin plastic TSOP II (TTP-32DC)
HM62W1400HLTT-12
HM62W1400HLTT-15
12 ns
15 ns
Pin Arrangement
HM62W1400HJP/HLJP Series
HM62W1400HTT/HLTT Series
1
1
A0
A1
A0
A1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A21
A20
A19
A18
A17
A16
OE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A21
A20
A19
A18
A17
A16
OE
2
2
3
3
A2
A2
4
4
A3
A3
5
5
A4
A4
6
6
A5
A5
7
7
CS
VCC
VSS
Din
WE
A6
CS
VCC
VSS
Din
WE
A6
8
8
VSS
VCC
Dout
A15
A14
A13
A12
A11
NC
VSS
VCC
Dout
A15
A14
A13
A12
A11
NC
9
9
10
11
12
13
14
15
16
10
11
12
13
14
15
16
A7
A7
A8
A8
A9
A9
A10
A10
(Top view)
(Top view)
2
HM62W1400H Series
Pin Description
Pin name
A0 to A21
Din
Function
Address input
Data input
Dout
CS
Data output
Chip select
Output enable
Write enable
Power supply
Ground
OE
WE
VCC
VSS
NC
No connection
Block Diagram
(LSB)
A2
A18
A8
VCC
Memory matrix
256 rows × 64 columns ×
256 blocks × 1 bit
(4,194,304 bits)
Row
decoder
A12
A17
A3
VSS
A7
A6
(MSB)
CS
Din
Column I/O
Dout
CS
Column decoder
A5
A11A9A10A20A21 A0 A13 A14 A15 A1 A19 A16 A4
CS
WE
OE
(LSB)
(MSB)
CS
3
HM62W1400H Series
Operation Table
CS
H
L
OE
×
WE
×
Mode
VCC current
Dout
Ref. cycle
—
Standby
Output disable
Read
ISB, ISB1
ICC
High-Z
High-Z
Dout
H
L
H
H
L
—
L
ICC
Read cycle (1) to (3)
Write cycle (1)
Write cycle (2)
L
H
L
Write
ICC
High-Z
High-Z
L
L
Write
ICC
Note: ×: H or L
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Supply voltage relative to VSS
Voltage on any pin relative to VSS
Power dissipation
VCC
–0.5 to +4.6
–0.5*1 to VCC+0.5*2
V
VT
V
PT
1.0
W
°C
°C
°C
Operating temperature
Storage temperature
Topr
Tstg
Tbias
0 to +70
–55 to +125
–10 to +85
Storage temperature under bias
Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns
2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 8 ns
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC*3
VSS*4
VIH
Min
3.0
Typ
3.3
0
Max
Unit
V
Supply voltage
3.6
0
0
V
Input voltage
2.2
—
VCC + 0.5*2
V
VIL
–0.5*1
—
0.8
V
Notes: 1. VIL (min) = –2.0 V for pulse width (under shoot) ≤ 8 ns
2. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 8 ns
3. The supply voltage with all VCC pins must be on the same level.
4. The supply voltage with all VSS pins must be on the same level.
4
HM62W1400H Series
DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0V)
Parameter
Symbol Min
Typ*1
—
Max
2
Unit
µA
Test conditions
Vin = VSS to VCC
Vin = VSS to VCC
Input leakage current
Output leakage current
IILII
—
—
—
IILOI
—
2
µA
Operation power
supply current
12 ns cycle ICC
—
180
mA
Min cycle
CS = VIL, lout = 0 mA
Other inputs = VIH/VIL
15 ns cycle ICC
—
—
—
—
160
60
Standby power supply 12 ns cycle ISB
current
mA
mA
Min cycle, CS = VIH,
Other inputs = VIH/VIL
15 ns cycle ISB
ISB1
—
—
—
50
5
0.05
f = 0 MHz
V
CC ≥ CS ≥ VCC - 0.2 V,
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC - 0.2 V
—*2
—
0.05*2
—
1*2
0.4
—
Output voltage
VOL
VOH
V
V
IOL = 8 mA
2.4
—
IOH = –4 mA
Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed.
2. This characteristics is guaranteed only for L-version.
Capacitance (Ta = +25°C, f = 1.0 MHz)
Parameter
Input capacitance*1
Symbol Min
Typ
—
Max
Unit
pF
Test conditions
Vin = 0 V
Cin
—
—
—
6
8
8
CDIN
CDOUT
—
pF
VDIN = 0 V
Input/output capacitance*1
—
pF
VDOUT = 0 V
Note: 1. This parameter is sampled and not 100% tested.
5
HM62W1400H Series
AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 3.0 V/0.0 V
Input rise and fall time: 3 ns
Input and output timing reference levels: 1.5 V
Output load: See figures (Including scope and jig)
3.3 V
319Ω
Dout
Zo=50 Ω
Dout
353Ω
RL=50 Ω
5 pF
1.5 V
Output load (A)
Output load (B)
(for tCLZ, tOLZ, tCHZ, tOHZ, tWHZ, and tOW
)
Read Cycle
HM62W1400H
-12
Min
12
—
—
—
3
-15
Min
15
—
—
—
3
Parameter
Symbol
tRC
Max
—
12
12
6
Max
—
15
15
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read cycle time
Address access time
tAA
Chip select access time
tACS
tOE
Output enable to outpput valid
Output hold from address change
Chip select to output in low-Z
Output enable to output in low-Z
Chip deselect to output in high-Z
Output disable to output in high-Z
tOH
—
—
—
6
—
—
—
7
tCLZ
3
3
1
1
1
1
tOLZ
tCHZ
tOHZ
0
0
—
—
—
—
6
7
6
HM62W1400H Series
Write Cycle
HM62W1400H
-12
-15
Parameter
Symbol
tWC
Min
12
8
Max
—
—
—
—
—
—
—
—
—
6
Min
15
10
10
10
0
Max
—
—
—
—
—
—
—
—
—
7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Write cycle time
Address valid to end of write
Chip select to end of write
Write pulse width
tAW
tCW
8
9
8
6
7
tWP
8
Address setup time
tAS
0
Write recovery time
tWR
0
0
Data to write time overlap
Data hold from write time
Write disable to output in low-Z
Output disable to output in high-Z
Write enable to output in high-Z
tDW
6
7
tDH
0
0
tOW
3
3
1
1
1
tOHZ
tWHZ
—
—
—
—
6
7
Note: 1. Transition is measured ±200 mV from steady voltage with Load (B). This parameter is sampled
and not 100% tested.
2. Address should be valid prior to or coincident with CS transition low.
3. WE and/or CS must be high during address transition time.
4. if CS and OE are low during this period, Dout pins are in the output state. Then, the data input
signals of opposite phase to the outputs must not be applied to them.
5. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition,
output remains a high impedance state.
6. tAS is measured from the latest address transition to the later of CS or WE going low.
7. tWR is measured from the earlier of CS or WE going high to the first address transition.
8. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition
among CS going low and WE going low. A write ends at the earliest transition among CS going
high and WE going high. tWP is measured from the beginnig of write to the end of write.
9. tCW is measured from the later of CS going low to the the end of write.
7
HM62W1400H Series
Timing Waveforms
Read Timing Waveform (1) (WE = VIH)
tRC
Address
Valid address
tAA
tOH
tCHZ
tACS
CS
OE
tOE
tOHZ
tOLZ
tCLZ
High Impedance
Dout
Valid data
Read Timing Waveform (2) (WE = VIH, CS = VIL, OE = VIL)
tRC
Address
Dout
Valid address
tAA
tOH
tOH
Valid data
8
HM62W1400H Series
Read Timing Waveform (3) (WE = VIH, CS = VIL, OE = VIL)*2
tRC
CS
tACS
tCHZ
tCLZ
High
Dout
High
Impedance
Valid data
Impedance
Write Timing Waveform (1) (WE Controlled)
tWC
Valid address
tAW
Address
tWR
OE
tCW
CS*3
tAS
tWP
WE*3
Dout
Din
tOHZ
High impedance*5
tDW
tDH
4
4
*
*
Valid data
9
HM62W1400H Series
Write Timing Waveform (2) (CS Controlled)
tWC
Valid address
tCW
Address
tWR
CS *3
tAW
tWP
WE *3
tAS
tWHZ
tOW
High impedance*5
Dout
Din
tDW
tDH
4
4
*
*
Valid data
10
HM62W1400H Series
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter
Symbol
Min
Typ*1
Max
Unit Test conditions
VCC for data retention
VDR
2.0
—
—
V
VCC ≥ CS ≥ VCC – 0.2 V
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
Data retention current
ICCDR
—
40
600
µA
VCC = 3 V, VCC ≥ CS ≥ VCC – 0.2 V
(1) 0 V ≤ Vin ≤ 0.2 V or
(2) VCC ≥ Vin ≥ VCC – 0.2 V
Chip deselect to data
retention time
tCDR
tR
0
5
—
—
—
—
ns
See retention waveform
Operation recovery time
ms
Note: 1. Typical values are at VCC = 3.0 V, Ta = +25˚C, and not guaranteed.
Low VCC Data Retention Timing Waveform
Data retention mode
tCDR
tR
VCC
3.0 V
VDR
2.2 V
CS
0 V
V
CC ≥ CS ≥ VCC – 0.2 V
11
HM62W1400H Series
Package Dimensions
HM62W1400HJP/HLJP Series (CP-32DB)
Unit: mm
20.71
21.08 Max
32
17
16
1
0.74
1.30 Max
9.40 ± 0.25
1.27
0.43 ± 0.10
0.41 ± 0.08
0.10
Hitachi Code
JEDEC
EIAJ
CP-32DB
Conforms
Conforms
Dimension including the plating thickness
Base material dimension
Weight (reference value) 1.2 g
12
HM62W1400H Series
HM62W1400HTT/HLTT Series (TTP-32DC)
Unit: mm
20.95
21.35 Max
32
17
16
1
1.27
*0.42 ± 0.08
0.40 ± 0.06
M
0.21
0.80
11.76 ± 0.20
1.15 Max
0° – 5°
0.50 ± 0.10
0.10
Hitachi Code
JEDEC
EIAJ
TTP-32DC
Conforms
—
*Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.51 g
13
HM62W1400H Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual
property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of
bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic,
safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for
maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and
other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the
guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or
failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the
equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage
due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
Europe
: http:semiconductor.hitachi.com/
: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore)
Asia (Taiwan)
: http://www.has.hitachi.com.sg/grp3/sicd/index.htm
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
Hitachi Europe GmbH
Electronic components Group
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
2000 Sierra Point Parkway Dornacher Straße 3
Brisbane, CA 94005-1897 D-85622 Feldkirchen, Munich
Tel: <1> (800) 285-1601
Fax: <1> (303) 297-0447
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Telex: 40815 HITEC HX
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
14
HM62W1400H Series
Revision Record
Rev. Date
Contents of Modification
Drawn by
A. Ide
Approved by
A. Ide
0.0 Apr. 28, 1997 Initial issue
0.1 Nov. 20, 1997 Change of Subtitle
0.2 Dec. 5, 1997 Features
K. Makuta
K. Makuta
T. Fukazawa K. Makuta
Addition of Operating current
Addition of TTL standby current
Addition of CMOS standby current
Addition of Data retention current
Addition of Data retention voltage
Change of Block Diagram
Operation table
Title: I/O to Dout
Dout: Din to High-Z
Absolute Maximum Ratings
Change of notes
Recommended DC Operatig Conditions
Change of notes
DC Characteristics
I
CC (max): 240/200/190 mA to 160/140/120 mA
ISB (max): 100/100/100 mA to 70/60/50 mA
SB1 (max): 10/0.5 mA to 5/1 mA
I
Testconditions ICC and ISB: Addition of Min cycle
Testconditions ISB1: Addition of f = 0 MHz
Chapacitance
Addition of CDIN
Input/output capacitance: CI/O to CDOUT
AC Characteristics
Change of Output load (A)
tOE, tCHZ and tOHZ (max): 5/6/8 ns to 5/6/7 ns
t
t
AW, tCW and tWP (min): 6/8/10 ns to 7/8/10 ns
DW (min): 5/6/8 ns to 5/6/7 ns
tOHZ and tWHZ (max): 5/6/8 ns to 5/6/7 ns
Note 4.: Correct error
Low VCC Data Retention Characteristics
I
CCDR: —/2/300 µA to —/—/300 µA
0.3 May. 15, 1998 Features
Change of Operating current
T. Fukazawa K. Makuta
T. Fukazawa K. Makuta
Change of Block Diagram
DC Characteristics
I
CC (max): 170/150/130 mA to 200/180/160 mA
1.0 Sep. 15, 1998 Delete of HM62W1400H-10 Series
Features
Change of Data retention current
DC Characteristics
I
SB1 (typ): —/— mA to 0.05/0.05 mA
Low VCC Data Retention Characteristics
CCDR: —/—/300 µA to —/40/600 µA
I
15
HM62W1400H Series
Rev. Date
Contents of Modification
Drawn by
Approved by
2.0 Nov. 11, 1998 Addition of TTP-32DC
Ordering Information
Addition of HM62W1400HTT/ HM62W1400HLTT Series
16
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