HMS39112 [ETC]
4-BIT SINGLE CHIP MICROCOMPUTERS; 4位单芯片微型计算机
| 型号： | HMS39112 |
| 厂家： | 
ETC |
| 描述： | 4-BIT SINGLE CHIP MICROCOMPUTERS |
| 文件： | 总73页 (文件大小：399K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dec. 2001
VER. 1.00
4-BIT SINGLE CHIP MICROCOMPUTERS
HMS38112/39112
USER`S MANUAL
• HMS38112
• HMS39112
VER. 1.00
Published by
MCU Application Team in MagnaChip Semiconductor Ltd. Co., Ltd.
MagnaChip Semiconductor Ltd. 2004 All Right Reserved.
Additional information of this manual may be served by MagnaChip Semiconductor Ltd. Offices in
Korea or Distributors and Representative listed at address directory.
MagnaChip Semiconductor Ltd. reserves the right to make changes to any Information here in at any
time without notice.
The information, diagrams, and other data in this manual are correct and reliable; however,
MagnaChip Semiconductor Ltd. is in no way responsible for any violations of patents or
other rights of the third party generated by the use of this manual.
HMS38112
1
2
3
4
5
HMS39112
ARCHITECTURE
INSTRUCTION
APPLICATION
Chapter 1.HMS38112
CHAPTER 1. HMS38112
Outline of characteristics
The HMS38112 is remote control transmitter which uses CMOS technology
This enables transmission code outputs of different configurations, multiple custom code
output, and double push key output for easy fabrication.
The HMS38112 is suitable for remote control of TV, VCR, FANS, Air-conditioners,
Audio Equipments, Toys, Games etc.
Characteristics
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Program memory : 1,024 bytes
Data memory : 32 4 bits
43 types of instruction set
3 levels of subroutine nesting
Operating frequency : 2.4MHz ~ 4MHz
Instruction cycle : fOSC/48
CMOS process (Single 3.0V power supply)
Stop mode (Through internal instruction)
Released stop mode by key input(mask option)
Built in Power-on Reset circuit
Built in Transistor for I.R LED Drive : IOL=250mA at VDD=3V and VO=0.3V
Built in Low Voltage reset circuit
Built in a watch dog timer (WDT)
Low operating voltage : 2.0 ~ 3.6V
20 pin PDIP/SOP/SSOP package
1-1
Chapter 1.HMS38112
Block Diagram
VDD GND
20
1
Power-on
Reset
Watchdog
timer
EPROM
10
3-level
Stack
Program counter
64word 16page
8bit
8
10
4
4
4
4
8
Instruction
Decoder
ALU
MUX
4
4
RAM
Word
Selector
Control Signal
2
16
RAM
16word x
2page x 4bit
X-Reg
Y-Reg
ST
4
ACC
4
10
4
R-Latch
D-Latch
10
OSC
Pulse
Generator
4
4
4
I.R.LED
Drive Tr.
2
3
4
5
6
7
8
9
10 11
12 13 14 15 16 17
D0 D1 D2 D3 D4 D5
18
19
OSC1 OSC2
K0 ~ K3
R0 ~ R3
PGND REMOUT
Fig 1-1 Block Diagram
1-2
Chapter 1.HMS38112
Pin Assignment
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
GND
OSC1
OSC2
VDD
REMOUT
PGND
K0
K1
K2
K3
R0
R1
D5
D4
D3
D2
D1
D0
R3
R2 10
Fig 1-2 HMS38112 Pin Assignment
(20 PIN)
1-3
Chapter 1.HMS38112
Pin Dimension
- NOTE -
1. DIMENSION * MARK DOES NOT INCLUDE MOLD PROTRUSION.
MAXIMUM ALLOWABLE PROTRUSION IS 0.010 INCH PER SIDE.
2. DIMENSION ** MARK DOES NOT INCLUDE MOLD PROTRUSION.
MAXIMUM ALLOWABLE PROTRUSION IS 0.010 INCH PRE SIDE.
3. UNSPECIFIED IS ACCORDING TO JEDEC MS-001 VARIATION AE.
Fig 1-3. 20PDIP (300MIL) Pin Dimension (UNIT : INCH)
- NOTE -
1. DIMENSION * MARK DOES NOT INCLUDE MOLD PROTRUSION.
MAXIMUM ALLOWABLE PROTRUSION IS 0.15 mm PER SIDE.
2. DIMENSION ** MARK DOES NOT INCLUDE MOLD PROTRUSION.
MAXIMUM ALLOWABLE PROTRUSION IS 0.25 mm PRE SIDE.
3. DIMENSIONING AND TOLERANCEING PER ANSI Y14.5M-1982.
4. UNSPECIFIED IS ACCORDING TO JEDEC MS-013, VARIATION “AC”.
Fig 1-4. 20SOP (300MIL) Pin Dimension (UNIT : mm)
1-4
Chapter 1.HMS38112
0.0098
0.0075
* 0.344
0.337
0 - 8
- NOTE -
1. DIMENSION * MARK DOES NOT INCLUDE MOLD PROTRUSION.
MAXIMUM ALLOWABLE PROTRUSION IS 0.006 INCH PER SIDE.
2. DIMENSION ** MARK DOES NOT INCLUDE MOLD PROTRUSION.
MAXIMUM ALLOWABLE PROTRUSION IS 0.010 INCH PRE SIDE.
3. DIMENSIONING AND TOLERANCEING PER ANSI Y14.5M-1982.
4. UNSPECIFIED IS ACCORDING TO JEDEC MO-137, VARIATION “AD”.
0.012
0.008
0.025 BSC
Fig 1-5. 20SSOP (150MIL) Pin Dimension (UNIT : inch)
1-5
Chapter 1.HMS38112
Pin Description and Circuit
Pin Description
Pin
I/O
Function
VDD
-
Connected to 2.0~ 3.6V power supply
GND
-
Connected to 0V power supply.
4-bit input port with built in pull-up resistor.
STOP mode is released by "L" input of each pin.
Input
K0 ~ K3
Each can be set and reset independently.
D0 ~ D5
R0 ~ R1
Output
Input
The output is the structure of N-channel-open-drain.
2-bit input port with built in pull-up resistor.
STOP mode is released by "L" input of each pin.
2-bit I/O port. (Input mode is set only when each of them output "H".)
In outputting, each can be set and reset independently(or at once.)
The output is in the form of C-MOS.
R2 ~ R3
I/O
STOP mode is released by "L" input of each pin.
Oscillator input. Input to the oscillator circuit and connection
point for ceramic resonator.
OSC1
Input
A feedback resistor is connected between this pin and OSC2.
OSC2
PGND
Output
-
Connect a resonator between this pin and OSC1.
Ground pin for internal high current N-channel transistor.
(connected to GND)
High current output port for driving I.R.LED.
The output is in the form N-channel open drain.
REMOUT
Output
1-6
Chapter 1.HMS38112
Pin Circuit
Pin
I/O
I/O circuit
Note
pull-up
- Built in MOS Tr for
pull-up, about 140
R0 ~ R1
I
.
pull-up
- CMOS output.
- "H" output at reset.
- Built in MOS Tr for
pull-up, about 140
R2 ~ R3
I/O
.
pull-up
- Built in MOS Tr for
pull-up, about 140
K0 ~ K3
D0 ~ D5
REMOUT
I
.
- Open drain output.
- "L" output at reset.
- D0~D3 are “L” output
at STOP MODE..
- D4 ~D5 pins “Low” or
keep before stop mode
at STOP MODE (option)
O
REMOUT
PGND
- Open drain output
- Output Tr. Disable at
reset.
RESETB
DATA
O
1-7
Chapter 1.HMS38112
Pin
I/O
I/O circuit
Note
OSC1
OSC2
OSC2
O
- Built in feedback-resistor
about 1
OSC1
I
Rf
STOP
Optional Features
The HMS38112 offers the following optional features.
These options are masked.
• I/O terminals having pull-up resistor : R2 ~ R3
• Input terminals having STOP release mode : K0 ~ K3, R0 ~ R3
• Output form at STOP mode : D4 ~D5 pins “L” or keep before stop mode
1-8
Chapter 1.HMS38112
Electrical Characteristics
Absolute maximum ratings (Ta = 25 )
Parameter
Symbol
Max. rating
Unit
Supply Voltage
VDD
PD
-0.3 ~ 5.0
700 *
V
Power dissipation
Storage temperature range
Input voltage
mW
Tstg
VIN
-55 ~ 125
-0.3 ~ VDD+0.3
-0.3 ~ VDD+0.3
V
V
Output voltage
VOUT
* Thermal derating above 25
: 6mW per degree
rise in temperature.
Recommended operating condition
Parameter
Symbol
Condition
Rating
Unit
Supply Voltage
VDD
2.4MHz ~ 4MHz
-
2.0 ~ 3.6
V
Operating temperature
Topr
-20 ~ +70
1-9
Chapter 1.HMS38112
Electrical characteristics (Ta=25 , VDD= 3V)
Limits
Parameter
Symbol
Unit
Condition
Min.
Typ. Max.
1
uA
VI=VDD
IIH
-
-
Input H current
RPU1
RPU2
VI=GND
K Pull-up Resistance
R Pull-up Resistance
300
300
70
70
140
140
VI=GND, Output off
RFD
VIH1
VIL1
Feedback Resistance
3.0
-
0.3
1.0
-
VOSC1=GND, VOSC2=VDD
-
V
V
V
V
V
2.1
K, R input H voltage
K, R input L voltage
0.9
-
-
-
-
-
0.4
0.9
-
I
OL=3mA
VOL2*1
0.15
0.4
D. R output L voltage
OSC2 output L voltage
IOL=150uA
IOH=-150uA
VOL3
VOH3
2.1
2.5
OSC2 output H voltage
mA
VOL=0.3V
250
REMOUT output L current
IOL1
1
1
uA
uA
uA
mA
IOLK1
IOLK2
ISTP
-
-
-
-
-
-
V0UT=VDD, Output off
V0UT=VDD, Output off
At STOP mode
REMOUT leakage current
D, R output leakage current
Current on STOP mode
1
-
1.5
fOSC=4MHz
IDD *2
0.5
Operating supply current
System clock
fOSC/48
MHZ version
4
MHz
fOSC
2.4
-
frequency
*1 Refer to Fig.1-6 < IOL2 vs. VOL2 Graph>
*2 IDD is measured at RESET mode.
1-10
Chapter 1.HMS38112
Fig 1-6. IOL2 vs. VOL2 Graph. ( D, R Port )
1-11
HMS38112
1
2
3
4
5
HMS39112
ARCHITECTURE
INSTRUCTION
APPLICATION
Chapter 2.HMS39112
CHAPTER 2. HMS39112
Outline of characteristics
The HMS39112 is remote control transmitter which uses CMOS technology
This enables transmission code outputs of different configurations, multiple custom code
output, and double push key output for easy fabrication.
The HMS39112 is suitable for remote control of TV, VCR, FANS, Air-conditioners,
Audio Equipments, Toys, Games etc.
It is possible to structure the 8 x 7 key matrix.
Characteristics
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Program memory : 1,024 bytes
Data memory : 32 4 bits
43 types of instruction set
3 levels of subroutine nesting
Operating frequency : 2.4MHz ~ 4MHz
Instruction cycle : fOSC/48
CMOS process (Single 3.0V power supply)
Stop mode (Through internal instruction)
Released stop mode by key input(mask option)
Built in Power-on Reset circuit
Built in Low Voltage reset circuit
Built in a watch dog timer (WDT)
Low operating voltage : 2.0 ~ 3.6V
20 pin PDIP/SOP/SSOP package
2-1
Chapter 2.HMS39112
Block Diagram
VDD GND
20
1
Power-on
Reset
Watchdog
timer
EPROM
10
3-level
Stack
Program counter
64word 16page
8bit
8
10
4
4
4
4
8
Instruction
Decoder
ALU
MUX
4
4
RAM
Word
Selector
Control Signal
2
16
RAM
16word x
2page x 4bit
X-Reg
Y-Reg
ST
4
ACC
4
10
4
R-Latch
D-Latch
10
OSC
Pulse
Generator
4
4
4
2
3
4
5
6
7
8
9
10 11
12 13 14 15 16 17 18
D0 D1 D2 D3 D4 D5 D6
19
OSC1 OSC2
K0 ~ K3
R0 ~ R3
REMOUT
Fig 2-1 Block Diagram
2-2
Chapter 2.HMS39112
Pin Assignment
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
GND
OSC1
OSC2
VDD
REMOUT
D6
K0
K1
D5
D4
D3
D2
D1
D0
R3
K2
K3/Vpp
R0
R1
R2 10
Fig 2-2 HMS39112 Pin Assignment
(20 PIN)
2-3
Chapter 2.HMS39112
Pin Dimension
- NOTE -
1. DIMENSION * MARK DOES NOT INCLUDE MOLD PROTRUSION.
MAXIMUM ALLOWABLE PROTRUSION IS 0.010 INCH PER SIDE.
2. DIMENSION ** MARK DOES NOT INCLUDE MOLD PROTRUSION.
MAXIMUM ALLOWABLE PROTRUSION IS 0.010 INCH PRE SIDE.
3. UNSPECIFIED IS ACCORDING TO JEDEC MS-001 VARIATION AE.
Fig 2-3. 20PDIP (300MIL) Pin Dimension (UNIT : INCH)
- NOTE -
1. DIMENSION * MARK DOES NOT INCLUDE MOLD PROTRUSION.
MAXIMUM ALLOWABLE PROTRUSION IS 0.15 mm PER SIDE.
2. DIMENSION ** MARK DOES NOT INCLUDE MOLD PROTRUSION.
MAXIMUM ALLOWABLE PROTRUSION IS 0.25 mm PRE SIDE.
3. DIMENSIONING AND TOLERANCEING PER ANSI Y14.5M-1982.
4. UNSPECIFIED IS ACCORDING TO JEDEC MS-013, VARIATION “AC”.
Fig 2-4. 20SOP (300MIL) Pin Dimension (UNIT : mm)
2-4
Chapter 2.HMS39112
0.0098
0.0075
* 0.344
0.337
0 - 8
- NOTE -
1. DIMENSION * MARK DOES NOT INCLUDE MOLD PROTRUSION.
MAXIMUM ALLOWABLE PROTRUSION IS 0.006 INCH PER SIDE.
2. DIMENSION ** MARK DOES NOT INCLUDE MOLD PROTRUSION.
MAXIMUM ALLOWABLE PROTRUSION IS 0.010 INCH PRE SIDE.
3. DIMENSIONING AND TOLERANCEING PER ANSI Y14.5M-1982.
4. UNSPECIFIED IS ACCORDING TO JEDEC MO-137, VARIATION “AD”.
0.012
0.008
0.025 BSC
Fig 2-5. 20SSOP (150MIL) Pin Dimension (UNIT : INCH)
2-5
Chapter 2.HMS39112
Pin Description and Circuit
Pin Description
Pin
I/O
Function
VDD
-
Connected to 2.0~ 3.6V power supply
GND
-
Connected to 0V power supply.
4-bit input port with built in pull-up resistor.
Input
K0 ~ K3
STOP mode is released by "L" input of each pin.(masked option)
Each can be set and reset independently.
D0 ~ D6
R0 ~ R1
R2 ~ R3
Output
Input
The output is the structure of N-channel-open-drain.
2-bit input port with built in pull-up resistor.
STOP mode is released by "L" input of each pin.(masked option)
2-bit I/O port. (Input mode is set only when each of them output "H".)
In outputting, each can be set and reset independently(or at once.)
The output is in the form of C-MOS.
I/O
STOP mode is released by "L" input of each pin.
Pull-up resistor and STOP release mode can be respectively selected
as masked option for each pin.(It is released by “L” input at STOP)
Oscillator input. Input to the oscillator circuit and connection
point for ceramic resonator.
OSC1
OSC2
Input
A feedback resistor is connected between this pin and OSC2.
Output
Connect a resonator between this pin and OSC1.
High current output port for driving I.R.LED.
The output is in the form N-channel open drain.
REMOUT
Output
2-6
Chapter 2.HMS39112
Pin Circuit
Pin
I/O
I/O circuit
Note
pull-up
- Built in MOS Tr for
pull-up, about 140
R0 ~ R1
I
.
pull-up
- CMOS output.
- "H" output at reset.
- Built in MOS Tr for
pull-up, about 140
R2 ~ R3
I/O
.
pull-up
- Built in MOS Tr for
pull-up, about 140
K0 ~ K3
D0 ~ D6
REMOUT
I
.
- Open drain output.
- "L" output at reset.
- D0~D3 are “L” output
at STOP MODE.
-D4 ~D6 pins “L” or keep
before stop mode
At STOP MODE(option)
O
- Open drain output
- “L” output at reset.
- High current output
source.
O
2-7
Chapter 2.HMS39112
Pin
I/O
I/O circuit
Note
OSC1
OSC2
OSC2
O
- Built in feedback-resistor
about 1
OSC1
I
Rf
STOP
Optional Features
The HMS39112 offers the following optional features.
These options are masked.
• I/O terminals having pull-up resistor : R2 ~ R3
• Input terminals having STOP release mode : K0 ~ K3, R0 ~ R3
• Output form at STOP mode : D4 ~D6 pins “L” or keep before stop mode
2-8
Chapter 2.HMS39112
Electrical Characteristics
Absolute maximum ratings (Ta = 25 )
Parameter
Symbol
Max. rating
Unit
Supply Voltage
VDD
PD
-0.3 ~ 5.0
700 *
V
Power dissipation
Storage temperature range
Input voltage
mW
Tstg
VIN
-55 ~ 125
-0.3 ~ VDD+0.3
-0.3 ~ VDD+0.3
V
V
Output voltage
VOUT
* Thermal derating above 25
: 6mW per degree
rise in temperature.
Recommended operating condition
Parameter
Symbol
Condition
Rating
Unit
Supply Voltage
VDD
2.4MHz ~ 4MHz
-
2.0 ~ 3.6
V
Operating temperature
Topr
-20 ~ +70
2-9
Chapter 2.HMS39112
Electrical characteristics (Ta=25 , VDD= 3V)
Limits
Parameter
Symbol
Unit
Condition
Min.
Typ. Max.
1
uA
VI=VDD
IIH
-
-
Input H current
RPU1
RPU2
VI=GND
K Pull-up Resistance
R Pull-up Resistance
300
300
70
70
140
140
VI=GND, Output off
RFD
VIH1
VIL1
Feedback Resistance
3.0
-
0.3
1.0
-
VOSC1=GND, VOSC2=VDD
-
V
V
V
V
V
2.1
K, R input H voltage
K, R input L voltage
0.9
-
-
-
-
-
0.4
0.9
-
I
OL=3mA
VOL2*1
0.15
0.4
D. R output L voltage
OSC2 output L voltage
IOL=150uA
IOH=-150uA
VOL3
VOH3
2.1
0.5
2.5
1.1
OSC2 output H voltage
3
mA
mA
VOL1=0.4V
REMOUT output L current
IOL1*2
-30
VOH1=2V
-5
-15
REMOUT output H current
IOH1*3
IOLK2
1
1
uA
uA
-
-
-
-
-
V0UT=VDD, Output off
At STOP mode
fOSC=4MHz
D, R output leakage current
Current on STOP mode
ISTP
1.5
mA
IDD *4
0.5
Operating supply current
System clock
fOSC/48
MHZ version
4
MHz
fOSC
2.4
-
frequency
*1 Refer to Fig.2-6 < IOL2 vs. VOL2 Graph>
*2 Refer to Fig.2-7 < IOL1 vs. VOL1 Graph>
*3 Refer to Fig.2-8 < IOH1 vs. VOH1 Graph>
*4 IDD is measured at RESET mode.
2-10
Chapter 2.HMS39112
Fig 2-6. IOL2 vs. VOL2 Graph. ( D, R Port )
Fig 2-7. IOL1 vs VOL1 Graph (REMOUT Port)
2-11
Chapter 2.HMS39112
Fig 2-8. IOH1 vs VOH1 Graph (REMOUT Port)
2-12
HMS38112
1
2
3
4
5
HMS39112
ARCHITECTURE
INSTRUCTION
APPLICATION
Chapter 3. Architecture
CHAPTER 3. Architecture
Program Memory
The HMS38112/39112 can incorporate maximum 1,024 words (64 words 16
pages 8bits) for program memory. Program counter PC (A0~A5) and page
address register (A6~A9) are used to address the whole area of program memory
having an instruction (8bits) to be next executed.
The program memory consists of 64 words on each page, and thus each page
can hold up to 64 steps of instructions.
The program memory is composed as shown below.
Program capacity (pages)
0
1
2
3
4
8
5
6
Page 0
Page 1
Page 2
Page 15
6
63
0
1
2
15
A0~A5
A6~A9
Program counter (PC)
6
Page address register (PA)
Page buffer (PB)
4
4
Stack register
(Level "1")
(Level "2")
(Level "3")
(SR)
(PSR)
Fig 3-1 Configuration of Program Memory
3-1
Chapter 3. Architecture
Address Register
The following registers are used to address the ROM.
• Page address register (PA) :
Holds ROM's page number (0~Fh) to be addressed.
• Page buffer register (PB) :
Value of PB is loaded by an LPBI command when newly addressing a page.
Then it is shifted into the PA when rightly executing a branch instruction (BR)
and a subroutine call (CAL).
• Program counter (PC) :
Available for addressing word on each page.
• Stack register (SR) :
Stores returned-word address in the subroutine call mode.
(1) Page address register and page buffer register :
Address one of pages #0 to #15 in the EPROM by the 4-bit binary counter.
Unlike the program counter, the page address register is usually unchanged so
that the program will repeat on the same page unless a page changing command
is issued. To change the page address, take two steps such as (1) writing in the
page buffer what page to jump (execution of LPBI) and (2) execution of BR or CAL,
because instruction code is of eight bits so that page and word can not be specified
at the same time.
In case a return instruction (RTN) is executed within the subroutine that has been
called in the other page, the page address will be changed at the same time.
(2) Program counter :
This 6-bit binary counter increments for each fetch to address a word in the
currently addressed page having an instruction to be next executed.
For easier programming, at turning on the power, the program counter is
reset to the zero location. The PA is also set to "0". Then the program
counter specifies the next address in random sequence.
When BR, CAL or RTN instructions are decoded, the switches on each step
are turned off not to update the address. Then, for BR or CAL, address
data are taken in from the instruction operands (a0 to a5), or for RTN, and
address is fetched from stack register No. 1.
(3) Stack register :
This stack register provides two stages each for the program counter (6bits)
and the page address register (4bits) so that subroutine nesting can be
made on two levels.
3-2
Chapter 3. Architecture
Data Memory (RAM)
Up to 32 nibbles (16 words 2pages 4bits) is incorporated for storing data.
The whole data memory area is indirectly specified by a data pointer (X,Y). Page
number is specified by zero bit of X register, and words in the page by 4 bits in
Y-register. Data memory is composed in 16 nibbles/page. Figure 4-2 shows the
configuration.
D0
D9 R0 R3 REMOUT
Data memory page (0~1)
Output port
0
1
2
3
Page 0
Page 1
15
4
0
1
a0~a3
Y-register (Y)
X-register (X)
Fig 3-2 Composition of Data Memory
X-register (X)
X-register is consist of 2bit, X0 is a data pointer of page in the RAM,
X1 is reserved.
X1=0
D0
X1=1
Y=0
Y=1
Reserved
Reserved
D1
Table 3-1 Mapping table between X and Y register
Y-register (Y)
Y-register has 4 bits. It operates as a data pointer or a general-purpose register.
Y-register specifies an address (a0~a3) in a page of data memory, as well as it
is used to specify an output port. Further it is used to specify a mode of carrier
signal outputted from the REMOUT port. It can also be treated as a general-
purpose register on a program.
3-3
Chapter 3. Architecture
Accumulator (ACC)
The 4-bit register for holding data and calculation results.
Arithmetic and Logic Unit (ALU)
In this unit, 4bits of adder/comparator are connected in parallel as it's main
components and they are combined with status latch and status logic (flag.)
(1) Operation circuit (ALU) :
The adder/comparator serves fundamentally for full addition and data
comparison. It executes subtraction by making a complement by processing
an inversed output of ACC (ACC+1)
(2) Status logic :
This is to bring an ST, or flag to control the flow of a program. It occurs when
a specified instruction is executed in three cases such as overflow or underflow
in operation and two inputs unequal.
State Counter (SC)
A fundamental machine cycle timing chart is shown below. Every instruction is
one byte length. Its execution time is the same. Execution of one instruction
takes 6 clocks for fetch cycle and 6 clocks for execute cycle (12 clocks in total).
Virtually these two cycles proceed simultaneously, and thus it is apparently
completed in 6 clocks (one machine cycle). Exceptionally BR, CAL and RTN
instructions is normal execution time since they change an addressing sequentially.
Therefore, the next instruction is prefetched so that its execution is completed
within the fetch cycle.
T2
T1
T3 T4 T5 T6 T1 T2 T3 T4 T5 T6
Fetch cycle N
Execute cycle N
Fetch cycle N-1
Execute cycle N-1
Phase
Phase
Phase
Machine
Cycle
Machine
Cycle
Fig. 3-3 Fundamental timing chart
3-4
Chapter 3. Architecture
Clock Generator
The HMS38112/39112 have an internal clock oscillator. The oscillator circuit is
designed to operate with an external ceramic resonator.
Oscillator circuit is able to organize by connecting
ceramic resonator to outside.
* It is necessary to connect capacitor to outside in order to change ceramic resonator,
you must refer to a manufacturer`s resonator matching guide.
OSC1
OSC2
2
3
C1
C2
* All type have the built-in loading capacitors.
3-5
Chapter 3. Architecture
Pulse Generator
The following frequency and duty ratio are selected for carrier signal outputted
from the REMOUT port depending on a PMR (Pulse Mode Register) value set in
a program.
T
T1
PMR
REMOUT signal
T1/T = 1/2
0
T=1/fPUL = 96/fOSC
T=1/fPUL = 96/fOSC
T=1/fPUL = 64/fOSC
T=1/fPUL = 64/fOSC
T=1/fPUL = 88/fOSC
,
,
,
,
,
1
T1/T = 1/3
2
T1/T = 1/2
3
T1/T = 1/4
4
T1/T = 4/11
5
No Pulse (same to D0 ~ D9)
T=1/fPUL = 96/fOSC
No pulse (same to D0 ~ D9)
6
,
T1/T = 1/4
7
* Default value is "0"
Table 3-2 PMR selection table
3-6
Chapter 3. Architecture
Reset Operation
HMS38112/39112 have three reset sources. One is a built-in Power-on reset circuit, another
is a built-in Low VDD Detection circuit, the other is the overflow of Watch Dog Timer
(WDT). All reset operations are internal in the HMS38112.
Built-in Power On Reset Circuit
HMS38112/39112 has a built-in Power-on reset circuit consisting of an about
1
Resistor and a 3pF Capacitor. When the Power-on reset pulse occurs,
system reset signal is latched and WDT is cleared. After the overflow time of WDT
(213 x System clock time), system reset signal is released.
VDD
1
Counter
System
(WDT)
RESETB
3pF
GND
<HMS38/39XXX>
VCC
System
RESETB
treset
About 108msec at
fosc = 3.64MHz
Fig. 3-4 Power-On Reset Circuit and Timing Chart
3-7
Chapter 3. Architecture
Built-in Low VDD Reset Circuit
HMS38112/39112 have a Low VDD detection circuit.
If VDD become Reset Voltage of Low VDD Detection circuit at a active status,
system reset occur and WDT is cleared.
After VDD is increased upper Reset Voltage again, WDT is re-counted and
if WDT is overflowed, system reset is released.
VDD
Reset Voltage
Internal
RESETB
About 108msec at fosc =3.64MHz
Fig. 3-5 Low Voltage Detection diagram
3-8
Chapter 3. Architecture
Watch Dog Timer (WDT)
Watch dog timer is organized binary of 14 steps. The signal of fOSC/48 cycle comes
in the first step of WDT after WDT reset. If this counter was overflowed, reset
signal automatically come out so that internal circuit is initialized.
The overflow time is 8 6 213/fOSC (108.026ms at fOSC = 3.64MHz)
Normally, the binary counter must be reset before the overflow by using reset
instruction (WDTR), Power-on reset pulse or Low VDD detection pulse.
* It is constantly reset in STOP mode. When STOP is released, counting is
restarted. (Refer to STOP Operation>)
Binary counter(14 steps)
fOSC/48
RESET (edge-trigger)
CPU reset
Reset
by instruction
Power-On Reset
Low VDD Detection
Fig 3-6 Block Diagram of Watch-dog Timer
3-9
Chapter 3. Architecture
STOP Operation
Stop mode can be achieved by STOP instructions.
In stop mode :
1. Oscillator is stopped, the operating current is low.
2. Watch dog timer is reset, D0~D3 output and REMOUT output are "L" .
3. Part other than WDT, D0~D3 output and REMOUT output have a value before
come into stop mode.
Stop mode is released when one of K or R input is going to "L".
1. State of D0~D3 output and REMOUT output is return to state of before stop mode
is achieved.
2. After 210 System clock time for stable oscillating, first instruction start to operate.
3. In return to normal operation, WDT is counted from zero again.
But, at executing stop instruction, if one of K or R input is chosen to "L", stop instruction
is same to NOP instruction.
3-10
HMS38112
1
2
3
4
5
HMS39112
ARCHITECTURE
INSTRUCTION
APPLICATION
Chapter 4. Instruction
CHAPTER 4. Instruction
INSTRUCTION FORMAT
All of the 43 instruction in HMS38112/39112 is format in two fields of OP
code and operand which consist of eight bits. The following formats are available
with different types of operands.
*Format
All eight bits are for OP code without operand.
*Format
Two bits are for operand and six bits for OP code.
Two bits of operand are used for specifying bits of RAM and X-register (bit 1 and
bit 7 are fixed at 0 )
*Format
Four bits are for operand and the others are OP code.
Four bits of operand are used for specifying a constant loaded in RAM or Y-
register, a comparison value of compare command, or page addressing in ROM.
*Format
Six bits are for operand and the others are OP code.
Six bits of operand are used for word addressing in the ROM.
4-1
Chapter 4. Instruction
INSTRUCTION TABLE
The HMS38112/39112 provides the following 43 basic instructions.
Category Mnemonic Function
ST*1
S
S
S
S
S
S
S
S
S
S
S
S
S
E
S
S
S
S
C
B
C
B
S
C
B
1
LAY
LYA
A
Y
A
Y
A
0
Register to
Register
2
3
LAZ
4
LMA
LMAIY
LYM
LAM
XMA
LYI i
LMIIY i
LXI n
SEM n
REM n
TM n
BR a
CAL a
RTN
LPBI i
AM
M(X,Y)
M(X,Y)
A
5
A, Y
M(X,Y)
M(X,Y)
Y+1
RAM to
Register
6
Y
A
A
Y
7
8
M(X,Y)
i
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
M(X,Y)
i, Y
Y+1
Immediate
X
n
M(n)
M(n)
1
RAM Bit
Manipulation
0
TEST M(n) = 1
if ST = 1 then Branch
if ST = 1 then Subroutine call
Return from Subroutine
ROM
Address
PB
A
i
A + M(X,Y)
M(X,Y) - A
M(X,Y) + 1
M(X,Y) - 1
A + 1
SM
A
IM
A
Arithmetic
DM
A
IA
A
IY
Y
Y + 1
DA
A
A - 1
4-2
Chapter 4. Instruction
Category Mnemonic
Function
ST*1
B
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DY
Y
A
A
Y - 1
Arithmetic
EORM
A + M (X,Y)
A + 1
S
NEGA
ALEM
ALEI i
MNEZ
Z
TEST A M(X,Y)
TEST A
TEST M(X,Y)
E
i
E
0
N
Comparison
YNEA
YNEI i
KNEZ
RNEZ
LAK
TEST Y
TEST Y
TEST K
TEST R
A
i
N
N
0
0
N
N
A
A
K
R
S
LAR
S
Input /
Output
Output(Y)
Output(Y)
1 at HMS39112, 0 at HMS38112
0 at HMS39112, 1 at HMS39112
SO
S
S
S
S
S
S
RO
WDTR
STOP
LPY
Watch Dog Timer Reset
Stop operation
Control
PMR
Y
NOP
No operation
Note) i = 0~f, n = 0~3, a = 6bit PC Address
*1 Column ST indicates conditions for changing status. Symbols have the following
meanings
S : On executing an instruction, status is unconditionally set.
C : Status is only set when carry or borrow has occurred in operation.
B : Status is only set when borrow has not occurred in operation.
E : Status is only set when equality is found in comparison.
N : Status is only set when equality is not found in comparison.
Z : Status is only set when the result is zero.
4-3
Chapter 4. Instruction
Port Operation
Value of X-reg
0 or 1
Value of Y-reg
Operation
1(High-Z)
SO : D(Y)
RO : D(Y)
0 ~ 6
0
REMOUT port repeats "H" and "L" in pulse frequency.
(When PMR = 5, it is fixed at "H")
SO : REMOUT(PMR)
RO : REMOUT(PMR)
1 at HMS39112, 0 at HMS38112
0 at HMS39112, 1 at HMS38112
0 or 1
8
0 or 1
0 or 1
0 or 1
0 or 1
9
C ~ D
E
SO : D0 ~ D6 1 (High-Z)
RO : D0 ~ D6
0
SO : R(Y-Ah)
RO : R(Y-Ah)
1
0
SO : R2 ~ R3
RO : R2 ~ R3
1
0
F
SO : D0 ~ D6
RO : D0 ~ D6
1(High-Z), R2 ~ R3
0, R2 ~ R3
1
0
4-4
Chapter 4. Instruction
DETAILS OF INSTRUCTION SYSTEM
All 43 basic instructions of the HMS38112/39112 are one by one described
in detail below.
Description Form
Each instruction is headlined with its mnemonic symbol according to the
instructions table given earlier.
Then, for quick reference, it is described with basic items as shown below. After
that, detailed comment follows.
• Items :
- Naming :
- Status :
- Format :
- Operand :
- Function
Full spelling of mnemonic symbol
Check of status function
Categorized into
to
Omitted for Format
4-5
Chapter 4. Instruction
(1) LAY
Naming :
Status :
Format :
Function :
<Comment>
Load Accumulator from Y-Register
Set
I
A
Y
Data of four bits in the Y-register is unconditionally transferred
to the accumulator. Data in the Y-register is left unchanged.
(2) LYA
Naming :
Status :
Format :
Function :
<Comment>
Load Y-register from Accumulator
Set
I
Y
A
Load Y-register from Accumulator
(3) LAZ
Naming :
Status :
Format :
Function :
<Comment>
Clear Accumulator
Set
I
A
0
Data in the accumulator is unconditionally reset to zero.
(4) LMA
Naming :
Status :
Format :
Load Memory from Accumulator
Set
I
Function :
<Comment>
M(X,Y)
A
Data of four bits from the accumulator is stored in the RAM
location addressed by the X-register and Y-register. Such data
is left unchanged.
(5) LMAIY
Naming :
Status :
Load Memory from Accumulator and Increment Y-Register
Set
I
Format :
Function :
<Comment>
M(X,Y)
A, Y
Y+1
Data of four bits from the accumulator is stored in the RAM
location addressed by the X-register and Y-register. Such data
is left unchanged.
4-6
Chapter 4. Instruction
(6) LYM
Naming :
Load Y-Register form Memory
Status :
Format :
Set
I
Function :
<Comment>
Y
M(X,Y)
Data from the RAM location addressed by the X-register and
Y-register is loaded into the Y-register. Data in the memory is
left unchanged.
(7) LAM
Naming :
Status :
Format :
Load Accumulator from Memory
Set
I
Function :
<Comment>
A
M(X,Y)
Data from the RAM location addressed by the X-register and
Y-register is loaded into the Y-register. Data in the memory is
left unchanged.
(8) XMA
Naming :
Status :
Format :
Exchanged Memory and Accumulator
Set
I
Function :
<Comment>
M(X,Y)
A
Data from the memory addressed by X-register and Y-register
is exchanged with data from the accumulator. For example,
this instruction is useful to fetch a memory word into the
accumulator for operation and store current data from the
accumulator into the RAM. The accumulator can be restored
by another XMA instruction.
(9) LYI i
Naming :
Status :
Load Y-Register from Immediate
Set
Format :
Operand :
Function :
<Purpose>
Constant 0
i
15
Y
i
To load a constant in Y-register. It is typically used to specify
Y-register in a particular RAM word address, to specify the
address of a selected output line, to set Y-register for
specifying a carrier signal outputted from OUT port, and to
initialize Y-register for loop control. The accumulator can be
restored by another XMA instruction.
<Comment>
Data of four bits from operand of instruction is transferred to
the Y-register.
4-7
Chapter 4. Instruction
(10) LMIIY i
Naming :
Status :
Load Memory from Immediate and Increment Y-Register
Set
Format :
Operand :
Function :
<Comment>
Constant 0
M(X,Y)
i
15
i, Y
Y + 1
Data of four bits from operand of instruction is stored into the
RAM location addressed by the X-register and Y-register.
Then data in the Y-register is incremented by one.
(11) LXI n
Naming :
Status :
Load X-Register from Immediate
Set
Format :
Operand :
Function :
<Comment>
X file address 0
n
3
X
n
A constant is loaded in X-register. It is used to set X-register in
an index of desired RAM page. Operand of 1 bit of command
is loaded in X-register.
(12) SEM n
Naming :
Status :
Set Memory Bit
Set
Format :
Operand :
Function :
<Comment>
Bit address 0
M(X,Y,n)
n
3
1
Depending on the selection in operand of operand, one of four
bits is set as logic 1 in the RAM memory addressed in
accordance with the data of the X-register and Y-register.
(13) REM n
Naming :
Status :
Reset Memory Bit
Set
Format :
Operand :
Function :
<Comment>
Bit address 0
M(X,Y,n)
n
3
0
Depending on the selection in operand of operand, one of four
bits is set as logic 0 in the RAM memory addressed in
accordance with the data of the X-register and Y-register.
4-8
Chapter 4. Instruction
(14) TM n
Naming :
Test Memory Bit
Status :
Comparison results to status
Format :
Operand :
Function :
Bit address 0
M(X,Y,n)
n
3
1?
ST
1 when M(X,Y,n)=1, ST
0 when M(X,Y,n)=0
<Purpose>
A test is made to find if the selected memory bit is logic. 1
Status is set depending on the result.
(15) BR a
Naming :
Status :
Branch on status 1
Conditional depending on the status
Format :
Operand :
Function :
Branch address a (Addr)
When ST =1 , PA
When ST = 0, PC
PB, PC
PC + 1, ST
a(Addr)
1
Note : PC indicates the next address in a fixed sequence that
is actually pseudo-random count.
<Purpose>
For some programs, normal sequential program execution can
be change.
A branch is conditionally implemented depending on the status
of results obtained by executing the previous instruction.
<Comment>
• Branch instruction is always conditional depending on the
status.
a. If the status is reset (logic 0), a branch instruction is not
rightly executed but the next instruction of the sequence is
executed.
b. If the status is set (logic 1), a branch instruction is executed
as follows.
• Branch is available in two types - short and long. The former
is for addressing in the current page and the latter for
addressing in the other page. Which type of branch to exeute
is decided according to the PB register. To execute a long
branch, data of the PB register should in advance be modified
to a desired page address through the LPBI instruction.
4-9
Chapter 4. Instruction
(16) CAL a
Naming :
Status :
Subroutine Call on status 1
Conditional depending on the status
Format :
Operand :
Function :
Subroutine code address a(Addr)
When ST =1 , PC
SR1
a(Addr)
PC + 1,
SR1
PA
PB
PA
PSR1
PSR2
PSR1
PSR2
PSR3
PB
SR2
SR3
SR2
When ST = 0 PC
PC + 1
PS ST
1
Note : PC actually has pseudo-random count against the next
instruction.
<Comment>
• In a program, control is allowed to be transferred to a mutual
subroutine. Since a call instruction preserves the return
address, it is possible to call the subroutine from different
locations in a program, and the subroutine can return control
accurately to the address that is preserved by the use of the
call return instruction (RTN).
Such calling is always conditional depending on the status.
a. If the status is reset, call is not executed.
b. If the status is set, call is rightly executed.
The subroutine stack (SR) of three levels enables a subroutine
to be manipulated on three levels. Besides, a long call (to call
another page) can be executed on any level.
• For a long call, an LPBI instruction should be executed before
the CAL. When LPBI is omitted (and when PA=PB), a short
call (calling in the same page) is executed.
4-10
Chapter 4. Instruction
(17) RTN
Naming :
Return from Subroutine
Set
Status :
Format :
Function :
PC
SR1
SR2
SR3
SR3
PA, PB
PSR1
PSR2
PSR3
ST
PSR1
PSR2
PSR3
PSR2
1
SR1
SR2
SR3
<Purpose>
Control is returned from the called subroutine to the calling
program.
<Comment>
Control is returned to its home routine by transferring to the PC
the data of the return address that has been saved in the stack
register (SR1).
At the same time, data of the page stack register (PSR1) is
transferred to the PA and PB.
(18) LPBI i
Naming :
Status :
Load Page Buffer Register from Immediate
Set
Format :
Operand :
Function :
<Purpose>
ROM page address 0
PB
A new ROM page address is loaded into the page buffer
register (PB).
i
15
i
This loading is necessary for a long branch or call instruction.
The PB register is loaded together with three bits from 4 bit
operand.
<Comment>
(19) AM
Naming :
Status :
Add Accumulator to Memory and Status 1 on Carry
Carry to status
Format :
Function :
A
M(X,Y)+A, ST
ST
1(when total>15),
0 (when total 15)
<Comment>
Data in the memory location addressed by the X and Y-register
is added to data of the accumulator. Results are stored in the
accumulator. Carry data as results is transferred to status.
When the total is more than 15, a carry is caused to put 1
in the status. Data in the memory is not changed.
4-11
Chapter 4. Instruction
(20) SM
Naming :
Status :
Subtract Accumulator to Memory and Status 1 Not Borrow
Carry to status
Format :
Function :
A
M(X,Y) - A
ST
ST
1(when A M(X,Y))
0(when A > M(X,Y))
<Comment>
Data of the accumulator is, through a 2`s complemental
addition, subtracted from the memory word addressed by the
Y-register. Results are stored in the accumulator. If data of
the accumulator is less than or equal to the memory word, the
status is set to indicate that a borrow is not caused.
If more than the memory word, a borrow occurs to reset the
status to 0 .
(21) IM
Naming :
Increment Memory and Status 1 on Carry
Carry to status
Status :
Format :
Function :
A
M(X,Y) + 1
ST
ST
1(when M(X,Y) 15)
0(when M(X,Y) < 15)
<Comment>
Data of the memory addressed by the X and Y-register is
fetched. Adding 1 to this word, results are stored in the
accumulator. Carry data as results is transferred to the status.
When the total is more than 15, the status is set. The memory
is left unchanged.
(22) DM
Naming :
Decrement Memory and Status 1 on Not Borrow
Carry to status
Status :
Format :
Function :
A
M(X,Y) - 1
ST
ST
1(when M(X,Y) 1)
0 (when M(X,Y) = 0)
<Comment>
Data of the memory addressed by the X and Y-register is
fetched, and one is subtracted from this word (addition of Fh)>
Results are stored in the accumulator. Carry data as results is
transferred to the status. If the data is more than or equal to
one, the status is set to indicate that no borrow is caused. The
memory is left unchanged.
4-12
Chapter 4. Instruction
(23) IA
Naming :
Increment Accumulator
Set
Status :
Format :
Function :
<Comment>
A
A+1
Data of the accumulator is incremented by one. Results are
returned to the accumulator.
A carry is not allowed to have effect upon the status.
(24) IY
Naming :
Status :
Increment Y-Register and Status 1 on Carry
Carry to status
Format :
Function :
Y
Y + 1
ST
ST
1 (when Y = 15)
0 (when Y < 15)
<Comment>
Data of the Y-register is incremented by one and results are
returned to the Y-register.
Carry data as results is transferred to the status. When the
total is more than 15, the status is set.
(25) DA
Naming :
Status :
Decrement Accumulator and Status 1 on Borrow
Carry to status
Format :
Function :
A
A - 1
ST
ST
1(when A 1)
0 (when A = 0)
<Comment>
Data of the accumulator is decremented by one. As a result
(by addition of Fh), if a borrow is caused, the status is reset to
0 by logic. If the data is more than one, no borrow occurs
and thus the status is set to 1 .
4-13
Chapter 4. Instruction
(26) DY
Naming :
Status :
Decrement Y-Register and Status 1 on Not Borrow
Carry to status
Format :
Function :
Y
Y -1
ST
ST
1 (when Y 1)
0 (when Y = 0)
<Purpose>
<Comment>
Data of the Y-register is decremented by one.
Data of the Y-register is decremented by one by addition of
minus 1 (Fh).
Carry data as results is transferred to the status. When the
results is equal to 15, the status is set to indicate that no
borrow has not occurred.
(27) EORM
Naming :
Status :
Exclusive or Memory and Accumulator
Set
Format :
Function :
<Comment>
A
M(X,Y) + A
Data of the accumulator is, through a Exclusive OR,
subtracted from the memory word addressed by X and Y-
register. Results are stored into the accumulator.
(28) NEGA
Naming :
Status :
Negate Accumulator and Status 1 on Zero
Carry to status
Format :
Function :
A
A + 1
ST
ST
1(when A = 0)
0 (when A != 0)
<Purpose>
<Comment>
The 2`s complement of a word in the accumulator is obtained.
The 2`s complement in the accumulator is calculated by adding
one to the 1`s complement in the accumulator. Results are
stored into the accumulator. Carry data is transferred to the
status. When data of the accumulator is zero, a carry is
caused to set the status to 1 .
4-14
Chapter 4. Instruction
(29) ALEM
Naming :
Accumulator Less Equal Memory
Carry to status
Status :
Format :
Function :
A
M(X,Y)
ST
ST
1 (when A M(X,Y))
0 (when A > M(X,Y))
<Comment>
Data of the accumulator is, through a complemental addition,
subtracted from data in the memory location addressed by the
X and Y-register. Carry data obtained is transferred to the
status. When the status is 1 , it indicates that the data of
the accumulator is less than or equal to the data of the
memory word. Neither of those data is not changed.
(30) ALEI
Naming :
Status :
Accumulator Less Equal Immediate
Carry to status
Format :
Function :
A
i
ST
ST
1 (when A i)
0 (when A > i)
<Purpose>
Data of the accumulator and the constant are arithmetically
compared.
<Comment>
Data of the accumulator is, through a complemental addition,
subtracted from the constant that exists in 4bit operand. Carry
data obtained is transferred to the status. The status is set
when the accumulator value is less than or equal to the
constant. Data of the accumulator is left unchanged.
(31) MNEZ
Naming :
Memory Not Equal Zero
Status :
Comparison results to status
Format :
Function :
M(X,Y)
0
ST
ST
1(when M(X,Y) 0)
0 (when M(X,Y) = 0)
<Purpose>
A memory word is compared with zero.
<Comment>
Data in the memory addressed by the X and Y-register is
logically compared with zero. Comparison data is thransferred
to the status. Unless it is zero, the status is set.
4-15
Chapter 4. Instruction
(32) YNEA
Naming :
Status :
Y-Register Not Equal Accumulator
Comparison results to status
Format :
Function :
Y
A
ST
ST
1 (when Y A)
0 (when Y = A)
<Purpose>
Data of Y-register and accumulator are compared to check if
they are not equal.
<Comment>
Data of the Y-register and accumulator are logically compared.
Results are transferred to the status. Unless they are equal,
the status is set.
(33) YNEI
Naming :
Status :
Y-Register Not Equal Immediate
Comparison results to status
Format :
Operand :
Function :
Constant 0
i
15
Y
i
ST
ST
1 (when Y i)
0 (when Y = i)
<Comment>
The constant of the Y-register is logically compared with 4bit
operand. Results are transferred to the status. Unless the
operand is equal to the constant, the status is set.
(34) KNEZ
Naming :
Status :
K Not Equal Zero
The status is set only when not equal
Format :
Function :
<Purpose>
<Comment>
When K 0, ST
A test is made to check if K is not zero.
Data on K are compared with zero. Results are transferred to
the status. For input data not equal to zero, the status is set.
1
(35) RNEZ
Naming :
Status :
R Not Equal Zero
The status is set only when not equal
Format :
Function :
<Purpose>
<Comment>
When R 0, ST
A test is made to check if R is not zero.
Data on R are compared with zero. Results are transferred to
the status. For input data not equal to zero, the status is set.
1
4-16
Chapter 4. Instruction
(36) LAK
Naming :
Load Accumulator from K
Set
Status :
Format :
Function :
<Comment>
A
K
Data on K are transferred to the accumulator
(37) LAR
Naming :
Status :
Load Accumulator from R
Set
Format :
Function :
<Comment>
A
R
Data on R are transferred to the accumulator
(38) SO
Naming :
Status :
Set Output Register Latch
Set
Format :
Function :
D(Y)
1
0
Y
7
REMOUT
D0~D9
1(PMR=5)
1 (High-Z)
Y = 8
Y = 9
Ah
Y = Eh
Y = Fh
R(Y)
R
1
Y
Dh
1
D0~D9, R
1
<Purpose>
A single D output line is set to logic 1, if data of Y-register is
between 0 to 7.
Carrier frequency come out from REMOUT port, if data of
Y-register is 8.
All D output line is set to logic 1, if data of Y-register is 9.
It is no operation, if data of Y-register between 10 to 15.
When Y is between Ah and Dh, one of R output lines is set at
logic 1.
When Y is Eh, the output of R is set at logic 1.
When Y is Fh, the output D0~D9 and R are set at logic 1.
Data of Y-register is between 0 to 7, selects appropriate D
output.
<Comment>
Data of Y-register is 8, selects REMOUT port.
Data of Y-register is 9, selects all D port.
Data in Y-register, when between Ah and Dh, selects an
appropriate R output (R0~R3).
Data in Y-register, when it is Eh, selects all of R0~R3.
Data in Y-register, when it is Fh, selects all of D0~D9 and
R0~R3.
4-17
Chapter 4. Instruction
(39) RO
Naming :
Status :
Reset Output Register Latch
Set
Format :
Function :
D(Y)
0
0
Y
7
REMOUT
D0~D9
0
Y = 8
Y = 9
Ah
Y = Eh
Y = Fh
0
R(Y)
R
0
Y
Dh
0
D0~D9, R
0
<Purpose>
A single D output line is set to logic 0, if data of Y-register is
between 0 to 9.
REMOUT port is set to logic 0, if data of Y-register is 9.
All D output line is set to logic 0, if data of Y-register is 9.
When Y is between Ah and Dh, one of R output lines is set at
logic 0.
When Y is Eh, the output of R is set at logic 0
When Y is Fh, the output D0~D9 and R are set at logic 1.
Data of Y-register is between 0 to 7, selects appropriate D
output.
<Comment>
Data of Y-register is 8, selects REMOUT port.
Data of Y-register is 9, selects D port.
Data in Y-register, when between Ah and Dh, selects an
appropriate R output (R0~R3).
Data in Y-register, when it is Eh, selects all of R0~R3.
Data in Y-register, when it is Fh, selects all of D0~D9 and
R0~R3.
(40) WDTR
Naming :
Status :
Watch Dog Timer Reset
Set
Format :
Function :
<Purpose>
Reset Watch Dog Timer (WDT)
Normally, you should reset this counter before overflowed
counter for dc watch dog timer. this instruction controls this
reset signal.
4-18
Chapter 4. Instruction
(41) STOP
Naming :
STOP
Set
Status :
Format :
Function :
<Purpose>
Operate the stop function
Stopped oscillator, and little current.
(See 1-12 page, STOP function.)
(42) LPY
Naming :
Status :
Pulse Mode Set
Set
Format :
Function :
<Comment>
PMR
Y
Selects a pulse signal outputted from REMOUT port.
(43) NOP
Naming :
Status :
No Operation
Set
Format :
Function :
No operation
4-19
HMS38112
1
2
3
4
5
HMS39112
ARCHITECTURE
INSTRUCTION
APPLICATION
Chapter 5. Application
Guideline for S/W
1. All rams need to be initialized to zero in reset address for proper design.
2. Make the output ports `H` after reset.
3. Do not use WDTR instruction in subroutine.
4. Before reading the input port the waiting time should be more than 200uS.
5. To decrease current consumption, make the output port as high in normal routine except
for key scan strobe and STOP mode.
6. We recommend you do not use all 64 bytes in a page. You had better write ` BR $` in
unused area. This will help you prevent unusual operation of MCU.
7. Be careful not to use long call or branch (CALL,BL) with arithmetic manipulation.
If you want to use branch right after arithmetic manipulation, the long call or branch will be
against your intention.
ex)
LAR
; The value of R ports -> Accumulator
14 : S = 0
ALEI 14 ; A 14 : S = 1,
A
BL TRUE ; S is always 1 because BL is composed of LPBI and BR.
-------------- Fail
LAR
ALEI 14 ; A 14 : S = 1,
BR TRUE ; When S is 1 Branch will occur. Otherwise Branch will not occur and
LAK ; next instruction will be operated.
-------------- Right
; The value of R ports -> Accumulator
A
14 : S = 0
5-1
Chapter 5. Application
HMS38112 Circuit Diagram
4
5
3
41
42
K0
K1
K2
K3
R0
R1
R2
R3
33
34
25
26
17
18
9
1
2
OSC2
10
2
1
OSC1
GND
6
43
44
35
36
27
28
19
20
11
12
3
4
We recommend
alkaline battery
7
8
+
45
46
47
48
37
38
39
40
29
30
31
32
21
22
23
24
13
14
15
16
5
6
7
8
Vdd 20
9
10
11
12
19
REM
OUT
D0
D1
D2
D3
D4
D5
18
PGND
13
14
15
16
17
=
5-2
Chapter 5. Application
HMS39112 Circuit Diagram
4
5
3
41
42
K0
K1
K2
K3
R0
R1
R2
R3
33
34
25
26
17
18
9
1
2
49
50
OSC2
10
2
1
OSC1
GND
6
43
44
35
36
27
28
19
20
11
12
3
4
51
52
We recommend
alkaline battery
7
8
+
45
46
47
48
37
38
39
40
29
30
31
32
21
22
23
24
13
14
15
16
5
6
7
8
53
54
55
56
Vdd 20
9
10
11
12
REM
OUT
19
D0
D1
D2
D3
D4
D5
D6
13
14
15
16
17
18
=
5-3
Chapter 5. Application
Truth Table for example program
CUSTOM:04H
5-4
Chapter 5. Application
Output waveform of uPD6121G
A single pulse, modulated with 37.917KHz signal at 3.64MHz
Tc
Carrier frequency
fCAR = 1/Tc = fOSC/96
Duty ratio = T1/Tc = 1/3
T1
- Configuration of Flame
1st flame
Lead code
Custom code
Custom code
Data code
Data code
9ms
4.5ms
C0 C1 C2 C3 C4 C5 C6 C7 C0 C1 C2 C3 C4 C5 C6 C7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D5 D7
- Repeat code
0.56ms
9ms
2.25ms
- Bit Description
Bit 0
Bit 1
0.56ms
0.56ms
1.125ms
2.25ms
- Flame Interval : Tf
The transmitted waveform as long as a key is depressed
Tf=108mS
Tf=108mS
5-5
Chapter 5. Application
Example program - uPD6121G
B L
K E Y 1 2
5-6
Chapter 5. Application
5-7
Chapter 5. Application
5-8
Chapter 5. Application
5-9
Chapter 5. Application
5-10
Chapter 5. Application
5-11
Chapter 5. Application
HMS38112 TEST B/D Example
1. Attach resonator to X1
2. Connect base and collector at Q1
3. Connect PGND and TRGND with jumper at E
E
D6
PGND
C
B
E
TRGND
Q1
R3 R2 R1
X1
REMOUT
TROUT
OSC
C
D
GND
DS1
DS2
SW57~64 SW49~56
A
B
K0K1K2K3R0R1R2R3
K0K1K2K3R0R1R2R3
D4D5D6D8 D5D6D7D9
D6D7D8D9 D6D7D8D9
K0
1
K1 K2
K3
R0 R1 R2 R3
2
3
4
5
6
7
8
D0
D1
D2
D3
D4
D5
9
10
18
26
34
42
50
58
11
19
27
35
43
51
59
12
20
28
36
44
52
60
13
21
29
37
45
53
61
14
22
30
38
46
54
62
15
23
31
39
47
55
63
16
24
32
40
48
56
64
17
25
33
41
49
57
* DS1 is connected to A. If D6 switch is on among DS1 , A becomes D6 port.
* DS2 is connected to B. If D7 switch is on among DS2 , B becomes D7 port.
* If D6 switch among SW49~SW56 is on at D, the key 49~56 can be used as D6 port.
* If D7 switch among SW57~SW64 is on at D, the key 57~64 can be used as D7 port.
* note : the position of SW49~56 and SW57~64 in B/D is changed. The reference position is right.
* If you want to increase the remote controller valid distance, you try to disconnect R2 resistor
and lessen R1 resistor.
5-12
Chapter 5. Application
HMS39112 TEST B/D Example
1. Attach resonator to X1
2. Attach 2222A transistor to Q1
3. Connect PGND and D6 with jumper at E
4. Attach about 150 to R3.
E
D6
PGND
C
B
E
TRGND
Q1
R3 R2 R1
X1
REMOUT
TROUT
OSC
C
D
GND
DS1
DS2
SW57~64 SW49~56
A
B
K0K1K2K3R0R1R2R3
K0K1K2K3R0R1R2R3
D4D5D6D8 D5D6D7D9
D6D7D8D9 D6D7D8D9
K0
1
K1 K2
K3
R0 R1 R2 R3
2
3
4
5
6
7
8
D0
D1
D2
D3
D4
D5
9
10
18
26
34
42
50
58
11
19
27
35
43
51
59
12
20
28
36
44
52
60
13
21
29
37
45
53
61
14
22
30
38
46
54
62
15
23
31
39
47
55
63
16
24
32
40
48
56
64
17
25
33
41
49
57
* DS1 is connected to A. If D6 switch is on among DS1 , A becomes D6 port.
* DS2 is connected to B. If D7 switch is on among DS2 , B becomes D7 port.
* If D6 switch among SW49~SW56 is on at D, the key 49~56 can be used as D6 port.
* If D7 switch among SW57~SW64 is on at D, the key 57~64 can be used as D7 port.
* note : the position of SW49~56 and SW57~64 in B/D is changed. The reference position is right.
* If you want to increase the remote controller valid distance, you try to disconnect R2 resistor
and lessen R1 resistor.
5-13
MASK ORDER & VERIFICATION SHEET
HMS3 112 -R
1. Customer Information
Company Name
Tel:
Fax:
Name & Signature
Order Date
2. Device Information
E-Mail
(
)
File Name
Package
Mask Data
20 DIP
20 SOP
20 SSOP
. RHX
. DMP
Check Sum
@27C256
3. Mask Option
Inclusion of
Pull-up
Register
Port R2 R3
Port K0 K1 K2 K3 R0 R1 R2 R3
Y/N
Release of
Stop mode
Y/N
Status of
D port while
Stop mode
Port D4 D5 D6
a/b
3. a: State of “ L” forcibly, b: Remain the state just before
stop instruction. You must select “a” option when you use
Dport as key application.
4. D6 port is available for HMS38112 but
not available for HMS39112
1. Don’t use WDTR instruction in subroutine.
2. Use Br $ at start (except 0 page ) , end and
unused address in every page.
4. Marking Specification
Standard Marking
User Marking
MagnaChip
User LOGO
R
YWW
R
YWW
5. Delivery Schedule
Date
Quantity
Confirmation
Mask Sample
Risk Order
.
.
.
.
pcs
pcs
6. ROM CODE Verification
MagnaChip Semiconductor Ltd. write in below
Customer write in below
Verification Date :
Approval Date :
.
.
Please confirm our verification data.
I agree with your verification data and confirm
you to make mask set.
Check Sum :
TEL :82-270-4037 FAX :82-270-4075
@27c256
TEL :
FAX :
Company Name :
Name &
Signature
MagnaChip Semiconductor Ltd.
MCU APPLICATION TEAM
Section Name
Signature
:
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