HMS81008_技术文档

HYNIX SEMICONDUCTOR

8-BIT SINGLE-CHIP MICROCONTROLLERS

HMS81004/08/16/24/32E

HMS81020/32TL

User’s Manual (Ver. 2.00)

REVISION HISTORY

VERSION 2.00 (NOV., 2001)

1. Modify the maximum supply voltage on page 12.

2. Add the chapter 17 and 18.

Version 2.00

Published by

SP MCU Application Team

Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors

and Representatives listed at address directory.

Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice.

The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no

way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

HMS81032E/HMS81032TL

1. OVERVIEW............................................1

Description .......................................................1

Features ...........................................................1

Development Tools ..........................................2

14. INTERRUPTS....................................46

Interrupt priority and sources ........................ 47

Interrupt control register ................................ 47

Interrupt accept mode ................................... 48

Interrupt Sequence ........................................ 49

BRK Interrupt ................................................ 51

Multi Interrupt ................................................ 51

External Interrupt ........................................... 51

Key Scan Input Processing ........................... 52

2. BLOCK DIAGRAM ...............................3

3. PIN ASSIGNMENT (Top View) ............4

4. PACKAGE DIMENSION ........................5

5. PIN FUNCTION......................................8

6. PORT STRUCTURES..........................10

15. STANDBY FUNCTION ......................54

Sleep Mode ................................................... 54

Stop Mode ..................................................... 54

Standby mode release .................................. 55

Operation of standby mode release .............. 57

7. ELECTRICAL CHARACTERISTICS....12

Absolute Maximum Ratings ...........................12

Recommended Operating Conditions ............12

DC Electrical Characteristics ..........................12

REMOUT Port Ioh Characteristics Graph ......13

REMOUT Port Iol Characteristics Graph .......14

AC Characteristics .........................................14

16. RESET FUNCTION ...........................59

External RESET ............................................ 59

Power on RESET .......................................... 59

Low voltage detection mode ......................... 61

17. OVERVIEW OF HMS81032TL ..........64

Standard Mode pin assignment ................. 64

PROM Mode pin assignment ..................... 65

Standard Mode Pin Desciption ...................... 66

PROM Mode Pin Description ........................ 67

EPROM Mode ............................................... 68

Timing Diagram in EPROM Mode ................. 71

Programming Flow Chart .............................. 75

REMOUT Port Ioh Characteristics Graph ..... 76

REMOUT Port Iol Characteristics Graph ....... 76

8. MEMORY ORGANIZATION.................16

Registers ........................................................16

Program Memory ...........................................19

Data Memory ..................................................22

List for Control Registers ................................23

Addressing Mode ...........................................25

9. I/O PORTS...........................................29

R0 Ports .........................................................29

R1 Ports .........................................................29

R2 Port ...........................................................31

18. GENERAL CIRCUIT DIAGRAM ........78

General circuit diagram of HMS81032E ........ 78

General circuit diagram of HMS81032TL ..... 79

10. CLOCK GENERATOR.......................32

Oscillation Circuit ...........................................33

A. MASK ORDER SHEET ........................ ii

11. BASIC INTERVAL TIMER..................35

12. WATCH DOG TIMER.........................37

13. Timer0, Timer1, Timer2......................38

B. INSTRUCTION.................................... iii

B.1 Terminology List ....................................... iii

B.2 Instruction Map .........................................iv

B.3 Instruction Set ............................................v

NOV 2001 Ver 2.00

HMS81032E/HMS81032TL

NOV 2001 Ver 2.00

HMS8132E/HMS81032TL

HMS81004E/08E/16E/24E/32E

HMS81020/32TL

CMOS SINGLE- CHIP 8-BIT MICROCONTROLLER

FOR UNIVERSAL REMOTE CONTROLLER

1. OVERVIEW

1.1 Description

The HMS81004E/08E/16E/24E/32E is an advanced CMOS 8-bit microcontroller with 4/8/16/24/32K bytes of ROM. The

device is one of GMS800 family. The HYNIX HMS81004E/08E/16E/24E/32E is a powerful microcontroller which provides

a highly flexible and cost effective solution to many UR applications.The HMS81004E/08E/16E/24E/32E provides the fol-

lowing standard features: 4/8/16/24/32K bytes of ROM, 448 bytes of RAM, 8-bit timer/counter, on-chip oscillator and clock

circuitry. In addition, the HMS81004E/08E/16E/24E/32E supports power saving modes to reduce power consumption.

Device Name

HMS81004E

HMS81008E

HMS81016E

HMS81024E

HMS81032E

HMS81020TL

HMS81032TL

ROM Size

4K Bytes

8K Bytes

16K Bytes

24K Bytes

32K Bytes

-

EPROM Size

RAM Size

Package

-

448 Bytes

(included

256 bytes

20 SOP/PDIP

24 SOP/Skinny DIP

28 SOP/Skinny DIP

-

stack memory)

-

20K Bytes

32K Bytes

-

1.2 Features

• Instruction Cycle Time:

- 1us at 4MHz

- Watch Dog Timer ............ 6Bit * 1ch

• 8 Interrupt sources

- Nested Interrupt control is available.

- External input: 2

• Programmable I/O pins

- Keyscan input

20 PIN

24 PIN

28 PIN

- Basic Interval Timer

- Watchdog timer

- Timer : 3

INPUT

OUTPUT

I/O

3

2

3

2

3

2

13

17

21

• Power On Reset

• Power saving Operation Modes

- STOP Operation

- SLEEP Operation

• Operating Voltage

- 2.0 ~ 3.6 V @ 4MHz (MASK)

- 2.0 ~ 4.0 V @ 4MHZ (OTP)

• Low Voltage Detection Circuit

• Timer

- Timer / Counter

• Watch Dog Timer Auto Start (During 1second

after Power on Reset)

......... 16Bit * 1ch

......... 8Bit * 2ch

- Basic Interval Timer ...... 8Bit * 1ch

Nov. 2001 Ver 2.00

1

HMS81032E/HMS81032TL

1.3 Development Tools

The HMS81004E/08E/16E/24E/32E are supported by a full-fea-

tured macro assembler, an in-circuit emulator CHOICE-Dr.^TM

and OTP programmers. Macro assembler operates under the MS-

Windows 95/98^TM/NT4/W2000.

- MS- Window base assembler

- Linker / Editor / Debugger

Software

Hardware

(Emulator)

- CHOICE-Dr.

- CHOICE-Dr. EVA 81C5EVA

Please contact sales part of HYNIX

- Universal single programmer.

- 4 gang programmer

- stand alone

OTP program-

mer

2

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

2. BLOCK DIAGRAM

G8MC

Core

R0

PORT

R00~R07

Watchdog

Timer

RAM

REMOUT

R17/T0

R16/T1

R15/T2

R14/EC

(448byte)

Timer

R1

PORT

R10~R17

ROM

R12/INT2

R11/INT1

Interrupt

(32kbyte)

Key Scan

INT.

Generation

Block

R00~R07

R10~R17

R2

PORT

R20~R24

TEST

Clock Gen.

&

Prescaler

&

RESET

System

Control

B.I.T

XIN

XOUT

VDD VSS

Nov. 2001 Ver 2.00

3

HMS81032E/HMS81032TL

3. PIN ASSIGNMENT (Top View)

R13

R12

R11

1

2

3

4

5

6

7

8

9

R13

R12

R11

R10

VDD

XOUT

XIN

R00

R01

R02

R03

R20

1

2

3

4

5

6

7

8

9

R14

R15

R16

R17

REMOUT

RESET

TEST

R07

R06

R05

28

27

26

25

24

23

22

21

20

19

18

17

16

15

24

23

22

21

20

19

18

17

16

15

14

13

R14

R15

R16

R17

REMOUT

RESET

TEST

R07

R06

R05

R11

R10

VDD

XOUT

XIN

R00

R01

R02

1

2

3

4

5

6

7

8

20

19

18

17

16

15

14

13

R16

R17

REMOUT

RESET

TEST

R07

R10

VDD

XOUT

XIN

R00

R01

R02 10

R03 11

R20 12

R21 13

R22 14

24PIN

28PIN

20PIN

R06

R05

10

11

12

R04

VSS

R24

R04

VSS

R03

12 R04

9

R20

11 VSS

10

R23

4

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

4. PACKAGE DIMENSION

20 SOP

UNIT: INCH

MAX

MIN

0.512

0.495

0 ~ 8°

0.020

0.013

0.042

0.016

0.050 BSC

20 PDIP

0.300 BSC

1.043

1.015

0.270

0.245

MAX 0.180

MIN 0.015

0.021

0.015

0.100 BSC

0 ~ 15°

0.065

0.050

Nov. 2001 Ver 2.00

5

HMS81032E/HMS81032TL

24 SOP

UNIT: INCH

MAX

MIN

0.614

0.598

0 ~ 8°

0.020

0.013

0.042

0.016

0.050 BSC

24 SKDIP

0.300 BSC

1.265

1.160

0.300

0.250

MAX 0.180

MIN 0.015

0.021

0.015

0.100 BSC

0 ~ 15°

0.065

0.045

6

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

28 SOP

UNIT: INCH

MAX

MIN

0.713

0.697

0 ~ 8°

0.020

0.013

0.042

0.016

0.050 BSC

28 SKDIP

0.300 BSC

1.375

1.355

0.300

0.275

MAX 0.180

MIN 0.020

0.021

0.015

0.100 BSC

0 ~ 15°

0.055

0.045

Nov. 2001 Ver 2.00

7

HMS81032E/HMS81032TL

5. PIN FUNCTION

V

_DD: Supply voltage.

_SS: Circuit ground.

used as outputs or inputs.

In addition, R1 serves the functions of the various follow-

ing special features.

TEST: Used for shipping inspection of the IC. For normal

operation, it should be connected to V_DD

.

Port pin

Alternate function

RESET: Reset the MCU.

R11

R12

R14

R15

R16

R17

INT1 (External Interrupt input 1)

INT2 (External Interrupt input 2)

EC (Event Counter input)

T2 (Timer / Counter input 2)

T1 (Timer / Counter input 1)

T0 (Timer / Counter input 0)

X

_IN: Input to the inverting oscillator amplifier and input to

the internal main clock operating circuit.

X

_OUT: Output from the inverting oscillator amplifier.

R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0

pins 1 or 0 written to the Port Direction Register can be

used as outputs or inputs.

R20~R24: R2 is an 8-bit CMOS bidirectional I/O port. R2

pins 1 or 0 written to the Port Direction Register can be

used as outputs or inputs.

R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1

pins 1 or 0 written to the Port Direction Register can be

8

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

INPUT/

OUTPUT

PIN NAME

R00

Function

@RESET

@STOP

I/O

I

R01

- Each bit of the port can be individually configured as

an input or an output by user software

- Push-pull output

- CMOS input with pull-up resister (option)

- Can be programmable as key scan input

- Pull-up resisters are automatically disabled at output

mode

R02

State of

before

Stop

R03

INPUT

R04

R05

R06

R07

R10

- Each bit of the port can be individually configured as

an input or an output by user software

- Push-pull output

- CMOS input with pull-up resister (option)

- Can be programmable as key scan input or open

drain output

- Pull-up resisters are automatically disabled at output

mode

- Direct driving of LED(N-Tr.)

R11/INT1

R12/INT2

R13

State of

before

Stop

INPUT

R14/EC

R15/T2

R16/T1

R17/T0

R20

- Each bit of the port can be individually configured as

an input or an output by user software

- Push-pull output

- CMOS input with pull-up resister (option)

- Pull-up resisters are automatically disabled at output

mode

R21

State of

before

Stop

R22

INPUT

R23

R24

- Direct driving of LED(N-Tr.)

XIN

Oscillator input

Low

XOUT

REMOUT

RESET

TEST

VDD

O

Oscillator output

High

O

High current output

Includes pull-up resistor

Positive power supply

Ground

‘L’ output

‘L’ level

‘L’ output

I

state of

before stop

I

P

VSS

P

Nov. 2001 Ver 2.00

9

HMS81032E/HMS81032TL

6. PORT STRUCTURES

R0[0:7]

R11/INT1, R12/INT2, R14/EC

OTP: connected

MASK: option (default connected)

LVD

Circuit

V_DD

OTP: connected

MASK: option (default connected)

LVD

Circuit

V_DD

Pull up

Reg.

Pull-up Tr.

Pull up

Reg.

Pull-up Tr.

Open Drain

Reg.

V_DD

Open Drain

Reg.

V_DD

Data Reg.

Dir. Reg.

Function Sele-

ction Reg.

V_SS

Dir Reg.

V_SS

MUX

Rd

Key Scan

Input

Tr.: Transistor

Reg.: Register

to R11...INT1

to R12...INT2

to R14...EC

Noise

Filter

KS_EN

Standby Release Level Control Register

Key Scan

Input

MUX

KS_EN

Tr.: Transistor

Reg.: Register

R10, R13

Standby Release Level Control Register

OTP: connected

MASK: option (default connected)

LVD

Circuit

V_DD

Pull up

Reg.

Pull-up Tr.

Open Drain

Reg.

V_DD

Data Reg.

Function Sele-

ction Reg.

V_SS

Dir Reg.

MUX

Rd

Key Scan

Input

KS_EN

Tr.: Transistor

Reg.: Register

Standby Release Level Control Register

10

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

R15/T2, R16/T1, R17/T0

TEST

V_DD

OTP: connected

MASK: option (default connected)

LVD

Circuit

V_DD

V_SS

Noise

Filter

Pull up

Reg.

Pull-up Tr.

Open Drain

Reg.

V_DD

Data Reg.

REMOUT

V_DD

Function Sele-

ction Reg.

V_SS

Internal Signal

Dir Reg.

V_SS

MUX

Rd

to R15...T2

to R16...T1

to R17...T0

XIN, XOUT

MUX

Key Scan

Input

MUX

KS_EN

Tr.: Transistor

Reg.: Register

XOUT

XIN

Standby Release Level Control Register

Noise

Filter

from STOP circuit

R2[0:4]

V_SS

OTP: connected

MASK: option (default connected)

LVD

Circuit

V_DD

RESET

Pull up

Reg.

Pull-up Tr.

V_DD

V_SS

Open Drain

Reg.

Noise

Filter

V_DD

Data Reg.

Dir. Reg.

from Power On Reset

V_SS

MUX

Tr.: Transistor

Reg.: Register

Rd

Nov. 2001 Ver 2.00

11

HMS81032E/HMS81032TL

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Supply voltage........................................... -0.3 to +4.1 V

Input Voltage .....................................-0.3 to V_DD+0.3 V

Output Voltage ...................................-0.3 to V_DD+0.3 V

Operating Temperature........................................ 0~70°C

Storage Temperature ......................................-65~150°C

Power Dissipation................................................700 mA

Note: Stresses above those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the de-

vice. This is a stress rating only and functional operation of

the device at any other conditions above those indicated in

the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

7.2 Recommended Operating Conditions

Specifications

Unit

Parameter

Supply Voltage

Symbol

Condition

Min.

2.0

1.0

0

Max.

V_DD

f_XIN

f_XIN=4MHz

3.6

V

V_DD=2.0~3.6V

-

Operating Frequency

4.0

MHz

°C

T_OPR

Operating Temperature

+70

7.3 DC Electrical Characteristics

(T_A=-0~70°C, V_DD=2.0~3.6V, GND=0V)

Specifications

Typ.

Parameter

Symbol

Condition

Unit

Min.

0.8 V_DD

Max.

V_DD

V_IH1

V_IH2

V_IL1

V_IL2

R11,R12,R14,RESET

-

V

High level

input Voltage

0.7 V_DD

V_DD

R0,R1(except R11,R12,R14), R2

R11,R12,R14,RESET

0.2 V_DD

0.3 V_DD

0

Low level

input Voltage

R0,R1(except R11,R12,R14), R2

High level input

Leakage Current

I_IH

I_IL

R0,R1,R2,RESET,V_IH= VDD

-

1

µA

Low level input

Leakage Current

R0,R1,R2,RESET (without pull-up),V_IL= 0

-1

V_OH1

V_OH2

V_OH3

V_OL1

V_OL2

V_OL3

R0, I_OH=-0.5mA

VDD-0.4

-

V

High level

output Voltage

R1, R2, I_OH=-1.0mA

XIN, XOUT,I_OH=-200µA

R0, I_OL=1mA

VDD-0.4

VDD-0.9

-

0.4

0.8

Low level

output Voltage

R1, R2, I_OL=5mA

XIN, XOUT,I_OL=200µA

High level output

Leakage Current

I_OHL

I_OLL

R0,R1,R2, V_OH= VDD

R0,R1,R2, V_OL= 0

-

1

µA

Low level output

Leakage Current

-1

12

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

Specifications

Unit

Parameter

High Level

Symbol

Condition

Min.

Typ.

Max.

I_OH

I_OL

REMOUT, V_OH=2V

-30

-12

-5

mA

output current

Low Level

output current

REMOUT, V_OL=1V

0.5

-

3

I_p

Input pull-up current

R0,R1,R2, RESET, VDD=3V

15

-

30

2.4

4

60

6

µA

mA

I_DD1

I_DD2

Operating current, fxin=4Mhz, VDD=2.0V

Operating current, fxin=4Mhz, VDD=3.6V

-

10

Sleep mode current, fxin=4Mhz,

VDD=2.0V

I_SLP1

I_SLP2

I_STP1

I_STP2

V_RET

-

1

2

3

-

2

3

mA

µA

V

Sleep mode current, fxin=4Mhz,

VDD=3.6V

Power Supply Current

Stop mode current, Oscillator Stop

VDD=2.0V

-

8

Stop mode current, Oscillator Stop

VDD=3.6V

-

10

-

RAM retention

supply voltage

-

0.7

7.4 REMOUT Port Ioh Characteristics Graph

(typical process & room temperature)

.

Ioh(mA)

0

Vdd 2V

-5

Vdd 3V

-10

-15

-20

-25

-30

Vdd 4V

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Voh (V)

Figure 7-1 Ioh vs Voh

Nov. 2001 Ver 2.00

13

HMS81032E/HMS81032TL

7.5 REMOUT Port Iol Characteristics Graph

(typical process & room temperature)

.

Iol(mA)

5

Vdd 4V

4

3

Vdd 3V

2

1

Vdd 2V

0

-1

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Vol (V)

Figure 7-2 Iol vs Vol

7.6 AC Characteristics

(T_A=0~+70°C, V_DD=2.0~3.6V, V_SS=0V)

Specifications

Parameter

Symbol

Pins

Unit

Min.

Typ.

Max.

t_CP

t_SYS

t_CPH

t_CPL

t_RCP

t_FCP

t_IH

X_IN

External clock input cycle time

System clock cycle time

250

500

40

-

500

1000

ns

1000

2000

X_IN

External clock pulse width High

External clock pulse width Low

External clock rising time

-

ns

X_IN

40

-

ns

X_IN

External clock falling time

-

nS

t_SYS

ns

Interrupt pulse width High

INT1, INT2

RESET

EC

2

t_IL

Interrupt pulse width Low

2

-

t_RSTL

t_ECH

t_ECL

t_REC

t_FEC

RESET Input pulse width low

Event counter input pulse width high

Event counter input pulse width low

Event counter input pulse rising time

Event counter input pulse falling time

8

-

2

-

EC

2

-

EC

-

40

ns

EC

-

14

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

t_CPH

t_CPL

t_CP

V_DD-0.5V

X_IN

0.5V

t_RCP

t_FCP

t_IH

t_IL

INT1

INT2

0.8V_DD

0.2V_DD

t_RSTL

RESET

0.2V_DD

t_ECH

t_ECL

0.8V_DD

EC

0.2V_DD

t_REC

t_FEC

Figure 7-3 Timing Diagram

Nov. 2001 Ver 2.00

15

HMS81032E/HMS81032TL

8. MEMORY ORGANIZATION

The HMS81004E/08E/16E/24E/32E has separate address

spaces for Program memory and Data Memory. Program

memory can only be read, not written to. It can be up to

32K bytes of Program memory. Data memory can be read

and written to up to 448 bytes including the stack area.

8.1 Registers

This device has six registers that are the Program Counter

(PC), an Accumulator (A), two index registers (X, Y), the

Stack Pointer (SP), and the Program Status Word (PSW).

The Program Counter consists of 16-bit register.

the register contents are added to the specified address,

which becomes the actual address. These modes are ex-

tremely effective for referencing subroutine tables and

memory tables. The index registers also have increment,

decrement, comparison and data transfer functions, and

they can be used as simple accumulators.

ACCUMULATOR

X REGISTER

A

X

• X Register

In the case of division instruction, execute as register.

Y

Y REGISTER

• Y Register

SP

STACK POINTER

In the case of 16-bit operation instruction, execute as the

upper 8-bit of YA. (16-bit accumulator). In the case of

multiplication instruction, execute as a multiplicand regis-

ter. After multiplication operation, the upper 8-bit of the

result enters. In the case of division instruction, execute as

the upper 8-bit of dividend. After division operation, re-

mains enters. Y register can be used as loop counter of con-

ditional branch command. (e.g.DBNE Y, rel)

PCH

PCL

PROGRAM COUNTER

PROGRAM STATUS

WORD

PSW

Figure 8-1 Configuration of Registers

Accumulator:

The Accumulator is the 8-bit general purpose register, used

for data operation such as transfer, temporary saving, and

conditional judgement, etc. The Accumulator can be used

as a 16-bit register with Y Register as shown below.

Stack Pointer:

The Stack Pointer is an 8-bit register used for occurrence

interrupts, calling out subroutines and PUSH, POP, RETI,

RET instruction. Stack Pointer identifies the location in the

stack to be accessed (save or restore).

In the case of multiplication instruction, execute as a mul-

tiplier register. After multiplication operation, the lower 8-

bit of the result enters. (Y*A => YA). In the case of divi-

sion instruction, execute as the lower 8-bit of dividend. Af-

ter division operation, quotient enters.

Generally, SP is automatically updated when a subroutine

call is executed or an interrupt is accepted. However, if it

is used in excess of the stack area permitted by the data

memory allocating configuration, the user-processed data

may be lost. The SP is post-decremented when a subrou-

tine call or a push instruction is executed, or when an inter-

rupt is accepted. The SP is pre-incremented when a return

or a pop instruction is executed.

Y

A

The stack can be located at any position within 100_Hto

1FF_Hof the internal data memory. The SP is not initialized

by hardware, requiring to write the initial value (the loca-

tion with which the use of the stack starts) by using the ini-

tialization routine. Normally, the initial value of "FF_H" is

used.

Two 8-bit Registers can be used as a "YA" 16-bit Register

Figure 8-2 Configuration of YA 16-bit Register

X, Y Registers:

In the addressing mode which uses these index registers,

16

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

Caution:

Stack Address (100_H~ 1FF_H)

The Stack Pointer must be initialized by software be-

cause its value is undefined after RESET.

15

8

7

0

01_H

SP

Example: To initialize the SP

LDX

TXSP

#0FFH

Hardware fixed

; SP ← FF_H

At execution of

a CALL/TCALL/PCALL

At acceptance

of interrupt

At execution

of RET instruction

At execution

of RETI instruction

01FC

01FD

01FC

01FD

01FE

01FC

PSW

01FD

01FE

01FD

01FE

Push

down

Push

down

Pop

up

01FE

01FF

PCL

PCH

PCL

PCH

PCL

PCH

Pop

up

PCH

01FF

SP before

execution

01FF

01FD

01FF

01FC

01FD

01FF

01FC

01FF

SP after

execution

At execution

of PUSH instruction

PUSH A (X,Y,PSW)

of POP instruction

POP A (X,Y,PSW)

01FC

0100H

Stack

depth

01FD

01FE

01FD

01FE

Push

down

Pop

up

A

01FF

01FFH

SP before

01FF

01FE

01FF

execution

SP after

execution

Figure 8-3 Stack Operation

Program Counter:

reflect the current state of the CPU. The PSW is described

in Figure 8-4. It contains the Negative flag, the Overflow

flag, the Break flag the Half Carry (for BCD operation),

the Interrupt enable flag, the Zero flag, and the Carry flag.

The Program Counter is a 16-bit wide which consists of

two 8-bit registers, PCH and PCL. This counter indicates

the address of the next instruction to be executed. In reset

state, the program counter has reset routine address

(PC_H:0FF_H, PC_L:0FE_H).

[Carry flag C]

This flag stores any carry or borrow from the ALU of CPU

after an arithmetic operation and is also changed by the

Shift Instruction or Rotate Instruction.

Program Status Word:

The Program Status Word (PSW) contains several bits that

Nov. 2001 Ver 2.00

17

HMS81032E/HMS81032TL

[Zero flag Z]

This flag is set when the result of an arithmetic operation

or data transfer is "0" and is cleared by any other result.

MSB

LSB

C

N

V

G

B

H

I

Z

RESET VALUE: 00_H

CARRY FLAG RECEIVES

PSW

NEGATIVE FLAG

CARRY OUT

OVERFLOW FLAG

ZERO FLAG

SELECT DIRECT PAGE

when g=1, page is addressed by RPR

INTERRUPT ENABLE FLAG

HALF CARRY FLAG RECEIVES

CARRY OUT FROM BIT 1 OF

BRK FLAG

ADDITION OPERLANDS

Figure 8-4 PSW (Program Status Word) Register

[Interrupt disable flag I]

the direct addressing mode, addressing area is from zero

page 00_Hto 0FF_Hwhen this flag is "0". If it is set to "1",

addressing area is 1 Page. It is set by SETG instruction and

cleared by CLRG.

This flag enables/disables all interrupts except interrupt

caused by Reset or software BRK instruction. All inter-

rupts are disabled when cleared to "0". This flag immedi-

ately becomes "0" when an interrupt is served. It is set by

the EI instruction and cleared by the DI instruction.

[Overflow flag V]

This flag is set to "1" when an overflow occurs as the result

of an arithmetic operation involving signs. An overflow

occurs when the result of an addition or subtraction ex-

ceeds +127(7F_H) or -128(80_H). The CLRV instruction

clears the overflow flag. There is no set instruction. When

the BIT instruction is executed, bit 6 of memory is copied

to this flag.

[Half carry flag H]

After operation, this is set when there is a carry from bit 3

of ALU or there is no borrow from bit 4 of ALU. This bit

can not be set or cleared except CLRV instruction with

Overflow flag (V).

[Break flag B]

[Negative flag N]

This flag is set by software BRK instruction to distinguish

BRK from TCALL instruction with the same vector ad-

dress.

This flag is set to match the sign bit (bit 7) status of the re-

sult of a data or arithmetic operation. When the BIT in-

struction is executed, bit 7 of memory is copied to this flag.

[Direct page flag G]

This flag assigns RAM page for direct addressing mode. In

18

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

8.2 Program Memory

A 16-bit program counter is capable of addressing up to

64K bytes, but this device has 4/8/16/24/32K bytes pro-

gram memory space only physically implemented. Ac-

cessing a location above FFFF_Hwill cause a wrap-around

to 0000_H.

Example: Usage of TCALL

LDA

#5

TCALL 0FH

;

1BYTE INSTRUCTION

INSTEAD OF 2 BYTES

NORM AL CALL

:

;

;TABLE CALL ROUTINE

;

Figure 8-5, shows a map of Program Memory. After reset,

the CPU begins execution from reset vector which is stored

in address FFFE_Hand FFFF_Has shown in Figure 8-6.

FUNC_A: LDA

LRG0

RET

;

As shown in Figure 8-5, each area is assigned a fixed loca-

tion in Program Memory. Program Memory area contains

the user program.

FUNC_B: LDA

LRG1

2

1

RET

;

;TABLE CALL ADD. AREA

;

8000_H

A000_H

C000_H

E000_H

F000_H

ORG

DW

0FFC0H

FUNC_A

FUNC_B

;

TCALL ADDRESS AREA

The interrupt causes the CPU to jump to specific location,

where it commences the execution of the service routine.

The External interrupt 0, for example, is assigned to loca-

tion 0FFFA_H. The interrupt service locations spaces 2-byte

interval: 0FFF8_Hand 0FFF9_Hfor External Interrupt 1,

0FFFA_Hand 0FFFB_Hfor External Interrupt 0, etc.

Any area from 0FF00_Hto 0FFFF_H, if it is not going to be

used, its service location is available as general purpose

Program Memory.

FF00_H

PCALL

AREA

FFC0_H

TCALL

Address

Vector Area Memory

AREA

FFE0_H

0FFDE_H

E0

S/W Interrupt Vector Area

INTERRUPT

-

VECTOR AREA

FFFF_H

E2

-

E4

-

E6

Basic Interval Timer Interrupt Vector Area

Watch Dog Timer Interrupt Vector Area

Figure 8-5 Program Memory Map

E8

EA

-

Page Call (PCALL) area contains subroutine program to

reduce program byte length by using 2 bytes PCALL in-

stead of 3 bytes CALL instruction. If it is frequently called,

it is more useful to save program byte length.

EC

EE

-

Timer2 Interrupt Vector Area

Timer1 Interrupt Vector Area

F0

F2

F4

F6

F8

FA

FC

FE

Timer0 Interrupt Vector Area

-

Table Call (TCALL) causes the CPU to jump to each

TCALL address, where it commences the execution of the

service routine. The Table Call service area spaces 2-byte

for every TCALL: 0FFC0_Hfor TCALL15, 0FFC2_Hfor

TCALL14, etc., as shown in Figure 8-7.

External Interrupt 2 Vector Area

External Interrupt 1 Vector Area

Key Scan Interrupt Vector Area

-

RESET Vector Area

NOTE:

"-" means reserved area.

Figure 8-6 Interrupt Vector Area

Nov. 2001 Ver 2.00

19

HMS81032E/HMS81032TL

Address

Program Memory

TCALL 15

TCALL 14

TCALL 13

TCALL 12

TCALL 11

TCALL 10

TCALL 9

0FFC0_H

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

Address

0FF00_H

PCALL Area Memory

PCALL Area

(192 Bytes)

TCALL 8

0FFBF_H

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

TCALL 7

TCALL 6

TCALL 5

TCALL 4

TCALL 3

TCALL 2

TCALL 1

TCALL 0 / BRK *

NOTE:

* means that the BRK software interrupt is using

same address with TCALL0.

Figure 8-7 PCALL and TCALL Memory Area

PCALL→ rel

TCALL→ n

4F35

PCALL 35H

4A

TCALL 4

4A

01001010

4F

35

Reverse

➊

~

PC:

11111111

F_HF_H

11010110

D_H6_H

~

0FF00H

0FF35H

➌

0FF00H

➋

0FFD7H

25

0FFFFH

D1

0FFFFH

20

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

Example: The usage software example of Vector address and the initialize part.

ORG

0FFE0H

DW

NOT_USED

BIT_INT

WDT_INT

NOT_USED

TMR2_INT

TMR1_INT

TMR0_INT

NOT_USED

INT2

; BIT

; Watch Dog Timer

; Timer-2

; Timer-1

; Timer-0

;

; Int.2

; Int.1

; Key Scan

;

INT1

KEY_INT

NOT_USED

RESET

; Reset

ORG

08000H

;HMS81032E Program start address

;********************************************

;

MAIN

PROGRAM

*

;********************************************

;

RESET:

NOP

CLRG

DI

;Disable All Interrupts

LDX

#0

{X}+

#0C0H

RAM_CLR

RAM_CLR: LDA

;RAM Clear(!0000H->!00BFH)

STA

CMPX

BNE

;

LDX

TXSP

#0FFH

;Stack Pointer Initialize

LDM

:

R0, #0

;Normal Port 0

R0DD,#1000_0010B

P0PC,#1000_0010B

PMR1,#0000_0010B

;Normal Port Direction

;Pull Up Selection Set

;R1 port / int

:

LDM

:

CKCTLR,#0011_1101B

;WDT ON, 16mS Time delay after stop mode release

Nov. 2001 Ver 2.00

21

HMS81032E/HMS81032TL

8.3 Data Memory

Figure 8-8 shows the internal Data Memory space availa-

ble. Data Memory is divided into 3 groups, a user RAM,

control registers, Stack.

Note that unoccupied addresses may not be implemented

on the chip. Read accesses to these addresses will in gen-

eral return random data, and write accesses will have an in-

determinate effect.

0000H

More detailed informations of each register are explained

in each peripheral section.

RAM

Note: Write only registers can not be accessed by bit ma-

nipulation instruction. Do not use read-modify-write instruc-

tion. Use byte manipulation instruction.

(192 Bytes)

PAGE0

00BFH

00C0H

CONTROL

REGISTERS

00FFH

Example; To write at CKCTLR

0100H

LDM

CLCTLR,#09H;Divide ratio ÷16

RAM (STACK)

(256 Bytes)

Stack Area

PAGE1

The stack provides the area where the return address is

saved before a jump is performed during the processing

routine at the execution of a subroutine call instruction or

the acceptance of an interrupt.

01FFH

When returning from the processing routine, executing the

subroutine return instruction [RET] restores the contents of

the program counter from the stack; executing the interrupt

return instruction [RETI] restores the contents of the pro-

gram counter and flags.

Figure 8-8 Data Memory Map

User Memory

The HMS81004E/08E/16E/24E/32E has 448 × 8 bits for

the user memory (RAM).

The save/restore locations in the stack are determined by

the stack pointed (SP). The SP is automatically decreased

after the saving, and increased before the restoring. This

means the value of the SP indicates the stack location

number for the next save. Refer to Figure 8-3 on page 17.

Control Registers

The control registers are used by the CPU and Peripheral

function blocks for controlling the desired operation of the

device. Therefore these registers contain control and status

bits for the interrupt system, the timer/ counters, analog to

digital converters and I/O ports. The control registers are in

address range of 0C0_Hto 0FF_H.

22

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

List for Control Registers

8.4

Read

Address

Function Register

Symbol

RESET Value

Write

R/W

W

00C0h

00C1h

00C2h

00C3h

00C4h

00C5h

00C6h

PORT R0 DATA REG.

R0

undefined

00000000b

undefined

00000000b

undefined

00000000b

PORT R0 DATA DIRECTION REG.

PORT R1 DATA REG.

R0DD

R1

R/W

W

PORT R1 DATA DIRECTION REG.

PORT R2 DATA REG.

R1DD

R2

R/W

W

PORT R2 DATA DIRECTION REG.

reserved

R2DD

CLOCK CONTROL REG.

CKCTLR

BITR

W

--110111b

undefined

-0001111b

00000000b

--000000b

--0000--b

-00-----b

00C7h

BASIC INTERVAL REG.

R

00C8h

00C9h

00CAh

00CBh

00CCh

00CDh

00CEh

00CFh

00D0h

00D1h

00D2h

00D3h

00D4h

WATCH DOG TIMER REG.

PORT R1 MODE REG.

WDTR

PMR1

IMOD

IEDS

W

INT. MODE REG.

R/W

W

EXT. INT. EDGE SELECTION

INT. ENABLE REG. LOW

IENL

R/W

W

INT. REQUEST FLAG REG. LOW

INT. ENABLE REG. HIGH

INT. REQUEST FLAG REG. HIGH

TIMER0 (16bit) MODE REG.

TIMER1 (8bit) MODE REG.

TIMER2 (8bit) MODE REG.

TIMER0 HIGH-MSB DATA REG.

TIMER0 HIGH-LSB DATA REG.

TIMER0 LOW-MSB DATA REG.

TIMER0 HIGH-MSB COUNT REG.

TIMER0 LOW-LSB DATA REG.

TIMER0 LOW-LSB COUNT REG.

TIMER1 HIGH DATA REG.

TIMER1 LOW DATA REG.

TIMER1 LOW COUNT REG.

TIMER2 DATA REG.

IRQL

-00-----b

IENH

000-000-b

00000000b

undefined

00000000b

IRQH

TM0

TM1

TM2

T0HMD

T0HLD

T0LMD

W

00D5h

R

T0LLD

W

00D6h

00D7h

00D8h

R

T1HD

T1LD

W

R

T2DR

TM01

W

00D9h

TIMER2 COUNT REG.

R

00DAh

00DBh

00DCh

00DDh

00DEh

TIMER0 / TIMER1 MODE REG.

Reserved

R/W

STANDBY MODE RELEASE REG0

PORT R1 OPEN DRAIN ASSIGN REG.

SMPR0

SMPR1

R1ODC

W

00000000b

Nov. 2001 Ver 2.00

23

HMS81032E/HMS81032TL

00DFh

00E0h

00E1h

00E2h

00E3h

00E4h

00E5h

00E6h

00E7h

00E8h

00E9h

00EAh

00EBh

00ECh

00EDh

00EEh

00EFh

00F0h

00F1h

00F2

PORT R2 OPEN DRAIN ASSIGN REG.

R2ODC

R0ODC

W

00000000b

Reserved

PORT R0 OPEN DRAIN ASSIGN REG.

Reserved

SLEEP MODE REG.

SLPM

W

- - - - - - - 0b

Reserved

00F3h

00F4h

00F5h

00F6h

00F7h

00F8h

00F9h

00FAh

00FBh

00FCh

00FDh

00FEh

00FFh

Reserved

STANDBY RELEASE LEVEL CONT. REG. 0

STANDBY RELEASE LEVEL CONT. REG. 1

PORT R0 PULL-UP REG. CONT. REG.

PORT R1 PULL-UP REG. CONT. REG.

PORT R2 PULL-UP REG. CONT. REG.

Reserved

SRLC0

SRLC1

R0PC

R1PC

R2PC

W

00000000b

Reserved

Registers are controlled by byte manipulation instruction such as LDM etc., do not use bit manipulation

instruction such as SET1, CLR1 etc. If bit manipulation instruction is used on these registers,

content of other seven bits are may varied to unwanted value.

W

R/W

Registers are controlled by both bit and byte manipulation instruction.

- : this bit location is reserved.

24

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

8.5 Addressing Mode

E45535 LDM

35H,#55H

The HMS81004E/08E/16E/24E/32E uses six addressing

modes;

• Register addressing

• Immediate addressing

• Direct page addressing

• Absolute addressing

• Indexed addressing

0C35_H

data

data ← 55H

~

➊

0F100_H

➋

E4

55

35

0F101_H

0F102_H

• Register-indirect addressing

(1) Register Addressing

Register addressing accesses the A, X, Y, C and PSW.

(3) Direct Page Addressing → dp

In this mode, a address is specified within direct page.

Example; G=0

(2) Immediate Addressing → #imm

In this mode, second byte (operand) is accessed as a data

immediately.

C535

LDA

35H

;A ←RAM[35H]

Example:

0435

ADC

#35H

35_H

data

MEMORY

➋

~

data → A

~

➊

04

35

0E550_H

0E551_H

C5

35

A+35H+C → A

When G-flag is 1, then RAM address is defined by 16-bit

address which is composed of 8-bit RAM paging register

(RPR) and 8-bit immediate data.

(4) Absolute Addressing → !abs

Absolute addressing sets corresponding memory data to

Data, i.e. second byte (Operand I) of command becomes

lower level address and third byte (Operand II) becomes

upper level address.

Example: G=1, RPR=0CH

With 3 bytes command, it is possible to access to whole

memory area.

ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,

LDY, OR, SBC, STA, STX, STY

Example;

Nov. 2001 Ver 2.00

25

HMS81032E/HMS81032TL

0735F0 ADC

!0F035H

;A←ROM[0F035H]

D4

LDA

{X}

;ACC←RAM[X].

115_H

data

➋

0F035_H

data

➋

data → A

~

A+data+C → A

➊

0F100_H

0F101_H

0F102_H

07

35

F0

D4

0E550_H

➊

address: 0F035

X indexed direct page, auto increment→ {X}+

The operation within data memory (RAM)

ASL, BIT, DEC, INC, LSR, ROL, ROR

In this mode, a address is specified within direct page by

the X register and the content of X is increased by 1.

Example; Addressing accesses the address 0135_Hregard-

less of G-flag and RPR.

LDA, STA

983501 INC

!0135H

;A ←ROM[135H]

Example; G=0, X=35_H

DB

LDA

{X}+

135_H

data

➌

35_H

➋

~

data

➋

~

data+1 → data

data → A

36H → X

~

0F100_H

0F101_H

0F102_H

~

98

35

01

➊

address: 0135

DB

(5) Indexed Addressing

X indexed direct page (no offset) → {X}

In this mode, a address is specified by the X register.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA

Example; X=15_H, G=1, RPR=01_H

X indexed direct page (8 bit offset) → dp+X

This address value is the second byte (Operand) of com-

mand plus the data of ꢀ-register. And it assigns the mem-

ory in Direct page.

ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA

STY, XMA, ASL, DEC, INC, LSR, ROL, ROR

Example; G=0, X=0F5_H

26

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

C645

LDA

45H+X

JMP, CALL

Example; G=0

3F35

JMP

[35H]

3A_H

data

➌

data → A

~

➋

~

35_H

0A

E3

0E550_H

0E551_H

C6

45

➊

36_H

45H+0F5H=13AH

jump to address 0E30A_H

➋

~

➊

0E30A_H

~

Y indexed direct page (8 bit offset) → dp+Y

0FA00_H

3F

35

This address value is the second byte (Operand) of com-

mand plus the data of Y-register, which assigns Memory in

Direct page.

This is same with above (2). Use Y register instead of X.

Y indexed absolute → !abs+Y

Sets the value of 16-bit absolute address plus Y-register

data as Memory. This addressing mode can specify mem-

ory in whole area.

X indexed indirect → [dp+X]

Processes memory data as Data, assigned by 16-bit pair

memory which is determined by pair data

[dp+X+1][dp+X] Operand plusꢁX-register data in Direct

page.

Example; Y=55_H

D500FA LDA

!0FA00H+Y

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, X=10_H

1625

ADC

[25H+X]

0F100_H

0F101_H

0F102_H

D5

➊

00

FA

0FA00H+55H=0FA55H

35_H

05

~

➋

36_H

E0

0E005_H

➋

~

0FA55_H

data

~

data → A

➌

25 + X(10) = 35_H

➊

0E005_H

data

~

0FA00_H

16

25

(6) Indirect Addressing

Direct page indirect → [dp]

➌ A + data + C → A

Assigns data address to use for accomplishing command

which sets memory data (or pair memory) by Operand.

Also index can be used with Index register X,Y.

Nov. 2001 Ver 2.00

27

HMS81032E/HMS81032TL

Y indexed indirect → [dp]+Y

Absolute indirect → [!abs]

Processes memory data as Data, assigned by the data

[dp+1][dp] of 16-bit pair memory paired by Operand in Di-

rect pageꢁplus Y-register data.

The program jumps to address specified by 16-bit absolute

address.

JMP

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, Y=10_H

Example; G=0

1F25E0 JMP

[!0C025H]

1725

ADC

[25H]+Y

PROGRAM MEMORY

0E025_H

0E026_H

25

E7

25_H

05

E0

26_H

jump to

address 0E30A_H

➋

0E005_H+ Y(10) = 0E015_H

➋

~

0E725_H

0E015_H

data

➊

~

0FA00_H

1F

0FA00_H

17

25

➌ A + data + C → A

E0

28

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

9. I/O PORTS

The HMS81004E/08E/16E/24E/32E has 24 I/O ports

which are PORT0(8 I/O), PORT1 (8 I/O), PORT2 (8 I/O).

Pull-up resistor of each port can be selectable by program.

Each port contains data direction register which controls I/

O and data register which stores port data.

(1) R0 I/O Data Direction Register (R0DD)

R0 I/O Data Direction Register (R0DD) is 8-bit register,

and can assign input state or output state to each bit. If

R0DD is “1”, port R0 is in the output state, and if “0”, it is

in the input state. R0DD is write-only register. Since

R0DD is initialized as “00h” in reset state, the whole port

R0 becomes input state.

9.1 R0 Ports

(2) R0 Data Register (R0)

R0 is an 8-bit CMOS bidirectional I/O port (address

0C0_H). Each I/O pin can independently used as an input or

an output through the R0DD register (address 0C1_H).

R0 data register (R0) is 8-bit register to store data of port

R0. When set as the output state by R0DD, and data is writ-

ten in R0, data is output into R0 pin. When set as the input

state, input state of pin is read. The initial value of R0 is un-

known in reset state.

R0 has internal pull-ups that is independently connected or

disconnected by R0PC. The control registers for R0 are

shown below.

(3) R0 Open drain Assign Register (R0ODC)

R0 Open Drain Assign Register (R0ODC) is 8bit register,

and can assign R0 port as open drain output port each bit,

if corresponding port is selected as output. If R0ODC is se-

lected as “1”, port R0 is open drain output, and if selected

as, “0” it is push-pull output. R0ODC is write-only register

and initialized as “00h” in reset state.

ADDRESS: 0C0_H

RESET VALUE: Undefined

R0 Data Register (R/W)

R07 R06 R05 R04 R03 R02 R01 R00

R0

ADDRESS: 0C1_H

RESET VALUE: 00_H

R0 Direction Register (W)

R0DD

(4) R0 Pull-up Control Register (R0PC)

Port Direction

0: Input

1: Output

R0 Pull-up Control Register (R0PC) is 8-bit register and

can control pull-up on or off each bit, if corresponding port

is selected as input. If R0PC is selected as “1”, pull-up is

disabled and if selected as “0”, it is enabled. R0PC is write-

only register and initialized as “00h” in reset state. The

pull-up is automatically disabled, if corresponding port is

selected as output.

ADDRESS:0F8_H

RESET VALUE: 00_H

R0 Pull-up Control Register (W)

R0PC

Pull-up select

1: Without pull-up

0: With pull-up

ADDRESS:0E4_H

RESET VALUE: 00_H

R0 Open drain Assign Register (W)

R0ODC

9.2 R1 Ports

R1 is an 8-bit CMOS bidirectional I/O port (address

0C2_H). Each I/O pin can independently used as an input or

an output through the R1DD register (address 0C3_H).

Open drain select

0: Push-pull

1: Open drain

R1 has internal pull-ups that is independently connected or

disconnected by register R1PC. The control registers for

R1 are shown below.

Nov. 2001 Ver 2.00

29

HMS81032E/HMS81032TL

and can assign R1 port as open drain output port each bit,

if corresponding port is selected as output. If R1ODC is se-

lected as “1”, port R1 is open drain output, and if selected

as “0”, it is push-pull output. R1ODC is write-only register

and initialized as “00h” in reset state.

ADDRESS: 0C2_H

RESET VALUE: Undefined

R1 Data Register (R/W)

R17 R16 R15 R14 R13 R12 R11 R10

R1

ADDRESS: 0C3_H

RESET VALUE: 00_H

R1 Direction Register (W)

R1DD

(4) R1 Port Mode Register (PMR1)

R1 Port Mode Register (PMR1) is 8-bit register, and can

assign the selection mode for each bit. When set as “0”,

corresponding bit of PMR1 acts as port R1 selection mode,

and when set as “1”, it becomes function selection mode.

Port Direction

0: Input

1: Output

ADDRESS: 0F9_H

RESET VALUE: 00_H

R1 Pull-up Control Register (W)

R1PC

PMR1 is write-only register and initialized as “00h” in re-

set state. Therefore, becomes Port selection mode. Port R1

can be I/O port by manipulating each R1DD bit, if corre-

sponding PMR1 bit is selected as “0”.

Pull-up select

1: Without pull-up

0: With pull-up

ADDRESS: 0DE_H

RESET VALUE: 00_H

R1 Open drain Assign Register (W)

P1ODC

Selection

Bit Name PMR1

Remarks

Mode

R17 (I/O)

T0 (O)

0

-

Open drain select

0: Push-pull

1: Open drain

T0S

1

Timer0

0

R16 (I/O)

T1 (O)

-

T1S

1

ADDRESS: 0C9_H

RESET VALUE: 00_H

Timer1

R1 Port Mode Register (W)

PMR1

0

R15 (I/O)

T2 (O)

-

Timer2

-

T2S

1

Mode select

0: Port R1 selection

1: Function selection

0

R14 (I/O)

EC (I)

ECS

1

Timer0 Event

0

R12 (I/O)

INT2 (I)

(1) R1 I/O Data Direction Register (R1DD)

INT2S

1

Timer0 Input Cap-

ture

R1 I/O Data Direction Register (R1DD) is 8-bit register,

and can assign input state or output state to each bit. If

R1DD is “1”, port R1 is in the output state, and if “0”, it is

in the input state. R1DD is write-only register. Since

R1DD is initialized as “00h” in reset state, the whole port

R1 becomes input state.

0

R11 (I/O)

INT1 (I)

INT1S

1

(2) R1 Data Register (R1)

Table 9-1 Selection mode of PMR1

R1 data register (R1) is 8-bit register to store data of port

R1. When set as the output state by R1DD, and data is

written in R1, data is output into R1 pin. When set as the

input state, input state of pin is read. The initial value of

R1 is unknown in reset state.

(5) R1 Pull-up Control Register (R1PC)

R1 Pull-up Control Register (R1PC) is 8-bit register and

can control pull-up on or off each bit, if corresponding port

is selected as input. If R1PC is selected as “1”, pull-up is

disabled and if selected as “0”, it is enabled. R1PC is write-

only register and initialized as “00h” in reset state. The

(3) R1 Open drain Assign Register (R1ODC)

R1 Open Drain Assign Register (R1ODC) is 8bit register,

30

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

pull-up is automatically disabled, if corresponding port is

selected as output.

(1) R2 I/O Data Direction Register (R2DD)

R2 I/O Data Direction Register (R2DD) is 8-bit register,

and can assign input state or output state to each bit. If

R2DD is “1”, port R2 is in the output state, and if “0”, it is

in the input state. R2DD is write-only register. Since

R2DD is initialized as “00h” in reset state, the whole port

R2 becomes input state.

9.3 R2 Port

R2 is an 8-bit CMOS bidirectional I/O port (address

0C4_H). Each I/O pin can independently used as an input or

an output through the R2DD register (address 0C5_H).

(2) R2 Data Register (R2)

R2 data register (R2) is 8-bit register to store data of port

R2. When set as the output state by R2DD, and data is writ-

ten in R2, data is outputted into R2 pin. When set as the in-

put state, input state of pin is read. The initial value of R2

is unknown in reset state.

R2 has internal pull-ups that is independently connected or

disconnected by R2PC (address 0FA_H). The control regis-

ters for R2 are shown as below.

ADDRESS: 0C4_H

RESET VALUE: Undefined

(3) R2 Open drain Assign Register (R2ODC)

R2 Data Register (R/W)

R2 Open Drain Assign Register (R2ODC) is 8bit register,

and can assign R2 port as open drain output port each bit,

if corresponding port is selected as output. If R2ODC is se-

lected as “1”, port R2 is open drain output, and if selected

as “0”, it is push-pull output. R2ODC is write-only register

and initialized as “00h” in reset state.

-

R24 R23 R22 R21 R20

R2

ADDRESS: 0C5_H

RESET VALUE: 00_H

R2 Direction Register (W)

R2DD

Port Direction

0: Input

1: Output

(4) R2 Pull-up Control Register (R2PC)

R2 Pull-up Control Register (R2PC) is 8-bit register and

can control pull-up on or off each bit, if corresponding port

is selected as input. If R2PC is selected as “1”, pull-up ia

disabled and if selected as ”0”, it is enabled. R2PC is write-

only register and initialized as “00h” in reset state. The

pull-up is automatically disabled, if corresponding port is

selected as output.

ADDRESS:0FA_H

RESET VALUE: 00_H

R2 Pull-up Control Register (W)

R2PC

Pull-up select

1: Without pull-up

0: With pull-up

ADDRESS:0DF_H

RESET VALUE: 00_H

R2 Open drain Assign Register (W)

R2ODC

Open drain select

0: Push-pull

1: Open drain

Nov. 2001 Ver 2.00

31

HMS81032E/HMS81032TL

10. CLOCK GENERATOR

Clock generating circuit consists of Clock Pulse Generator

(C.P.G), Prescaler, Basic Interval Timer (B.I.T) and Watch

Dog Timer. The clock applied to the Xin pin divided by

two is used as the internal system clock.

state.

ADDRESS: 0C7_H

INITIAL VALUE: --110111b

Clock Control Register (W)

7

6

5

4

3

2

1

0

CKCTLR

Prescaler consist of 12-bit binary counter. The clock sup-

plied from oscillation circuit is input to prescaler(fex)

The divided output from each bit of prescaler is provided

to peripheral hardware

ENPCK 0: Stopped

1: Provided

Clock to peripheral hardware can be stopped by bit4 (EN-

PCK) of CKCTLR Register. ENPCK is set to “1” in reset

fex

OSC

CIRCUIT

Internal system clock (CPU clock)

CLOCK PULSE

GENERATOR

PRESCALER

PS4 PS5 PS6

PS0

PS1

PS2

PS3

PS7

PS8

PS9

PS10 PS11 PS12

÷1

÷2

÷4

÷8

÷16

÷32

÷64 ÷128 ÷256 ÷512 ÷1024 ÷2048 ÷4096

Peripheral clock

f_EX(MHz)

PS0

PS1

2M

PS2

PS3

PS4

250K

4u

PS5

125K

8u

PS6

62.5K 31.25K 15.63K 7.183K 3.906K

16u 32u 64u 128u 256u

PS7

PS8

PS9

PS10 PS11

PS12

0.976K

1024u

Frequency

period

4M

1M

1u

500K

2u

1.953K

512u

4

250n

500n

Figure 10-1 Block diagram of Clock Generator

32

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

10.1 Oscillation Circuit

Oscillation circuit is designed to be used either with a ce-

ramic resonator or crystal oscillator. Figure 10-2 shows

circuit diagrams using a crystal (or ceramic) oscillator. As

shown in the diagram, oscillation circuits can be construct-

ed by connecting a oscillator between Xout and Xin. Clock

from oscillation circuit makes CPU clock via clock pulse

generator, and then enters prescaler to make peripheral

hardware clock. Alternately, the oscillator may be driven

from an external source as Figure 10-3 . In the STOP

mode, oscillation stop, Xout state goes to “HIGH” , Xin

state goes to “LOW” , and built-in feed back resistor is dis-

abled.

Oscillation circuit is designed to be used either with a ce-

ramic resonator or crystal oscillator. Since each crystal and

ceramic resonator have their own characteristics, the user

should consult the crystal manufacturer for appropriate

values of external components. In addition, see Figure 10-

4 for the layout of the crystal.

Note: Minimize the wiring length. Do not allow the wiring to

intersect with other signal conductors. Do not allow the wir-

ing to come near changing high current. Set the potential of

the grounding position of the oscillator capacitor to that of

SS

V

. Do not ground it to any ground pattern where high cur-

rent is present. Do not fetch signals from the oscillator.

Xout

Cout

Cin

Xin

Vss

X_OUT

X_IN

Figure 10-2 External Crystal(Ceramic) oscillator circuit

OPEN

Xout

External

Clock

Source

Figure 10-4 Recommend Layout of Oscillator PCB

circuit

Xin

Vss

Figure 10-3 External clock input circuit

Nov. 2001 Ver 2.00

33

HMS81032E/HMS81032TL

Frequency

Resonator Maker

Part Name

ZTT2.00

Load Capacitor

Cin=Cout=open

Cin=Cout=30pF

Cin=Cout=open

Cin=Cout=30pF

Cin=Cout=open

Cin=Cout=30pF

Operating Voltage

2.0~3.6

CQ

ZTA2.00

2.0~3.6

2.00MHz

MURATA

CQ

CSTLS2M00G56-B0

CSTCC2.00MG0H6

CSTCC2M00G56-R0

ZTT4.00

2.0~3.6

CQ

ZTA4.00

2.0~3.6

MURATA

TDK

CSTS0400MG06

CSTLS4M00G56-B0

CSTCR4M00G55-R0

FCR4.0MC5

2.0~3.6

4.00MHz

2.0~3.6

TDK

FCR4.0MSC5

CRT4.00MS

2.0~3.6

CORETECH

2.0~3.6

CRM4.00MS

2.0~3.6

Table 10-1 recommendatory resonator

34

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

11. BASIC INTERVAL TIMER

The HMS81004E/08E/16E/24E/32E has one 8-bit Basic

Interval Timer that is free-run and can not stop. Block dia-

gram is shown in Figure 11-1.

The Basic Interval Timer is controlled by the clock control

register (CKCTLR) shown in Figure 11-2. If bit3(BTCL)

of CKCTLR is set to “1”, B.I.T is cleared, and then, after

one machine cycle, BTCL becomes “0”, and B.I.T starts

counting. BTCL is set to ``0`` in reset state.

The Basic Interval Timer generates the time base for

Standby release time, watchdog timer counting, and etc. It

also provides a Basic interval timer interrupt (IFBIT). As

the count overflow from FF_Hto 00_H, this overflow causes

the interrupt to be generated.

The input clock of B.I.T can be selected from the prescaler

within a range of 2us to 256us by clock input selection bits

(BTS2~BTS0). (at fex = 4MHz). In reset state, or power on

reset, BTS2=“1”, BTS1= “1”, BTS0= “1” to secure the

longest oscillation stabilization time. B.I.T can generate

the wide range of basic interval time interrupt request (IF-

BIT) by selecting prescaler output.

-8bit binary up-counter

-Use the bit output of prescaler as input to secure the oscil-

lation stabilization time after power-on

-Secures the oscillation stabilization time in standby mode

(stop mode) release

By reading of the Basic Interval Timer Register (BITR),

we can read counter value of B.I.T. Because B.I.T can be

cleared or read, the spending time up to maximum 65.5ms

can be available. B.I.T is read-only register. If B.I.T regis-

ter is written, then CKCTLR register with same address is

written.

-Contents of B.I.T can be read

-Provides the clock for watch dog timer

÷8

÷16

Basic Interval Timer

÷32

source

clock

÷64

overflow

8-bit up-counter

IFBIT

MUX

÷128

÷256

÷512

÷1024

Basic Interval Timer Interrupt

To Watchdog timer (WDTR)

clear

3

Select Input clock

[0C7_H]

BTS[2:0]

CKCTLR

BTCL

BITR

Read

clock control register

Internal bus line

Figure 11-1 Block diagram of Basic Interval Timer

Nov. 2001 Ver 2.00

35

HMS81032E/HMS81032TL

W

5

W

4

W

3

W

2

W

1

W

0

7

-

6

-

ADDRESS: 0C7_H

INITAIL VALUE: --110111_B

BTCL

ENPCK

BTCL BTS2 BTS1 BTS0

WDTON

CKCTLR

Basic Interval Timer source clock select

000: f_XIN÷ 8

001: f_XIN÷ 16

010: f_XIN÷ 32

011: f_XIN÷ 64

100: f_XIN÷ 128

101: f_XIN÷ 256

110: f_XIN÷ 512

111: f_XIN÷ 1024

Caution:

Both register are in same address,

when write, to be a CKCTLR,

when read, to be a BITR.

Clear bit

0: Normal operation, free-run

1: Clear 8-bit counter (BITR) to “0” and count up again.

This bit becomes to “0” automatically after one machine cycle.

Peripheral clock

0:stopped

1:provided

Watch Dog Timer function control

0:6bit timer

1:Watch Dog Timer

R

7

R

6

R

5

R

4

R

3

BTCL

R

2

R

1

R

0

ADDRESS: 0C7_H

INITIAL VALUE: Undefined

BITR

8-BIT FREE-RUN BINARY COUNTER

Figure 11-2 CKCTLR AND BITR

B.I.T. Input

Standby release

time(ms)

BTS[2:0]

CPU Source clock

clock@4Mhz(us)

000

001

010

011

100

101

110

111

÷ 8

÷16

÷32

÷64

÷128

÷256

÷512

÷1024

2

4

8

16

32

64

128

256

0.512

1.024

2.048

4.096

8.192

16.384

32.768

65.536

36

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

12. WATCH DOG TIMER

Watch Dog Timer (WDT) consists of 6-bit binary counter,

6-bit comparator, and Watch Dog Timer Register

(WDTR).Watch Dog Timer can be used 6-bit general Tim-

er or specific Watch dog timer by setting bit5 (WDTON)

of Clock Control Register (CKCTLR).By assigning

bit6(WDTCL) of WDTR, 6-bit counter can be cleared.

As IFBIT (Basic Interval Timer Interrupt Request) is used

for input clock of WDT, Input clock cycle is possible from

512 us to 65,536 us by BTS. (at fex = 4MHz)

*At Hardware reset time,WDT starts automatically.

Therefore the user must select the CKCTLR and WDTR

before WDT overflow.

WDT Interrupt (IFWDT) interval is determined by the in-

terrupt IFBIT interval of Basic Interval Timer and the val-

ue of WDT Register.

-Reset WDTR value = 0F_h,=15

-Interval of WDT = 65,536 * 15 = 983040 us

(about 1second)

-Interval of IFWDT = (IFBIT interval) * (WDTR value)

W

6

W

5

W

4

W

3

W

2

W

1

W

0

7

-

ADDRESS: 0C8_H

INITIAL VALUE: -0001111_b

WDTR

WDTCL

BTCL

WDTR5 WDTR4 WDTR3 WDTR2

WDTR1 WDTR0

Watch Dog Timer Operation

0:Free-run

1:Automatically cleared, after one machine cycle

WDTON

IFBIT

WDT (6-bit)

To Reset circuit

WDT

INTERRUPT

IFWDT

Comparator

Clear

6

WDTR (6-bit)

[0C8_H]

Figure 12-1 Block diagram of Watch Dog Timer

Device come into the reset state by WDT

Note: When WDTR Register value is 63 (3Fh)

(Caution): Do not use “0” for WDTR Register value.

Nov. 2001 Ver 2.00

37

HMS81032E/HMS81032TL

13. Timer0, Timer1, Timer2

(1) Timer Operation Mode

Register (T1LD), Timer2 Data Register (T2DR). Any of

the PS0 ~ PS5, PS11 and external event input EC can be

selected as clock source for T0. Any of the PS0 ~ PS3, PS7

~ PS10 can be selected as clock T1. Any of the PS5 ~ PS12

can be selected as clock source for T2.

Timer consists of 16bit binary counter Timer0 (T0), 8bit

binary Timer1 (T1), Timer2 (T2), Timer Data Register,

Timer Mode Register (TM01, TM0, TM1, TM2) and con-

trol circuit. Timer Data Register Consists of Timer0 High-

MSB Data Register (T0HMD), Timer0 High-LSB Data

Register (T0HLD), Timer0 Low-MSB Data Register

(T0LMD), Timer0 Low-LSB Data Register (T0LLD),

Timer1 High Data Register (T1HD), Timer1 Low Data

* Relevant Port Mode Register (PMR1: 00C9h) value

should be assigned for event counter.

- 16-bit Interval Timer

- 16-bit Event Counter

Timer0 - 16-bit Input Capture

- Single/Modulo-N Mode

- Timer Output Initial Value Setting

- Timer0~Timer1 combination Logic Output

- One Interrupt Generating Every 2nd

Counter Overflow

- 16-bit rectangular-wave output

- 8-bit Interval Timer

Timer1

- 8-bit rectangular-wave output

- 8-bit Interval Timer

Timer2 - 8-bit rectangular-wave output

- Modulo-N Mode

Table 13-1 Timer Operation

16bit Timer (T0)

Resolution MAX. Count

8bit Timer (T1)

Resolution MAX. Count

8bit Timer (T2)

Resolution MAX. Count

PS0 (0.25us)

PS1 (0.5us)

PS2 (1us)

PS3 (2us)

PS4 (4us)

PS5 (8us)

PS11 (512us)

EC

16,384us

32,768us

65,536us

131,072us

262,144us

524,288us

33,554,432us

-

PS0 (0.25us)

PS1 (0.5us)

PS2 (1us)

64us

PS5 (8us)

2,048us

4,096us

128us

PS6 (16us)

PS7 (32us)

PS8 (64us)

PS9 (128us)

PS10 (256us)

PS11 (512us)

256us

8,192us

PS3 (2us)

512us

16,384us

32,768us

65,536us

131,072us

PS7 (32us)

PS8 (64us)

PS9 (128us)

PS10 (256us)

8,192us

16,384us

32,768us

65,536us

PS12 (1024us) 262,144us

Table 13-2 Function of Timer & Counter

38

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

T0HMD T0HLD

T0LMD T0LLD

T1HD

T1LD

T2DR

from

EC/R14

Timer0 (16bit)

Timer2(8bit)

Timer1(8bit)

TM01

7

0

T0OUTP T0INIT T1INIT

BTCL

TOUTS TOUTB

-

TOUT1 TOUT0

Edge

Selection

Polarity

Selection

Tout

Logic

from

INT2/R12

(Capture Signal)

T2OUT

(R15)

T0OUT

(R17)

TOUT

(REMOUT)

T1OUT

(R16)

Timer 01 mode register

TM01

R/W R/W

R/W R/W R/W R/W R/W

7

6

5

-

4

3

2

1

0

ADDRESS: 0DA_H

INITIAL VALUE: 00_H

T0OUTP T0INIT T1INIT

BTCL

TOUTS TOUTB

TOUT1 TOUT0

TOUT LOGIC

REMOUT Port Output Selection

(TOUT Logic or TOUTB)

0: Bit(TOUTB) Output Through REMOUT

1: TOUT Logic Output Through REMOUT

00: AND of T0 OUTPUT and T1 OUTPUT

01: NAND of T0 OUTPUT and T1 OUTPUT

10: OR of T0 OUTPUT and T1 OUTPUT

11: NOR of T0 OUTPUT and T1 OUTPUT

REMOUT Port Bit Control

Timer1 output initial value

0: REMOUT Output Low

1: REMOUT Output High

0: Timer1 output low

1: Timer1 output high

T0OUT Polarity Selection

Timer0 output initial value

0: T0OUT Polarity Equal to TOUT Logic input signal

1: T0OUT Polarity Reverse to TOUT Logic input signal

0: Timer0 output low

1: Timer0 output high

Figure 13-1 Block Diagram of Timer/Counter

Nov. 2001 Ver 2.00

39

HMS81032E/HMS81032TL

IEDS[5:4]

01

INT2

INTERRUPT

10

IFINT2

INT2/R12 PIN

11

MSB

16 BITS

LSB

T0HC

capture

T0LC

[0D5_H][0D6_H]

T0ST

CAP0

T0IFS

T0SL[2:0]

Edge Detector

delay

1

0

111

EC PIN

Interrupt

GEN.

CAP0

clear

IFT0

PS11

110

101

PS5

PS4

PS3

PS2

PS1

PS0

T0 COUNTER (16-bit)

100

011

010

001

000

OUTPUT

GEN.

T0OUT

Comparator

0

MUX(16-bit)

1

M UX

T0MOD T0CN

T0INIT

T0HMD

T0HLD

T0LMD

T0LLD

[0D5_H][0D6_H]

[0D3_H][0D4_H]

Timer 0 mode register

TM0

R/W R/W

R/W R/W R/W R/W R/W R/W

7

6

5

4

3

2

1

0

ADDRESS: 0D0_H

INITIAL VALUE: 00_H

CAP0 T0ST

T0CN T0M OD TB0TICFLS T0SL2 T0SL1 T0SL0

Timer0 input clock select (fex=4Mhz)

000: PS0 250ns

001: PS1 500ns

010: PS2 1us

Timer0 Interrupt select

0: Timer/Counter

1: Input capture (PS1:not supporting

input capture)

011: PS3 2us

100: PS4 4us

101: PS5 8us

110: PS11 512us

111: EC

Timer0 Start/Stop control

0: Timer0 Stop

1: Tiemr0 Start after clear

Timer0 Interrupt select

Timer0 Counter Continuation/Pause Control

0: Count Pause

0: Interrupt Every Count Overflow

1: Interrupt Every 2nd Count Overflow

1: Count Continuation

Timer0 Single/Modulo-N select

0: Modulo-N

1: Single Mode

Figure 13-2 Block Diagram of Timer0

40

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

T1ST

T1IFS

T1 COUNT REG.

[0D8_H]

T1SL[2:0]

PS10

Interrupt

GEN.

111

110

101

IFT1

PS9

PS8

PS7

PS3

PS2

PS1

PS0

clear

T1 COUNTER (8-bit)

100

011

010

001

000

OUTPUT

T1OUT

GEN.

Comparator

MUX(8-bit)

1

0

M UX

T1MOD T1CN

T1INIT

T1HD(8-bit)

[0D7_H]

T1LD(8-bit)

[0D8_H]

Timer 1 mode register

TM1

R/W R/W

R/W R/W R/W

7

6

5

4

3

2

1

0

ADDRESS: 0D1_H

INITIAL VALUE: 00_H

T1ST

T1CN T1MOD T1IFS BTC- L T1SL2 T1SL1 T1SL0

Timer1 input clock select (fex=4Mhz)

000: PS0 250ns

001: PS1 500ns

010: PS2 1us

Timer1 Start/Stop control

0: Timer1 Stop

1: Tiemr1 Start after clear

011: PS3 2us

100: PS7 32us

101: PS8 64us

110: PS9 128us

111: PS10 256us

Timer1 Counter Continuation/Pause Control

0: Count Pause

1: Count Continuation

Timer1 Single/Modulo-N select

0: Modulo-N

1: Single Mode

Timer1 Interrupt select

0: Interrupt Every Count Overflow

1: Interrupt Every 2nd Count Overflow

Figure 13-3 Block Diagram of Timer1

Nov. 2001 Ver 2.00

41

HMS81032E/HMS81032TL

T2ST

T2 COUNT REG.

[0D9_H]

T2SL[2:0]

PS12

111

Interrupt

GEN.

IFT2

PS11

110

clear

PS10

101

T2 COUNTER (8-bit)

PS9

100

PS8

011

OUTPUT

GEN.

PS7

010

T2OUT

Comparator

PS6

001

PS5

000

T2DR

M UX

T2CN

[0D9_H]

Timer 2 mode register

TM2

R/W R/W R/W R/W R/W

7

-

6

-

5

-

4

3

2

1

0

ADDRESS: 0D2_H

INITIAL VALUE: 00_H

T2ST BTT2CCLN T2SL2 T2SL1 T2SL0

Timer2 input clock select (fex=4Mhz)

000: PS5 8us

001: PS6 16us

Timer2 Start/Stop control

0: Timer2 Stop

1: Tiemr2 Start after clear

010: PS7 32us

011: PS8 64us

100: PS9 128us

Timer2 Counter Continuation/Pause Control

0: Count Pause

1: Count Continuation

101: PS10 256us

110: PS11 512us

111: PS12 1,024us

Figure 13-4 Block Diagram of Timer2

42

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

2) Timer0, Timer1

TIMER0 and TIMER1 have an up-counter. When value of

the up-counter reaches the content of Timer Data Register

(TDR), the up-counter is cleared to “00h”, and interrupt

(IFT0, IFT1) is occurred at the next clock.

T0 Data

MATCH

Register

(TDR = T0)

Value

6

T0 Value

5

4

3

2

1

0

TIME

Interrupt period

Timer 0 (IFT0)

Interrupt

Occur interrupt

Figure 13-5 Operation of Timer0

For Timer0, the internal clock (PS) and the external clock

(EC) can be selected as counter clock. But Timer1 and

Timer2 use only internal clock. As internal clock. Timer0

can be used as internal-timer which period is determined

by Timer Data Register (TDR). Chosen as external

clock, Timer0 executes as event-counter. The counter exe-

cution of Timer0 and Timer1 is controlled by T0CN,

T0ST, CAP0, T1CN, T1ST, of Timer Mode Register TM0

and TM1. T0CN, T1CN are used to stop and start Timer0

and Timer1 without clearing the counter. T0ST, T1ST is

used to clear the counter. For clearing and starting the

counter, T0ST or T1ST should be temporarily set to “0”

and then set to “1”. T0CN, T1CN, T0ST and T1ST should

be set “1”, when Timer counting-up. Controlling of CAP0

enables Timer0 as input capture. By programming of

CAP0 to “1”, the period of signal from INT2 can be mea-

sured and then, event counter value for INT2 can be read.

During counting-up, value of counter can be read Timer

execution is stopped by the reset signal (RESET=”L”)

Note: In the process of reading 16-bit Timer Data, first

read the upper 8-bit data. Then read the lower 8-bit data,

and read the upper 8-bit data again. If the earlier read upper

8-bit data are matched with the later read upper 8-bit data,

read 16-bit data are correct. If not, caution should be taken

in the selection of upper 8-bit data.

(Example)

1) Upper 8-bit Read 0A 0A

2) Lower 8-bit Read FF 01

3) Upper 8-bit Read 0B 0B

=====================

0AFF 0B01

Nov. 2001 Ver 2.00

43

HMS81032E/HMS81032TL

TDR

enable

disable

clear & start

stop

TIME

Timer 0 (IFT0)

Interrupt

Occur interrupt

T0ST

Start & Stop

T0ST = 1

T0ST = 0

T0CN

T0CN = 1

Control count

T0CN = 0

Figure 13-6 Start/Stop Operation of Timer0

T2

T3

T1

T0

INT2

Figure 13-7 Input capture operation of Timer0

44

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

3) Single/Modulo-N Mode

Timer0 (Timer1) can select initial (T0INIT, T1INIT of

TM01) output level of Timer Output port. If initial level is

“L”, Low-Data Register value of Timer Data Register is

transferred to comparator and T0OUT (T1OUT) is to be

“Low”, if initial level is High? High -Data Register is

transferred and to be “High”. Single Mode can be set by

Mode Select bit (T0MOD, T1MOD) of Timer Mode Reg-

ister (TM0, TM1) to “1” When used as Single Mode, Tim-

er counts up and compares with value of Data Register. If

the result is same, Time Out interrupt occurs and level

of Timer Output port toggle, then counter stops as reset

state. When used as Modulo-N Mode, T0MOD (T1MOD)

should be set “0”. Counter counts up until the value of Data

Register and occurs Time-out interrupt. The level of Timer

Output port toggle and repeats process of

counting the value which is selected in Data Register.

During Modulo-N Mode, If interrupt select bit (T0IFS,

T1IFS) of Mode Register is “0”, Interrupt occurs on every

Time-out. If it is “1”, Interrupt occurs every second time-

out.

Note: Timer Output is toggled whenever time out happen

[Single Mode]

8bit/16bit

counting

Timer-output toggle

Int occurs

Count stop

Timer Enable initial

value toggle

[Module-N Mode]

8bit/16bit

counting

Timer Enable initial

value toggle

Timer-output toggle

Int occurs (IFS=1) Each 2nd time out

Int occurs (IFS=0) when Time out

Figure 13-8 Operation Diagram for Single/Modulo-N Mode

(4) Timer 2

Timer2 operates as a up-counter. The content of T2DR are

compared with the contents of up-counter. If a match is

found. Timer2 interrupt (IFT2) is generated and the up-

counter is cleared to “00h”. Therefore, Timer2 executes as

a interval timer. Interrupt period is determined by the count

source clock for the Timer2 and content of T2DR.

When T2ST is set to “1”, count value of Timer 2 is cleared

and starts counting-up. For clearing and starting the

Timer2. T2ST have to set to “1” after set to “0”. In order to

write a value directly into the T2DR, T2ST should be set

to “0”. Count value of Timer2 can be read at any time.

Nov. 2001 Ver 2.00

45

HMS81032E/HMS81032TL

14. INTERRUPTS

The HMS81004E/08E/16E/24E/32E interrupt circuits

consist of Interrupt Mode Register (MOD), Interrupt en-

able register (IENH, IENL), Interrupt request flags of

IRQH, IRQL, Priority circuit and Master enable flag ("I"

flag of PSW). 8 interrupt sources are provided. The config-

uration of interrupt circuit is shown in Figure 14-1.

- 8 interrupt source (2Ext, 3Timer, BIT, WDT and

Key Scan)

- 8 interrupt vector

- Nested interrupt control is possible

- Programmable interrupt mode

The HMS81004E/08E/16E/24E/32E contains 8 interrupt

sources; 3 externals and 5 internals. Nested interrupt ser-

vices with priority control is also possible. Software inter-

rupt is non-maskable interrupt, the others are all maskable

interrupts.

(Hardware and software interrupt accept mode)

- Read and write of interrupt request flag are possible.

- In interrupt accept, request flag is automatically cleared.

Internal Data Bus

00CE_H

00CC_H

00CA_H

0

7

0

7

-

IENL

-

IENH

-

IMOD

00CF_H

IRQH

KSCN

KSCNR

INT1R

INT2R

T0R

I-flag

INT1

INT2

IFT0

To CPU

Interrupt

Vector

IFT1

IFT2

T1R

T2R

Address

Generator

IFWDT

IFBIT

WDTR

BITR

IRQL

00CD_H

Standby mode release

RESET

Figure 14-1 Block Diagram of Interrupt

46

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

14.1 Interrupt priority and sources

Each interrupt vector is independent and has its own pri-

ority. Software interrupt (BRK) is also available. Interrupt

source classification is shown in Table 14-1.

14.2 Interrupt control register

I flag of PSW is a interrupt mask enable flag. When I flag

= “0”, all interrupts become disable. When I flag = “1”, in-

terrupts can be selectively enabled and disabled by con-

tents of corresponding Interrupt Enable Register. When

interrupt is occurred, interrupt request flag is set, and Inter-

rupt request is detected at the edge of interrupt signal. The

accepted interrupt request flag is automatically cleared

during interrupt cycle process. The interrupt request flag

maintains “1” until the interrupt is accepted or is cleared in

program. In reset state, interrupt request flag register

(IRQH, IRQL) is cleared to “0”. It is possible to read the

state of interrupt register and to manipulate the contents of

register and to generate interrupt. (Refer to software inter-

rupt)

Mask

Priority

Reset/Interrupt

Hardware Reset

Key Scan

Symbol

RESET

INT Vector H

FFFF

INT Vector L

FFFE

Non-maskable

-

1

2

3

4

5

6

7

8

-

KSCNR

INT1R

INT2R

T0R

FFFB

FFFA

External Interrupt1

External Interrupt2

Timer0

FFF9

FFF8

FFF7

FFF6

Hardware Interrupt

Software Interrupt

FFF3

FFF2

maskable

Timer1

T1R

FFF1

FFF0

Timer2

T2R

FFEF

FFEE

FFE8

Watch Dog Timer

WDTR

FFE9

Basic Interval Timer BITR

BRK Instruction BRK

FFE7

FFE6

-

FFDF

FFDE

Table 14-1 Interrupt Source

Nov. 2001 Ver 2.00

47

HMS81032E/HMS81032TL

R/W R/W

WDTE BITE

ADDRESS: 0CC_H

INITIAL VALUE: -00- ----_B

-

IENL

MSB

LSB

Watchdog timer

Basic Interval Timer

VALUE

0: Disable

1: Enable

R/W R/W

KSCNE INT1E INT2E

MSB

R/W

R/W R/W R/W

T0E T1E T2E

ADDRESS: 0CE_H

INITIAL VALUE: 000- 000-_B

-

IENH

LSB

Key scan

Timer2

External interrupt 1

Timer1

Timer0

External interrupt 2

.

R/W R/W

WDTR BITR

ADDRESS: 0CD_H

INITIAL VALUE: -00- ----_B

-

IRQL

MSB

LSB

Watchdog timer

Basic Interval Timer

R/W R/W

KSCNR INT1R INT2R

MSB

R/W

R/W R/W R/W

T0R T1R T2R

ADDRESS: 0CF_H

INITIAL VALUE: 000- 000-_B

-

IRQH

LSB

Timer2

Key scan

External interrupt 1

Timer1

Timer0

External interrupt 2

Figure 14-2 Interrupt Enable & Request Flag

14.3 Interrupt accept mode

The interrupt priority order is determined by bit (IM1,

IM0) of IMOD register. The condition allow for accepting

interrupt is set state of the interrupt mask enable flag and

the interrupt enable bit must be “1”. In Reset state, these

IP3 - IP0 registers become all “0”.

48

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

l

R/W R/W

R/W R/W R/W R/W R/W R/W

Interrupt mode register

IMOD

7

6

5

4

3

2

1

0

ADDRESS: 0CA_H

INITIAL VALUE: --000000_B

-

IM 1

IM0

BTIPC3L

IP2

IP1

IP0

Priority

00: Fixed by hardware

01: Changeable by IP3~IP0

1x: Interrupt is inhibited

Selection interrupt

0001: KSCNR

0010: INT1R

0011: INT2R

0101: T0R

0110: T1R

0111: T2R

1010: WDTR

1011: BITR

Figure 14-3 Interrupt Accept Mode & Selection by IP3~IP0

14.4 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the

interrupt latch is cleared to “0” by a reset or an instruction. Inter-

rupt acceptance sequence requires 8 f_XINafter the completion of

the current instruction execution. The interrupt service task is ter-

minated upon execution of an interrupt return instruction [RETI].

2. Interrupt request flag for the interrupt source accepted is

cleared to “0”.

3. The contents of the program counter (return address)

and the program status word are saved (pushed) onto the

stack area. The stack pointer decreases 3 times.

Interrupt acceptance

4. The entry address of the interrupt service program is

read from the vector table address and the entry address

is loaded to the program counter.

1. The interrupt master enable flag (I-flag) is cleared to

“0” to temporarily disable the acceptance of any follow-

ing maskable interrupts. When a non-maskable inter-

rupt is accepted, the acceptance of any following

interrupts is temporarily disabled.

5. The instruction stored at the entry address of the inter-

rupt service program is executed.

Nov. 2001 Ver 2.00

49

HMS81032E/HMS81032TL

System clock

Instruction Fetch

Address Bus

SP-2

PSW

V.L.

V.H.

New PC

OP code

SP

SP-1

PC

Not used

PCH

PCL

V.L.

ADL

ADH

Data Bus

Internal Read

Internal Write

Interrupt Processing Step

Interrupt Service Task

V.L. and V.H. are vector addresses.

ADL and ADH are start addresses of interrupt service routine as vector contents.

Figure 14-4 Timing chart of Interrupt Acceptance and Interrupt Return Instruction

the program status word are automatically saved on the stack, but

External Interrupt1

Vector Table Address

accumulator and other registers are not saved itself. These regis-

ters are saved by the software if necessary. Also, when multiple

interrupt services are nested, it is necessary to avoid using the

same data memory area for saving registers.

Entry Address

012_H

0E3_H

0FFF8_H

0FFF9_H

0E_H

2E_H

0E312_H

0E313_H

The following method is used to save/restore the general-purpose

registers.

Example: Register save using push and pop instructions

Correspondence between vector table address for External Interrupt1

and the entry address of the interrupt service program.

INTxx: PUSH

PUSH

A

X

Y

;SAVE ACC.

;SAVE X REG.

;SAVE Y REG.

PUSH

A interrupt request is not accepted until the I-flag is set to “1”

even if a requested interrupt has higher priority than that of the

current interrupt being serviced.

interrupt processing

POP

RETI

Y

X

A

;RESTORE Y REG.

;RESTORE X REG.

;RESTORE ACC.

;RETURN

When nested interrupt service is required, the I-flag should be set

to “1” by “EI” instruction in the interrupt service program. In this

case, acceptable interrupt sources are selectively enabled by the

individual interrupt enable flags.

General-purpose register save/restore using push and pop instruc-

tions;

Saving/Restoring General-purpose Register

During interrupt acceptance processing, the program counter and

50

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

However, multiple processing through software for special fea-

tures is possible. Generally when an interrupt is accepted, the I-

flag is cleared to disable any further interrupt. But as user sets I-

flag in interrupt routine, some further interrupt can be serviced

even if certain interrupt is in progress.

main task

acceptance of

interrupt

service task

saving

registers

Example:

During Timer1 interrupt is in progress, INT1 interrupt

serviced without any suspend.

restoring

registers

TIMER1: PUSH

A

interrupt return

PUSH

LDM

EI

X

Y

IENH,#40H

IENL,#00H

;Enable INT1 only

;Disable other

;Enable Interrupt

:

14.5 BRK Interrupt

Software interrupt can be invoked by BRK instruction, which has

the lowest priority order.

:

LDM

POP

RETI

IENH,#0FFH ;Enable all interrupts

Interrupt vector address of BRK is shared with the vector of

TCALL 0 (Refer to Program Memory Section). When BRK inter-

rupt is generated, B-flag of PSW is set to distinguish BRK from

TCALL 0.

IENL,#0FFH

Y

X

A

Each processing step is determined by B-flag as shown in Figure

14-5

Main Program

service

TIMER 1

service

INT1

service

=0

enable INT1

B-FLAG

disable other

=1

EI

BRK or

TCALL0

BRK

INTERRUPT

ROUTINE

TCALL0

ROUTINE

Occur

TIMER1 interrupt

Occur

INT1

RETI

RET

enable INT1

enable other

Figure 14-5 Execution of BRK/TCALL0

In this example, the INT1 interrupt can be serviced without any

pending, even TIMER1 is in progress.

Because of re-setting the interrupt enable registers IENH,IENL

and master enable “EI” in the TIMER1 routine.

14.6 Multi Interrupt

If two requests of different priority levels are received simulta-

neously, the request of higher priority level is serviced. If re-

quests of the interrupt are received at the same time

simultaneously, an internal polling sequence determines by hard-

ware which request is serviced.

Figure 14-6 Execution of Multi Interrupt

14.7 External Interrupt

The external interrupt on INT1 and INT2 pins are edge triggered

depending on the edge selection register IEDS (address 0D8_H) as

shown in Figure14-7.

Nov. 2001 Ver 2.00

51

HMS81032E/HMS81032TL

INT1 pin

INT2 pin

IFINT1

INT1 INTERRUPT

IFINT2

INT2 INTERRUPT

2

Edge selection

Register

IEDS

[0CBH]

W

Ext. Int. Edge Selection reg.

IEDS

7

6

-

5

4

3

2

1

0

-

ADDRESS: 0CB_H

INITIAL VALUE: --0000--_B

-

IED2H IED2L IBETDC1LH IED1L

-

IED2*

IED1*

01: Falling Edge Selection

10: Rising Edge Selection

11: Both Edge Selection

01: Falling Edge Selection

10: Rising Edge Selection

11: Both Edge Selection

Figure 14-7 External Interrupt Block Diagram

Response Time

The INT1 ~ INT2 edge are latched into IFINT1 ~ IFINT2 at every

machine cycle. The values are not actually polled by the circuitry

until the next machine cycle. If a request is active and conditions

are right for it to be acknowledged, a hardware subroutine call to

the requested service routine will be the next instruction to be ex-

ecuted. The DIV itself takes twelve cycles. Thus, a minimum of

twelve complete machine cycles elapse between activation of an

external interrupt request and the beginning of execution of the

first instruction of the service routine.

max. 12 f_XINperiod

8 f_XINperiod

Interrupt

latched

Interrupt

processing

Interrupt

routine

goes

active

Figure 14-8 shows interrupt response timings.

Figure 14-8 Interrupt Response Timing Diagram

14.8 Key Scan Input Processing

Key Scan Interrupt is generated by detecting low or high

Input from each Input pin (R0, R1) is one of the sources

which release standby (SLEEP, STOP) mode. Key Scan

ports are all 16bit which are controlled by Standby Mode

Release Register (SMRR0, SMRR1). Key Input is consid-

ered as Interrupt, therefore, KSCNE bit of IEHN should be

set for correct interrupt executing, SLEEP mode and STOP

mode, the rest of executing is the same as that of external

Interrupt. Each SMRR Register bit is allowed for each port

(for Bit= “0”, no Key Input, for Bit= “1”, Key Input avail-

able). At reset, SMRR becomes “00h”. So, there is no Key

Input source.

52

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

Standby release level control register (SRLC) can select

the key scan input level “L” or “H” for standby release by

each bit pin (R0, R1). Standby release level control register

(SRLC) is write-only register and initialized as “00h” in re-

set state.

SMRR0

SRLC0

R00

R01

R02

R03

R04

R05

R06

R07

R0 PORT LOGIC

R1 PORT LOGIC

Internal

Key Scan

Input

R10

R11

R12

R13

R14

R15

R16

R17

SMRR1

SRLC1

W

7

6

5

4

3

2

1

0

ADDRESS: 0DC_H

INITIAL VALUE: 00_H

BTCL

KR04 KR03 KR02

KR07

KR06

KR05

KR01

KR00

SMRR0

KR0*

1: Select

0: No Select

W

7

6

5

4

3

2

1

0

ADDRESS: 0DD_H

INITIAL VALUE: 00_H

BTCL

KR14 KR13 KR12

KR17

KR16

KR15

KR11

KR10

SMRR1

SRLC0

KR1*

1: Select

0: No Select

W

7

W

6

W

0

W

5

W

4

W

3

W

2

W

1

ADDRESS: 0F6_H

INITIAL VALUE: 00_H

BTCL

KLR07 KLR06 KLR05 KLR04 KLR03 KLR02

KLR01 KLR00

KLR0*

1: High

0: Low

W

7

6

5

4

3

2

1

0

ADDRESS: 0F7_H

INITIAL VALUE: 00_H

BTCL

KLR17 KLR16 KLR15 KLR14 KLR13 KLR12

KLR11 KLR10

SRLC1

KLR1*

1: High

0: Low

Figure 14-9 Block Diagram of Key Scan Block

Nov. 2001 Ver 2.00

53

HMS81032E/HMS81032TL

15. STANDBY FUNCTION

15.1 Sleep Mode

SLEEP mode can be entered by setting the bit of SLEEP

mode register (SLPM). In the mode, CPU clock stops but

oscillator keeps running. B.I.T and a part of peripheral

hardware execute, but prescaler output which provide

clock to peripherals can be stopped by program. (Except,

PS10 can’t stopped.) In SLEEP mode, more consuming

power can be saved by not using other peripheral hardware

except for B.I.T. By setting ENPCK (peripheral clock con-

trol bit) of CKCTLR (clock control register) to “0”, periph-

eral hardware halted, and SLEEP mode is entered. To

release SLEEP mode by BITR (basic interval timer inter-

rupt), bit10 of prescaler should be selected as B.I.T input

clock before entering SLEEP mode. “NOP” instruction

should be follows setting of SLEEP mode for rising pre-

charge time of data bus line.

ADDRESS: 0F0_H

INITIAL VALUE: -------0b

Sleep Mode Control Register (W)

-

0

SLPM

SLPM0

0: Sleep mode release

1: sleep mode

ADDRESS: 0C7_H

INITIAL VALUE: --110111b

Clock Control Register (W)

7

6

5

4

3

2

1

0

CKCTLR

(ex) setting of SLEEP mode : set the bit of SLEEP

; mode register (SLPM)

ENPCK 0: Stopped

1: Provided

NOP

: NOP instruction

15.2 Stop Mode

STOP mode can be entered by STOP instruction during

program. In STOP mode, oscillator is stopped to make all

clocks stop, which leads to less power consumption. All

registers and RAM data are preserved. “NOP” instruction

should be follows STOP instruction for rising precharge

time of Data Bus line.

(ex) STOP : STOP instruction execution

NOP : NOP instruction

54

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

Clock Pulse

Generator

OSC

Circuit

CPU Clock

MUX

Basic

Interval

Timer

Prescaler

Clear

Control Signal

STOP

S

Q

S

Q

Overflow Detection

R

Release Signal from Interrupt

RESETB

Figure 15-1 Block Diagram of Standby Circuit

15.3 Standby mode release

Release of STANDBY mode is executed by RESET input

and Interrupt signal. Register value is defined when Reset.

When there is a release signal of STOP mode (Interrupt,

RESET input), the instruction execution starts after stabi-

lization oscillation time is set by value of BTS2 ~ BTS0

and set ENPCK to “1”.

Release Signal

RESETB

SLEEP

STOP

O

KSCN(Key Input)

INT1,INT2

B.I.T.

Table 15-1 Release Signal of Standby Mode

Nov. 2001 Ver 2.00

55

HMS81032E/HMS81032TL

Release Factor

Release Method

RESETB

By RESETB Pin=Low level, Standby mode is released and system is initialized

Standby mode is released by low input of selected pin by key scan Input(SMRR0,SMRR1).

In case of interrupt mask enable flag= “0”, program executes just after standby instruction,

if flag= “1” enters each interrupt service routine.

KSCN(Key Input)

When external interrupt (INT1,INT2)ꢀenable flag is “1”, standby mode is released at the

rising edge of each terminal. When standby mode is released at interrupt. Mask Enable

flag= “0”, program executes from the next instruction of standby instruction. When “1”,

enters each interrupt service routine.

INT1,INT2

When B.I.T. is executed only by bit10 of prescaler(PS10), SLEEP mode can be released.

Interrupt release SLEEP mode, when BIT interrupt enable flag is “1”. When standby mode

is released at interrupt. Mask enable flag= “0”, program executes from the next instruction

of SLEEP instruction. When “1”, enters each interrupt service routine.

Basic Interval

Timer(IFBIT)

Table 15-2

SLEEP command

[SLEEP MODE]

Xin

SLEEP mode

release by interrupt

RESET

Longer than 2 machine cycle

[STOP MODE]

Xin

STOP mode

Stable OSC.time

release by interrupt

RESET

Program setting time by CKCTLR

Longer than stable OSC. Time

Figure 15-2 Block Diagram of Standby Circuit

56

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

15.4 Operation of standby mode release

After standby mode is released, the operation begins ac-

cording to content of related interrupt register just before

standby mode start (Figure 15-3).

STOP Command

Standby Mode

Interrupt Request GEN.

0

Int. enable reg.

1

Standby Mode Release

PSW

0

I Flag

1

Standby Next Command

Execution

Interrupt Service Routine

.

Figure 15-3 Standby Mode Release Flow

tering STOP mode, clock of bit10 (PS10) of prescaler is

selected or peripheral hardware clock control bit (ENPCK)

to “1”, Therefore the clock necessary for stabilization oscil-

lation time should be input into B.I.T. otherwise, standby

mode is released by reset signal. In case of interrupt re-

quest flag and interrupt enable flag are both “1”, standby

mode is not entered.

(1) Interrupt Enable Flag(I) of PSW = “0”

Release by only interrupt which interrupt enable flag =

“1”, and starts to execute from next to standby instruction

(SLEEP or STOP).

(2) Interrupt Enable Flag(I) of PSW = “1”

Released by only interrupt which each interrupt enable flag

= “1”, and jump to the relevant interrupt service routine.

Note: When STOP instruction is used, B.I.T should guar-

antee the stabilization oscillation time. Thus, just before en-

Nov. 2001 Ver 2.00

57

HMS81032E/HMS81032TL

Internal circuit

SLEEP mode

Active

STOP mode

Stop

Oscillator

Internal CPU

Register

RAM

Stop

Retained

Active

Retained

Stop

I/O port

Prescaler

PS10 selected:Active

Others: Stop

Basic Interval Timer

Stop

Watch-dog Timer

Timer

Stop

Address Bus,Data Bus

Retained

Table 15-3 Operation State in Standby Mode

58

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

16. RESET FUNCTION

16.1 External RESET

The RESET pin should be held at low for at least 2machine

cycles with the power supply voltage within the operating

voltage range and must be connected 0.1uF capacitor for

stable system initialization. The RESET pin contains a

Schmitt trigger with an internal pull-up resistor.

RESET

0.1uF capacitor

GND

Figure 16-1 RESET Pin connection

16.2 Power on RESET

Power On Reset circuit automatically detects the rise of

power voltage (the rising time should be within 50ms) the

power voltage reaches a certain level, RESET terminal is

maintained at “L” Level until a crystal ceramic oscillator

oscillates stably. After power applies and starting of oscil-

lation, this reset state is maintained for about oscillation

cycle of 219 (about 65.5ms: at 4MHz).The execution of

built-in Power On Reset circuit is as follows:

detection circuit.

(2) Once B.I.T Overflow detection circuit is reset. Then,

Prescaler starts to count.

(3) Prescaler output is inputted into B.I.T and PS10 of

Prescaler output is automatically selected. If overflow of

B.I.T is detected, Overflow detection circuit is set.

4) Reset circuit generates maximum period of reset pulse

from Prescaler and B.I.T

(1) Latch the pulse from Power On Detection Pulse Gener-

ator circuit, and reset Prescaler, B.I.T and B.I.T Overflow

Nov. 2001 Ver 2.00

59

HMS81032E/HMS81032TL

VDD

Internal Reset

RESET

Noise

Filter

0.1uF

Power on

Detect Pulse

Generator

GND

Clear

Basic

Interval

Timer

B.I.T.

OSC

Circuit

PS10

MSB

Overflow

Detection

Circuit

Prescaler

Figure 16-2 Block Diagram of Power On Reset Circuit

Note: When Power On Reset, oscillator stabilization time

doesn`t include OSC. Start time.

VDD

Prescaler Count Start

OSC. Start Time

Figure 16-3 Oscillator stabiliaztion diagram

60

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

1

2

3

4

5

6

7

Oscillator

(X pin)

IN

RESET

ADDRESS

BUS

FFFE FFFF Start

?

DATA

BUS

OP

ADH

?

FE

ADL

MAIN PROGRAM

RESET Process Step

Stabilization Time

ADL and ADH are start addresses of interrupt service routine as vector contents.

Figure 16-4 Timing Diagram of Reset

16.3 Low voltage detection mode

(1) Low voltage detection condition

all port can be selected with Pull-up resistor by Mask op-

tion. If there is no information on the Mask option sheet,

the default pull up option (all port connect to pull-up resis-

tor) is selected.

An on board voltage comparator checks that VDD is at the

required level to ensure correct operation of the device. If

VDD is below a certain level, Low voltage detector forces

the device into low voltage detection mode.

(3) Release of Low Voltage Detection Mode

(2) Low Voltage Detection Mode

Reset signal result from new battery (normally 3V) wakes

the low voltage detection mode and come into normal reset

state. It depends on user whether to execute RAM clear

routine or not

There is no power consumption except stop current, stop

mode release function is disabled. All I/O port is config-

ured as input mode and Data memory is retained until volt-

age through external capacitor is worn out. In this mode,

LVD(V)

1.85

1.80

1.75

1.70

1.65

1.60

1.55

-25

-20 -15 -10 -5

0

5

10

15 20

25

30

35

40

45

50

55

60

65 70

75 80

85

90

Temperature (°C)

Figure 16-5 Low Voltage vs Temperature

Nov. 2001 Ver 2.00

61

HMS81032E/HMS81032TL

(4) SRAM BACK-UP after Low Voltage Detection.

about hours depend on Vdd-GND Capacitor

SRAM Data Backup

VDD

3V

Low Voltage detection point

2V(Min.)

1.7V(typ.20 °C)

Power on Reset

(SRAM retention)

0.7V(Vret)

0V

Power on Reset

(SRAM unstable)

Time

User replaces

batteries

User removes

batteries

Figure 16-6 Oscillator stabilizing diagram

Interrupt

disable

Stop release

All I/O port

disable

input Mode

Low Level

STOP

Remout port

OSC

All I/O port pull-up on

SRAM Data

Mask Option

retention until Fret

Table 16-1 The operation after Low Voltage detection

62

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

(5) S/W flow chart example after Reset using SRAM Back-up

RESET

Stack Pointer initialize

Check the SRAM value

(RAM Pattern, Checksum)

N

SRAM DATA

VALID?

Y

Clear all Ram area

Use Saved SRAM value

Main routine

Figure 16-7 S/W flow chart example after Reset using SRAM Back-up

Nov. 2001 Ver 2.00

63

HMS81032E/HMS81032TL

17. OVERVIEW OF HMS81032TL

17.1 Standard Mode pin assignment

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

24

23

22

21

20

19

18

17

16

15

14

13

R13

R12

R11

R10

VDD

XOUT

XIN

R14

R13

R12

R11

R10

VDD

XOUT

XIN

R14

R15

3

R16

4

R17

5

REMOUT

RESET

TEST

R07

REMOUT

RESET

TEST

R07

24Pin

(300mil width

PDIP & SOP)

6

28Pin

(300mil width

PDIP & SOP)

7

8

R00

R01

R02

R03

R20

R21

R22

R00

R01

R02

R03

R20

9

R06

10

11

12

13

14

10

11

12

R05

R04

VSS

R24

VSS

R23

39 38 37 36 35 34 33 32 31 30 29

1

2

20

19

18

17

16

15

14

13

12

11

R11

R10

R16

R17

40

28

27

26

25

24

23

22

21

20

19

18

NC

3

VDD

XOUT

XIN

REMOUT

RESET

TEST

R07

41

42

43

44

1

R17

R16

R15

R14

NC

R04

VSS

R24

R23

NC

4

20Pin

(300mil width

PDIP & SOP)

5

6

R00

7

R01

R06

8

R02

R05

44Pin PLCC

2

R13

R12

R11

R10

NC

R22

R21

R20

R03

NC

9

R03

R04

3

10

R20

VSS

4

5

6

7

8

9

10 11 12 13 14 15 16 17

Figure 17-1 Standard Mode pin assignment

64

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

17.2 PROM Mode pin assignment

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

No Connect

3

AL ꢀ

ꢂ WE

4

AH ꢀ

ꢂ VE

5

ꢂ RDE

VDD ꢀ

6

ꢂ VSS

7

VSS ꢀ

ꢂ VPP

28Pin

8

A0 / A8 / D0 ꢁ

A1 / A9 / D1 ꢁ

A2 / A10 / D2 ꢁ

A3 / A11 / D3 ꢁ

R20 ꢀ

ꢁ D7 / A15 / A7

ꢁ D6 / A14 / A6

ꢁ D5 / A13 / A5

ꢁ D4 / A12 / A4

ꢂ VSS

9

10

11

12

13

14

No Connect

Figure 17-2 pin assignment

Nov. 2001 Ver 2.00

65

HMS81032E/HMS81032TL

17.3 Standard Mode Pin Desciption

Pin Number

Input

Output

Type

Name

Function

@ RESET

@ STOP

20Pin

24Pin

28Pin

44Pin

R00

6

7

8

9

8

11

15

16

19

27

30

31

32

5

R01

9

ꢀ 8bit CMOS input with pull_up

resistor (option).

R02

8

10

11

14

15

16

17

4

10

11

18

19

20

21

3

ꢀ 8bit push-pull output.

ꢀ During output, pull-up resistor

is disabled automatically.

ꢀ Programmable key scan Input

function.

R03

9

Input

Output

Input

Remain

R04

12

13

14

15

2

R05

R06

R07

R10

R11/ INT1

R12/ INT2

R13

1

3

4

ꢀ 8bit CMOS input with pull_up

resistor (option).

---

20

19

10

---

5

2

3

ꢀ 8bit push-pull output.

ꢀ During output, pull-up resistor

is disabled automatically.

ꢀ Programmable key scan Input

function.

1

2

Input

Output

Input

Remain

R14 / EC

R15/T2

R16/T1

R17/T0

R20

24

23

22

21

12

---

7

28

27

26

25

12

13

14

15

16

---

7

44

43

42

41

20

21

22

24

25

13

14

36

10

9

ꢀ LED driver : include N-TR

ꢀ Programmable open drain output

R21

R22

ꢀ 8bit CMOS input with pull_up

resistor (option).

R23

Input

Output

ꢀ 8bit push-pull output.

Input

Remain

ꢀ During output, pull-up resistor

is disabled automatically.

ꢀ LED driver : include N-TR

R24

R25

R26

R27

XIN

Input

Oscillator Input

Low

XOUT

Output

4

6

Oscillator Output

High

Remocon signal output pin

Large current output capability

Low level

output

Low level

output

REMOUT

RESET

TEST

Output

Input

18

17

16

20

19

18

24

23

22

38

37

33

Low Active, include pull-up resistor,

External capacitor needed (0.1uF)

Low level

Remain

Input

Low Active, include pull-up resistor

Positive Power Supply

VDD

VSS

Power

3

5

8

11

---

13

---

17

---

26

35

Ground

66

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

17.4 PROM Mode Pin Description

Standard

Modeꢁ

Pin Name

EPROM

Modeꢁ

Pin Name

Input

Output

Type

28Pin

Number

Function

1

R13

No Connection

2

R12

3

R11

AL

Input

Address Low Input Enable

Address High Input Enable

4

R10

AH

5

VDD

XOUT

XIN

VDD

Power

Positive Power Supply

Ground

6

VDD

7

VSS

8

R00

A0/A8/D0

A1/A9/D1

A2/A10/D2

A3/A11/D3

R20

9

R01

ꢀ Input Mode : Address 3~0

: Address 11~8

ꢀ Output Mode : Data 3~0

Input

Output

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

R02

R03

R20

Input

---

No Connection

Ground

R21

R22

R23

R24

VSS

R04

VSS

Power

A4/A12/D4

A5/A13/D5

A6/A14/D6

A7/A15/D7

VPP

R05

ꢀ Input Mode : Address 7~4

: Address 15~12

ꢀ Output Mode : Data 7~4

Input

Output

R06

R07

TEST

RESET

REMOUT

R17

Input

Power

Input

Program Voltage

Ground

VSS

RDE

Read Enable

Verify Enable

Program Enable

No Connection

VE

R16

WE

R15

R14

Nov. 2001 Ver 2.00

67

HMS81032E/HMS81032TL

17.5 EPROM Mode

Mode setting during power up

Mode setting

VPP

RDE

H

MS

H

L

VE

H

WE

H

AL

H

AH

H

PROM Write & Verify

PROM Verify or Read

LOCK Bit Write

11.5V

H

LOCK Bit Read

H

L

H

ROM Size Write

ROM Size Read

H

L

H

L

H

Mode setting after power up

Mode setting

VPP

RDE

L

MS

H

VE

WE

H

L

AL

H

L

AH

L

Remark

H

L

Address High Latch

Address Low Latch

PROM Write

PROM

Write

&

H

L

11.5V

H

L

Verify

H

L

PROM Verify

H

L

Address High Latch

Address Low Latch

PROM Verify or Read

R0=6X : LOCK Bit Write Data

Program

PROM

Verify

or

11.5V

L

H

L

Read

H

LOCK Bit

Write

11.5V

L

H

L

H

R0=6X : LOCK Bit Write Data

LOCK Bit

Read

LOCK Bit Read (R04 Port is High)

(R05 Port is Low)

H

L

H

68

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

Programming DC charateristics

Items

Input high voltage

Input low voltage

Output high voltage

Output low voltage

VDD current

Symbol

VIH

Min.

4.5

-0.1

4.0

-

Typ.

VDD

VSS

-

Max.

VDD+0.3

0.4

Unit

V

Test condition

-

VIL

V

VOH

VOL

IDD

-

V

IOH=-2.5mA

-

0.4

V

IOL=1mA

-

100

5.5

mA

V

-

VPP current

IPP

-

WE=VIL

VDD voltage

VDD

VPP

VSS

4.5

11.2

0

5.0

11.5

0

VPP voltage

11.8

0

V

-

VSS voltage

V

GROUND Level

Programming AC charateristics

(Vdd=5.0V±0.5V, Vpp=11.5V±0.3V, Vss=0V, Ta=25±5 °C)

Items

Symbol

Min.

Typ.

Max.

Unit

us

ns

us

ns

High Address Setup Time

High Address Pulse Width

High Address Hold Time

Low Address Setup Time

Low Address Pulse Width

Low Address Hold Time

Program Setup Time

Program Pulse Width

Program Hold Time

2

-

t^AHS

t^AH

-

2

-

t^AHH

2

-

ALS

t

2

-

t^AL

t^ALH

t^WES

t^WE

2

-

2

-

180

2

200

220

-

t^WEH

t^VED

t^VE

Data Out Delay Time

Data Out Time

-

150

-

2

Data Out Floating Time

-

130

t^VEF

Nov. 2001 Ver 2.00

69

HMS81032E/HMS81032TL

Verify or Read DC characteristics

(Vdd=5.0V±0.5V, Vpp=11.5V±0.3V, Vss=0V, Ta=25±5 °C)

Items

VDD Active current

Input high voltage

Input low voltage

Output high voltage

Output low voltage

Symbol

IDD1

VIH

Min.

Typ.

Max.

30

Unit

mA

V

Test condition

VE=VIL

-

VDD-0.2

-0.2

VDD+0.2

0.2

VIL

V

VOH

VOL

0.7VDD

-

V

IOH=-2.5mA

IOL=1mA

0.4

V

Verify or Read AC characteristics

(Vdd=5.0V±0.5V, Vpp=11.5V±0.3V, Vss=0V, Ta=25±5 °C)

Items

Symbol

t^AHS

t^AH

Min.

Typ.

Max.

Unit

us

ns

us

ns

High Address Setup Time

High Address Pulse Width

High Address Hold Time

Low Address Setup Time

Low Address Pulse Width

Low Address Hold Time

Address Delay Time

2

-

t^AHH

t^ALS

t^AL

-

t^ALH

t^ADD

t^VED

t_VE

170

150

-

Data Out Delay Time

Data Out Time

-

2

-

Data Out Hold Time

55

-

t^VEH

t^VEF

Data Out Floating Time

0

70

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

17.6 Timing Diagram in EPROM Mode

EPROM Write & Verify

5V

VDD

(VDD)

Min.

50ms

11.5V

VPP

(TESTB)

0V

VSS

(RESETB)

RDE

(REMOUT)

Min. Min.

2us 10us

Latch Timing

AH

(R10)

`H`

Latch Timing

tAHS tAH tAHH

AL

(R11)

tALS tAL tALH

WE

(R16)

tVED

tWES

tWE

tWEH

VE

(R17)

tVE tVEF

MS

(R20)

R0

[7:0]

AH

AL

DIN

DOUT

Verify

Mode setting

1Byte PGM

Repeat area

ꢀ 1. R0[7:0] address input is latched when AH(R10), AL(R11) is rising.

2. R0[7:0] Data out (DOUT) is valid during R17 is `Low`.

3. Writing time (R16 is `Low`) is 200us, and verify data.

Maximum repeat count is 20.

4. If cell can not be programmed within maximum repeat count, judge as IC is fail.

AH : High Byte Address Input

AL : Low Byte Address Input

DIN : Data Input

ꢀ

DOUT : Data Output

Nov. 2001 Ver 2.00

71

HMS81032E/HMS81032TL

EPROM Verify or Read

5V

VDD

(VDD)

Min.

50ms

11.5V

VPP

(TESTB)

0V

VSS

(RESETB)

RDE

(REMOUT)

Min. Min.

2us 10us

Latch Timing

AH

(R10)

`H`

Latch Timing

tALH

tAHS tAH tAHH

AL

(R11)

tALS tAL

WE

(R16)

tVED

VE

(R17)

tVE tVEF

MS

(R20)

R0

[7:0]

AH

AL

DOUT

Mode setting

Verify

ꢀ AH : High Byte Address Input

AL : Low Byte Address Input

DIN : Data Input

DOUT : Data Output

72

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

Lock Bit Write

5V

VDD

(VDD)

Min.

50ms

11.5V

VPP

(TESTB)

0V

VSS

(RESETB)

RDE

(REMOUT)

Min. Min.

2us 10us

Latch Timing

AH

(R10)

`H`

AHS AH AHH

t

AL

(R11)

WE

(R16)

WES

t

WE

t

WEH

t

VE

(R17)

MS

(R20)

`L`

R0

[7:0]

DIN ( 06XH )

Mode setting

PGM

ꢀ 1. DIN = 06XH : LOCK bit Write Data. ( X means “don’t care” )

2. Writing time (R16 is `Low`) is 200us, and can not verify locked or not in this mode.

Repeat count is fixed to 20.

Nov. 2001 Ver 2.00

73

HMS81032E/HMS81032TL

LOCK Bit Read

5V

VDD

(VDD)

Min.

50ms

11.5V

VPP

(TESTB)

0V

VSS

(RESETB)

RDE

(REMOUT)

Min. Min.

2us 10us

Latch Timing

AH

(R10)

`H`

ADD VE VEH

t

AHS AH AHH

t

AL

(R11)

VED

t

VEF

t

WE

(R16)

VE

(R17)

MS

(R20)

`L`

R0

[7:0]

DOUT

Mode setting

Lock bit Read

LOCK bit read

Normal Locked

R04

R05

L

H

L

74

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

17.7 Programming Flow Chart

Start

Set EPROM write to wirte/verify mode.

VDD = 5V ꢁ 0.5V

VPP = 11.5V ꢁ 0.3V

Start Address

n = 0

n + 1 ꢂ n

Yes

No

N ꢃ 20 ?

Data write : tWE = 200us ꢁ 10%

Fail

Verify

Pass

No

Last Address ?

Address + 1 ꢂ Address

Yes

Set EPROM write to Verify mode.

VDD = 5ꢁ0.5 V

VDD = 2.7ꢁ0.2 V

VPP = 11.5V

Fail

Verify all Address

Pass

Device Pass

Device Fail

ROM size : 32KB

Start address : 0x8000

End address : 0xFFFF

Blank data : 0x00

Nov. 2001 Ver 2.00

75

HMS81032E/HMS81032TL

17.8 REMOUT Port Ioh Characteristics Graph

(typical process & room temperature)

.

Ioh(mA)

0

Vdd 2V

-5

Vdd 3V

-10

-15

-20

-25

-30

Vdd 4V

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Voh (V)

Figure 17-3 Ioh vs Voh

17.9 REMOUT Port Iol Characteristics Graph

(typical process & room temperature)

.

Iol(mA)

5

4

3

Vdd 4V

2

Vdd 3V

1

Vdd 2V

0

-1

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Vol (V)

Figure 17-4 Iol vs Vol

76

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

LVD(V)

2.0

1.9

1.8

1.7

1.6

1.5

1.4

-25

-20 -15 -10 -5

0

5

10

15 20

25

30

35

40

45

50

55

60

65 70

75 80

85

90

Temperature (°C)

Figure 17-5 Low Voltage vs Temperature

Nov. 2001 Ver 2.00

77

HMS81032E/HMS81032TL

18. GENERAL CIRCUIT DIAGRAM

18.1 General circuit diagram of HMS81032E

In case of using high gain Tr for longer transmission distance application.

We recommend to attach proper value of capacitor between REMOUT pin

of chip and VSS of system to prevent excessive overshoot voltage of system

power (over the maximum supply VCC of chip) during signal transmission.

H M S81032E

R14

R15

24

23

22

21

20

19

18

17

16

15

14

13

R13

R12

R11

R10

V D D

X out

X in

1

2

Infrared LED

R16

3

R17

4

REM O U T

RESET

TEST

R07

5

0.1uF

6

4 M H z

7

R00

R01

R02

R03

R20

8

R06

9

above 220 uF

R05

10

11

12

+

-

R04

0.1uF

D C 3V

alkaline battery

V SS

Indicator LED

33 25

R 00

R 01

57 49 41

58 50 42

17

9

1

2

3

4

5

6

7

8

34 26

35 27

36 28

37 29

38 30

39 31

40 32

18 10

19 11

20 12

21 13

22 14

23 15

24 16

59 51

60 52

43

44

R 02

R 03

R 04

61 53 45

62 54 46

R 05

R 06

R 07

63 55

64 56

47

48

Figure 18-1 GENERAL CIRCUIT DIAGRAM OF HMS81032E

78

Nov. 2001 Ver 2.00

HMS8132E/HMS81032TL

18.2 General circuit diagram of HMS81032TL

H M S81032TL

R14

R15

24

23

22

21

20

19

18

17

16

15

14

13

R13

R12

R11

R10

V D D

X out

X in

1

2

Infrared LED

R16

3

R17

4

REM O U T

RESET

TEST

R07

5

0.1uF

6

4 M H z

7

8

R00

R01

R02

R03

R20

R06

9

above 220 uF

R05

10

11

12

+

R04

0.1uF

D C 3V

alkaline battery

-

V SS

Indicator LED

33 25

9

1

2

3

4

5

6

7

8

R 00

57 49 41

58 50 42

17

34 26

35 27

36 28

37 29

38 30

39 31

40 32

R 01

R 02

R 03

R 04

18 10

19 11

20 12

21 13

22 14

23 15

24 16

59 51

60 52

43

44

61 53 45

62 54 46

R 05

R 06

R 07

63 55

64 56

47

48

Figure 18-2 GENERAL CIRCUIT DIAGRAM OF HMS81032TL

Nov. 2001 Ver 2.00

79

HMS81032E/HMS81032TL

80

Nov. 2001 Ver 2.00

APPENDIX

A. MASK ORDER SHEET

MASK ORDER & VERIFICATION SHEET

E -UE

HMS810

Customer should write inside thick line box.

1. Customer Information

2. Device Information

20SOP

24SOP

20PDIP

Company Name

Application

24SKDIP

28SKDIP

Package

YYYY

MM

DD

28SOP

28PIN DIE

Order Date

Fax:

Tel:

Mask Data

Check Sum

File Name: (

(

.OTP)

@27c256)

Name&Signature:

3. Inclusion of pull-up resistor in Low Volatage Detection mode

*1

*2

*1

*2

R07

R05 R06

R15 R16

Port R00 R01 R02 R03 R04

Y/N

R10 R11 R12 R13 R14

R17

R20 R21 R22 R23 R24

*1 : is not avilable for 20PIN. So default option is pull-up on.

*2 : is not avilable for 20PIN & 24PIN. So default option is pull-up on.

4. Marking Specification

(Please check mark into

)

04/08/16/24/32

Customer’s logo

Hynix ROM Code

Number

E -UE

HMS810

YYWW

E -UE

KOREA

HMS810

YYWW

KOREA

Lot Number

Customer logo is not required.

If the customer logo must be used in the special mark, please submit a clean original of the logo.

Customer’s part number

5. Delivery Schedule

Date

MM

Quantity

pcs

Hynix Confirmation

YYYY

DD

Customer Sample

Risk Order

MM

This box is written after “6.Verification”.

6. ROM Code Verification

YYYY

MM

DD

YYYY

MM

DD

Approval Date:

Verification Date:

I agree with your verification data and confirm

you to m ake m ask set.

Please confirm our verification data.

Tel:

Fax:

Check Sum:

Name &

Signature:

Tel:

Name &

Signature:

Fax:

JUNE 2001

APPENDIX

B. INSTRUCTION

B.1 Terminology List

Terminology

Description

A

X

Accumulator

X - register

Y

Y - register

PSW

#imm

dp

Program Status Word

8-bit Immediate data

Direct Page Offset Address

Absolute Address

Indirect expression

Register Indirect expression

!abs

[ ]

{ }

{ }+

.bit

Register Indirect expression, after that, Register auto-increment

Bit Position

A.bit

dp.bit

M.bit

rel

Bit Position of Accumulator

Bit Position of Direct Page Memory

Bit Position of Memory Data (000_H~0FFF_H)

Relative Addressing Data

U-page (0FF00_H~0FFFF_H) Offset Address

Table CALL Number (0~15)

upage

n

+

Addition

Upper Nibble Expression in Opcode

0

x

y

Bit Position

Upper Nibble Expression in Opcode

1

−

×

Subtraction

Multiplication

/

Division

( )

Contents Expression

AND

OR

Exclusive OR

~

←

→

↔

=

NOT

Assignment / Transfer / Shift Left

Shift Right

Exchange

Equal

≠

Not Equal

NOV 2001 Ver 2.00

iii

APPENDIX

B.2 Instruction Map

00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111

LOW

HIGH

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

SET1

BBS

ADC

dp

ADC

dp+X

ADC

!abs

ASL

A

ASL

dp

TCALL SETA1

.bit

BIT

dp

POP

A

PUSH

A

000

-

BRK

dp.bit A.bit,rel dp.bit,rel #imm

0

SBC

#imm

SBC

dp

SBC

dp+X

SBC

!abs

ROL

A

ROL

dp

TCALL CLRA1 COM

POP

X

PUSH

X

BRA

rel

001

010

011

100

101

110

111

CLRC

CLRG

DI

2

.bit

dp

CMP

#imm

CMP

dp

CMP

dp+X

CMP

!abs

LSR

A

LSR

dp

TCALL NOT1

TST

dp

POP

Y

PUSH PCALL

Y

4

M.bit

Upage

OR

#imm

OR

dp

OR

dp+X

OR

!abs

ROR

A

ROR TCALL

dp

OR1

OR1B

CMPX

dp

POP

PSW

PUSH

PSW

RET

6

AND

#imm

AND

dp

AND

dp+X

AND

!abs

INC

A

INC

dp

TCALL AND1 CMPY CBNE

INC

X

CLRV

SETC

SETG

EI

TXSP

TSPX

XCN

8

AND1B

dp

dp+X

EOR

#imm

EOR

dp

EOR

dp+X

EOR

!abs

DEC

A

DEC

dp

TCALL EOR1 DBNE

XMA

dp+X

DEC

X

10

EOR1B

dp

LDA

#imm

LDA

dp

LDA

dp+X

LDA

!abs

LDY

dp

TCALL

12

LDC

LDCB

LDX

dp

LDX

dp+Y

TXA

TAX

DAS

LDM

dp,#imm

STA

dp

STA

dp+X

STA

!abs

STY

dp

TCALL

14

STC

M.bit

STX

dp

STX

dp+Y

XAX

STOP

LOW 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011

11100

1C

11101

1D

11110

1E

11111

1F

HIGH

10

11

12

13

14

15

16

17

18

19

1A

1B

BPL

rel

ADC

{X}

ADC

ASL

!abs

ASL

dp+X

TCALL

1

JMP

!abs

BIT

!abs

ADDW

dp

LDX

#imm

JMP

[!abs]

CLR1

dp.bit

BBC

000

A.bit,rel dp.bit,rel

!abs+Y [dp+X] [dp]+Y

BVC

rel

SBC

{X}

SBC

ROL

!abs

ROL

dp+X

TCALL CALL

TEST SUBW

!abs dp

LDY

#imm

JMP

[dp]

001

010

011

100

101

110

111

!abs+Y [dp+X] [dp]+Y

3

!abs

BCC

rel

CMP

{X}

CMP

LSR

!abs

LSR

dp+X

TCALL

5

TCLR1 CMPW CMPX CALL

MUL

!abs+Y [dp+X] [dp]+Y

!abs

dp

#imm

[dp]

BNE

rel

OR

{X}

OR

ROR

!abs

ROR TCALL DBNE CMPX LDYA CMPY

dp+X

RETI

!abs+Y [dp+X] [dp]+Y

7

Y

!abs

dp

#imm

BMI

rel

AND

{X}

AND

INC

!abs

INC

dp+X

TCALL

9

CMPY INCW

INC

Y

DIV

TAY

TYA

DAA

NOP

!abs+Y [dp+X] [dp]+Y

!abs

dp

BVS

rel

EOR

{X}

EOR

DEC

!abs

DEC

dp+X

TCALL

11

XMA

{X}

XMA

dp

DECW

dp

DEC

Y

!abs+Y [dp+X] [dp]+Y

BCS

rel

LDA

{X}

LDA

LDY

!abs

LDY

dp+X

TCALL

13

LDA

{X}+

LDX

!abs

STYA

dp

XAY

XYX

!abs+Y [dp+X] [dp]+Y

BEQ

rel

STA

{X}

STA

STY

!abs

STY

dp+X

TCALL

15

STA

{X}+

STX

!abs

CBNE

dp

!abs+Y [dp+X] [dp]+Y

iv

NOV 2001 Ver 2.00

APPENDIX

B.3 Instruction Set

Arithmetic / Logic Operation

Op

Code

Byte

No

Cycle

No

Flag

NVGBHIZC

No.

Mnemonic

Operation

1

ADC #imm

04

05

06

07

15

16

17

14

84

85

86

87

95

96

97

94

08

09

19

18

44

45

46

47

55

56

57

54

5E

6C

7C

7E

8C

9C

2C

DF

CF

A8

A9

B9

B8

AF

BE

2

3

2

1

2

3

2

1

2

3

2

3

2

1

2

3

2

3

2

1

2

3

1

2

3

4

5

6

3

2

3

4

5

6

3

2

4

5

2

3

4

5

6

3

2

3

4

2

3

4

3

2

4

5

2

Add with carry.

2

ADC dp

A ← ( A ) + ( M ) + C

3

ADC dp + X

ADC !abs

ADC !abs + Y

ADC [ dp + X ]

ADC [ dp ] + Y

ADC { X }

AND #imm

AND dp

4

NV--H-ZC

5

6

7

8

9

Logical AND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

A ← ( A ) ( M )

AND dp + X

AND !abs

AND !abs + Y

AND [ dp + X ]

AND [ dp ] + Y

AND { X }

ASL A

N-----Z-

N-----ZC

Arithmetic shift left

ASL dp

C

7

6 5 4 3 2 1 0

←

← ← ← ← ← ← ← ← ← “0”

ASL dp + X

ASL !abs

CMP #imm

CMP dp

CMP dp + X

CMP !abs

CMP !abs + Y

CMP [ dp + X ]

CMP [ dp ] + Y

CMP { X }

CMPX #imm

CMPX dp

CMPX !abs

CMPY #imm

CMPY dp

CMPY !abs

COM dp

Compare accumulator contents with memory contents

( A ) - ( M )

Compare X contents with memory contents

( X ) - ( M )

N-----ZC

Compare Y contents with memory contents

( Y ) - ( M )

1’S Complement : ( dp ) ← ~( dp )

Decimal adjust for addition

Decimal adjust for subtraction

Decrement

N-----Z-

N-----ZC

N-----Z-

DAA

DAS

DEC A

DEC dp

M ← ( M ) - 1

DEC dp + X

DEC !abs

DEC X

DEC Y

NOV 2001 Ver 2.00

v

APPENDIX

Op

Code

Byte

No

Cycle

No

Flag

NVGBHIZC

No.

Mnemonic

Operation

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

DIV

9B

A4

A5

A6

A7

B5

B6

B7

B4

88

89

99

98

8F

9E

48

49

59

58

5B

64

65

66

67

75

76

77

74

28

29

39

38

68

69

79

78

24

25

26

27

35

36

37

34

4C

1

2

3

2

1

2

3

1

2

3

1

2

3

2

1

2

3

1

2

3

2

3

2

1

2

12

2

3

4

5

6

3

2

4

5

2

4

5

9

2

3

4

5

6

3

2

4

5

2

4

5

2

3

4

5

6

3

Divide : YA / X Q: A, R: Y

NV--H-Z-

EOR #imm

EOR dp

Exclusive OR

A ← ( A ) ( M )

EOR dp + X

EOR !abs

EOR !abs + Y

EOR [ dp + X ]

EOR [ dp ] + Y

EOR { X }

INC A

N-----Z-

Increment

N-----ZC

N-----Z-

INC dp

M ← ( M ) + 1

INC dp + X

INC !abs

INC X

INC Y

LSR A

Logical shift right

LSR dp

N-----ZC

N-----Z-

7

6 5 4 3 2 1 0

C

“0” → → → → → → → → →

→

LSR dp + X

LSR !abs

MUL

Multiply : YA ← Y × A

Logical OR

OR #imm

OR dp

A ← ( A ) ( M )

OR dp + X

OR !abs

N-----Z-

OR !abs + Y

OR [ dp + X ]

OR [ dp ] + Y

OR { X }

ROL A

Rotate left through Carry

ROL dp

N-----ZC

7

6 5 4 3 2 1 0

C

← ← ← ← ← ← ← ←

ROL dp + X

ROL !abs

ROR A

Rotate right through Carry

6 5 4 3 2 1 0

→ → → → → → → →

ROR dp

7

C

ROR dp + X

ROR !abs

SBC #imm

SBC dp

Subtract with Carry

A ← ( A ) - ( M ) - ~( C )

SBC dp + X

SBC !abs

SBC !abs + Y

SBC [ dp + X ]

SBC [ dp ] + Y

SBC { X }

TST dp

NV--HZC

Test memory contents for negative or zero, ( dp ) - 00

Exchange nibbles within the accumulator

N-----Z-

H

89

XCN

CE

1

5

A ~A ↔ A ~A

0

7

4

3

vi

NOV 2001 Ver 2.00

APPENDIX

Register / Memory Operation

Op

Code

Byte

No

Cycle

No

Flag

NVGBHIZC

No.

Mnemonic

Operation

1

LDA #imm

C4

C5

C6

C7

D5

D6

D7

D4

DB

E4

1E

CC

CD

DC

3E

C9

D9

D8

E5

E6

E7

F5

F6

F7

F4

FB

EC

ED

FC

E9

F9

F8

2

3

2

1

3

2

3

2

3

2

3

2

1

2

3

2

3

1

2

1

2

3

4

5

6

3

4

5

2

3

4

2

3

4

5

6

7

4

5

4

5

2

4

5

6

5

4

Load accumulator

2

LDA dp

A ← ( M )

3

LDA dp + X

LDA !abs

LDA !abs + Y

LDA [ dp + X ]

LDA [ dp ] + Y

LDA { X }

LDA { X }+

LDM dp,#imm

LDX #imm

LDX dp

4

5

N-----Z-

6

7

8

9

X- register auto-increment : A ← ( M ) , X ← X + 1

Load memory with immediate data : ( M ) ← imm

Load X-register

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

--------

N-----Z-

X ← ( M )

LDX dp + Y

LDX !abs

LDY #imm

LDY dp

Load Y-register

Y ← ( M )

N-----Z-

--------

LDY dp + X

LDY !abs

STA dp

Store accumulator contents in memory

STA dp + X

STA !abs

STA !abs + Y

STA [ dp + X ]

STA [ dp ] + Y

STA { X }

STA { X }+

STX dp

( M ) ← A

X- register auto-increment : ( M ) ← A, X ← X + 1

Store X-register contents in memory

( M ) ← X

STX dp + Y

STX !abs

STY dp

--------

Store Y-register contents in memory

STY dp + X

STY !abs

TAX

( M ) ← Y

E8

9F

Transfer accumulator contents to X-register : X ← A

Transfer accumulator contents to Y-register : Y ← A

Transfer stack-pointer contents to X-register : X ← sp

Transfer X-register contents to accumulator: A ← X

Transfer X-register contents to stack-pointer: sp ← X

Transfer Y-register contents to accumulator: A ← Y

Exchange X-register contents with accumulator :X ↔ A

Exchange Y-register contents with accumulator :Y ↔ A

Exchange memory contents with accumulator

( M ) ↔ A

N-----Z-

--------

TAY

TSPX

AE

C8

8E

BF

EE

DE

BC

AD

BB

FE

TXA

TXSP

TYA

XAX

XAY

XMA dp

XMA dp+X

XMA {X}

XYX

N-----Z-

--------

Exchange X-register contents with Y-register : X ↔ Y

NOV 2001 Ver 2.00

vii

APPENDIX

16-BIT operation

Op

Code

Byte

No

Cycle

No

Flag

NVGBHIZC

No.

1

Mnemonic

Operation

16-Bits add without Carry

YA ← ( YA ) ( dp +1 ) ( dp )

ADDW dp

CMPW dp

DECW dp

INCW dp

LDYA dp

STYA dp

SUBW dp

1D

5D

BD

9D

7D

DD

3D

2

5

4

6

5

NV--H-ZC

N-----ZC

N-----Z-

--------

NV--H-ZC

Compare YA contents with memory pair contents :

2

(YA) − (dp+1)(dp)

Decrement memory pair

( dp+1)( dp) ← ( dp+1) ( dp) - 1

3

Increment memory pair

( dp+1) ( dp) ← ( dp+1) ( dp ) + 1

4

Load YA

YA ← ( dp +1 ) ( dp )

5

Store YA

( dp +1 ) ( dp ) ← YA

6

16-Bits subtract without carry

YA ← ( YA ) - ( dp +1) ( dp)

7

Bit Manipulation

Op

Code

Byte

No

Cycle

No

Flag

NVGBHIZC

No.

Mnemonic

Operation

1

2

AND1 M.bit

AND1B M.bit

BIT dp

8B

0C

1C

y1

3

2

3

2

1

3

2

1

3

4

5

4

2

5

4

5

4

2

6

Bit AND C-flag : C ← ( C ) ( M .bit )

Bit AND C-flag and NOT : C ← ( C ) ~( M .bit )

Bit test A with memory :

-------C

MM----Z-

3

Z ← ( A ) ( M ) , N ← ( M ) , V ← ( M )

4

BIT !abs

7

6

5

CLR1 dp.bit

CLRA1 A.bit

CLRC

Clear bit : ( M.bit ) ← “0”

Clear A bit : ( A.bit ) ← “0”

Clear C-flag : C ← “0”

Clear G-flag : G ← “0”

Clear V-flag : V ← “0”

--------

-------0

--0-----

-0--0---

-------C

--------

-------C

--------

-------1

--1-----

--------

6

2B

20

7

8

CLRG

40

9

CLRV

80

10

11

12

13

14

15

16

17

18

19

20

21

EOR1 M.bit

EOR1B M.bit

LDC M.bit

LDCB M.bit

NOT1 M.bit

OR1 M.bit

OR1B M.bit

SET1 dp.bit

SETA1 A.bit

SETC

AB

CB

4B

6B

x1

Bit exclusive-OR C-flag : C ← ( C )

( M .bit )

Bit exclusive-OR C-flag and NOT : C ← ( C ) ~(M .bit)

Load C-flag : C ← ( M .bit )

Load C-flag with NOT : C ← ~( M .bit )

Bit complement : ( M .bit ) ← ~( M .bit )

Bit OR C-flag : C ← ( C ) ( M .bit )

Bit OR C-flag and NOT : C ← ( C ) ~( M .bit )

Set bit : ( M.bit ) ← “1”

0B

A0

C0

EB

Set A bit : ( A.bit ) ← “1”

Set C-flag : C ← “1”

SETG

Set G-flag : G ← “1”

STC M.bit

Store C-flag : ( M .bit ) ← C

Test and clear bits with A :

A - ( M ) , ( M ) ← ( M ) ~( A )

22

23

TCLR1 !abs

TSET1 !abs

5C

3C

3

6

N-----Z-

Test and set bits with A :

A - ( M ) , ( M ) ← ( M ) ( A )

viii

NOV 2001 Ver 2.00

APPENDIX

Branch / Jump Operation

Op

Code

Byte

No

Cycle

No

Flag

NVGBHIZC

No.

Mnemonic

Operation

1

2

3

4

BBC A.bit,rel

BBC dp.bit,rel

BBS A.bit,rel

BBS dp.bit,rel

y2

y3

x2

x3

2

3

2

3

4/6

5/7

4/6

5/7

Branch if bit clear :

--------

if ( bit ) = 0 , then pc ← ( pc ) + rel

Branch if bit set :

if ( bit ) = 1 , then pc ← ( pc ) + rel

Branch if carry bit clear

if ( C ) = 0 , then pc ← ( pc ) + rel

5

6

BCC rel

BCS rel

BEQ rel

BMI rel

BNE rel

BPL rel

BRA rel

BVC rel

50

D0

F0

90

70

10

2F

30

2

2/4

4

--------

Branch if carry bit set

if ( C ) = 1 , then pc ← ( pc ) + rel

Branch if equal

if ( Z ) = 1 , then pc ← ( pc ) + rel

7

Branch if minus

if ( N ) = 1 , then pc ← ( pc ) + rel

8

Branch if not equal

if ( Z ) = 0 , then pc ← ( pc ) + rel

9

Branch if plus

if ( N ) = 0 , then pc ← ( pc ) + rel

10

11

12

Branch always

pc ← ( pc ) + rel

Branch if overflow bit clear

if (V) = 0 , then pc ← ( pc) + rel

2/4

Branch if overflow bit set

if (V) = 1 , then pc ← ( pc ) + rel

13

14

15

BVS rel

B0

3B

5F

2

3

2

2/4

8

CALL !abs

CALL [dp]

Subroutine call

M( sp)←( pc ), sp←sp - 1, M(sp)← (pc ), sp ←sp - 1,

H

L

8

--------

if !abs, pc← abs ; if [dp], pc ← ( dp ), pc ← ( dp+1 ) .

L

Compare and branch if not equal :

if ( A ) ≠ ( M ) , then pc ← ( pc ) + rel.

Decrement and branch if not equal :

if ( M ) ≠ 0 , then pc ← ( pc ) + rel.

Unconditional jump

H

16

17

18

19

20

21

22

CBNE dp,rel

CBNE dp+X,rel

DBNE dp,rel

DBNE Y,rel

JMP !abs

FD

8D

AC

7B

1B

1F

3F

3

2

3

2

5/7

6/8

5/7

4/6

3

--------

JMP [!abs]

JMP [dp]

5

pc ← jump address

4

U-page call

M(sp) ←( pc ), sp ←sp - 1, M(sp) ← ( pc ),

23

24

PCALL upage

TCALL n

4F

nA

2

1

6

8

--------

H

L

sp ← sp - 1, pc ← ( upage ), pc ← ”0FF ” .

L

H

Table call : (sp) ←( pc ), sp ← sp - 1,

H

M(sp) ← ( pc ),sp ← sp - 1,

L

pc ← (Table vector L), pc ← (Table vector H)

L

H

NOV 2001 Ver 2.00

ix

APPENDIX

Control Operation & Etc.

Op

Code

Byte

No

Cycle

No

Flag

NVGBHIZC

No.

1

Mnemonic

Operation

Software interrupt : B ← ”1”, M(sp) ← (pc ), sp ←sp-1,

M(s) ← (pc ), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1,

H

BRK

0F

1

8

---1-0--

L

pc ← ( 0FFDE ) , pc ← ( 0FFDF ) .

L

H

2

3

DI

EI

60

E0

FF

0D

2D

4D

6D

0E

2E

4E

6E

1

3

2

4

Disable all interrupts : I ← “0”

Enable all interrupt : I ← “1”

No operation

-----0--

-----1--

--------

4

NOP

5

POP A

sp ← sp + 1, A ← M( sp )

sp ← sp + 1, X ← M( sp )

sp ← sp + 1, Y ← M( sp )

sp ← sp + 1, PSW ← M( sp )

M( sp ) ← A , sp ← sp - 1

M( sp ) ← X , sp ← sp - 1

M( sp ) ← Y , sp ← sp - 1

M( sp ) ← PSW , sp ← sp - 1

Return from subroutine

6

POP X

--------

restored

--------

7

POP Y

8

POP PSW

PUSH A

PUSH X

PUSH Y

PUSH PSW

9

10

11

12

13

RET

6F

1

5

--------

sp ← sp +1, pc ← M( sp ), sp ← sp +1, pc ← M( sp )

L

H

Return from interrupt

sp ← sp +1, PSW ← M( sp ), sp ← sp + 1,

14

15

RETI

7F

1

6

3

restored

--------

pc ← M( sp ), sp ← sp + 1, pc ← M( sp )

L

H

STOP

EF

Stop mode ( halt CPU, stop oscillator )

x

NOV 2001 Ver 2.00


型号：	HMS81008
厂家：	ETC
描述：	REMOTE CONTROLLER 遥控器\n 遥控远程控制遥控器
文件：	总94页 (文件大小：1595K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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