HMS81C4316_技术文档

HMS81C43xx / GMS87C4060

HMS81C43xx/GMS87C4060

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

FOR TELEVISION

1. OVERVIEW

1.1 Description

The HMS81C43xx/GMS87C4060 is an advanced CMOS 8-bit microcontroller with 8~32K(60K) bytes of ROM. The device

is one of GMS800 family. The HYNIX’s HMS81C43xx/GMS87C4060 is a powerful microcontroller which provides a high-

ly flexible and cost effective solution to many TV applications. The HMS81C43xx/GMS87C4060 provides the following

standard features: 8~32K(60K) bytes of ROM, 256~512/1,536 bytes of RAM, 8-bit timer/counter .

Device name

ROM Size

RAM Size

Package

8~32K bytes

Mask ROM

256~512

bytes

HMS81C43xx

32 PDIP

60K bytes

EPROM

GMS87C4060

1,536 bytes

52 SDIP

1.2 GMS87C4060 (OTP) Features

• 60K Bytes On-chip Program Memory

- Timer/Counter : 8bit x 4ch (16bit x 2ch)

- Basic interval timer : 8bit x 1ch

- Watch Dog Timer

• 1,536 Bytes of On-chip Data RAM

(Included 256 bytes stack memory)

• Number of Interrupt sources : 18

• Instruction Cycle Time (ex:NOP)

- 0.5us at 8MHz

• On Screen Display

- Number of characters : 512 (6 characters are

reserved for IC test)

• 40 Programmable I/O pins

- 33 Input/Ooutput and 7 Output pins

- Character size : 12 dots(X) x 16 dots(Y)

- Character display size : Large, Medium, Small

- DIsplay capability : 24Characters x 16 Lines

- Character, Back ground color : 16kinds

- Special functions : Rounding, Outline, Sprite,

Shadow, Half Tone Background,...

• Serial I/O : 8bit x 1ch

2

• I C Bus interface

- Multimaster (2 Pairs interface pins)

• A/D Converter : 8bit x 6ch (TBD LSB)

• Pulse Width Modulation

- 14bit x 1ch

• Buzzer Driving port

- 500Hz ~ 250kHz @8MHz (Duty 50%)

-

8bit x 6ch

• Operating Range : 4.5V to 5.5V

• Timer

1.3 HMS81C43xx Family Features

• On-chip Program Memry and Data memry

HMS81C4332 ( 32K ROM, 512 RAM)

HMS81C4324 ( 24K ROM, 256 RAM)

HMS81C4316 ( 16K ROM, 256 RAM)

HMS81C4308 ( 8K ROM, 256 RAM)

(Included 64/256 bytes stack memory)

• Instruction Cycle Time (ex:NOP)

- 1.0us at 4MHz

• 21 Programmable I/O pins

- 19 Input/Output and 3 Output pins

2

• I C Bus interface

- Multimaster (2 Pairs interface pins)

November 2001 ver 1.2

1

HMS81C43xx / GMS87C4060

• A/D Converter : 8bit x 6ch (TBD LSB)

- Character size : 12 dots(X) x 16 dots(Y)

- Character display size : Large, Medium, Small

- DIsplay capability : 24Characters x 16 Lines

- Character, Back ground color : 8 kinds

- Special functions : Rounding, Outline,

Shadow, Half tone Background...

• Pulse Width Modulation

- 14bit x 1ch

-

8bit x 2ch

• Timer

- Timer/Counter : 8bit x 4ch (16bit x 2ch)

• Buzzer Driving port

- 250Hz ~ 125kHz @4MHz (Duty 50%)

- Basic interval timer : 8bit x 1ch

- Watch Dog Timer

• Operating Range : 4.5V to 5.5V

•

• Number of Interrupt sources : 18

• On Screen Display

- Number of characters : 256

1.4 Development Tools

The HMS81C43xx/GMS87C4060 is supported by a full-

HYNIX’s Macro Assembler /

Assembler / Linker

featured macro assembler / linker , OSD font editor, an in-

Linker

TM

circuit emulator CHOICE-Dr

.

Font Editor

Debugger

MS-Windows GUI version

CHOICE-Dr.

(with EVA81C4xxx board)

In Circuit Emulators

2

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

2. BLOCK DIAGRAM

R10 / AN0

R11 / AN1

R12 / AN2

R13 / AN3

R14 / AN4

R15 / AN5

R16 / VD

R17 / HD

R50 / BUZZ

R51 / PWM8

R52 / INT0

R53

R54 / YM

R55 / YS

R56 / I

R,G,B

OSC1

OSC2

OSD

Display

Memory

OSD (On Screen Display) Controller

R1

R5

Data bus

Buzzer

8bit A/D

Convertor

Accumulator

& Index X,Y

Stack pointer

PSW

ALU

Data

Memory

PC

PWM

14bit x 1

8bit x 6

Program

Memory

Interrupt Controller

Vector Table

8-bit Basic

Interval

Timer

RESET

System controller

TEST

8-bit x 4

Timer/

Counter

Interrupt

Interval

M easure

System

Serial I/O

Interface

I²C

Interface

Clock Controller

Watchdog

Timer

Timing generator

XIN

Clock generator

XOUT

Data bus

VDD

VSS

Power

Supply

R0

R6

R4

R2

R40 / PWM0

R67 / INT1

R00

R01

R02

R03

R04

R05

R06

R07

R20 / INT2

R21 / Sclk

R22 / Sout

R23 / Sin

R24 / INT3

R25 / EC2

R26 / INT4

R27 / EC3

R41 / PWM1

R42 / PWM2

R43 / PWM3

R44 / SCL0

R45 / SCL1 / PWM4

R46 / SDA0

R47 / SDA1 / PWM5

November 2001 ver 1.2

3

HMS81C43xx / GMS87C4060

3. PIN ASSIGNMENT

1

2

3

4

5

6

7

8

R17/HD

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

R

G

B

R56

R16/VD

R15/AN5

R14/AN4

R13/AN3

R12/AN2

R11/AN1

R10/AN0

Vss

R55/YS

R54/YM

OSC1

OSC2

TEST

Vdd

RESET

R53

R52/INT0

R51/PWM8

R50/BUZZ

R26/INT4

9

10

11

12

13

14

15

16

Xin

Xout

R47/SDA1/PWM5

R46/SDA0

R45/SCL1/PWM4

R44/SCL0

R27/EC3

R26/INT4

R25/EC2

R24/INT3

R23/Sin

R22/Sout

R21/Sclk

R20/INT2

R17/HD

R16/VD

RESET

Vss

1

2

3

4

5

6

7

8

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

R40/PWM0

R41/PWM1

R42/PWM2

R43/PWM3

R44/SCL0

R45/SCL1/PWM4

R46/SDA0

R47/SDA1/PWM5

R50/BUZZ

R51/PWM8

R52/INT0

R53

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

Xout

Xin

Vss

Vdd

TEST

OSC1

R15/AN5

R14/AN4

R13/AN3

R12/AN2

R11/AN1

R10/AN0

R07

OSC2

R54/YM

R55/YS

R56/I

B

G

R

R00

R01

R02

R06

R05

R04

R03

R67/INT1

4

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

4. PACKAGE DIAGRAM

UNIT: inch

HYNIX

HMS81C4332

TYP 0.600 BSC

1.665

1.645

0.550

0.530

MIN 0.015

0.140

0.120

0.022

0.015

0 ~ 15°

0.1 BSC

0.065

0.045

November 2001 ver 1.2

5

HMS81C43xx / GMS87C4060

Figure 4-1 52pin Shrink DIP Package Diagram

52

27

0 ~ 15

HYNIX

GMS87C4060

26

1

0.25 0.05

45.97 0.13

0.76 0.13

UNIT: mm

0.47 0.13

1.02 0.25

1.778

0.25

6

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

5. PIN FUNCTION

V

R40~R47

: R40~R43 are 8-bit NMOS open drain output

: Supply voltage.

DD

and R45~R47 are bidirectional CMOS Input / NMOS open

drain output port. R4 pins 1 or 0 written to the Port Direc-

tion Register can be used as outputs or inputs.

: Circuit ground.

SS

TEST

: Used for shipping inspection of the IC. For normal

operation, it should not be connected .

In addition, R4 serves the functions of the various follow-

ing special features.

RESET

: Reset the MCU.

X

: Input to the inverting oscillator amplifier and input to

IN

Port pin

Alternate function

the internal main clock operating circuit.

PWM0 (Pulse Width Modulation output 0)

PWM1 (Pulse Width Modulation output 1)

PWM2 (Pulse Width Modulation output 2)

PWM3 (Pulse Width Modulation output 3)

R40

R41

R42

R43

R44

R45

X

: Output from the inverting oscillator amplifier.

OUT

OSC1

circuit.

: Input to the internal On Screen Display operating

2

SCL0 (I C Clock 0)

OSC2

: Output from the inverting OSC1 amplifier.

2

SCL1 (I C Clock 1)

PWM4 (Pulse Width Modulation output 4)

R00~R07

: R0 is an 8-bit CMOS bidirectional I/O port. R0

pins 1 or 0 written to the Port Direction Register can be

used as outputs or inputs.

2

R46

R47

SDA0 (I C Data 0)

2

SDA1 (I C Data 1)

PWM5 (Pulse Width Modulation output 5)

R10~R17

: R1 is an 8-bit CMOS bidirectional I/O port. R1

pins 1 or 0 written to the Port Direction Register can be

used as outputs or inputs.

R50~R56

: R50~R53 are 4-bit CMOS bidirectional I/O and

R54~R56 are CMOS output port. R5 pins 1 or 0 written to

the Port Direction Register can be used as outputs or in-

puts.

In addition, R1 serves the functions of the various follow-

ing special features.

In addition, R5 serves the functions of the various follow-

ing special features.

Port pin

Alternate function

R10

R11

R12

R13

R14

R15

R16

R17

AN0 (A/D converter input 0)

AN1 (A/D converter input 1)

AN2 (A/D converter input 2)

AN3 (A/D converter input 3)

AN4 (A/D converter input 4)

AN5 (A/D converter input 5)

VD (Vertical Sync. input)

Port pin

Alternate function

BUZZ (Buzzer output)

PWM8 (Pulse Width Modulation output 8)

INT0 (External interrupt input 0)

YM (Back ground)

R50

R51

R52

R54

R55

R56

YS (Edge)

I (Intencity)

HD (Horisontal Sync. input)

R20~R27

: R2 is a 8-bit CMOS bidirectional I/O port. Each

R67

: R67 is an 1-bit CMOS bidirectional I/O port. R67

pins 1 or 0 written to the their Port Direction Register can

be used as outputs or inputs.

pins 1 or 0 written to the Port Direction Register can be

used as outputs or inputs.

In addition, R2 serves the functions of the various follow-

ing special features.

In addition, R67 serves the functions of the various follow-

ing special features.

Port pin

Alternate function

Port pin

Alternate function

R20

R21

R22

R23

R24

R25

R26

R27

INT2 (External interrupt input 2)

Sclk (Serial communication clock)

Sout (Serial communication data out)

Sin (Serial communication data in)

INT3 (External interrupt input 3)

EC2 (Event counter input 2)

R67

INT1 (External interrupt input 1)

R,G,B

: R,G,B CMOS output port. Each pins controls Red,

Green,. Blue color control.

INT4 (External interrupt input 4)

EC3 (Event counter input 3)

November 2001 ver 1.2

7

HMS81C43xx / GMS87C4060

PIN NAME

Pin No.

In/Out

Function

V

39

12, 40

38

11

14

13

37

36

9

-

Supply voltage

Circuit ground

DD

SS

TEST

I

For test purposes. Should not be connected. (N.C.)

Reset signal input

RESET

I

X

I

Main oscillation input

IN

X

O

I

Main oscillation output

OUT

OSC1

On screen display oscillation input

OSC2

O

I/O

O

On screen display osc. output

Horisontal Sync. input

Vertical Sync. input

Red signal output

Green signal output

Blue signal output

Intencity signal output

Edge signal output

Background signal output

8bit PWM

R17/HD

R16/VD

R

10

30

31

32

33

34

35

52

51

50

49

On screen display functions

G

B

R56/I

R55/YS

R54/YM

R40/PWM0

R41/PWM1

R42/PWM2

R43/PWM3

8bit PWM

PWM functions

R45/SCL1/

PWM4

2

47

45

I/O

Include I C Serial clock 1 (SCL1)

R47/SDA1/

PWM5

2

Include I C Serial data 1 (SDA1)

R51/PWM8

R44/SCL0

43

48

I/O

14bit PWM

2

I C Serial clock 0

2

I C functions

2

R46/SDA0

R23/Sin

46

5

I/O

I C Serial data 0

Serial data input

R22/Sout

R21/Sclk

R27/EC3

R25/EC2

R50/Buzzer

6

SCI functions

Serial data output

7

Serial communication clock

Event counter input 3

Event counter input 2

500Hz ~ 250KHz @8MHz

1

Timer event functions

Buzzer function

3

44

Table 5-1 Port Function Description

8

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

PIN NAME

R52/INT0

Pin No.

42

26

8

In/Out

I/O

Function

External interrupt input 0

External interrupt input 1

External interrupt input 2

External interrupt input 3

External interrupt input 4

Analog input 0

R67/INT1

R20/INT2

R24/INT3

R26/INT4

R10/AN0

R11/AN1

R12/AN2

R13/AN3

R14/AN4

R15/AN5

R00

External interrupt functions

4

2

20

19

18

17

16

15

29

28

27

25

24

23

22

21

41

Analog input 1

Analog input 2

A/D conversion functions

Analog input 3

Analog input 4

Analog input 5

R01

R02

R03

R04

Digital I/O functions

R05

R06

R07

R53

Table 5-1 Port Function Description

November 2001 ver 1.2

9

HMS81C43xx / GMS87C4060

6. PORT STRUCTURES

RESET

OSC1, OSC2

V_DD

Main frequency

clock

RESET

Noise

Canceler

OSC1

V_DD

V_SS

OSC2

OSDON

TEST

V_SS

V_DD

R00~07, R53

V_DD

V_SS

DB

Data Reg.

Dir. Reg.

X , X

IN

OUT

V_SS

MUX

V_DD

Main frequency

clock

RD

X_IN

V_SS

V_DD

R10~15 (AN0~5)

V_DD

X_OUT

DB

Data Reg.

Dir. Reg.

V_SS

MUX

RD

AN0~5

10

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

R16, 17, 20, 24, 25, 26, 27, 52, 67

R23/Sin

V_DD

DB

Data Reg.

Dir. Reg.

DB

Data Reg.

Dir. Reg.

Selection

DB

V_SS

MUX

M UX

DB

RD

HD,VD,

EC2~3

INT0~INT4

Sin

R21/Sclk, R22/Sout

R40~43 (PWM0~3)

DB

Data Reg.

DB

Data Reg.

Dir. Reg.

V_DD

M UX

PWM0~3

Selection

Sout, Sclk

Selection

V_SS

DB

R44, 45, 46, 47 (SCL, SDA, PWM)

V_SS

M UX

DB

Data Reg.

M UX

SCL,SDA

RD

PWM4,PWM5

Sclk

Selection

Dir. Reg.

DB

V_SS

M UX

RD

SCL, SDA

November 2001 ver 1.2

11

HMS81C43xx / GMS87C4060

R50/BUZZ, R51/PWM8

DB

Data Reg.

V_DD

M UX

Buzz, PWM8

Selection

Dir. Reg.

DB

V_SS

M UX

RD

R54/YM, R55/YS, R56/I

V_DD

OSD ON or Data Reg Write.

DB

Data Reg.

M UX

YM, YS, I

Selection

V_SS

R, G, B

V_DD

R, G, B

i

OSD_ON

V_SS

12

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

7. ELECTRICAL CHARACTERISTICS

7.1 Absolute Maximum Ratings

Supply voltage........................................... -0.3 to +6.0 V

Storage Temperature ................................-40 to +125 °C

Maximum current (ΣI ) ...................................... 80 mA

OL

Maximum current (ΣI )...................................... 50 mA

OH

Voltage on any pin with respect to Ground (V

............................................................... -0.3 to V +0.3

)

SS

Note: Stresses above those listed under "Absolute Maxi-

mum Ratings" may cause permanent damage to the de-

vice. This is a stress rating only and functional operation of

the device at any other conditions above those indicated in

the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for ex-

tended periods may affect device reliability.

DD

Maximum current out of V pin ........................100 mA

SS

Maximum current into V pin ............................80 mA

DD

Maximum current sunk by (I per I/O Pin) ........20 mA

OL

Maximum output current sourced by (I per I/O Pin)

OH

.................................................................................8 mA

7.2 Recommended Operating Conditions

Specifications

Unit

Parameter

Symbol

Condition

Min.

4.5

4

Max.

5.5

8

f

=8MHz

=16MHz

XIN

V

Supply Voltage

V

DD

f

OSC

f

V

=4.5~5.5V

Operating Frequency

MHz

XIN

DD

On Screen Display Oper-

ating Frequency

f

=4.5~5.5V

8

16

OSC

DD

T

Operating Temperature

-10

70

C

°

OPR

7.3 DC Electrical Characteristics - HMS81C43xx

(T =-10~70°C, V =4.5~5.5V),

A

DD

Specifications

Typ.

Parameter

Symbol

Condition

Unit

Min.

Max.

TEST, RESET, Xin, OSC1, R17~16,

R27~20, R47~44, R52, R67

V

0.8 V

0.7 V

0

V

-

V

IH1

DD

High level input voltage

Low level input voltage

V

R0, R15~10, R53~50

IH2

DD

TEST, RESET, Xin, OSC1, R17~16,

R27~20, R47~44, R52, R67

V

0.12 V

IL1

DD

V

0.3 V

R0, R15~10, R53~50

0

IL2

DD

I

= -5mA

OH

V

- 1

-

DD

R0, R1, R2, R5, R67

V

High level output voltage

Low level output voltage

OH

I

= -1.2mA

OH

-

V

DD

-

R,G,B

I

OL

= 5mA

V

1.0

30

OL

R0, R1, R2, R4, R5, R67, R, G, B

Supply current in

ACTIVE mode

I

V

-

mA

DD

November 2001 ver 1.2

13

HMS81C43xx / GMS87C4060

Specifications

Typ.

Parameter

Symbol

Condition

Unit

Min.

Max.

V

TEST

= 5.5v, V

= 0.4V

DD

I

pull-up lekage current

-1.5

-400

A

µ

RUP

V

= 5.5V V

= V

DD

,

High input leakage

current

I

All input, I/O pins except X , OSC1,

R47~40

-5

-

5

IZH

IN

V

= 5.5V V

= 0V

DD

,

Low input leakage

current

I

All input, I/O pins except X , OSC1,

R47~44

A

µ

IZL

IN

V

= 5.5V V = V , N-ch Tr. off

Open drain leakage

current

DD

,

OH

DD

I

-

10

-

LOZ

R47~40

RAM data retention

voltage

V

1.2

V

RAM

DD

V

= 4.5V

DD

,

= V

= 2.25V

SCL0

SDA0

SCL1

SDA1

2

I C port impedance

R

-

120

-

Ω

BS

(I/O Transistor off)

SCL0:SCl1 (R44:R45)

SDA0:SDA1 (R46:R47)

Vt+ ~

Vt-

TEST, RESET, Xin, OSC1, R17~16,

R27~20, R47~44, R52, R67

Hysterisis

1.0

V

14

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

7.4 A/D Comparator Characteristics

(T =-10~70°C, V =5.0V)

A

DD

Specifications

Unit

Parameter

Symbol

Pins

Min.

Typ.

Max.

V

Analog Input Voltage Range

Accuracy

AN0~AN5

-

V

AIN

SS

DD

N

-

LSB

ΤΒ∆

FS

7.5 AC Characteristics

(T =-10~70°C, V =5V±10%, V =0V)

A

DD

SS

Specifications

Parameter

Symbol

Pins

Unit

Min.

Typ.

Max.

8

f

X

IN

4

-

MHz

nS

XIN

Operating Frequency

f

OSC

8

16

OSC

t

X

62.5

125

MCPW

IN

External Clock Pulse Width

External Clock Transition Time

t

S

0.5

S

µ

SCPW

CLK

t

X

-

20

-

nS

MRCP, MFCP

IN

t

S

SRCP, SFCP

CLK

t

ST

X , X

IN OUT

Oscillation Stabilizing Time

Interrupt Pulse Width

RESET Input Width

-

mS

1

t

INT0~4

RESET

2

t

IW

SYS

1

t

8

2

-

RST

SYS

Event Counter Input Pulse

Width

1

t

EC2, EC3

t

ECW

SYS

t

Event Counter Transition Time

20

nS

REC, FEC

1. t_SYSis one of 2/f_XINmain clock operation mode,

November 2001 ver 1.2

15

HMS81C43xx / GMS87C4060

t_MCPW

1/f_XIN

V_DD-0.5V

X

S

IN

0.5V

t_MRCP

t_SCPW

t_MFCP

t_SCPW

1/f_SCLK

V_DD-0.5V

CLK

t_SRCP

t_SFCP

t_IW

INT0 ~ 4

0.8V_DD

0.2V_DD

t_RST

RESET

0.2V_DD

t_ECW

0.8V_DD

EC2, EC3

0.2V_DD

t_REC

t_FEC

Figure 7-1 Timing Chart

16

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

7.6 Typical Characteristics

This data will generate after evaluation.

Not available at this time.

November 2001 ver 1.2

17

HMS81C43xx / GMS87C4060

8. MEMORY ORGANIZATION

The GMS81C43xx/GMS87C4060 has separate address

spaces for Program memory, Data Memory and Display

memory. Program memory can only be read, not written

to. It can be up to 32K/60K bytes of Program memory.

Data memory can be read and written to up to 256~512/

1,536 bytes including the stack area. Font memory has pre-

pared 16K bytes for OSD.

8.1 Registers

This device has six registers that are the Program Counter

(PC), a Accumulator (A), two index registers (X, Y), the

Stack Pointer (SP), and the Program Status Word (PSW).

The Program Counter consists of 16-bit register.

(save or restore).

Generally, SP is automatically updated when a subroutine

call is executed or an interrupt is accepted. However, if it

is used in excess of the stack area permitted by the data

memory allocating configuration, the user-processed data

may be lost.

ACCUMULATOR

X REGISTER

A

X

The stack can be located at any position within 0100 to

H

01FF of the internal data memory. The SP is not initial-

H

Y

Y REGISTER

ized by hardware, requiring to write the initial value (the

location with which the use of the stack starts) by using the

SP

STACK POINTER

initialization routine. Normally, the initial value of "FF "

H

PCH

PCL

PROGRAM COUNTER

is used.

PROGRAM STATUS

WORD

PSW

Stack Address ( 0100_H~ 013F or 01FF_H

)

15

8

7

0

01

SP

Figure 8-1 Configuration of Registers

Hardware fixed

Accumulator:

The Accumulator is the 8-bit general pur-

pose register, used for data operation such as transfer, tem-

porary saving, and conditional judgement, etc.

Caution:

The Accumulator can be used as a 16-bit register with Y

Register as shown below.

The Stack Pointer must be initialized by software be-

cause its value is undefined after RESET.

Y

Example: To initialize the SP for 81C4324 (256 RAM)

Y

A

LDX

TXSP

#03FH

; SP ← 3F

H

A

Two 8-bit Registers can be used as a "YA" 16-bit Register

Program Counter

: The Program Counter is a 16-bit wide

which consists of two 8-bit registers, PCH and PCL. This

counter indicates the address of the next instruction to be

executed. In reset state, the program counter has reset rou-

Figure 8-2 Configuration of YA 16-bit Register

X, Y Registers

: In the addressing mode which uses these

index registers, the register contents are added to the spec-

ified address, which becomes the actual address. These

modes are extremely effective for referencing subroutine

tables and memory tables. The index registers also have in-

crement, decrement, comparison and data transfer func-

tions, and they can be used as simple accumulators.

tine address (PC :0FF , PC :0FE ).

H

L

H

Program Status Word

: The Program Status Word (PSW)

contains several bits that reflect the current state of the

CPU. The PSW is described in Figure 8-3 . It contains the

Negative flag, the Overflow flag, the Break flag the Half

Carry (for BCD operation), the Interrupt enable flag, the

Zero flag, and the Carry flag.

Stack Pointer

: The Stack Pointer is an 8-bit register used

for occurrence interrupts and calling out subroutines. Stack

Pointer identifies the location in the stack to be accessed

[Carry flag C]

This flag stores any carry or borrow from the ALU of CPU

18

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

after an arithmetic operation and is also changed by the

Shift Instruction or Rotate Instruction.

MSB

LSB

C

N

V

G

B

H

I

Z

RESET VALUE : 00_H

CARRY FLAG RECEIVES

PSW

NEGATIVE FLAG

CARRY OUT

OVERFLOW FLAG

ZERO FLAG

SELECT DIRECT PAGE

when G=1, page is addressed by RPR

INTERRUPT ENABLE FLAG

HALF CARRY FLAG RECEIVES

CARRY OUT FROM BIT 1 OF

BRK FLAG

ADDITION OPERLANDS

Figure 8-3 PSW (Program Status Word) Register

[Zero flag Z]

[Direct page flag G]

This flag is set when the result of an arithmetic operation

or data transfer is "0" and is cleared by any other result.

This flag assigns RAM page for direct addressing mode. In

the direct addressing mode, addressing area is from zero

page 00 to 0FF when this flag is "0". If it is set to "1",

addressing area is assigned by DPGR register (address

H

[Interrupt disable flag I]

This flag enables/disables all interrupts except interrupt

caused by Reset or software BRK instruction. All inter-

rupts are disabled when cleared to "0". This flag immedi-

ately becomes "0" when an interrupt is served. It is set by

the EI instruction and cleared by the DI instruction.

0F8 ). It is set by SETG instruction and cleared by CLRG.

H

[Overflow flag V]

This flag is set to "1" when an overflow occurs as the result

of an arithmetic operation involving signs. An overflow

occurs when the result of an addition or subtraction ex-

[Half carry flag H]

ceeds +127(7F ) or -128(80 ). The CLRV instruction

H

After operation, this is set when there is a carry from bit 3

of ALU or there is borrow from bit 4 of ALU. This bit can

not be set or cleared except CLRV instruction with Over-

flow flag (V).

clears the overflow flag. There is no set instruction. When

the BIT instruction is executed, bit 6 of memory is copied

to this flag.

[Negative flag N]

[Break flag B]

This flag is set to match the sign bit (bit 7) status of the re-

sult of a data or arithmetic operation. When the BIT in-

struction is executed, bit 7 of memory is copied to this flag.

This flag is set by software BRK instruction to distinguish

BRK from TCALL instruction with the same vector ad-

dress.

November 2001 ver 1.2

19

HMS81C43xx / GMS87C4060

At execution of

a CALL/TCALL/PCALL

At acceptance

of interrupt

At execution

of RET instruction

At execution

of RETI instruction

01FC

01FD

01FE

01FC

01FD

01FE

01FC

01FD

01FE

PSW

01FD

Push

down

Pop

up

01FE

01FF

PCL

PCH

PCL

PCH

PCL

down

Pop

up

PCH

01FF

SP before

execution

01FF

01FD

01FF

01FC

01FD

01FF

01FC

01FF

SP after

execution

At execution

of PUSH instruction

PUSH A (X,Y,PSW)

of POP instruction

POP A (X,Y,PSW)

01FC

0100H

Stack

depth

01FD

01FE

01FD

01FE

Push

down

Pop

up

A

01FF

01FFH

SP before

01FF

01FE

01FF

execution

SP after

execution

Figure 8-4 Stack Operation

20

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

8.2 Program Memory

A 16-bit program counter is capable of addressing up to

64K bytes, but HMS81C43xx/GMS87C4060 has 8~32K/

60K bytes program memory space only physically imple-

Example: Usage of TCALL

LDA

#5

TCALL 0FH

;

1BYTE INST RU CT IO N

IN STEAD O F 2 BYTES

N O R M AL CALL

mented. Accessing a location above FFFF will cause a

H

:

wrap-around to 0000 .

H

;

;TABLE CALL ROUTINE

;

Figure 8-5 , shows a map of Program Memory. After reset,

the CPU begins execution from reset vector which is stored

FUNC_A: LDA

LRG0

in address FFFE and FFFF as shown in Figure 8-6 .

H

RET

;

As shown in Figure 8-5 , each area is assigned a fixed lo-

cation in Program Memory. Program Memory area con-

tains the user program.

FUNC_B: LDA

LRG1

1

2

RET

;

;TABLE CALL ADD. AREA

;

ORG

DW

0FFC0H

FUNC_A

FUNC_B

;

TC ALL ADD R ESS AREA

87C4060:1000H

81C4332:8000H

81C4324:A000H

81C4316:C000H

The interrupt causes the CPU to jump to specific location,

where it commences the execution of the service routine.

The External interrupt 0, for example, is assigned to loca-

PROGRAM

MEMORY

81C4308:E000H

FEFFH

FF00H

tion 0FFFC . The interrupt service locations spaces 2-byte

H

interval: 0FFF8 and 0FFF9 for External Interrupt 1,

H

FFBFH

FFC0H

0FFFC and 0FFFD for External Interrupt 0, etc.

H

TCALL

AREA

PCALL

AREA

Any area from 0FF00 to 0FFFF , if it is not going to be

FFDFH

FFE0H

H

INTERRUPT

VECTOR AREA

used, its service location is available as general purpose

Program Memory.

FFFFH

Address

Vector Area Memory

I²C Bus Interface Interrupt Vector Area

Serial I/O Interrupt Vector Area

0FFE0_H

E2

Figure 8-5 Program Memory Map

E4

Page Call (PCALL) area contains subroutine program to

reduce program byte length by using 2 bytes PCALL in-

stead of 3 bytes CALL instruction. If it is frequently called,

it is more useful to save program byte length.

Basic Interval Timer Interrupt Vector Area

Watchdog Timer Interrupt Vector Area

External Interrupt 3/4 Vector Area

E6

E8

EA

Timer/Counter 3 Interrupt Vector Area

Timer/Counter 1 Interrupt Vector Area

V-Sync Interrupt Vector Area

EC

EE

Table Call (TCALL) causes the CPU to jump to each

TCALL address, where it commences the execution of the

service routine. The Table Call service area spaces 2-byte

for every TCALL: 0FFC0 for TCALL15, 0FFC2 for

F0

1 Frame Timer Interrupt Vector Area

F2

F4

F6

F8

FA

FC

FE

Timer/Counter 2 Interrupt Vector Area

Timer/Counter 0 Interrupt Vector Area

External Interrupt 2 Vector Area

External Interrupt 1 Vector Area

H

TCALL14, etc., as shown in Figure 8-7 .

On Screen Display Interrupt Vector Area

External Interrupt 0 Vector Area

RESET Vector Area

NOTE:

"-" means reserved area.

Figure 8-6 Interrupt Vector Area

November 2001 ver 1.2

21

HMS81C43xx / GMS87C4060

Address

Program Memory

TCALL 15

TCALL 14

TCALL 13

TCALL 12

TCALL 11

TCALL 10

TCALL 9

0FFC0_H

C1

C2

C3

C4

C5

C6

C7

C8

C9

CA

CB

CC

CD

CE

CF

Address

0FF00_H

PCALL Area Memory

PCALL Area

(192 Bytes)

TCALL 8

0FFBF_H

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DA

DB

DC

DD

DE

DF

TCALL 7

TCALL 6

TCALL 5

TCALL 4

TCALL 3

TCALL 2

TCALL 1

TCALL 0 / BRK *

NOTE:

* means that the BRK software interrupt is using

same address with TCALL0.

Figure 8-7 PCALL and TCALL Memory Area

PCALL→ rel

TCALL→ n

4F35

PCALL 35H

4A

TCALL 4

4A

01001010

4F

35

Reverse

þ

~

PC:

11111111

F_HF_H

11010110

D_H6_H

Upper address is

assumed 0FF_H.

~

Sub-routine

0D125H

0FF00H

Ã

0FF00H

À

0FF35H

0FFFFH

Sub-routine

0FFD6H

0FFD7H

25

D1

0FFFFH

22

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

Example: The usage software example of Vector address and the initialize part in HMS81C4324.

ORG

0FFE0H

DW

I2C

SERIAL

BIT

; I2C

; Serial I/O

; Basic interval timer

; Watch dog timer

; Interrupt 3/4

; Timer 3

WATCHDOG

INT3_4

TIMER3

TIMER1

VSYNC

One_Frame

TIMER2

TIMER0

INT2

; Timer 1

; Vertical Sync.

; 1 Frame interrupt

; Timer 2

; Timer 0

; Interrupt 2

; Interrupt 1

; On Screen Display

; Interrupt 0

; Reset

INT1

OSD

INT0

RESET

ORG

0A000H

; Start Address of 24 kbytes Program Memory

;********************************************

MAIN PROGRAM

;

*

;********************************************

;

RESET:

DI

; Disable All Interrupts

LDX

LDA

#0

; RAM Page0 Clear(!0000H->!00BFH)

RAM_CLR: STA

{X}+

#0C0H

RAM_CLR

CMPX

BNE

;

CALL

OSD_Stop

#03FH

; Stop OSD display

;

LDX

TXSP

; Stack Pointer Initialize

LDM

:

R0, #0

R0DD,#1000_0010B

; Normal Port 0

; Normal Port Direction

:

November 2001 ver 1.2

23

HMS81C43xx / GMS87C4060

8.3 Data Memory

Figure 8-8 shows the internal Data Memory space availa-

ble. Data Memory is divided into four groups, a user RAM,

control registers, Stack, and OSD memory.

Note: Write only registers can not be accessed by bit ma-

nipulation instruction. Do not use read-modify-write instruc-

tion. Use byte manipulation instruction.

0000H

Example; To write at CKCTLR

RAM (192 bytes)

Page0

LDM

CLCTLR,#09H ;Divide ratio ÷8

00C0H

Peripheral Reg. (64 bytes)

0100H

RAM (256 bytes)

Stack area

Stack Area

Page1

Page2

The stack provides the area where the return address is

saved before a jump is performed during the processing

routine at the execution of a subroutine call instruction or

the acceptance of an interrupt.

0200H

0300H

0400H

0500H

RAM (256 bytes)

Page3

Page4

When returning from the processing routine, executing the

subroutine return instruction [RET] restores the contents of

the program counter from the stack; executing the interrupt

return instruction [RETI] restores the contents of the pro-

gram counter and flags.

RAM (256 bytes)

RAM (64 bytes)

Page5

Page6

0600H

063FH

Empty area

The save/restore locations in the stack are determined by

the stack pointed (SP). The SP is automatically decreased

after the saving, and increased before the restoring. This

means the value of the SP indicates the stack location

number for the next save. Refer to Figure 8-4 on page 20.

0A00H

0AE0H

OSD RAM (192 bytes)

PageA

PageC

Peripheral Reg. (32 bytes)

Sprite RAM (96 bytes)

0C00H

0C5FH

Figure 8-8 Data Memory Map

User Memory

Addressing

Address

Symbol

R/W Reset Value

mode

The GMS87C4060 has 1,536 × 8 bits for the user memory

(RAM). HMS81C4332 has 512 x 8 bit for the user mem-

1

00C0H

00C1H

00C2H

00C3H

00C4H

00C5H

00C8H

00C9H

00CAH

00CBH

00CCH

00CDH

00CEH

00CFH

R0

R0DD

R1

R1DD

R2

R2DD

R4

R4DD

R5

R5DD

R6

R6DD

FUNC1

FUNC2

R/W

W

R/W

W

R/W

W

R/W

W

R/W

W

R/W

W

byte, bit

????????

00000000

????????

00000000

????????

00000000

????????

0000----

????????

----0000

?-------

0-------

-0000000

---00000

2

byte

Peripheral Reg. (64

ory (RAM) addressed 000H ~ 23FH except

byte, bit

byte

byte, bit

byte

byte, bit

byte

byte, bit

byte

bytes)

. HMS81C4308/16/24 has 256 x 8 bit RAM ad-

dressed 000H ~ 13FH except peripheral register

(0C0h~0FFh)

Control Registers

The control registers are used by the CPU and Peripheral

function blocks for controlling the desired operation of the

device. Therefore these registers contain control and status

bits for the interrupt system, the timer/ counters, analog to

digital converters and I/O ports. The basic control registers

byte, bit

byte

are in address range of 00C0 to 00FF . And OSD control

H

registers are assigned within 0AE0 ~ 0AFF .

Table 8-1Control registers

H

Note that unoccupied addresses may not be implemented

on the chip. Read accesses to these addresses will in gen-

eral return random data, and write accesses will have an in-

determinate effect.

More detailed informations of each register are explained

in each peripheral section.

24

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

1. "byte, bit" means that register can be addressed by not only bit

but byte manipulation instruction.

2. "byte" means that register can be addressed by only byte

manipulation instruction. On the other hand, do not use any

read-modify-write instruction such as bit manipulation for clear-

ing bit.

0D0H

0D1H

0D2H

0D3H

0D4H

0D5H

0D6H

TM0

TM2

R/W

R

byte

-0000000

????????

--010111

-0111111

00000000

11111111

0001000-

00000000

-0000001

????????

TDR0

TDR1

TDR2

TDR3

BITR

CKCTLR

WDTR

ICAR

ICDR

ICSR

ICCR1

ICCR2

SIOM

SIOR

byte, bit

byte

W

byte

0D7H

0D8H

0D9H

0DAH

0DBH

0DCH

0DEH

0DFH

R/W

byte, bit

0E0H

0E1H

0E2H

0E3H

0E4H

0E5H

0E8H

0E9H

0EAH

0EBH

0EEH

0EFH

PWMR0

PWMR1

PWMR2

PWMR3

PWMR4

PWMR5

PWM8H

PWM8L

PWMCR1 R/W

PWMCR2 R/W

BUR

AIPS

W

R/W

byte

????????

--??????

00000000

--0-0000

????????

--000000

byte

byte, bit

byte

W

byte

0F0H

0F1H

0F2H

0F3H

0F4H

0F5H

0F6H

0F7H

0F9H

0FAH

0FBH

0FCH

0FDH

ADCM

ADR

R/W

R

W

R/W

R

byte, bit

byte

byte, bit

byte

--011101

????????

--000000

0000000-

00000000

0000-000

1----001

????????

----0000

????????

IEDS

IMOD

IENL

IRQL

IENH

IRQH

IDCR

IDFS

IDR

R

R/W

W

byte

byte, bit

byte

DPGR

TMR

0AE0H OSDcon1 R/W

0AE1H OSDcon2 R/W

byte, bit

byte

00000000

-0000000

????????

01111010

10000111

---00000

????????

0AE2H OSDPOL

0AE3H FDWSET

0AE4H EDGEcol

W

R

W

0AE5H

0AE6H

OSDLN

LHPOS

0AE8H SPVPOS

0AE9H SPHPOS

0AF0H

0AF1H

0AF3H

0AF4H

L1ATTR

L1VPOS

L2ATTR

L2VPOS

Table 8-1Control registers

November 2001 ver 1.2

25

HMS81C43xx / GMS87C4060

8.4 Addressing Mode

The GMS800 series uses six addressing modes;

• Register addressing

(3) Direct Page Addressing → dp

In this mode, a address is specified within direct page.

Example; G=0

• Immediate addressing

• Direct page addressing

• Absolute addressing

E551: C535

LDA

35H;A ←RAM[35H]

• Indexed addressing

35_H

data

• Register-indirect addressing

À

~

data

A

→

~

þ

0E550_H

0E551_H

C5

35

(1) Register Addressing

Register addressing accesses the A, X, Y, C and PSW.

(2) Immediate Addressing → #imm

In this mode, second byte (operand) is accessed as a data

immediately.

(4) Absolute Addressing → !abs

Example:

Absolute addressing sets corresponding memory data to

Data , i.e. second byte(Operand I) of command becomes

lower level address and third byte (Operand II) becomes

upper level address.

FE10: 0435

ADC

#35H

MEMORY

With 3 bytes command, it is possible to access to whole

memory area.

0FE10_H

04

35

A+35H+C

A

→

ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,

LDY, OR, SBC, STA, STX, STY

Example;

F100: 0735F0 ADC!0F035H

;A ←ROM[0F035H]

When G-flag is 1, then RAM address is defined by 16-bit

address which is composed of 8-bit direct page accessable

register (DPGR) and 8-bit immediate data.

Example: G=1, DPGR=0CH

0F035_H

data

A

F100: E45535

LDM

35H,#55H

~

A+data+C

A

→

0F100_H

0F101_H

0F102_H

07

35

F0

P

address: 0F035

data

0C35_H

data

55H

←

~

þ

A

0F100_H

E4

55

35

0F101_H

0F102_H

26

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

The operation within data memory (RAM)

ASL, BIT, DEC, INC, LSR, ROL, ROR

X indexed direct page, auto increment→ {X}+

In this mode, a address is specified within direct page by

the X register and the content of X is increased by 1.

Example; Addressing accesses the address 0135 regard-

H

less of G-flag and DPGR.

LDA, STA

F100: 983501 INC!0135H

;A ←ROM[135H]

Example; G=0, X=35

H

F100: DB

LDA

{X}+

135_H

data

Ã

À

~

35_H

~

data

À

data+1

data

→

data

36H

A

X

→

0F100_H

0F101_H

0F102_H

98

35

01

~

þ

address: 0135

0F100_H

DB

(5) Indexed Addressing

X indexed direct page (8 bit offset) → dp+X

X indexed direct page (no offset) → {X}

This address value is the second byte (Operand) of com-

mand plus the data of -register. And it assigns the mem-

ory in Direct page.

In this mode, a address is specified by the X register.

ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA

Example; X=15 , G=1, DPGR=03

H

ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA

STY, XMA, ASL, DEC, INC, LSR, ROL, ROR

E550: D4

LDA

{X};ACC←RAM[X].

Example; G=0, X=0F5

H

E550: C645

LDA

45H+X

315_H

data

À

data

A

→

~

3A_H

data

þ

Ã

À

D4

0E550_H

data

A

→

~

0E550_H

0E551_H

C6

45

þ

45H+0F5H=13AH

November 2001 ver 1.2

27

HMS81C43xx / GMS87C4060

FA00: 3F35

JMP

[35H]

Y indexed direct page (8 bit offset) → dp+Y

This address value is the second byte (Operand) of com-

mand plus the data of Y-register, which assigns Memory in

Direct page.

35_H

36_H

0A

E3

This is same with above (2). Use Y register instead of X.

À ^{jump to address 0E30A}

H

Y indexed absolute → !abs+Y

~

Sets the value of 16-bit absolute address plus Y-register

data as Memory. This addressing mode can specify mem-

ory in whole area.

þ

0E30A_H

0FA00_H

~

Example; Y=55

H

3F

35

F100: D500FA

LDA

!0FA00H+Y

0F100_H

0F101_H

0F102_H

D5

þ

00

X indexed indirect → [dp+X]

FA

0FA00H+55H=0FA55H

Processes memory data as Data, assigned by 16-bit pair

memory w hich is deter mined by pair data

[dp+X+1][dp+X] Operand plus X-register data in Direct

page.

~

À

data

0FA55_H

data

A

→

Ã

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0, X=10

H

FA00: 1625

ADC

[25H+X]

(6) Indirect Addressing

Direct page indirect → [dp]

35_H

36_H

05

E0

Assigns data address to use for accomplishing command

which sets memory data(or pair memory) by Operand.

Also index can be used with Index register X,Y.

À ^0E005

~

H

~

25 + X(10) = 35_H

þ

0E005_H

0FA00_H

data

JMP, CALL

~

Example; G=0

16

25

A + data + C

A

→

Ã

28

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

Y indexed indirect → [dp]+Y

Absolute indirect → [!abs]

Processes momory data as Data, assigned by the data

[dp+1][dp] of 16-bit pair memory paired by Operand in Di-

rect page plus Y-register data.

The program jumps to address specified by 16-bit absolute

address.

JMP

ADC, AND, CMP, EOR, LDA, OR, SBC, STA

Example; G=0

Example; G=0, Y=10

H

FA00: 1F25E0

JMP

[!0C025H]

FA00: 1725

ADC

[25H]+Y

PROGRAM MEMORY

0E025_H

0E026_H

25

25_H

26_H

05

E0

E7

jump to

address 0E30A_H

À

0E005_H+ Y(10) = 0E015_H

À

~

0E725_H

0FA00_H

0E015_H

data

þ

~

1F

0FA00_H

17

25

A + data + C

A

→

Ã

E0

November 2001 ver 1.2

29

HMS81C43xx / GMS87C4060

9. I/O PORTS

The GMS87C4060 has digital ports (R0, R1, R2, R4, R5

and R6) and OSD ports (R,G,B), but HMS81C43xx has

R1, R2, R4, R5 and OSD ports (R,G,B)

function for the peripheral features on the device. In gen-

eral, in a initial reset state, R ports are used as a general

purpose digital port.

These ports pins may be multiplexed with an alternate

9.1 Registers for Port

Port Data Registers

ister) during initial setting as shown in Figure 9-1 .

The Port Data Registers in I/O buffer in each R ports are

represented as a Type D flip-flop, which will clock in a val-

ue from the internal bus in response to a "write to data reg-

ister" signal from the CPU. The Q output of the flip-flop is

placed on the internal bus in response to a "read data reg-

ister" signal from the CPU. The level of the port pin itself

is placed on the internal bus in response to "read data reg-

ister" signal from the CPU. Some instructions that read a

port activating the "read register" signal, and others acti-

vating the "read pin" signal

All the port direction registers in the HMS81C43xx/

GMS87C4060 have 0 written to them by reset function. On

the other hand, its initial status is input.

WRITE "55_H" TO PORT R0 DIRECTION REGISTER

0C0H

0C1H

BIT

R0 DATA

0

7

1

6

0

5

1

4

0

3

1

2

0

1

0

R0 DIRECTION

~

Port Direction Registers

~

0C8H

0C9H

R4 DATA

I

O

6

I

O

4

I

O

2

I

O

0

PORT

All pins have data direction registers which can define

these ports as output or input. A "1" in the port direction

register configure the corresponding port pin as output.

Conversely, write "0" to the corresponding bit to specify it

as input pin. For example, to use the even numbered bit of

R0 as output ports and the odd numbered bits as input

7

5

3

1

R4 DIRECTION

I : INPUT PORT

O : OUTPUT PORT

Figure 9-1 Example of port I/O assignment

ports, write "55 " to address 0C1 (R0 port direction reg-

H

30

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

9.2 I/O Ports Configuration

R0 Ports

The control registers for R1 are shown below.

R0 is an 8-bit CMOS bidirectional I/O port (address

ADDRESS : 00C2_H

RESET VALUE : Undefined

R1 Data Register

0C0 ). Each I/O pin can independently used as an input or

H

RW

R16

RW

an output through the R0DD register (address 0C1 ).

H

R17

R12

R11

R10

R15

R14

R13

R1

The control registers for R0 are shown below.

ADDRESS : 00C3_H

RESET VALUE : 0000 0000_b

R1 Direction Register

ADDRESS : 00C0_H

R0 Data Register

W

RESET VALUE : Undefined

RW

R07

RW

R06

RW

R1DD

R05

R04

R03

R02

R01

R00

R0

Port Direction

0: Input

1: Output

ADDRESS : 00C1_H

RESET VALUE : 0000 0000_b

R0 Direction Register

W

ADDRESS : 00F0_H

RESET VALUE : --01 1101_b

A/D Convertor mode Register

R0DD

RW

R

RW

Port Direction

0: Input

ADEN ADS2 ADS1 ADS0 ADST ADSF

ADCM

1: Output

A/D Enable

0: Disable

1: Enable

A/D Status

0: Busy

1: Finish

A/D Port select

000: AN0

001: AN1

010: AN2

011: AN3

100: AN4

In addition, Port R0 is only digital I/O. After reset, R0DD

value is "0", R0 acts as normal digital input port.

A/D Start

0: Ignore

1: A/D start

101: AN5

110: AN6

111: No Analog port

R1 Ports

ADDRESS : 00EF_H

Analog input pin selector Register

R1 is an 8-bit CMOS bidirectional I/O port (address

RESET VALUE : --00 0000_b

W

0C2 ). Each I/O pin can independently used as an input or

H

AIPS

an output through the R1DD register (address 0C3 ).

R1 port have secondary functions as following table.

H

Port Property

0: Digital I/O

1: Analog Input

Port Pin

Alternate Function

AN0 (A/D input 0)

AN1 (A/D input 1)

AN2 (A/D input 2)

AN3 (A/D input 3)

AN4 (A/D input 4)

AN5 (A/D input 5)

VD (Vertical Sync. input)

HD (Horizontal Sync. input)

ADDRESS : 00CF_H

RESET VALUE : ---0 0000_b

Port function select Register 2

R10

R11

R12

R13

R14

R15

R16

R17

W

VDS YMS YSS

IS

HDS

FUNC2

R16/VD select

0: R16 I/O

1: VD Input

R17/HD select

0: R17 I/O

1: HD Input

Port R1 is multiplexed with various special features.The

control registers controls the selection of alternate func-

tion. After reset, R1 port acts as normal digital input port.

The way to select alternate function such as A/D input or

HD,VD will be shown in each peripheral section.

November 2001 ver 1.2

31

HMS81C43xx / GMS87C4060

R2 Port

R4 Port

R2 is an 8-bit CMOS bidirectional I/O port (address

R4 is consrutced with 4-bit Open drain Output port and 4-

0C4 ). Each I/O pin can independently used as an input or

bit CMOS bidirectional I/O port (address 0C8 ). Each I/O

H

an output through the R2DD register (address 00C5 ).

pin can independently used as an input or an output

H

through the R4DD register (address 0C9 ).

H

The control registers for R2 are shown below.

The control registers for R4 are shown below.

ADDRESS : 00C4_H

R2 Data Register

ADDRESS : 00C8_H

R4 Data Register

RESET VALUE : Undefined

RW

R27

R22

R21

R20

R26

R25

R24

R23

R2

R47

R46

R45

R44

R43

R42

R41

R40

R4

ADDRESS : 00C5_H

RESET VALUE : 0000 0000_b

ADDRESS : 00C9_H

R2 Direction Register

R4 Direction Register

RESET VALUE : 0000 ----_b

W

R2DD

R4DD

Port Direction

0: Input

Port Direction

0: Input

1: Output

ADDRESS : 00DE_H

ADDRESS : 00DB_H

Serial I/O mode Register

I²C Control Register 1

RESET VALUE : -000 0001_b

RESET VALUE : 00-0 0000_b

RW

R

RW

IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF

BSW1 BSW0

ALS

ESO BC2

BC1

BC0

SIOM

Serial I/O

ICCR1

Seriial Status

0: Serial In

1: Serial Out

0: Busy

1: Finish

Bit count

000_b(8bit)

001_b~111_b(1~7bit)

Clock select

00: PS3

01: PS4

10: PS5

11: External

I²C enable

0: Disable

1: Enable

Serial Start

0: Ignore

1: Serial start

Slave address identification

0: Accept (Addressing format)

1: Decline (Free data format)

SM1 SM0 Mode

R21 R22 R23

Sclk Sout R23

Sclk R22 Sin

R21 R22 R23

0

1

0

1

-

0

1

R44 R45

R46

R47

BSW0

BSW1

Send

Receive

-

0

1

0

1

0

1

R44 R45/PWM4 R46

R47/PWM5

SCL0 R45/PWM4 SDA0 R47/PWM5

R44 SCL1

SCL SCL

R46

SDA1

SDA SDA

ADDRESS : 00CE_H

RESET VALUE : -000 0000_b

Port function select Register 1

W

ADDRESS : 00EA_H

PWM control Register 1

EC3S EC2S

INT3S INT2S INT1S INT0S

INT4S

RESET VALUE : 0000 0000_b

FUNC1

R27/EC3

RW

R20/INT2

0: R20

1: INT2

EN5

EN4

EN3

EN1

EN0

EN8 CNT

EN2

PWMCR1

0: R27

1: EC3

R24/INT3

0: R24

1: INT3

14/8bit PWM count

0: Count start

1: Count stop

R25/EC2

R26/INT4

0: R26

1: INT4

0: R25

1: EC2

EN5,4,3,2,1 : R47,45,43,42,41,40

0: R4x acts normal digital port

1: R4x acts PWM output port

ADDRESS : 00F2_H

RESET VALUE : --00 0000_b

R51/PWM8 select

0: R51

Ext. interrupt edge selection Register

1: PWM8

W

IED2H IED2L IED1H IED1L IED0H IED0L

IEDS

00: Ignore edge

INT2

01: Falling edge

10: Rising edge

11: Falling/Rising edge

32

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

R5 Port

R6 Port

R6 is an 1-bit CMOS bidirectional I/O port (address

0CC ). Each I/O pin can independently used as an input or

R5 is an 7-bit port (address 0CA ). Each I/O pin can inde-

pendently used as an input or an output through the R5DD

H

register (address 0CB ).

an output through the R6DD register (address 0CD ).

H

The control registers for R5 are shown below

The control registers for R6 are shown below

ADDRESS : 00CA_H

R5 Data Register

ADDRESS : 00CC_H

R6 Data Register

RESET VALUE : Undefined

RW

R52

R51

R56

R55

R54

R53

R50

R67

R5

R6

ADDRESS : 00CB_H

RESET VALUE : ---- 0000_b

ADDRESS : 00CD_H

R6 Direction Register

R5 Direction Register

R5DD

RESET VALUE : 0--- ----_b

W

R6DD

Port Direction

0: Input

1: Output

Port Direction

0: Input

1: Output

ADDRESS : 00CE_H

Port function select Register 1

RESET VALUE : -000 0000_b

W

EC3S EC2S INT4S INT3S INT2S INT1S INT0S

FUNC1

EC3S EC2S INT4S INT3S INT2S INT1S INT0S

FUNC1

R52/INT0

0: R52

1: INT0

R67/INT1

0: R67

1: INT1

ADDRESS : 00CF_H

Port function select Register 2

ADDRESS : 00F2_H

RESET VALUE : --00 0000_b

RESET VALUE : ---0 0000_b

Ext. interrupt edge selection Register

W

VDS YMS YSS

IS

HDS

FUNC2

IED2H IED2L IED1H IED1L IED0H IED0L

IEDS

R54/YM

0: R56

R55/YS

0: R55

R56/I

0: R56

INT1

00: Ignore edge

01: Falling edge

10: Rising edge

1: YM Output 1: YS Output 1: I Output

11: Falling/Rising edge

ADDRESS : 00EB_H

RESET VALUE : --0- 0000_b

PWM control Register 2

RW

BUZS

RW

POL2 POL1 EN7 EN6

PWMCR2

R50/BUZZ

0: R50

1: BUZZ

ADDRESS : 00F2_H

RESET VALUE : --00 0000_b

Ext. interrupt edge selection Register

W

IED2H IED2L IED1H IED1L IED0H IED0L

IEDS

00: Ignore edge

01: Falling edge

INT2

10: Rising edge

11: Falling/Rising edge

November 2001 ver 1.2

33

HMS81C43xx / GMS87C4060

10. CLOCK GENERATOR

As shown in Figure 10-1 , the clock generator produces the

basic clock pulses which provide the system clock to be

supplied to the CPU and the peripheral hardware. It con-

tains two oscillators: a main-frequency clock oscillator and

a sub-frequency clock oscillator. The system clock can

also be obtained from the external oscillator.

Minimum instruction cycle time

Main clock

(ex:NOP ; f 4clock is needed)

ex

3.6MHz

4MHz

1,111nS

1,000nS

500nS

8MHz

The clock generator produces the system clocks forming

clock pulse, which are supplied to the CPU and the periph-

eral hardware.

To the peripheral block, the clock among the not-divided

original clocks, divided by 2, 4,..., up to 1024 can be pro-

vided. Peripheral clock is enabled or disabled by bit 4 of

the peripheral clock enable register (ENPCK).

Internal system clock

Clock pulse Generator

f_EX

OSC

Circuit

PRESCALER

ENPCK

[0D6_H]

WDT

ENPCK BTCL BTS2 BTS1 BTS0

CKCTLR

ON

Clock control register

Peripheral clock

Figure 10-1 Block Diagram of Clock Generator

Note: On the initial reset, all peripherals are run because

peripheral clock is supplied to each function block. If you

want to see more details, see Clock Control Register

(CKCTLR).

ADDRESS : 00D6_H

Clock control register

RESET VALUE : --01 0111_b

W

WDT

ON

ENPCK BTCL BTS2 BTS1 BTS0

CKCTLR

Watch-dog

timer select

B.I.T Clock

ADDRESS : 00FD_H

Test mode register

B.I.T set

0: Normal 6bit timer

1: Watch-dog timer

RESET VALUE : 0000 0000_b

0: Free run

1: B.I.T clear

Peri. Clock

0: Stop

W

1: Supply

TMR

0000 0110b Normal operation mode

34

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

11. TIMER

11.1 Basic Interval Timer

The HMS81C43xx/GMS87C4060 has one 8-bit Basic In-

terval Timer that is free-run and can not be stopped. Block

diagram is shown in Figure 11-1 .

generated. The Basic Interval Timer is controlled by the

clock control register (CKCTLR) shown in Figure 11-2 .

Source clock can be selected by lower 3 bits of CKCTLR.

The Basic Interval Timer generates the time base for

watchdog timer counting, and etc. It also provides a Basic

interval timer interrupt (BITIF). As the count overflow

BITR and CKCTLR are located at same address, and ad-

dress 00D6 is read as a BITR and written to CKCTLR..

H

from FF to 00 , this overflow causes the interrupt to be

H

f_ex2⁴

÷

PS4

PS5

PS6

PS7

PS8

PS9

f_ex2⁵

÷

8-bit up-counter

BITR

f_ex2⁶

÷

source

clock

overflow

f_ex2⁷

÷

BITIF

MUX

f_ex2⁸

Basic Interval Timer Interrupt

÷

f_ex2⁹

÷

[0D6_H]

f_ex2¹⁰

Watchdog timer clock (WDTCK)

÷

PS10

PS11

clear

BTCL

f_ex2¹¹

÷

3

BITCK

Select Input clock

Clock control register

[0D6_H]

WDT

ENPCK BTCL BTS2 BTS1 BTS0

CKCTLR

ON

Internal bus line

Figure 11-1 Block Diagram of Basic Interval Timer

Interrupt

(overflow) Period

Source clock

BTS2~0

At f =8MHz

Pre-Scaler output

ex

4

f

ex

f

ex

f

ex

f

ex

f

ex

f

ex

f

ex

f

ex

2

÷

2

÷

2

÷

2

÷

2

÷

2

÷

2

÷

2

÷

000

001

010

011

100

101

110

111

PS4

PS5

PS6

PS7

PS8

PS9

PS10

PS11

0.512 mS

1.024

5

6

2.048

7

4.096

8

8.192

9

16.384

32.768

65.536

10

11

Table 11-1 Basic Interval Timer Interrupt Time

November 2001 ver 1.2

35

HMS81C43xx / GMS87C4060

W

ADDRESS : 00D6_H

WDT

ON

ENPCK BTCL BTS2 BTS1 BTS0

CKCTLR

RESET VALUE : --01 0111_b

Watch-dog

timer select

0: Normal 6bit timer

1: Watch-dog timer

B.I.T Clock

B.I.T set

0: Free run

Peri. Clock

0: Stop

1: Supply

1: Clear 8-bit counter (BITR) to "0". This bit becomes 0

automatically after 1 machine cycle

:

Caution

Both register are in same address,

when write, to be a CKCTLR,

when read, to be a BITR.

R

ADDRESS: 00D6_H

INITIAL VALUE: Undefined

BITR

8-BIT BINARY COUNTER

Figure 11-2 BITR: Basic Interval Timer Mode Register

11.2 Timer 0, 1

Timer 0, 1 consists of prescaler, multiplexer, 8-bit compare

data register, 8-bit count register, Control register, and

Comparator as shown in Figure 11-3 .

The control registers for Timer 0,1 are shown below.

ADDRESS : 00D0_H

Timer mode register 0

RESET VALUE : -000 0000_b

RW

These Timers can run separated 8bit timer or combined

16bit timer. These timers are operated by internal clock.

T1ST T1SL1 T1SL0 T0ST T0CN T0SL1 T0SL0

TM0

Timer 0 input clock

Timer 1 start

0: Count Hold

1: Count Clear and Start

00: PS2 (f_ex/ 2²)

01: PS4 (f_ex/ 2⁴)

10: PS6 (f_ex/ 2⁶)

11: PS8 (f_ex/ 2⁸)

The contents of TDR1 are compared with the contents of

up-counter T1. If a match is found, a timer/counter 1 inter-

rupt (T1IF) is generated, and the counter is cleared. Count-

ing up is resumed after the counter is cleared.

Timer 1 input clock

00: Timer 0 overflow (16bit mode)

Timer 0 control

0: Count Hold

1: Count Continue

01: PS2 (f_ex/ 2²)

10: PS4 (f_ex/ 2⁴)

11: PS6 (f_ex/ 2⁶)

Timer 0 start

0: Count Hold

1: Count Clear and Start

Note: You can read Timer 0, Timer 1 value from TDR0 or

TDR1. But if you write data to TDR0 or TDR1, it changes

Timer 0 or Timer 1 modulo data, not Timer value.

ADDRESS : 00D2_H

RESET VALUE : Undefined

Timer 0 data register

RW

The content of TDR0, TDR1 must be initialized (by soft-

TDR0

ware) with the value between 01 and FF ,not to 00 .

H

Or not, Timer 0 or Timer 1 can not count up forever.

ADDRESS : 00D3_H

Timer 1 data register

RESET VALUE : Undefined

RW

TDR1

36

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

.

Internal bus line

TM0

TDR0

TDR1

T0CN

8bit Comparator

T0IF

8bit Comparator

T1IF

Timer 0

Clock

Timer 1

PS2

PS4

PS6

PS8

MUX

Clear

Clock

Clear

T0ST

NC

PS2

PS4

PS6

T1ST

Figure 11-3 Simplified Block Diagram of 8bit Timer0, 1

TDR0

enable

disable

clear & start

stop

TIME

Timer 0 (T0IF)

Interrupt

Occur interrupt

T0ST

T0ST = 1

T0ST = 0

Start & Stop

T0CN

T0CN = 1

Control count

T0CN = 0

Figure 11-4 Count Example of Timer

November 2001 ver 1.2

37

HMS81C43xx / GMS87C4060

Internal bus line

TM0

TDR0

TDR1

0

T0CN

16bit Comparator

T1IF

Timer 0

Clock

Timer 1

Clock

PS2

PS4

PS6

PS8

MUX

Clear

T0ST

Figure 11-5 Simplified Block Diagram of 16bit Timer0, 1

11.3 Timer / Event Counter 2, 3

Timer 2, 3 consists of prescaler, multiplexer, 8-bit compare

data register, 8-bit count register, Control register, and

Comparator as shown in Figure 11-5 .

The control registers for Timer 2,3 are shown below

ADDRESS : 00D1_H

RESET VALUE : -000 0000_b

Timer mode register 2

RW

These Timers have two operating modes. One is the timer

mode which is operated by internal clock, other is event

counter mode which is operated by external clock from pin

R25/EC2, R27/EC3.

T3ST T3SL1

T2ST T2CN T2SL1 T2SL0

T3SL0

TM2

Timer 2 input clock

Timer 3 start

0: Count Hold

00: PS2 (f_ex/ 2²)

01: PS4 (f_ex/ 2⁴)

10: PS6 (f_ex/ 2⁶)

11: PS8 (f_ex/ 2⁸)

1: Count Clear and Start

Timer 3 input clock

00: Timer 2 overflow (16bit mode)

01: PS2 (f_ex/ 2²)

These Timers can run separated 8bit timer or combined

16bit timer.

Timer 2 control

0: Count Hold

1: Count Continue

10: PS4 (f_ex/ 2⁴)

11: PS6 (f_ex/ 2⁶)

Timer 2 start

0: Count Hold

1: Count Clear and Start

Note: You can read Timer 2, Timer 3 value from TDR2 or

TDR3. But if you write data to TDR2 or TDR3, it changes

Timer 2 or Timer 3 modulo data, not Timer value.

ADDRESS : 00D4_H

RESET VALUE : Undefined

Timer 2 data register

RW

W

RW

The content of TDR2, TDR3 must be initialized (by soft-

TDR2

ware) with the value between 01 and FF ,not to 00 .

H

Or not, Timer 2 or Timer 3 can not count up forever.

ADDRESS : 00D5_H

Timer 3 data register

RESET VALUE : Undefined

RW

TDR3

ADDRESS : 00CE_H

RESET VALUE : -000 0000_b

Port function select Register 1

W

EC3S EC2S INT4S INT3S INT2S INT1S INT0S

FUNC1

R25/EC2

0: R25

1: EC2

R27/EC3

0: R27

1: EC3

38

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

.

Internal bus line

TM2

TDR2

TDR3

T2CN

8bit Comparator

T2IF

8bit Comparator

T3IF

Timer 2

Clock

Timer 3

EC2

PS2

PS4

PS6

MUX

Clear

Clock

Clear

T2ST

NC

EC3

PS2

PS4

T3ST

Figure 11-6 Simplified Block Diagram of 8bit Timer/Event Counter 2,3

TDR2

enable

disable

clear & start

stop

TIME

Timer 2 (T2IF)

Interrupt

Occur interrupt

T2ST

Start & Stop

T2ST = 1

T2ST = 0

T2CN

T2CN = 1

Control count

T2CN = 0

Figure 11-7 Count Example of Timer / Event counter

November 2001 ver 1.2

39

HMS81C43xx / GMS87C4060

Internal bus line

TM2

TDR2

TDR3

0

T0CN

16bit Comparator

T3IF

Timer 2

Clock

Timer 3

Clock

EC2

PS4

PS6

PS8

MUX

Clear

T0ST

Figure 11-8 Simplified Block Diagram of 16bit Timer/Event Counter 2,3

n interrupt (TnIF) is generated and the up-counter is

Timer Mode

cleared to 0. Counting up is resumed after the up-counter

is cleared.

In the timer mode, the internal clock is used for counting

up. Thus, you can think of it as counting internal clock in-

put. The contents of TDRn (n=0~3) are compared with the

contents of up-counter, Timer n. If match is found, a timer

As the value of TDRn is changeable by software, time in-

terval is set as you want

Start count

Source clock

N-2

N-1

N

1

4

0

3

0

1

2

3

2

Up-counter

TDRn (n=0~3)

N

Match

Detect

Counter

Clear

TnIF (n=0~3) interrupt

Figure 11-9 Timer Mode Timing Chart

Event counter Mode

put.

In event timer mode, counting up is started by an external

trigger. This trigger means falling edge of the ECn (n=2~3)

pin input. Source clock is used as an internal clock selected

with TM2. The contents of TDRn are compared with the

contents of the up-counter. If a match is found, an TnIF in-

The maximum frequency applied to the ECn pin is f /2

[Hz] in main clock mode.

ex

In order to use event counter function, the bit EC2S, EC3

of the Port Function Select Register1 FUNC1(address

0CE ) is required to be set to "1".

H

terrupt is generated, and the counter is cleared to 00 . The

H

counter is restarted by the falling edge of the ECn pin in-

After reset, the value of TDRn is undefined, it should be

40

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

initialized to between 01 ~FF not to 00

H

Start count

ECn (n=2~3) pin

1

2

Up-counter

0

2

N-1

N

0

TDRn (n=2~3)

N

TnIF (n=2~3) interrupt

Figure 11-10 Event Counter Mode Timing Chart

The interval period of Timer is calculated as below equa-

tion.

-------

=

×

TDR2

TDR2=n

n

n-1

n-2

P_CP

8

7

6

5

4

3

2

1

0

TIME

Interrupt period

= P_CPx n

Timer 2 (T2IF)

Interrupt

Occur interrupt

Figure 11-11 Count Example of Timer / Event counter

November 2001 ver 1.2

41

HMS81C43xx / GMS87C4060

TDR2

enable

disable

clear & start

stop

TIME

Timer 2 (T2IF)

Interrupt

Occur interrupt

T2ST

Start & Stop

T2ST = 1

T2ST = 0

T2CN

T2CN = 1

Control count

T2CN = 0

Figure 11-12 Count Operation of Timer / Event counter

42

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

12. A/D Converter

The A/D convertor circuit is shown in Figure 12-1 .

alog input. The ADCM register control A/D converter’s

activity. The ADR register stores A/D converted 8bit re-

sult. The more details are shown Figure 12-2 .

The A/D convertor circuit consists of the comparator and

control register AIPS(00EF ), ADCM(00F0 ),

H

ADR(00F1 ). The AIPS register select normal port or an-

H

ADEN ADS2 ADS1 ADS0 ADST ADSF

ADCM [F0_H]

ADR [F1_H]

IFA

Control circuit

port

select

AN0

Comparator

AN1

S/H

Succesive

Approximation

Circuit

AN2

MUX

AN3

+

−

Vref

AN4

AN5

Register ladder

Figure 12-1 Block Diagram of A/D convertor circuit

;

1 : analog port

AIPS,#00??????b

Control

LDM

; Set ADEN, xxx is analog port number

The HMS81C43xx/GMS87C4060 contains a A/D con-

verter module which has six analog inputs.

LDM

ADCM,#001xxx00b

; or “SET1 ADEN”

; Set ADST, xxx is analog port number

1. First of all, you have to select analog input pin by set the

ADCM and AIPS.

LDM

ADCM,#001xxx10b

; or “SET1 ADST”

:

2. Set ADEN (A/D enable bit : ADCM bit5).

3. Set ADST (A/D start bit : ADCM bit1). We recommend

you do not set ADEN and ADST at once, it makes worse

A/D converted result.

5. After A/D conversion is completed, ADSF bit and inter-

rupt flag IFA will be set. (A/D conversion takes 36 ma-

chine cycle : 9uS when f =8MHz).

ex

4. ADST bit will be cleared automatically 1cycle after you

set this.

Note:

Make sure AIPS bits, if you using a port which is set

digital input by AIPS, analog voltage will be flow into MCU

internal logic not A/D converter. Sometimes device or port

is damaged permanently.

Example:

:

; Set AIPS, change ? to what you want

;

0 : digital port

November 2001 ver 1.2

43

HMS81C43xx / GMS87C4060

ADDRESS : 00F0_H

RESET VALUE : --01 1101_b

A/D Convertor mode Register

RW

R

ADEN ADS2 ADS1 ADS0 ADST ADSF

ADCM

A/D Enable

0: Disable

1: Enable

A/D Status

0: Busy

1: Finish

A/D Port select

000: AN0

001: AN1

010: AN2

011: AN3

100: AN4

A/D Start

0: Ignore

1: A/D start

101: AN5

11x: No Analog port

ADDRESS : 00F1_H

RESET VALUE : Undefined

A/D Result Register

R

ADR

8bit result is stored

ADDRESS : 00EF_H

RESET VALUE : --00 0000_b

Analog input pin selector Register

W

AIPS

Port Property

0: Digital I/O

1: Analog Input

Figure 12-2 A/D convertor Registers

44

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

13. Serial I/O

The Serial I/O circuit is shown in Figure 13-1 .

data or data which will be transfered. The SIOM register

controls serial communication mode, speed, start, etc.

The Serial I/O circuit consists of the octal counter, SI-

OR(DF ), SIOM(DE ). The SIOR register stores received

The more details about registers are shown Figure 13-2 .

H

IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF

D7

D6

D5

D4

D3

D2

D1

D0

SIOM [DE_H]

SIOR [DF_H]

PS3

PS4

IFSIO

Control

Circuit

Octal counter

MUX

PS5

Exclk

Sclk

Sout

1

MUX

Sin

0

Figure 13-1 Block Diagram of Serial I/O circuit

2. You have to select serial communication clock by set the

SCK1~0.

Control

The HMS81C43xx/GMS87C4060 contains a Synchronous

type Serial I/O module.

Ex: Frequency

SCK1 SCK0

Selected Clock

1. You have to select serial I/O pins by set the SM1~0.

(f =8MHz)

ex

0

1

0

1

0

1

PS3

PS4

1uS

2uS

Port select

SM1 SM0

Function

R21

Sclk

R21

R22

Sout

R22

R23

Sin

PS5

4uS

0

1

0

1

0

1

-

Send

Receive

-

External clock

User define

3. If you want to send data, write it to SIOR. Or not skip

this.

R23

4. Start serial communication by set SIOST(Serial I/O

start, SIOM bit1).

Note:

Sout pin can handle serial data output or serial data

. After serial communication is completed, SIOSF bit and

5

input. You can input serial data to Sout pin when IOSW bit

is 1. But Sin pin is dedicated serial data input pin.

interrupt flag IFSIO will be set.

November 2001 ver 1.2

45

HMS81C43xx / GMS87C4060

ADDRESS : 0DE_H

RESET VALUE : -000 0001_b

Serial I/O mode Register

RW

R

Serial I/O Interrupt

Service routine

IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF

SIOM

Serial Status

0: Busy

Clock Select

Input select

0: Sin

1: Sout

1: Finish

No

SIOSF=1?

Yes

Serial COMM. Start

0: Ignore

1: COMM. start

Send / Receive

Abnormal operation

SE=0

ADDRESS : 0DF_H

RESET VALUE : Undefined

Serial I/O data Register

// SE : Interrupt enable bit

RW

D7

RW

D6

RW

D5

RW

D4

RW

D3

RW

SIOR

D2

D1

D0

Write SIOM

// SR : Interrupt request flag

No

SR=0?

Yes

Figure 13-2 Serial I/O Registers

Overrun error

Normal operation

Figure 13-3 Example for serial I/O check by S/W

Input clock

Sclk

SIOST

D0

D1

D2

D3

D4

D5

D6

D7

Sout

Sin

IFSIO

Figure 13-4 Serial I/O Timing Chart

46

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

14. Pulse Width Modulation (PWM)

The PWM circuit is shown in Figure 14-1 , Figure .

The PWM circuit consists of the counter, comparator, Data

register.

Example

(f =8MHz)

ex

The PWM control registers are PWMR7~0, PWMCR2~1,

PWM8H, PWM8L.

14bit PWM

8bit PWM

Resolution

Input Clock

Frame cycle

0.5uS

2MHz

4uS

The more details about registers are shown Figure 14-2 .

250KHz

1,024uS

8,192uS

PWMCR2 [EB_H]

PWMCR1 [EA_H]

CNTB

PWM5

PWM4

PWMR5 [E5_H]

PWMR4 [E4_H]

PWMR3 [E3_H]

PWM3

PWM2

PWMR2 [E2_H]

PWMR1 [E1_H]

PWM1

PWMR0 [E0_H]

8bit comparator

PWM0

PS5

IF1Frame

8bit counter

Figure 14-1 8bit register (PWM7~0) circuit

PWMCR2 [EB_H]

CNTB

PWMCR1 [EA_H]

PWMR8H 8bit [E8_H]

PWMR8L 6bit [E9_H]

PWM8

14bit comparator

MSB

LSB

PS2

14bit counter

Figure 14-2 14bit register (PWM8) circuit

November 2001 ver 1.2

47

HMS81C43xx / GMS87C4060

8bit PWM Control

5. CNTB controls all PWM counter enable.

If CNTB=0, Counter is enabled.

The HMS81C43xx/GMS87C4060 contains a one 14bit

PWM and six 8bit PWM module.

14bit PWM Control

1. 8bit PWM0~5 is wholy same internal circuit, but

PWM0~5 output port is NMOS open drain.

1. 14bit PWM’s operation concept is not the same as 8bit

PWM.

2. Al l PWM polarity has the same by POL2’s value.

1 PWM frame contains 64 sub PWMs.

PWM8H : Set sub PWM’s basic Pulse Width.

PWM8L : Number of sub PWM which is added 1 clock.

3. Calulate Frame cycle and Pulse width is as following.

13

PWM Frame Cycle = 2 / f (Sec)

ex

5

PWM Width = (PWMRn+1) * 2 / f (n=0~5)

2. PWM polarity is selected by POL1’s value.

If POL1=0, Positive Polarity.

ex

Pulse Duty (%) = (PWMRn +1) / 256 *100(%) (n=0~5)

3. Calulate Frame cycle and Pulse width is as following.

16

Main PWM Frame Cycle = 2 / f (Sec).

ex

Positive Polarity (POL2=0)

Negative Polarity (POL2=1)

Sub PWM Frame Cycle = Main Frame Cycle / 64.

4. Table 14-1, “PWM8L and Sub frame matching table,”

on page 48 show PWM8L function.

1

2

1

2

Sub frame number which is

added 1 clock

Pulse

count

Bit value

1. Frame cycle

2. Pulse Width

if Bit0=1 32

1

2

4

8

if Bit1=1 16, 48

Figure 14-3 Wave form example for 8bit PWM

if Bit2=1 8, 24, 40, 56

if Bit3=1 4, 12, 20, 28, 36, 44, 52, 60

4. PWM output is enabled during ENn(n=0~5) bit (See

PWMCR1~2) contains 1.

2, 6, 10, 14, 18, 22, 26, 30, 34,

if Bit4=1

16

38, 42, 46, 50, 54

1, 3, 5, 7, 9, 11, 13, 15, 17, 19,

21, 23, 25, 27, 29, 31, 33, 35, 37,

39, 41, 43, 45, 47, 49, 51, 53, 55,

57, 59, 61, 63

ADDRESS : 0E0~E5_H

PWM Data Register

RESET VALUE : Undefined

if Bit5=1

32

W

D7

D6

D5

D4

D3

D2

D1

D0

PWMR0~5

ADDRESS : 0EA_H

Table 14-1 PWM8L and Sub frame matching table

PWM control Register 1

RESET VALUE : 0000 0000_b

RW

EN5

EN4 EN3 EN2

EN1

EN0 EN8 CNTB

PWMCR1

EN5,4,3,2,1 : R47,45,43,42,41,40

0: R4x acts normal digital port

1: R4x acts PWM output port

Main PWM Frame

14bit Counter enable

0: Counter run

1: Counter stop

0

1

2

61 62 63

.....

ADDRESS : 0EB_H

RESET VALUE : --0- 00--_b

PWM control Register 2

RW

Sub PWM Frame

BUZS

POL2 POL1

PWMCR2

Sub PWM Frame

which is added

1 clock

8bit PWM Polarity

0: Positive (PWM from Rising edge)

1: Negative (PWM from Rising edge)

1 clock width : PS2

Figure 14-4 8bit PWM Registers

Figure 14-5 Wave form example for 14bit PWM

48

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

5. PWM output is enabled during EN8 bit contains 1.

ADDRESS : 0E8_H

RESET VALUE : Undefined

6. CNTB controls PWM counter enable.

If CNTB=0, Counter is enabled.

PWM Width Data Register

RW

D7

RW

D6

RW

D5

RW

D4

RW

D3

RW

PWM8H

D2

D1

D0

ADDRESS : 0E9_H

PWM Sub-pulse count Register

RESET VALUE : Undefined

RW

D5

RW

D4

RW

D3

RW

D2

D1

D0

PWM8L

ADDRESS : 0EA_H

PWM control Register 1

RESET VALUE : 0000 0000_b

RW

EN5

EN4

EN3

EN1

EN0

EN8 CNTB

EN2

PWMCR1

14bit PWM enable

0: R51

1: PWM8

14bit Counter enable

0: Counter run

1: Counter stop

ADDRESS : 0EB_H

RESET VALUE : --0- 00--_b

RW

PWM control Register 2

RW

POL2 POL1

BUZS

PWMCR2

14bit PWM Polarity

0: Positive (PWM from Rising edge)

1: Negative (PWM from Rising edge)

Figure 14-6 14bit PWM Registers

November 2001 ver 1.2

49

HMS81C43xx / GMS87C4060

15. Interrupt interval measurement circuit

The Interrupt interval measurement circuit is shown in Fig-

ure 15-1 .

tor, 8bit counter, measured result storing register, FIFO

(9bit, 6level) interrupt, Control register, etc.

The Interrupt interval measurement circuit consists of the

input multiplexer, sampling clock multiplexer, Edge detec-

The more details about registers are shown Figure 15-2 .

FCLR IMS

I34H I34L

ISEL IDCK IDST

DPOL

FOE FFUL FEMP

IDCR [F9_H]

PS8

IDFS [FA_H]

1

MUX

0

8bit counter

PS9

Clear

Overflow

8

4

INTV

INT3

1

MUX

Edge detector

0

FCLR

INT4

MUX

0

FIFO

(9bit, 6level)

1

D7

D6

D5

D4

D3

D2

D1

D0

IDR [FB_H]

Figure 15-1 Block Diagram of Interrupt interval measurement circuit

edge is detected. After data was written, timer is cleard au-

tomatically and it counts continue.

Control

The HMS81C43xx/GMS87C4060 contains a Interrupt in-

terval measurement module.

. You can select interrupt occuring point by set Interrupt

5

Mode Select bit (IMS), every edge what you selected or

FIFO 4 level is filled.

1. Select interrupt input pin what you want to measure by

set the FUNC1 [00CE ].

H

6. If input signal’s interval is larger than maximum counter

2. Set IDCR [00F9 ] : FIFO clear, interrupt mode, inter-

rupt edge select, external interrupt select between INT3

and INT4, sampling clock select.

H

value (0FF ), counter occurring an interrupt and count

H

again from 00 .

H

7. See Figure 15-4 FIFO operating mechanism.

3. Set IDCR [00F9 ] : set IDST to start measuring.

H

4. Counter value is stored to IDR [00FB ] when selected

H

50

N ovem ber 2001 ver 1.2

HMS81C43xx / GMS87C4060

Interrupt interval determination

control Register

ADDRESS : 00F9_H

RESET VALUE : 0000 -000_b

RW

FCLR IMS

I34H I34L

ISEL IDCK IDST

IDCR

Interrupt input

Counter control

0: stop

See Figure 15-3

1: Clear & count

Int. occuring time

0: Every selected

edge by I34H/L

1: Every FIFO 4level

is filled

Sampling clock select

0: PS9

1: PS8

is filled

FIFO clear

0: Ignored

External Interrupt select

0: INT3

Detecting

edge

1: Clear and return to 0

1: INT4

Item

Symbol I34H

I34L

Interrupt interval determination

ADDRESS : 00FA_H

FIFO status Register

RESET VALUE : 1--- -001_b

Rising

edge

1

0

1

R

DPOL

FOE FFUL FEMP

Frame Cycle

IDFS

Falling

edge

FIFO Empty flag

0: Data filled

1: Empty

Data polarity

0: Data is stored every Falling edge

1: Data is stored every Rising edge

1

Both edge

FIFO Full flag

0: Not full

1: Full

FIFO overrun error flag

0: No Error

1: Error detected

Pulse width

Interrupt interval determination

FIFO Data Register

ADDRESS : 00FB_H

Figure 15-3 Setting for measurement

RESET VALUE : Undefined

R

IDR

D7

D6

D5

D4

D3

D2

D1

D0

ADDRESS : 00CE_H

RESET VALUE : -000 0000_b

Port function select Register 1

W

EC3S EC2S INT4S INT3S INT2S INT1S INT0S

FUNC1

R26/INT4

0: R26

R24/INT3

0: R24

1: INT4

1: INT3

Figure 15-2 Int. interval measurement Registers

1) FIFO storing mechanism

FEMP=1, FFUL=0

FEMP=0, FFUL=0

Data 1

FEMP=0, FFUL=1

Data 1

FEMP=0, FFUL=1

Data 1

Data 2

Data 3

Data 2

Data 3

Data 4

Data 5

Data 4

Data 5

Data 6

Data 7

Data in

Data 6 will be erased.

FOE=1 (Over run error)

2) FIFO reading mechanism

Read out

FEMP=0

Data 2

FEMP=1

FEMP=0

Data 1

Data 2

Figure 15-4 Example for FIFO operating mechanism

November 2001 ver 1.2

51

HMS81C43xx / GMS87C4060

16. Buzzer driver

The Buzzer driver circuit is shown in Figure 16-1 .

register controls source clock and output frequency.

The more details about registers are shown Figure 16-2 .

The Buzzer driver circuit consists of the 6bit counter, 6bit

comparator, Buzzer data register BUR(00EE ). The BUR

H

BUR write

BUCK BUCK

BU5 BU4

BU3

BU2

BU1 BU0

BUR [EE_H]

-1

-0

6

BUZZ

6bit Comparator

Output

Generator

clear

PS4

6

00

PS5

PS6

PS7

6bit counter

01

10

11

clear

MUX

BUZS

POL2 POL1 EN7

EN6

PWMCR2 [EB_H]

Figure 16-1 Block Diagram of Buzzer driver circuit

Control

3. Set BUZS bit for output enable.

The HMS81C43xx/GMS87C4060 contains a Buzzer driv-

er module.

4. Output waveform is rectagle clock which has 50% duty.

5. You can use this clock for the other purposes.

1. Select an input clock among PS4~7 by set the

BUCK1~0 of BUR.

ADDRESS : 0EE_H

RESET VALUE : ???? ????_b

Buzzer data Register

BUCK1

BUCK0

Clock source

PS4

W

BUCK BUCK

-1 -0

BU5 BU4 BU3

BU2

BU1 BU0

BUR

0

1

0

1

0

1

Input select

Clock Select

PS5

PS6

ADDRESS : 0EB_H

RESET VALUE : --0- 00--_b

RW

PWM control Register 2

RW

BUZS

RW

PS7

POL2 POL1

PWMCR2

R50/Buzz select

0: R50

1: Buzz output

2. Select output frequency by change the BU5~0.

Output frequency = 1 / (PSx * BUy *2) Hz.

x=4~7, y=5~0

See example Table 16-1 and Table 16-2.

Figure 16-2 Buzzer driver Registers

Note: Do not select 00 to BU5~0. It means counter stop.

H

N ovem ber 2001 ver 1.2

52

HMS81C43xx / GMS87C4060

BUR5~0

Output frequency (KHz)

PS5 PS6

62.5

BUR5~0

Output frequency (KHz)

Dec Hex

PS4

PS7

31.25

Dec Hex

PS4

PS5

PS6

PS7

1

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

250

125

62.5

1

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

375

187.5

125

93.75

75

62.5

187.5

93.75

46.875

23.438

15.625

11.719

9.375

7.813

6.696

5.895

5.208

4.688

4.261

3.906

3.606

3.348

3.125

2.930

2.757

2.604

2.467

2.344

2.232

2.131

2.038

1.953

1.875

1.803

1.736

1.674

1.616

1.563

1.512

1.465

1.420

1.379

1.339

1.302

1.267

1.234

1.202

1.172

1.143

1.116

1.09

2

31.25

20.833

15.625

12.5

10.461

8.928

7.813

6.944

6.25

15.625

10.436

7.813

6.25

2

93.75

62.5

46.875

31.35

23.436

18.75

15.625

13.393

11.719

10.417

9.375

8.523

7.813

7.211

6.696

6.25

3

83.333

62.5

42.666

31.25

25

20.888

17.858

15.625

13.888

12.5

11.364

10.417

9.615

8.929

8.333

7.813

7.353

6.944

6.579

6.25

3

4

46.875

37.5

5

50

5

6

41.666

35.714

31.25

27.728

25

5.208

4.464

3.907

3.472

3.125

2.841

2.604

2.404

2.242

2.083

1.953

1.838

1.736

1.644

1.562

1.438

1.420

1.359

1.302

1.25

1.202

1.158

1.116

1.078

1.042

1.008

0.976

0.947

0.919

0.893

0.868

0.845

0.822

0.801

0.781

0.762

0.744

0.727

0.710

0.694

0.679

0.665

0.651

0.638

0.625

0.613

0.601

0.590

0.579

0.568

0.558

0.548

0.539

0.530

0.521

0.512

0.504

0.496

6

31.25

26.786

23.436

20.833

18.75

17.045

15.625

14.423

13.393

12.5

7

53.572

46.875

41.666

37.5

34.09

31.25

28.846

26.786

25

23.436

22.058

20.833

19.736

18.75

17.858

17.045

16.304

15.625

15

14.424

13.888

13.393

12.932

12.5

12.096

11.718

11.364

11.03

10.714

10.416

10.136

9.868

9.616

9.375

9.146

8.929

8.72

8.523

8.334

8.152

7.978

7.813

7.654

7.5

7.352

7.212

7.076

6.944

6.818

6.696

6.578

6.466

6.356

6.25

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

22.728

20.834

19.23

17.858

16.666

15.626

14.706

13.888

13.158

12.5

11.904

11.364

10.87

10.416

10

9.616

9.26

5.682

5.209

4.808

4.484

4.166

3.906

3.676

3.472

3.289

3.125

2.976

2.841

2.718

2.604

2.5

2.404

2.315

2.232

2.155

2.084

2.016

1.953

1.894

1.838

1.786

1.736

1.689

1.645

1.602

1.563

1.524

1.488

1.453

1.421

1.389

1.359

1.33

11.719

11.029

10.417

9.868

9.375

8.929

8.523

8.152

7.813

7.5

7.212

6.944

6.696

6.466

6.25

6.048

5.859

5.682

5.515

5.357

5.208

5.068

4.934

4.808

4.688

4.573

4.464

4.36

5.859

5.515

5.208

4.934

4.688

4.464

4.261

4.076

3.906

3.75

3.606

3.472

3.348

3.233

3.125

3.024

2.930

2.841

2.757

2.679

2.604

2.534

2.467

2.404

2.344

2.287

2.232

2.18

5.952

5.682

5.435

5.208

5

4.808

4.63

8.928

8.62

4.464

4.31

8.334

8.064

7.812

7.576

7.352

7.124

6.944

6.756

6.578

6.41

4.167

4.032

3.906

3.788

3.676

3.571

3.472

3.378

3.289

3.205

3.125

3.049

2.976

2.907

2.841

2.778

2.717

2.66

6.25

6.098

5.952

5.814

5.682

5.556

5.434

5.32

4.261

4.167

4.076

3.989

3.906

3.827

3.75

3.676

3.606

3.538

3.472

3.409

3.348

3.289

3.233

3.178

3.125

3.074

3.024

2.976

2.131

2.083

2.038

1.995

1.953

1.913

1.875

1.838

1.802

1.769

1.736

1.705

1.674

1.645

1.616

1.589

1.563

1.537

1.512

1.488

1.065

1.042

1.019

0.997

0.977

0.957

0.938

0.919

0.901

0.884

0.868

0.852

0.837

0.822

0.808

0.795

0.781

0.768

0.756

0.744

5.208

5.102

5

4.902

4.808

4.716

4.63

4.546

4.464

4.386

4.31

4.238

4.166

4.098

4.032

3.968

2.604

2.551

2.5

1.302

1.276

1.25

2.451

2.404

2.358

2.315

2.273

2.232

2.193

2.155

2.119

2.083

2.049

2.016

1.984

1.225

1.202

1.179

1.157

1.136

1.116

1.096

1.078

1.059

1.042

1.025

1.008

0.992

6.148

6.048

5.952

Table 16-1 . Example for f =8MHz

Table 16-2 . Example for f =12MHz

ex

November 2001 ver 1.2

53

HMS81C43xx / GMS87C4060

17. On Screen Display (OSD)

The On Screen Display circuit is shown in Figure 17-1 .

The OSD circuit consists of the Position attribute register,

Line register, Full screen screen control register, sprite

control register, sprite position reigster, I/O polarity regis-

ter, sprite RAM, font ROM, VRAM, etc. The more details

about registers are shown Figure 17-2.

The HMS81C43xx/GMS87C4060 can support 512 OSD

chacters, but the last 6 characters (number 506 ~ 511,

1FA ~ 1FF ) are reserved for IC test and its pattern is

H

fixed by manufacturer. So you can use 506 characters for

your own.

Line 1,2 Attribute,

Position register

Full screen control

register

Line register

Sprite control register

OSDCON2 [AE1_H]

Sprite position register I/O polarity register

L1ATTR [AF0_H]

L1VPOS [AF1_H]

OSDLN [AE5_H]

OSDCON1 [AE0_H]

SPVPOS [AE8_H]

SPHPOS [AE9_H]

OSDPOL [AE2_H]

Horizontal position register

LHPOS [AE6_H]

Field detection register

FDWSET [AE3_H]

L2ATTR [AF3_H]

L2VPOS [AF4_H]

Color Mode Register

COLMOD [0AEF_H]

Edge color register

EDGECOL [AE4_H]

Mesh Control Register

MESHCON [0AEB_H]

OSD Control

Circuit

Sprite Control

Circuit

VRAM

Sprite RAM

Font ROM

R

G

Output

Control

Circuit

B

Sprite Control

Circuit

OSD, Sprite Generation Circuit

I

YS

YM

HSYNC

VSYNC

OSC1

Synchronization

Circuit

OSC2

Figure 17-1 Block Diagram of On Screen Display circuit

N ovem ber 2001 ver 1.2

54

HMS81C43xx / GMS87C4060

Character(foreground)