HN28F101RD-15 [ETC]
131072-word ?? 8-bit CMOS Flash Memory; 131072字？ 8位CMOS闪存
| 型号： | HN28F101RD-15 |
| 厂家： | 
ETC |
| 描述： | 131072-word ?? 8-bit CMOS Flash Memory |
| 文件： | 总18页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HN28F101 Series
131072-word × 8-bit CMOS Flash Memory
The Hitachi HN28F101 is a 131072-word x 8-bit
CMOS flash Memory, realizing on-board
programming. It programs or erases data with only
• Erasing endurance: 10,000 times
• Pin arrangement: 32-pin JEDEC standard
• Package
on-board power supply (12 V V supply/5 V
32-pin DIP
32-pin SOP
32-pin TSOP
32-pin PLCC
PP
V
supply). It programs data with fast program-
CC
ming algorithm by command inputs. It has two
types of erase algorithm : automatic erase and fast
erase by command inputs. Automatic erase func-
tion can erase data automatically without external
control only by inputting trigger pulse and inform
erase completion to CPU by status polling. The
HN28F101 can control programming erase
algorithm externally.
Ordering Information
Type No.
——————————————————————–
HN28F101P-12 120 ns 32-pin plastic
——————————————— DIP
HN28F101P-15 150 ns (DP-32)
———————————————
HN28F101P-20 200 ns
——————————————————————–
HN28F101FP-12 120 ns 32-pin plastic
——————————————— SOP
HN28F101FP-15 150 ns (FP-32D)
———————————————
HN28F101FP-20 200 ns
——————————————————————–
HN28F101T-12 120 ns 32-pin plastic
——————————————— TSOP
HN28F101T-15 150 ns (TFP-32DA)
———————————————
HN28F101T-20 200 ns
————————————————–——————
HN28F101R-12 120 ns 32-pin plastic
——————————————— TSOP
HN28F101R-15 150 ns (TFP-32DAR)
———————————————
HN28F101R-20 200 ns
——————————————————————–
HN28F101CP-12 120 ns 32-pin
——————————————— PLCC
HN28F101CP-15 150 ns (CP-32)
———————————————
HN28F101CP-20 200 ns
——————————————————————–
Access time Package
Features
• On-board power supply (V /V
)
CC PP
V
V
V
= 5 V ± 10%
CC
PP
PP
= V to V (Read)
SS
CC
= 12.0 V ± 0.6 V (Erase/Program)
• Fast access time
120 ns/150 ns/200 ns (max)
• Programming function
Byte programming
Programming time: 25 µs typ/byte
Address, data, control latch function
• On-board automatic erase function
Chip erase
Erase time: 1 s typ
Address, data, control latch function
Status polling function
• Low power dissipation
I
I
I
I
= 10 mA typ (Read)
= 20 µA max (Standby)
= 30 mA typ (Auto erase/Program)
= 20 µA max (Read/Standby)
CC
CC
PP
PP
HN28F101 Series
HN28F101 Series
Ordering Information (cont.)
Pin Description
Type No.
Access time Package
Pin name
——————————————————————–
A0-A16 Address
——————————————————————–
I/O0-I/O7 Input/output
——————————————————————–
CE Chip enable
——————————————————————–
OE Output enable
——————————————————————–
WE Write enable
——————————————————————–
Power supply
——————————————————————–
Programming power supply
——————————————————————–
Ground
Function
——————————————————————–
HN28F101TD-12
——————————————— TSOP
HN28F101TD-15 150 ns (TFP-32D)
———————————————
HN28F101TD-20 200 ns
——————————————————————–
HN28F101RD-12 120 ns 32-pin plastic
——————————————— TSOP
HN28F101RD-15 150 ns (TFP-32DR)
———————————————
HN28F101RD-20 200 ns
120 ns
32-pin plastic
V
CC
——————————————————————–
V
PP
V
SS
——————————————————————–
Pin Arrangement
HN28F101P/FP Series
HN28F101CP Series
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I /O0
I /O1
I /O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I / O7
I / O6
I / O5
I / O4
I / O3
4 3 2 1 32 31 30
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
29
28
27
26
25
24
23
22
21
A14
A13
A8
5
6
7
8
A9
A11
OE
A10
CE
9
10
11
12
13
I/O7
14 15 16 17 18 19 20
(Top view)
(Top view)
2
HN28F101 Series
HN28F101 Series
Pin Arrangement (cont)
HN28F101T/TD Series
1
2
3
4
5
6
7
8
OE
A10
CE
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
NC
WE
VCC
VPP
A16
A15
A12
A7
A6
A5
I / O7
I / O6
I / O5
I / O4
I / O3
VSS
I / O2
I / O1
I / O0
A0
9
10
11
12
13
14
15
16
A1
A2
A3
A4
(Top view)
HN28F101R/RD Series
1
OE
A10
CE
32
A11
A9
A8
A13
A14
NC
WE
VCC
VPP
A16
A15
A12
A7
A6
A5
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I / O7
I / O6
I / O5
I / O4
I / O3
VSS
I / O2
I / O1
I / O0
A0
A1
A2
A3
A4
(Top view)
3
HN28F101 Series
HN28F101 Series
Block Diagram
A5
A9
X –
Decoder
Address
Latch
1024 X 1024
Memory Matrix
A12
A16
I/O0
I/O7
Y – Gating
Input
Data
Latch
Data
Y – Decoder
Control
Address Latch
CE
OE
R / W / E
Control
A0 – A4, A10, A11
WE
V
CC
: High Threshold Inverter
H
VPP
H
VSS
Latch
4
HN28F101 Series
HN28F101 Series
Mode Selection
Pin
————————————————————————————————
V
(1)
(9)
CE
(22)
(30)
OE
(24)
(32)
WE
(31)
(7)
A9
(26)
(2)
I/O0 – I/O7
(13 – 15, 17 – 21)
(21 – 23, 25 – 29)
PP
DIP, SOP, PLCC
TSOP
Mode
———————————————————————————————————————————————–
*6
Read
Read
V
V
V
V
A9
Dout
CC
IL
IL
IH
————————————————————————————————————————––
Output disable High-Z
————————————————————————————————————————––
Standby High-Z
————————————————————————————————————————––
V
V
V
V
IH
X
CC
IL
IH
V
V
X
X
X
CC
IH
*1
*2
Identifier
V
V
V
V
VH
ID
CC
IL
IL
IH
———————————————————————————————————————————————–
*3,*5
Command
program
Read
V
V
V
V
IH
A9
Dout
PP
IL
IL
————————————————————————————————————————––
Output disable High-Z
————————————————————————————————————————––
Standby High-Z
V
V
V
V
IH
X
PP
IL
IH
V
V
X
X
X
PP
IH
————————————————————————————————————————––
*4
Write
V
V
V
V
IL
A9
Din
PP
IL
IH
———————————————————————————————————————————————–
Notes: 1. Device identifier code can be output in command programming mode. Refer to the table of
command address and data input.
2. V : 11.5 < V < 12.5V.
H
H
3. Data can be read when 12 V is applied to V . Device identifier code can be output by
PP
command inputs.
4. Refer to the table of command address and data input. Data is programmed, erased, or verified
after mode setting by command inputs.
5. Status of automatic erase can be verified in this mode. Status outputs on I/O7. I/O0 to I/O6 are
in high impedance state.
6. X : V or V . V = 0 V to V
IH
IL
PP
CC
5
HN28F101 Series
HN28F101 Series
Command Address and Data Input
First cycle
Second cycle
——————————————— ———————————————
*2
*3
*2
*3
The number Operation Address Data
Operation Address Data
mode
*1
*1
Command
of cycle
mode
———————————————————————————————————————————————–
*4
Read (memory)
1
Write
X
00H
Read
RA
Dout
———————————————————————————————————————————————–
Read identified codes Write 90H Read IA ID
2
X
———————————————————————————————————————————————–
*5
Setup erase/erase
2
Write
X
20H
Write
X
20H
———————————————————————————————————————————————–
*5
Erase verify
2
Write
EA
A0H
Read
X
EVD
———————————————————————————————————————————————–
Setup auto erase/
auto erase
2
Write
X
30H
Write
X
30H
*6
———————————————————————————————————————————————–
Setup program/
program
2
Write
X
40H
Write
PA
PD
*7
———————————————————————————————————————————————–
*7
Program verify
2
Write
X
C0H
Read
X
PVD
———————————————————————————————————————————————–
Reset Write FFH Write FFH
2
X
X
———————————————————————————————————————————————–
Notes: 1. Refer to command program mode in mode selection about operation mode.
2. Refer to device identifier mode. IA = Identifier address, PA = Programming address, EA = Erase
verify address, RA = Read address
3. Refer to device identifier mode. PA are latched by programming command. ID = Identifier
output code, PD = Programming data, PVD = Programming verify output data, EVD = Erase
verify output data
4. Command latch default value when applying 12 V to V is “00H”. Device is in read mode after
PP
V
is set 12 V (before other command is input).
PP
5. All data in chip are erased. Erase data according to fast high-reliability erase flowchart.
6. All data in chip are erased. Data are erased automatically by internal logic circuit. External
erase verify is not required. Erasure completion must be verified by status polling after
automatic erase starts.
7. Program data according to fast high-reliability programming flowchart.
6
HN28F101 Series
HN28F101 Series
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
———————————————————————————————————————————————–
*1
*2
All input and output voltage
Vin, Vout
–0.6 to +7.0
V
———————————————————————————————————————————————–
*1
V
voltage
V
–0.6 to +14.0
V
PP
PP
———————————————————————————————————————————————–
*1
V
voltage
V
–0.6 to +7.0
V
CC
CC
———————————————————————————————————————————————–
Operating temperature range Topr 0 to +70 °C
———————————————————————————————————————————————–
*3
Storage temperature range
Tstg
–55 to +125
°C
———————————————————————————————————————————————–
Storage temperature under bias Tbias –10 to +80 °C
———————————————————————————————————————————————–
Notes: 1. Relative to V
.
SS
2. Vin, Vout, V min = –2.0 V for pulse width < 20 ns.
ID
3. Device storage temperature range before programming.
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter
———————————————————————————————————————————————–
Input capacitance Cin pF Vin = 0 V
———————————————————————————————————————————————–
Output capacitance Cout 12 pF Vout = 0 V
———————————————————————————————————————————————–
Symbol
Min
Typ
Max
Unit
Test condition
—
—
6
—
—
7
HN28F101 Series
HN28F101 Series
Read Operation
DC Characteristics (V = 5 V ± 10%, V = V
V
, Ta = 0 to +70°C)
CC
PP
CC~ SS
Parameter
Symbol
Min
Typ
Max
Unit
Test condition
———————————————————————————————————————————————–
Input leakage current µA Vin = 0 to V
———————————————————————————————————————————————–
Output leakage current µA Vout = 0 to V
———————————————————————————————————————————————–
current 20 µA = 5.5 V
———————————————————————————————————————————————–
Standby V current mA CE = V
———————————————————————————————————–
20 µA CE = V
———————————————————————————————————————————————–
Operating V current 15 mA Iout = 0 mA, f = 1 MHz
———————————————————————————————————–
10 30 mA Iout = 0 mA, f = 8 MHz
———————————————————————————————————————————————–
I
—
—
2
LI
CC
CC
I
—
—
2
LO
V
I
—
—
V
PP
PP
PP1
I
—
—
1
CC
SB1
IH
CC
I
—
—
SB2
I
—
6
CC
CC1
I
—
CC2
*3
*1
Input voltage
V
–0.3
—
0.8
V
IL
———————————————————————————————————–
*2
V
2.2
—
V
+ 0.3
V
IH
CC
———————————————————————————————————————————————–
Output voltage 0.45 = 2.1 mA
———————————————————————————————————–
2.4 = –400 µA
———————————————————————————————————————————————–
Notes: 1. V min = –2.0 V for pulse width < 20 ns.
V
—
—
V
I
OL
OL
V
—
—
V
I
OH
OH
IL
2. V max = V
+ 1.5 V for pulse width < 20 ns.
IH
CC
If V is over the specified maximum value, read operation cannot be guaranteed.
IH
3. Only defined for DC and long cycle function test.
V
max = 0.45 V, V min = 2.4 V for AC function test.
IL
IH
8
HN28F101 Series
HN28F101 Series
AC Characteristics (V = 5 V ± 10%, V = V to V , Ta = 0 to +70°C)
CC
PP
SS
CC
Test Conditions
• Input pulse levels: 0.45 V/2.4 V
• Input rise and fall times: 10 ns
• Reference levels
for measuring timing: 0.8 V, 2.0 V
• Output load: 1TTL Gate + 100 pF (Including
scope and jig.)
HN28F101-12 HN28F101-15 HN28F101-20
—————— —————— ——————
Symbol Min Max Min Max Min Max
Test
Unit condition
Parameter
———————————————————————————————————————————————–
Address to output delay 120 150 200 ns CE = OE = V
———————————————————————————————————————————————–
CE to output delay 120 150 200 ns OE = V
———————————————————————————————————————————————–
60 70 80 ns
t
—
—
—
ACC
IL
t
—
—
—
CE
IL
OE to output delay
t
—
—
—
CE = V
IL
OE
———————————————————————————————————————————————–
*1
OE high to output float
t
0
40
0
50
0
60
ns
CE = V
DF
IL
———————————————————————————————————————————————–
Address to output hold ns CE = OE = V
———————————————————————————————————————————————–
t
5
—
5
—
5
—
OH
IL
Note: 1. t is defined as the time at which the output achieves the open circuit condition and data is no
DF
longer driven.
Read Timing Waveform
Address
CE
OE
WE
Standby Mode
Standby Mode
Active Mode
t CE
High
tDF
tOH
tOE
tACC
Data Out
Data Out Valid
9
HN28F101 Series
HN28F101 Series
Command Programming/Data Programming/Erase Operation
DC Characteristics (V = 5 V ± 10%, V = 12.0 V ± 0.6 V, Ta = 0 to +70°C)
CC
PP
Parameter
Symbol Min
Typ
Max
Unit
Test condition
———————————————————————————————————————————————–
Input leakage current µA Vin = 0 V to V
———————————————————————————————————————————————–
Output leakage current µA Vout = 0 V to V
———————————————————————————————————————————————–
Standby V current mA CE = V
———————————————————————————————————–
200 µA CE = V
———————————————————————————————————————————————–
Operating Read 15 mA Iout = 0 mA, f = 1 MHz
current —————————————————————————————–——————
10 30 mA Iout = 0 mA, f = 8 MHz
———————————————————————————————————–—————–
Program 10 mA
———————————————————————————————————–—————–
Erase 10 40 mA In automatic erase
———————————————————————–——————–—————–
15 mA In high-reliability erase
———————————————————————————————————————————————–
current Read mA = 12.6 V
———————————————————————————————————–—————–
Program 30 mA In programming
———————————————————————————————————–—————–
Erase 35 80 mA In automatic erase
——————————————————————————————–—————
10 30 mA In high-reliability erase
I
—
—
2
LI
CC
CC
I
—
—
2
LO
I
—
—
1
CC
SB1
IH
CC
I
—
—
SB2
I
—
6
CC1
V
CC
I
—
CC2
I
—
2
CC3
I
—
CC4
I
—
5
CC5
V
I
—
—
1
V
PP
PP
PP1
I
—
5
PP2
I
—
PP3
I
—
PP4
———————————————————————————————————————————————–
*4
Input voltage
V
– 0.3
—
0.8
V
IL
———————————————————————————————————–
*5
V
2.2
—
V
+ 0.3
V
IH
CC
———————————————————————————————————————————————–
Output voltage 0.45 = 2.1 mA
———————————————————————————————————–
2.4 = –400 µA
———————————————————————————————————————————————–
Notes: 1. V /V power on/off timing
V
—
—
V
I
OL
OL
V
—
—
V
I
OH
OH
CC PP
V
must be applied before or simultaneously V , and removed after or simultaneously V
.
CC
PP
PP
This V /V power on/off timing must be satisfied at V /V on/off caused by power failure.
CC PP
CC PP
5V
0V
VCC
0µs min
0µs min
12V
VPP
5V
0V
2. V must not exceed 14 V including overshoot.
PP
3. An influence may be had upon device reliability if the device is installed or removed while
= 12 V.
V
PP
4. V min = –1.0 V for pulse width < 20 ns.
IL
5. If V is over the specified maximum value, programming operation cannot be guaranteed.
IH
10
HN28F101 Series
HN28F101 Series
AC Characteristics (V = 5 V ± 10%, V = 12.0 V ± 0.6 V, Ta = 0 to +70°C)
CC
PP
Test condition
• Input pulse levels: 0.45 V/2.4 V
• Input rise and fall times: 10 ns
• Reference levels
for measuring timing: 0.8 V, 2.0 V
• Output load: 1TTL Gate + 100 pF (Including
scope and jig.)
HN28F101-12 HN28F101-15 HN28F101-20
—————— —————— ——————
Test
Parameter
———————————————————————————————————————————————–
Command programming cycle tim 120 150 200 ns
———————————————————————————————————————————————–
Address setup time ns
———————————————————————————————————————————————–
Address hold time 60 60 60 ns
———————————————————————————————————————————————–
Data setup time 50 50 50 ns
———————————————————————————————————————————————–
Data hold time 10 10 10 ns
———————————————————————————————————————————————–
CE setup time ns
———————————————————————————————————————————————–
CE hold time 50 50 50 ns
———————————————————————————————————————————————–
setup time 100 100 100 ns
———————————————————————————————————————————————–
hold time 100 100 100 ns
———————————————————————————————————————————————–
WE programming pulse width 70 70 80 ns
———————————————————————————————————————————————–
WE programming pulse high time 40 40 40 ns
———————————————————————————————————————————————–
Symbol Min
Max Min
Max Min
Max Unit condition
e
t
—
—
—
CWC
t
0
—
0
—
0
—
AS
t
—
—
—
AH
t
—
—
—
DS
t
—
—
—
DH
t
0
—
0
—
0
—
CES
t
—
—
—
CEH
V
t
—
—
—
PP
VPS
V
t
—
—
—
PP
VPH
t
—
—
—
WEP
t
—
—
—
WEH
OE setup time before command
programming
t
0
—
0
—
0
—
ns
OEWS
———————————————————————————————————————————————–
OE setup time before verify µs
———————————————————————————————————————————————–
Verify access time 120 150 200 ns
———————————————————————————————————————————————–
Verify access time in erase 300 300 300 ns
———————————————————————————————————————————————–
OE setup time before status polling t 120 120 120 ns
t
6
—
6
—
6
—
OERS
t
—
—
—
VA
t
—
—
—
VAE
—
—
—
OEPS
———————————————————————————————————————————————–
Status polling access time 120 150 200 ns
———————————————————————————————————————————————–
Standby time before programming 25 25 25 µs
———————————————————————————————————————————————–
Standby time in erase 11 11 11 ms
———————————————————————————————————————————————–
t
—
—
—
SPA
t
—
—
—
PPW
t
9
9
9
ET
*3
Output disable time
t
0
40
0
50
0
60
ns
DF
———————————————————————————————————————————————–
Total erase time in automatic erase
———————————————————————————————————————————————–
*3
t
—
30
—
30
—
30
s
AET
11
HN28F101 Series
HN28F101 Series
Notes: 1. CE, OE, and WE must be fixed high during V transition from 5 V to 12 V or from 12 V to 5 V.
PP
2. Refer to read operation when V = V
about read operation while V = 12 V .
PP
CC
PP
3. t is defined as the time at which the output achieves the open circuit condition and data is no
DF
longer driven.
4. Address are taken into on the falling edge of write-enable pulse and addresses are latched on
the rising edge of write-enabke pulse during chip-enable is low. Data is latched on the rising
edge of write-enable pulse during chip-enable is low.
Erase and Program Time
*4
Erase and program mode
———————————————————————————————————————————————
Chip (128 kB) erase time Auto erase mode 30 second
Min
Typ
Max
Unit
—
1
——————————————————————————————————
*2, 3
Fast high-reliability erase mode
—
0.6
30
second
———————————————————————————————————————————————
*3
*5
Chip (128 kB) program time Fast high-reliability program mode
—
5
81
second
———————————————————————————————————————————————
Notes: 1. Each values are same for all read access version.
2. Excludes pre-write process before erasure and verify process (6 µs x 128 kB).
3. Excludes system overhead.
4. Ta = 25°C, V = 12 V, V
= 5 V
PP
CC
5. Theoretical value calculated from fast high-reliability programming flowchart.
(25 µs program + 6 µs verify) x 20 times x 128 kB = 81 second.
12
HN28F101 Series
HN28F101 Series
Automatic Erase Timing Waveform
Setup auto erase
Auto erase & status polling
5.0 V
VCC
12 V
V
PP5.0 V
tVPS
tVPH
Address
CE
OE
tCEH
tCES
tAET
tSPA
tCES
tWEP
tCWC
CES
tOEPS
t
tWEP
t
OEWS
t
CEH
tWEH
WE
tDF
tDS
tDH
tDS tDH
I / O7
Command
in
Command
in
Status polling
I / O0 – I / O6
Command
in
Command
in
Status Polling
Status polling allows the status of the flash memory to be determined. If the flash memory is set to the
status polling mode during erase cycle, I/O7 pin is lowered to V level to indicate that the flash memory
OL
is performing erase operation. I/O7 pin is set to the V
level when erase operation has finished.
OH
Notes: In automatic erase mode, the device automatically processes to pre-write all “0“ before erasing.
Therefore, it is not required to pre-write by fast high-reliability programming.
13
HN28F101 Series
HN28F101 Series
Fast High-Reliability Programming
This device can be applied the fast high-reliability programming algorithm shown in following flowchart.
This algorithm allows to obtain fasterprogramming time without any voltage stress to the device nor
deterioration in reliability of programmed data.
START
Apply V = 12.0 ± 0.6 V
PP
Address = 0
n = 0
→
n
n + 1
Write setup program command
Write program address and data
µ
Wait 25
s
Write program verify command
→
Address + 1 Address
Wait 6 µs
NOGO
Verify
GO
NO
NO
LAST
Address ?
n = 20
YES
YES
Apply V = V
PP
CC
FAIL
END
Fast High-Reliability Programming Flowchart
Notes: In case of two or more devices are programmed simultaneously, following steps should be apllied
to avoid over programming for the verified device .
(1) Write set up program command to FFH,
(2) Write program command to FFH,
(3) Write program verify command to 00H and program verify address to read address.
14
HN28F101 Series
HN28F101 Series
Fast High-Reliability Programming Timing Waveform
Program verify
Setup program
Program
5.0 V
VCC
VPP
12 V
tVPS
tVPH
5.0 V
Address
valid
Address
CE
tAH
tAS
tCEH
tCES
OE
tCWC
tCES
tWEP
tCEH
tPPW
t
WEP tCEH
tOEWS
tCES
tWEP
tOERS
tWEH
tDH
WE
tDF
tVA
tDH
tDH
tDS
tDS
tDS
Data
in
Command
in
Command
in
Data out
I / O7
valid
Data
in
Command
in
Command
in
Data out
valid
I / O0 to I / O6
Notes: The data output level during program verification may result in an intermediate level between V
OH
and V due to an insufficiently programmed.
OL
15
HN28F101 Series
HN28F101 Series
Fast High-Reliability Erase
This device can be applied the fast high-reliability erase algorithm showm in following flowchart
This algorithm allows to abtain faster erase time without any voltage any voltage stress to the device nor
deterioration in reliability of data.
START
YES
All bits
DATA = 00H?
NO
All bits program 00H *1
Set address
n = 0
n + 1
n
Write setup erase / erase command
Wait 10 ms
Write erase verify command
Wait 6 µs
Address + 1 Address
NO
Verify
YES
NO
LAST
Address ?
NO
n = 3000
YES
YES
END
FAIL
*1. Program data to all bits according to fast high-reliability erasing flowchart.
Fast High-Reliability Erasing Flowchart
Notes: In case of two or more devices are erased simultaneously, following steps should be applied to
avoid over erase for verified device.
(1) Write set up erase command to A0H and set erase verify address to verify address.
(2) Write erase command to A0H.
(3) Write erase verify command to A0H.
16
HN28F101 Series
HN28F101 Series
Erase Timing Waveforms
Erase verify
Setup erase
Erase
5.0 V
12 V
V
CC
V
PP
t
VPS
5.0 V
t
VPH
Address
Address valid
t
t
AS
AH
CE
OE
t
OEWS
t
CEH
t
t
CES
t
CEH
WEP
CWC
t
t
t
t
t
t
WEP
WEP
OERS
CES
t
CES
ET
WE
t
t
CEH
VAE
t
t
DF
DH
t
t
DH
t
t
t
DS
t
WEH
DS DH
DS
Data out
valid
I/O0 to I/O7
Command in
Command in
Command in
Notes: The data output level during erasure verification may result in an intermediate level between VOH
and VOL due to an insufficiently erased.
17
HN28F101 Series
Mode Description
Device Identifier Mode
HN28F101 Series
The device identifier mode allows the reading out of binary codes that identify manufacturer and type of
device, from outputs of flash memory. By this mode, the device will be automatically matched its own
corresponding erase and programming algorithm, using programming equipment.
HN28F101 Series Identifier Code
Pins
DIP. SOP, PLCC
TSOP
A0
(12)
(20)
I/O7
(21)
(29)
I/O6 I/O5 I/O4 I/O3
I/O2
(15)
(23)
I/O1
(14)
(22)
I/O0 Hex
(13)
(21) Data
(20) (19) (18)
(28) (27) (26)
(17)
(25)
Identifier
———————————————————————————————————————————————–
Manufacturer code 07
———————————————————————————————————————————————–
Device code 19
———————————————————————————————————————————————–
Notes : 1. Device identifier code can be read out by applying 12.0 V ±0.5 V to A9 when V = V , or
V
0
0
0
0
0
1
1
1
IL
V
0
0
0
1
1
0
0
1
IH
PP
CC
inputting command while V is 12 V.
PP
2. A1 to A8, A10 to A16, and CE = OE = V , WE = V
IL
IH
3. V
= V = 5 V ±10%
CC
PP
18
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