HX6136FSRT_技术文档

Aerospace Electronics

FIFO—SOI

HX6409

HX6218

HX6136

FEATURES

• 1K x 36, 2K x 18, 4K x 9 Organizations

OTHER

• Fabricated with RICMOS^™IV Silicon on Insulator

• Read/Write Cycle Times

(SOI) 0.8 µm Process (L_eff= 0.65µm)

<35 ns (-55° to 125°C)

• Expandable in Width

RADIATION

• Supports Free-Running 50% Duty Cycle Clock

• Empty, Full, Half Full, 1/4 Full, 3/4 Full, Error Flags

• Parity Generation/Checking

• Total Dose Hardness through 1x10⁶rad(SiO₂)

• Neutron Hardness through 1x10¹⁴cm^-2

• Dynamic and Static Transient Upset Hardness

through 1x10⁹rad(Si)/s

• Fully Asynchronous with Simultaneous

Read and Write Operation

• Dose Rate Survivability through 1x10¹¹rad(Si)/s

• Soft Error Rate of <1x10^-10upsets/bit-day

• No Latchup

• Output Enable (OE)

• CMOS or TTL Compatible I/O

• Single 5 V ± 10% Power Supply

• Various Flat Pack Options

GENERAL DESCRIPTION

The HX6409, HX6218, and HX6136 are high speed, low-

power, first-in first-out memories with clocked read and

write interfaces. The HX6409 is a 4096 word by 9 bit

memory array, the HX6218 is a 2048 word by 18 bit

memory array, and the HX6136 is a 1024 word by 36 bit

memory array. The FIFOs support width expansion while

depthexpansionrequiresexternallogiccontrolusingstate

machinetechniques.Featuresincludeprogrammablepar-

ity control, an empty/full flag, a quarter/three quarter full

flag, a half full flag and an error flag.

The output port is controlled in a similar manner by a free-

running read clock (CKR) and a read enable pin (

). In

ENR

addition, the three FIFOs have an output enable pin (

and a master reset pin (

MR

)

OE

). The read (CKR) and write

(CKW) clocks may be tied together for single-clock

operation or the two clocks may be run independently for

asynchronous read/write applications. Clock frequencies

up to 30 MHz are achievable in the three configurations.

Honeywell’s enhanced SOI RICMOS™ IV (Radiation In-

sensitive CMOS) technology is radiation hardened through

the use of advanced and proprietary design, layout and

process hardening techniques. The FIFO is fabricated with

Honeywell’s radiation hardened technology, and is de-

signed for use in systems operating in radiation environ-

ments. The SOI RICMOS™ IV process is a 5-volt, SIMOX

CMOS technology with a 150 Å gate oxide and a minimum

drawn feature size of 0.8 µm, (0.65 µm effective gate

array—L_eff). Additional features include tungsten via plugs,

Honeywell’s proprietary SHARP planarization process,

andalightlydopeddrain(LDD)structureforimprovedshort

channel reliability.

These FIFOs provide solutions for a wide variety of data

buffering needs, including high-speed data acquisition,

multiprocessor interfaces, and communications buffer-

ing. These FIFOs have separate input and output ports

that are controlled by separate clock and enable sig-

nals. The input port is controlled by a free running clock

(CKW) and a write enable pin

. When

is

ENW

asserted, data is written into the FIFO on the rising edge

of the CKW signal. While is held active, data is

ENW

continually written into the FIFO on each CKW cycle.

Solid State Electronics Center • 12001 State Highway 55, Plymouth, MN 55441 • (800) 323-8295 • http://www.ssec.honeywell.com

HX6409/HX6218/HX6136

LOGIC BLOCK DIAGRAM

D: 0 - 8

D: 0 - 17

D: 0 - 35

Input

Register

CKW

ENW

Parity

Program

Register

Parity

Write Control

HF

E/F

QF/TQF

EF_Fault

Flag Logic

Memory

Array

4096 x 9

2048 x 18

1024 x 36

Read Pointer

Write Pointer

Reset Logic

MR

Tri-State

Output Register

Read Control

OE

CKR

ENR

Q: 0 - 8

Q: 0 - 17

Q: 0 - 35

FLAG DECODE TABLE

Word Count

EF_Fault E/ F

QF/TQF HF

State

4K x 9

2K x 18

0

1K x 36

0

1

0

1

0

1

0

1

0

Empty Fault (Enabled Read when Empty)

Empty

0

Less than or Equal to 1/4 Full

Less than or Equal to 1/2 Full

Greater that 1/2 Full

1 to 1024

1025 to 2048

2049 to 3071

3072 to 4095

4096

1 to 512

513 to 1024

1025 to1535

1536 to 2047

2048

1 to 256

257 to 512

513 to 767

768 to 1023

1024

Greater than or Equal to 3/4 Full

Full

Full Fault (Enabled Write when Full)

4096

2048

1024

2

HX6409/HX6218/HX6136

SIGNAL DEFINITIONS

Signal Name I/O

Description

D: 0 - 35

I

Data Inputs: Data Inputs are written into the FIFO on the rising edge of CKW when ENW

is active and the FIFO is not full.

Q: 0 - 35

O

Data Outputs: Data Outputs are read out of the FIFO memory and updated on the rising

ENR

edge of CKR when

high impedance state if

is active and the FIFO is not Empty. The Data Outputs are in a

is not active.

OE

ENW

I

Enable Write: An active low signal that enables the write of the Data Inputs on the CKW

rising edge (if FIFO is not full).

Enable Read: An active low signal that enables the read and update of the Data Outputs

on the CKR rising edge (if FIFO is not empty).

ENR

CKW

CKR

HF

I

Write Clock: The rising edge clocks data into the FIFO when

is low (active). On the

ENW

rising edge, this signal also updates the Half Full, 3/4 Full, Full, and Full Fault Flags.

ENR

is low (active). On

I

Read Clock: The rising edge clocks data out of the FIFO when

the rising edge, this signal also updates the 1/4 Full, Empty, and Empty Fault Flags.

O

Half Full Flag: Updated on the rising edge of CKW and indicating that the FIFO is greater

than half full.

E/ F

Empty or Full Flag: Empty is updated on the rising edge of CKR, and Full is updated on

the rising edge of CKW.

QF/TQF

1/4 Full or 3/4 Full Flag: 1/4 Full is updated on the rising edge of CKR, and 3/4 Full is

updated on the rising edge of CKW. 1/4 Full signifies 256 or less words in the 1K x 36

FIFO and 3/4 Full signifies 256 words or less until a full condition.

EF_Fault

O

Empty or Full Fault Flag: empty Fault is updated on the rising edge of CKR, and Full

Fault is updated on the rising edge of CKW. Empty Fault signifies a read to an already

empty FIFO, and Full Fault signifies a write to an already full FIFO. Once a fault condition

is detected, the Fault Flag remains latched until the empty or full condition is removed.

I

Master Reset: Active low signal which, when active, resets device to empty condition.

MR

OE

Output Enable: Active low signal which, when active, enables low impedance Data

Outputs, Q: 0 - 35.

PROGRAMMABLE PARITY OPTIONS

D2

D1

X

O

I

D0 Conditions

O

I

X

O

I

Parity Disabled

Generate Even Parity, Q8, Q17, Q26, Q35

I

Generate Odd Parity, Q8, Q17, Q26, Q35

I

O

I

Check for Even Parity, Error on Q8, Q17, Q26, Q35, Error is a Low Signal

Check for Odd Parity, Error on Q8, Q17, Q26, Q35, Error is a Low Signal

I

3

HX6409/HX6218/HX6136

RADIATION CHARACTERISTICS

Total Ionizing Radiation Dose

All FIFO configurations will meet all stated functional and

electrical specifications over the entire operating tempera-

ture range after the specified total ionizing radiation dose.

All electrical and timing performance parameters will re-

main within specifications after rebound at VDD = 5.5 V

and T = 125°C extrapolated to ten years of operation. Total

dose hardness is assured by wafer level testing of process

monitor transistors and product using 10 KeV X-ray and

radiation sources. Transistor gate threshold shift correla-

tions have been made between 10 KeV X-rays applied at

a dose rate of 1x10⁵rad(SiO₂)/min at T = 25°C and gamma

rays (Cobalt 60 source) to ensure that wafer level X-ray

testing is consistent with standard military radiation test

environments.

Each FIFO will meet any functional or electrical specifica-

tion after exposure to a radiation pulse of ≤50 ns duration

up to 1x10¹¹rad(Si)/s, when applied under recommended

operating conditions. Note the current conducted during

the pulse by the inputs, outputs and power supply may

significantly exceed the normal operating levels. The appli-

cation design must accommodate these effects.

Neutron Radiation

Each FIFO configuration will meet any functional or timing

specificationafteratotalneutronfluenceofupto1x10¹⁴cm^-

²applied under recommended operating or storage condi-

tions.Thisassumesanequivalentneutronenergyof1MeV.

Transient Pulse Ionizing Radiation

Soft Error Rate

Each FIFO configuration is capable of writing, reading

and retaining stored data during and after exposure to a

transient ionizing radiation pulse of <50 ns duration up to

1x10⁹rad(Si)/s, when applied under recommended oper-

ating conditions. To ensure validity of all specified perfor-

mance parameters before, during, and after radiation

(timing degradation during transient pulse radiation (tim-

ing degradation during transient pulse radiation is ≤10%),

it is suggested that stiffening capacitance be placed near

the package VDD and VSS, with a maximum inductance

between the package (chip) and stiffening capacitor of

0.7 nH per part. If there are no operate-through or valid

stored data requirements, typical circuit board mounted

de-coupling capacitors are recommended.

This FIFO configuration has a soft error rate (SER) perfor-

mance of <1x10^-10upsets/bit-day, under recommended

operating conditions. This hardness level is defined by the

Adams 90% worst case cosmic ray environment.

Latchup

This FIFO configuration will not latch up due to any of the

above radiation exposure conditions when applied under

recommended operating conditions. Fabrication with the

SIMOX substrate with its oxide isolation ensure latchup

immunity.

RADIATION-HARDNESS RATINGS (1)

Parameter

Total Dose

Units

Limits (2)

Test Conditions

≥1x10⁶

≥1x10⁹

≥1x10¹¹

<1x10^-10

≥1x10¹⁴

rad(SiO₂)

TA=25°C

Pulse width ≤50 ns

Transient Dose Rate Upset

Transient Dose Rate Survivability

Soft Error Rate

rad(Si)/s

Pulse width ≤50 ns, X-ray,

VDD=6.0 V, TA=25°C

rad(Si)/s

TA=125°C, Adams 90%

worst case environment

1 MeV equivalent energy,

Unbiased, TA=25°C

upsets/bit-day

Neutron Fluence

N/cm²

(1) Device will not latch up due to any of the specified radiation exposure conditions.

(2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55°C to 125°C.

4

HX6409/HX6218/HX6136

ABSOLUTE MAXIMUM RATINGS (1)

Rating

Max

7.0

Symbol

Min

Units

Parameter

VDD

Supply Voltage Range (2)

-0.5

V

VPIN

Voltage on Any Pin (2)

-0.5

-65

VDD+0.5

150

V

°C

TSTORE

TSOLDER

PD

Storage Temperature (Zero Bias)

Soldering Temperature (5 Seconds)

Maximum Power Dissipation (3)

DC or Average Output Current

ESD Input Protection Voltage (4)

Thermal Resistance (Jct-to-Case)

Junction Temperature

270

°C

2.5

W

IOUT

25

mA

V

VPROT

ΘJC

2000

5

°C/W

°C

TJ

175

(1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not

implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.

(2) Voltage referenced to VSS.

(3) FIFO power dissipation (IDDSB + IDDOP) plus FIFO output driver power dissipation due to external loading must not exceed this specification.

(4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab.

RECOMMENDED OPERATING CONDITIONS

Description

Parameter

Units

Symbol

Min

4.5

Typ

5.0

25

Max

5.5

VDD

TA

Supply Voltage (referenced to VSS)

Ambient Temperature

V

°C

V

-55

125

VPIN

Voltage on Any Pin (referenced to VSS)

-0.3

VDD+0.3

CAPACITANCE (1)

Worst Case

Min Max

Typical

(1)

Test Conditions

Units

Symbol

Parameter

CI

Input Capacitance

Output Capacitance

7

9

pF

VI=VDD or VSS, f=1 MHz

VIO=VDD or VSS, f=1 MHz

CO

(1) This parameter is tested during initial design characterization only.

DATA RETENTION CHARACTERISTICS

Worst Case (2)

Symbol

Parameter

Typical

(1)

Units

Test Conditions

Min

Max

NCS=VDR

VDR

IDR

Data Retention Voltage

Data Retention Current

2.5

V

VI=VDR or VSS

NCS=VDD=VDR

VI=VDR or VSS

500

µA

(1) Typical operating conditions: TA= 25°C, pre-radiation.

(2) Worst case operating conditions: TC= -55°C to +125°C, post total dose at 25°C.

5

HX6409/HX6218/HX6136

DC ELECTRICAL CHARACTERISTICS

Worst Case (1)

Symbol

Test Parameters

Min

0.7xVDD

2.2

Max

Units

Conditions

VIH

Input High Voltage

CMOS

TTL

—

V

VDD=5.5V

VIL

Input Low Voltage

CMOS

TTL

—

0.3xVDD

0.8

V

VDD=4.5V

VOH1

VOH2

VOL

II

High Output Voltage

Low Output Voltage

Input Leakage Current

3.5

VDD-0.4

—

VDD=4.5V

IOH=-4.0ma

—

V

VDD=4.5V

IOH=-100µa

0.4

V

VDD=4.5V

IOL=4.0ma

-1.0

+1.0

µA

VDD=5.5V

VIN=0V or VDD

TC=-55°C TO +125°C

IOZL

IOZH

Output OFF, High Z Current

-10.0

+10.0

µA

OE>VIH

,

VSS<VO<VDD

VIN=0V or VDD

CLK(s)=1 MHz

VIN=0V or VDD

CLK(s)=1 MHz

VIN=0V or VDD

CLK(s)=40MHz

VIN=0V or VDD

CLK(s)=40MHz

IDDSB

IDDOP

IDDSB

IDDOP

Standby Power Supply Current (2)

Operating Power Supply Current (2)

Standby Power Supply Current (2)

Operating Power Supply Current (2)

—

1

7

mA

40

280

(1) Worst case operating conditions: VDD =4.5 V to 5.5 V, TC=-55°C to +125°C, post total dose at 25°C.

(2) Standby current for the device includes the Read Clock (CKR) and Write Clock (CKW) only. Both the Read Enable (

) and Write Enable

ENR

(

) are disabled (

,

=Vdd). For operating currents,

and are enabled (=0.0 V) and data inputs are switching at one

ENW

ENR

half the clock speed between 0.0 V and VDD.

2.9 V

Valid high

output

+

-

Vref1

Vref2

249Ω

+

-

Valid low

output

DUT

output

Tester Equivalent Load Circuit

6

HX6409/HX6218/HX6136

AC TIMING CHARACTERISTICS (1)

Worst Cast (2)

—55•C to 125°C

Symbol

TCKW

TCKR

TCKH

TCKL

TA

Test Parameter

Min

24

34

24

14

10

—

2

Max

—

30

—

10

—

10

17

—

17

—

30

—

Units

ns

Write Clock Cycle

Read Clock Cycle

Clock High Read

Clock High Write

Clock Low

Data Access Time

TOH

Previous Output Data Hold After Rd High

Previous Flag Hold After Rd/Wr High

Data Set-UP

TFH

2

TSD

9

THD

Data Hold

4

TSEN

THEN

TOE

Enable Set-UP

8

Enable Hold

2

OE Low to Output Data Valid

OE Low to Output Data in Low Z

OE High to Output Data in High Z

Flag Delay

—

1

TOLZ

TOHZ

TFD

—

0

TSKEW1

TSKEW2

TPMR

TSCMR

TOHMR

TMRR

TMRF

TAMR

TSMRP

THMRP

TFTP

Opposite Clock after Clock (3)

Opposite Clock before Clock (4)

Master Reset Pulse Width (Low)

Last Valid Clock Low Set-up to Master Reset Low

Data Hold from Master Reset Low

Master Reset Recovery

25

0

2

8

Master Reset High to Flags Valid

Master Reset High to Data Outputs Low

Parity Program Mode—MR Low Set-up

Parity Program Mode—MR Low Hold

Parity Program Mode—Write HIGH to Read HIGH

Parity Program Mode—Data Access Time

Parity Program Mode—Data Hold Time from MR HIGH

—

34

24

34

—

4

TAP

TOHP

(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and

output timing reference levels shown in the Tester AC Timing characteristics Table, capacitive output loading C_L=50 pF. For C_L>50 pF,

derate access times by 0.02 ns/pF (typical).

(2) Worst case operating conditions: VDD=4.5V to 5.5V, TC= -55°C to +125°C, post total dose at 25°C.

(3) For flag updates, tskew1 is the minimum time an opposite clock can occur after a clock and still not be included in the current clock cycle.

At less that tskew1, inclusion of the opposite clock is arbitrary.

(4) For flag updates, tskew2 is the minimum time an opposite clock can occur before a clock and still be included in the current clock cycle. At

less than tskew2, inclusion of the opposite clock is arbitrary.

(5) Timing parameters are defined in Figures 1 through 6.

7

HX6409/HX6218/HX6136

AC TIMING WAVEFORMS

Tckw

Tckh

Tckl

CKW

Data

Enabled WR

Thd

Disabled WR

Then

Tsd

Tsen

Then

ENW

Flags

Tfh

Tfd

Figure 1. Write Timing

Tckw

Tckh

Tckl

CKR

Data

Enabled RD

Ta

Disabled RD

Toh

Tsen

Then

Tsen

Then

ENR

Flags

Tfh

Tfd

Figure 2. Read Timing

8

HX6409/HX6218/HX6136

Tpmr

MR

Tscmr

Tmrr

First

Write

CKW

ENW

CKR

Tmrr

ENR

Data

Tphmr

Tamr

All Data

Outputs Low

Valid Data

Tmrf

HF

Tmrf

Other

Flags

Figure 3. Master Reset Timing

NOTE: If ENW is held high during Master Reset, the parity is disabled.

Latent Cycle

Enable

Read

Enable

Read

Flag

Update

CKR

ENR

CKW

Tskew2

Tskew1

Enable

Write

ENW

HF

high

Tfd

Flags

Figure 4. Read Flag Update Timing

NOTE: When an empty condition occors, the empty flag is set. The performance of another read requires at

least one write, on read clock to reset the empty flag and then an enabled read clock.

9

HX6409/HX6218/HX6136

Latent Cycle

Flag

Update

Enable

Write

CKW

Write

Tskew2

ENW

Tskew1

Enable

Read

CKR

ENR

Tfd

Flags

Figure 5. Write Flag Update Timing

NOTE: When a full condition occurs, the full flag is set. The performance of another write requires at least one

read, one write clock to reset the full flag and then one enabled write clock.

Read M+1

CKR

Low

ENR

OE

Toe

Tohz

Valid Data Word M

Valid Data Word M+1

Data

Tolz

Figure 6. Output Enable Timing

Tsmrp

Thmrp

MR

Tckh

Tscmr

Parity

Write

Tmrr

First Write

CKW

ENW

Tftp

Tnd

Tsd

Parity

Word

Data In Last Word

Word

Thmrp

Tscmr

Tsmrp

Parity

Read

CKR

Tckh

ENR

Tamr

Tohmr

Tap

Tohp

Parity

Word

Data Out

Valid Data

Figure 7. Parity Programming Mode

10

HX6409/HX6218/HX6136

TESTER AC TIMING CHARACTERISTICS

TTL I/O Configuration

CMOS I/O Configuration

3 V

0 V

VDD-0.5 V

Input

Levels*

1.5 V

VDD/2

0.5 V

1.5 V

VDD/2

Output

Sense

Levels

VDD-0.4V

0.4 V

VDD-0.4V

High Z

0.4 V

3.4 V

2.4 V

3.4 V

High Z

2.4 V

High Z = 2.9V

* Input rise and fall times <1 ns/V

and are available per the applicable Standard Microcir-

cuits Drawing (SMD). QML devices offer ease of procure-

ment by eliminating the need to create detailed specifica-

tions and offer benefits of improved quality and cost

savings through standardization.

QUALITY AND RADIATION HARDNESS

ASSURANCE

Honeywellmaintainsahighlevelofproductintegritythrough

process control, utilizing statistical process control, a com-

plete “Total Quality Assurance System,” a computer data

baseprocessperformancetrackingsystemandaradiation

hardness assurance strategy.

RELIABILITY

Honeywellunderstandsthestringentreliabilityrequirements

for space and defense systems and has extensive experi-

ence in reliability testing on programs of this nature. This

experience is derived from comprehensive testing of VLSI

processes. Reliability attributes of the RICMOS^TMprocess

were characterized by testing specially designed irradiated

and non-irradiated test structures from which specific failure

mechanisms were evaluated. These specific mechanisms

included, but were not limited to, hot carriers, electromigra-

tionandtimedependentdielectricbreakdown.Thisdatawas

then used to make changes to the design models and

process to ensure more reliable products.

The radiation hardness assurance strategy starts with a

technology that is resistant to the effects of radiation.

Radiation hardness is assured on every wafer by irradiat-

ing test structures as well as SRAM product, and then

monitoring key parameters which are sensitive to ionizing

radiation. Conventional MIL-STD-883 TM 5005 Group E

testing, which includes total dose exposure with Cobalt 60,

may also be performed as required. This Total Quality

approach ensures our customers of a reliable product by

engineering in reliability, starting with process develop-

ment and continuing through product qualification and

screening.

In addition, the reliability of the RICMOS™ process and

product in a military environment was monitored by testing

irradiated and non-irradiated circuits in accelerated dy-

namic life test conditions. Packages are qualified for prod-

uct use after undergoing Group B & D testing as outlined

in MIL-STD-883, TM 5005, Class S. The product is quali-

fied by following a screening and testing flow to meet the

customer’s requirements. Quality conformance testing is

performed as an option on all production lots to ensure the

ongoing reliability of the product.

SCREENING LEVELS

Honeywell offers several levels of device screening to

meet your system needs. “Engineering Devices” are avail-

able with limited performance and screening for bread-

boarding and/or evaluation testing. Hi-Rel Level B and S

devices undergo additional screening per the require-

mentsofMIL-STD-883.AsaQMLsupplier,Honeywellalso

offers QML Class Q and V devices per MIL-PRF-38535

11

HX6409/HX6218/HX6136

Pin List for HX6409

1

Signal

VSS

Q0

7

Signal

Q5

13

Signal

QT/TQF

HF

19

20

21

22

23

24

Signal

ENR

CKW

ENW

MR

25

26

27

28

29

30

Signal

D6

31

Signal

D0

2

8

Q6

14

15

16

17

D5

32

VDD

3

Q1

9

Q7

EF

D4

4

Q2

10

11

Q8

VSS

D3

5

Q3

OE

VDD

CKR

D8

D2

6

Q4

12 EF_FAULT 18

D7

D1

Pin List for HX6218

1

Signal

CKR

ENR

CKW

ENW

MR

13

14

15

16

17

18

19

20

21

22

23

24

Signal

D17

D16

D15

D14

VDD

VSS

D13

D12

D11

D10

D9

25

26

27

28

29

30

31

32

33

34

35

36

Signal

VSS

D8

37

38

39

40

41

42

43

44

45

46

47

48

Signal

Q1

Signal

Q11

Q12

Q13

VDD

VSS

Q14

Q15

Q16

Q17

VDD

Signal

VSS

VDD

OE

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

2

Q2

3

D7

Q3

4

D6

Q4

64 EF_FAULT

5

D5

Q5

65

66

67

68

QF/TQF

HF

6

VDD

VSS

VDD

D4

Q6

7

D3

Q7

E?F

8

D2

Q8

VDD

9

D1

VSS

VDD

Q9

10

11

12

D0

VDD

Q0

VDD

Q10

12

HX6409/HX6218/HX6136

Pin List for HX6236

1

Signal

VSS

NC

23

24

25

26

27

28

Signal

CKW

NC

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

Signal

NC

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

Signal

VSS

NC

D8

89

Signal

Q2

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

Signal

Q19

Q20

NC

2

D25

NC

90

NC

3

NC

ENW

NC

91

Q3

4

NC

D24

VSS

VDD

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

D9

D7

92

NC

Q21

VDD

VSS

Q22

Q23

Q24

Q25

Q26

Q27

Q28

NC

5

OE

MR

D6

93

Q4

6

NC

NNC

NC

D5

94

Q5

7

EF_FAULT 29

95

Q6

8

QF/TQF

HF

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

NC

D4

96

Q7

9

NC

D3

97

Q8

10

11

12

13

14

15

16

17

18

19

20

21

22

NC

D2

98

NC

EF

VSS

VDD

D35

D34

D33

D32

D31

D30

D29

D28

D27

D26

99

VSS

VDD

Q9

NC

D1

100

101

102

103

104

105

106

107

108

109

110

NC

D0

Q10

Q11

Q12

Q13

Q14

Q15

Q16

Q17

Q18

NC

Q29

Q30

Q31

Q32

Q33

Q34

Q35

VDD

VSS

VDD

NC

VSS

VDD

NC

Q0

CKR

NC

Q1

ENR

NC

VDD

NC

13

HX6409/HX6218/HX6136

PACKAGING

featurenon-conductiveceramictiebars. Thetiebarsallows

electrical testing of the device, while preserving the lead

integrityduringshippingandhandling,uptothepointoflead

forming and insertion.

TheFIFOisofferedina32-lead, 68-leadanda132-leadflat

pack, depending on the configuration. These packages are

constructed of multilayer ceramic (Al₂O₃) and features

internal power and ground planes. The flat packs also

PACKAGE DRAWING FOR 6409 (22018533-001)

Optional capacitors

in cutout

All dimensions in inches

VDD VSS VDD

A

b

C

D

e

0.135 ± 0.015

0.017 ± 0.002

0.004 to 0.009

0.820 ± 0.008

0.050 ± 0.005 [1]

0.600 ± 0.008

E

1

22018533-001

Z

b

(width)

E

E2 0.500 ± 0.008

E3 0.040 ref

TOP

VIEW

BOTTOM

VIEW

D

F

L

0.750 ± 0.005 [2]

0.295 min [3]

0.026 to 0.045

0.035 ± 0.010

0.080 ref

e

(pitch)

Q

S

U

V

W

X

Y

Z

S

U

0.380 ref

L

Y

X

W

0.050 ref

0.075 ref

Kovar

Lid [4]

Cutout

Area

Ceramic

Body

0.010 ref

Lead

Alloy 42

A

Q

C

0.135 ref

[1] BSC - Basic lead spacing between centers

[2] Where lead is brazed to package

[3] Parts delivered with leads unformed

[4] Lid connected to VSS

V

E2

E3

14

HX6409/HX6218/HX6136

PACKAGE DRAWING FOR 6218 (22019075-001)

D/E

F

A1

A

(4 Places)

All dimensions in inches

60

44

A

0.092 ± 0.010

0.080 ± 0.008

0.018 ± 0.002

0.010 ± 0.002

A1

b

61

43

c

D/E 0.950 ± 0.015

e

0.050 ± 0.005 (1)

0.800 ± 0.008 (1)

68 ref.

F

N

68

Terminal 1 ID Area

1

(1) BSC – Basic lead spacing between centers

e

9

27

10

26

b

c

(N Places)

PACKAGE DRAWING FOR 6136 (22018696-001)

HD/HE

D/E

A

e1

4 Places

A1

99

67

Dimensions in inches

min

max

100

66

0.109

0.063

0.047

0.009

0.008

0.958

A

0.091

0.057

0.036

0.005

0.004

0.942

L

A1

A2

b

4 Places

c

D/E

e

0.025 BSC

.800 BSC

e1

e

HD/HE 2.485

2.505

Ref.

L

N

0.575

132

34

Non-Conductive

Tie Bar: 4 Places

1

33

Index Corner &

Terminal No. 1 ID Area

b

c

N Places

A2

15

HX6409/HX6218/HX6136

ORDERING INFORMATION (1)

6409

H

X

D

S

H

C

SCREEN LEVEL

S=Level S

B=Level B

E=Engr Device (2)

PART NUMBER

6409 = 4K x 9

6218 = 2K x 18

6136 = 1K x 36

INPUT

BUFFER TYPE

C=CMOS Level

T=TTL Level

PROCESS

X=SOI

TOTAL DOSE

HARDNESS

PACKAGE DESIGNATION

D=68-Lead CQFP

SOURCE

H=HONEYWELL

R=1x10⁵rad(SiO₂)

F=3x10⁵rad(SiO₂)

H=1x10⁶rad(SiO₂)

N=No Level Guaranteed

F=132-Lead CQFP

T=32-Lead CQFP

(1) Orders may be faxed to 612-954-2051. Please contact our Customer Service Department at 612-954-2888 for further information.

(2) Engineering Device description: Parameters are tested from -55 to 125°C, 24 hr burn-in, no radiation guaranteed.

Contact Factory with other needs.

To learn more about Honeywell Solid State Electronics Center,

visit our web site at http://www.ssec.honeywell.com

Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability

arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

900157, Rev. D

2/99


型号：	HX6136FSRT
厂家：	ETC
描述：	x36 Synchronous FIFO X36同步FIFO\n 先进先出芯片
文件：	总16页 (文件大小：159K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HX6136FSRT [ETC]

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