HY57V56420HLT-H [ETC]
x4 SDRAM ; 由x4 SDRAM\n
| 型号： | HY57V56420HLT-H |
| 厂家： | 
ETC |
| 描述： | x4 SDRAM
|
| 文件： | 总13页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY57V56420H(L)T
4 Banks x 16M x 4Bit Synchronous DRAM
DESCRIPTION
The HY57V56420H is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large
memory density and high bandwidth. HY57V56420H is organized as 4banks of 16,777,216x4.
HY57V56420H is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage
levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or
write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•
•
•
Single 3.3±0.3V power supply
•
•
•
Auto refresh and self refresh
All device pins are compatible with LVTTL interface
8192 refresh cycles / 64ms
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
All inputs and outputs referenced to positive edge of system
clock
•
•
Data mask function by DQM
Internal four banks operation
•
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY57V56420HT-6
HY57V56420HT-K
HY57V56420HT-H
HY57V56420HT-8
HY57V56420HT-P
HY57V56420HT-S
HY57V56420HLT-6
HY57V56420HLT-K
HY57V56420HLT-H
HY57V56420HLT-8
HY57V56420HLT-P
HY57V56420HLT-S
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
Normal
4Banks x 16Mbits x 4
LVTTL
400mil 54pin TSOP II
Low power
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 1.3/Nov. 01
1
HY57V56420H(L)T
PIN CONFIGURATION
V
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DD
NC
DDQ
NC
2
NC
V
3
V
SSQ
NC
4
DQ0
5
DQ3
V
DDQ
V
6
SSQ
NC
NC
7
NC
NC
8
V
9
V
DDQ
NC
DQ1
SSQ
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
DQ2
V
V
DDQ
SSQ
NC
DD
NC
NC
54 pin TSOP II
400 mil x 875mil
0.8 mm pin pitch
V
V
SS
NC
DQM
CLK
CKE
A12
A11
A9
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A8
A7
A1
A2
A6
A5
A3
V
A4
V
DD
SS
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CLK
Clock
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CKE
CS
Clock Enable
Chip Select
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
BA0, BA1
A0 ~ A12
Bank Address
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA9, CA11
Auto-precharge flag : A10
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
RAS, CAS, WE
DQM
Data Input/Output Mask
Data Input/Output
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
DQ0 ~ DQ3
VDD/VSS
VDDQ/VSSQ
NC
Power Supply/Ground
Data Output Power/Ground
No Connection
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Rev. 1.3/Nov. 01
2
HY57V56420H(L)T
FUNCTIONAL BLOCK DIAGRAM
16Mbit x 4banks x 4 I/O Synchronous DRAM
Self refresh logic
& timer
Internal Row
counter
16Mx4 Bank3
16Mx4 Bank2
16Mx4 Bank1
16Mx4 Bank0
CLK
Row
Pre
Row active
CKE
CS
Decoders
RAS
CAS
WE
DQ0
DQ1
DQ2
DQ3
Memory
Cell
refresh
Array
Column
Active
Column
Pre
DQM
Decoders
Y decoders
Column Add
Counter
Bank Select
A0
A1
Address
Registers
Burst
Counter
A12
BA0
BA1
CAS Latency
Pipe Line Control
Mode Registers
Data Out Control
Rev. 1.3/Nov. 01
3
HY57V56420H(L)T
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
°C
°C
V
Storage Temperature
TSTG
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
VIN, VOUT
VDD, VDDQ
IOS
V
mA
W
PD
1
Soldering Temperature Time
TSOLDER
260 10
°C Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
Input High Voltage
Input Low Voltage
VDD, VDDQ
VIH
3.0
2.0
3.3
3.0
0
3.6
VDDQ + 0.3
0.8
V
V
V
1
1,2
1,3
VIL
VSSQ - 2.0
Note :
1.All voltages are referenced to VSS = 0V
2.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration
3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration
AC OPERATING CONDITION (TA=0 to 70°C, VDD=3.3 ± 0.3V, VSS=0V)
Parameter
Symbol
Value
Unit
Note
AC Input High / Low Level Voltage
VIH / VIL
Vtrip
2.4/0.4
1.4
1
V
V
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
tR / tF
Voutref
CL
ns
V
Output Timing Measurement Reference Level
Output Load Capacitance for Access Time Measurement
1.4
50
pF
1
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
Rev. 1.3/Nov. 01
4
HY57V56420H(L)T
CAPACITANCE (TA=25°C, f=1MHz)
-6/K/H
Max
-8/P/S
Unit
Parameter
Pin
Symbol
Min
Min
Max
Input capacitance
CLK
CI1
CI2
2.5
2.5
3.5
3.8
2.5
2.5
4.0
5.0
pF
pF
A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS,
WE, DQM
Data input / output capacitance
DQ0 ~ DQ3
CI/O
4.0
6.5
4.0
6.5
pF
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250 Ω
Output
Output
50pF
50pF
DC Output Load Circuit
AC Output Load Circuit
DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)
Parameter
Symbol
Min.
Max
Unit
Note
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
ILI
-1
-1
2.4
-
1
1
uA
uA
V
1
2
ILO
VOH
VOL
-
IOH = -4mA
IOL = +4mA
0.4
V
Note :
1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2.DOUT is disabled, VOUT=0 to 3.6V
Rev. 1.3/Nov. 01
5
HY57V56420H(L)T
DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Speed
Parameter
Symbol
Test Condition
Unit Note
-6
-K
-H
-8
-P
-S
Burst length=1, One bank active
Operating Current
IDD1
130
120
120
120
110
110
mA
mA
1
tRC ≥ tRC(min), IOL=0mA
IDD2P
CKE ≤ VIL(max), tCK = min
CKE ≤ VIL(max), tCK = ∞
2
2
Precharge Standby Current
in Power Down Mode
IDD2PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD2N
20
15
Precharge Standby Current
in Non Power Down Mode
mA
mA
mA
mA
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
IDD2NS
IDD3P
CKE ≤ VIL(max), tCK = min
CKE ≤ VIL(max), tCK = ∞
5
5
Active Standby Current
in Power Down Mode
IDD3PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min
Input signals are changed one time during
2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD3N
30
20
Active Standby Current
in Non Power Down Mode
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
IDD3NS
CL=3
150
120
240
140
130
220
130
120
220
130
120
210
120
120
200
120
110
200
tCK ≥ tCK(min), IOL=0mA
Burst Mode Operating Current IDD4
1
All banks active
CL=2
Auto Refresh Current
Self Refresh Current
IDD5
IDD6
tRRC ≥ tRRC(min), All banks active
mA
mA
mA
2
3
4
3
CKE ≤ 0.2V
1.5
Note :
1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V56420HT-6/K/H/8/P/S/10
4.HY57V56420HLT-6/K/H/8/P/S/10
Rev. 1.3/Nov. 01
6
HY57V56420H(L)T
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-6
-K
-H
-8
-P
-S
Parameter
Symbol
Unit
Note
Min
6
Max
Min
7.5
10
2.5
2.5
-
Max
Min
7.5
10
2.5
2.5
-
Max
Min
8
Max
Min
10
10
3
Max
Min
10
12
3
Max
CAS Latency = 3 tCK3
CAS Latency = 2 tCK2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
System clock
cycle time
1000
1000
1000
1000
1000
1000
10
2.5
2.5
-
10
3
Clock high pulse width
Clock low pulse width
tCHW
tCLW
-
-
-
-
-
-
-
-
-
1
1
-
-
-
3
3
3
CAS Latency = 3 tAC3
CAS Latency = 2 tAC2
tOH
5.4
5.4
5.4
-
6
6
-
-
6
6
-
-
6
6
-
Access time from
clock
2
-
6
-
6
-
6
-
-
-
Data-out hold time
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2
-
-
2.7
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
2
-
-
3
3
3
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
tDS
2
-
2
-
2
-
1
1
1
1
1
1
1
1
tDH
-
-
-
1
-
1
-
1
-
tAS
-
-
-
2
-
2
-
2
-
tAH
-
-
-
1
-
1
-
1
-
CKE setup time
tCKS
tCKH
tCS
-
-
-
2
-
2
-
2
-
CKE hold time
-
-
-
1
-
1
-
1
-
Command setup time
Command hold time
CLK to data output in low Z-time
-
-
-
2
-
2
-
2
-
tCH
-
-
-
1
-
1
-
1
-
tOLZ
-
-
-
2
-
2
-
2
-
CAS Latency = 3 tOHZ3
CAS Latency = 2 tOHZ2
2.7
3
5.4
6
2.7
3
5.4
6
2.7
3
5.4
6
3
6
6
3
6
6
3
6
6
CLK to data output
in high Z-time
3
3
3
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 1.3/Nov. 01
7
HY57V56420H(L)T
AC CHARACTERISTICS II
-6
-K
-H
-8
-P
-S
Parameter
Symbol
Unit
Note
Min
60
60
18
42
18
12
1
Max
Min
60
60
15
45
15
15
1
Max
Min
65
65
20
45
20
15
1
Max
Min
68
68
20
48
20
16
1
Max
Min
70
70
20
50
20
20
1
Max
Min
70
70
20
50
20
20
1
Max
Operation
Auto Refresh
tRC
-
-
-
-
-
-
ns
ns
RAS Cycle Time
tRRC
tRCD
tRAS
tRP
-
-
-
-
-
-
RAS to CAS Delay
RAS Active Time
-
-
-
-
-
-
ns
100K
100K
100K
100K
100K
100K
ns
RAS Precharge Time
-
-
-
-
-
-
-
-
-
-
-
-
ns
RAS to RAS Bank Active Delay
CAS to CAS Delay
tRRD
tCCD
tWTL
tDPL
tDAL
tDQZ
tDQM
tMRD
ns
-
-
-
-
-
-
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
ms
Write Command to Data-In Delay
Data-In to Precharge Command
Data-In to Active Command
DQM to Data-Out Hi-Z
0
-
0
-
0
-
0
-
0
-
0
-
2
-
2
-
2
-
2
-
2
-
2
-
5
-
5
-
5
-
5
-
5
-
5
-
2
-
2
-
2
-
2
-
2
-
2
-
DQM to Data-In Mask
0
-
0
-
0
-
0
-
0
-
0
-
MRS to New Command
2
-
2
-
2
-
2
-
2
-
2
-
CAS Latency = 3 tPROZ3
CAS Latency = 2 tPROZ2
3
-
3
-
3
-
3
-
3
-
3
-
Precharge to
Data Output Hi-Z
2
-
2
-
2
-
2
-
2
-
2
-
Power Down Exit Time
Self Refresh Exit Time
Refresh Time
tPDE
tSRE
tREF
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
-
64
-
64
-
64
-
64
-
64
-
64
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 1.3/Nov. 01
8
HY57V56420H(L)T
IBIS SPECIFICATION
IOH Characteristics (Pull-up)
66MHz and 100MHz Pull-up
100MHz
(Min)
100MHz
(Max)
66MHz
(Min)
Voltage
0
0.5
1
1.5
2
2.5
3
3.5
(V)
3.45
3.3
3.0
2.6
2.4
2.0
1.8
1.65
1.5
1.4
1.0
0
I(mA)
I(mA)
-2.4
I(mA)
0
-100
-200
-300
-400
-500
-600
-27.3
0
-74.1
-0.7
-7.5
-21.1
-34.1
-58.7
-67.3
-73
-129.2
-153.3
-197
-13.3
-27.5
-35.5
-41.1
-47.9
-52.4
-72.5
-93
-226.2
-248
Voltage (V)
-77.9
-80.8
-88.6
-93
-269.7
-284.3
-344.5
-502.4
I
I
OH Min (100MHz)
OH Min (66MHz)
I
OH Max (66 /100MHz)
IOL Characteristics (Pull-down)
66MHz and 100MHz Pull-down
100MHz
(Min)
100MHz
(Max)
66MHz
(Min)
Voltage
250
200
150
100
50
(V)
0
I(mA)
0
I(mA)
0
I(mA)
0
0.4
27.5
41.8
51.6
58.0
70.7
72.9
75.4
77.0
77.6
80.3
81.4
70.2
17.7
26.9
33.3
37.6
46.6
48.0
49.5
50.7
51.5
54.2
54.9
0.65
0.85
1.0
107.5
133.8
151.2
187.7
194.4
202.5
208.6
212.0
219.6
222.6
1.4
1.5
0
1.65
1.8
0
0.5
1
1.5
Voltage (V)
OL Min (100MHz)
OL Min (66MHz)
OL Max (100MHz)
2
2.5
3
3.5
1.95
3.0
I
I
I
3.45
Rev. 1.3/Nov. 01
9
HY57V56420H(L)T
VDD Clamp @ CLK, CKE, CS, DQM & DQ
Minimum VDD clamp current
(Referenced to VDD)
VDD (V)
I(mA)
20
15
10
5
0.0
0.2
0.4
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.23
1.34
3.02
5.06
7.35
9.83
12.48
15.30
18.31
0
0
1
2
3
Voltage
I (mA)
VSS Clamp @ CLK, CKE, CS, DQM & DQ
Minimum VSS clamp current
VSS (V)
I (mA)
-3
-2.5
-2
-1.5
-1
-0.5
0
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.9
-0.8
-0.7
-0.6
-0.4
-0.2
0.0
-57.23
-45.77
-38.26
-31.22
-24.58
-18.37
-12.56
-7.57
-3.37
-1.75
-0.58
-0.05
0.0
0
-10
-20
-30
-40
-50
-60
Voltage
I (mA)
0.0
0.0
0.0
Rev. 1.3/Nov. 01
10
HY57V56420H(L)T
DEVICE OPERATING OPTION TABLE
HY57V56420H(L)T-6
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
166MHz(6ns)
133MHz(7.5ns)
125MHz(8ns)
3CLKs
3CLKs
3CLKs
3CLKs
3CLKs
3CLKs
7CLKs
6CLKs
6CLKs
10CLKs
9CLKs
9CLKs
3CLKs
3CLKs
3CLKs
5.4ns
5.4ns
6ns
2.7ns
2.7ns
3ns
HY57V56420H(L)T-K
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
125MHz(8ns)
100MHz(10ns)
3CLKs
3CLKs
2CLKs
3CLKs
3CLKs
2CLKs
6CLKs
6CLKs
5CLKs
9CLKs
9CLKs
7CLKs
3CLKs
3CLKs
2CLKs
5.4ns
6ns
6ns
2.7ns
3ns
3ns
HY57V56420H(L)T-H
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
125MHz(8ns)
100MHz(10ns)
3CLKs
3CLKs
2CLKs
3CLKs
3CLKs
2CLKs
6CLKs
6CLKs
5CLKs
9CLKs
9CLKs
7CLKs
3CLKs
3CLKs
2CLKs
5.4ns
6ns
6ns
2.7ns
3ns
3ns
HY57V56420H(L)T-8
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
125MHz(8ns)
100MHz(10ns)
83MHz(12ns)
3CLKs
2CLKs
2CLKs
3CLKs
2CLKs
2CLKs
6CLKs
5CLKs
4CLKs
9CLKs
7CLKs
6CLKs
3CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
HY57V56420H(L)T-P
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
83MHz(12ns)
66MHz(15ns)
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
HY57V56420H(L)T-S
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
83MHz(12ns)
66MHz(15ns)
3CLKs
2CLKs
2CLKs
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
Rev. 1.3/Nov. 01
11
HY57V56420H(L)T
COMMAND TRUTH TABLE
A10/
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
ADDR
BA
Note
AP
Mode Register Set
H
H
H
H
X
L
H
L
L
X
H
L
L
X
H
H
L
X
H
H
X
OP code
No Operation
X
X
X
X
X
X
X
Bank Active
L
RA
V
V
Read
L
L
L
H
H
L
L
L
H
L
CA
CA
X
Read with Autoprecharge
Write
H
L
H
H
X
X
X
V
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Burst Stop
H
H
X
V
X
X
L
L
H
H
L
L
L
H
H
H
H
X
L
X
V
X
X
DQM
X
X
Auto Refresh
H
X
L
L
L
L
L
H
H
Burst-Read-Single-
WRITE
A9 Pin High
(Other Pins OP code)
H
H
L
X
X
Entry
L
H
L
L
X
H
X
H
X
H
X
V
L
X
H
X
H
X
H
X
V
H
X
H
X
H
X
H
X
V
1
X
Self Refresh
Exit
L
H
L
H
L
X
X
X
H
L
Entry
Precharge
power down
X
X
H
L
Exit
H
H
L
Entry
Clock
Suspend
Exit
H
L
L
X
X
H
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Rev. 1.3/Nov. 01
12
HY57V56420H(L)T
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
UNIT : mm(inch)
11.938(0.4700)
11.735(0.4620)
22.327(0.8790)
22.149(0.8720)
10.262(0.4040)
10.058(0.3960)
0.150(0.0059)
0.050(0.0020)
1.194(0.0470)
0.991(0.0390)
5deg
0deg
0.210(0.0083)
0.120(0.0047)
0.597(0.0235)
0.406(0.0160)
0.400(0.016)
0.80(0.0315)BSC
0.300(0.012)
Rev. 1.3/Nov. 01
13
相关型号：
©2020 ICPDF网 联系我们和版权申明