HY57V654020BLTC-10_技术文档

HY57V654020B

4 Banks x 4M x 4Bit Synchronous DRAM

DESCRIPTION

The Hynix HY57V654020B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which

require large memory density and high bandwidth. HY57V654020B is organized as 4banks of 4,194,304x4.

HY57V654020B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-

nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output

voltage levels are compatible with LVTTL.

Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by

a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read

or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or

write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)

FEATURES

•

Single 3.3±0.3V power supply

•

Auto refresh and self refresh

All device pins are compatible with LVTTL interface

4096 refresh cycles / 64ms

JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin

pitch

Programmable Burst Length and Burst Type

- 1, 2, 4, 8 or Full page for Sequential Burst

- 1, 2, 4 or 8 for Interleave Burst

•

All inputs and outputs referenced to positive edge of system

clock

•

Data mask function by DQM

Internal four banks operation

•

Programmable CAS Latency ; 2, 3 Clocks

ORDERING INFORMATION

Part No.

Clock Frequency

Power

Organization

Interface

Package

HY57V654020BTC-6

HY57V654020BTC-75

HY57V654020BTC-8

HY57V654020BTC-10P

HY57V654020BTC-10S

HY57V654020BTC-10

HY57V654020BLTC-6

HY57V654020BLTC-75

HY57V654020BLTC-8

HY57V654020BLTC-10P

HY57V654020BLTC-10S

HY57V654020BLTC-10

166MHz

133MHz

125MHz

100MHz

166MHz

133MHz

125MHz

100MHz

Normal

4Banks x 4Mbits x4

LVTTL

400mil 54pin TSOP II

Low power

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of

circuits described. No patent licenses are implied.

Rev. 1.7/Nov. 01

1

HY57V654020B

PIN CONFIGURATION

VDD

NC

1

2

3

4

5

6

7

8

9

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

VSS

NC

VDDQ

NC

VSSQ

NC

DQ0

VSSQ

NC

VDDQ

NC 10

DQ1 11

VSSQ 12

NC 13

VDD 14

NC 15

DQ3

VDDQ

NC

VSSQ

NC

DQ2

VDDQ

NC

VSS

NC

54pin TSOP II

400mil x 875mil

0.8mm pin pitch

/WE 16

/CAS 17

/RAS 18

/CS 19

BA0 20

BA1 21

A10/AP 22

A0 23

DQM

CLK

CKE

NC

A11

A9

A8

A7

A1 24

A6

A2 25

A5

A3 26

A4

VDD 27

VSS

PIN DESCRIPTION

PIN NAME

DESCRIPTION

The system clock input. All other inputs are registered to the SDRAM on the

rising edge of CLK

CLK

Clock

Controls internal clock signal and when deactivated, the SDRAM will be one

of the states among power down, suspend or self refresh

CKE

CS

Clock Enable

Chip Select

Enables or disables all inputs except CLK, CKE and DQM

Selects bank to be activated during RAS activity

Selects bank to be read/written during CAS activity

BA0, BA1

A0 ~ A11

Bank Address

Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9

Auto-precharge flag : A10

Address

Row Address Strobe,

Column Address Strobe,

Write Enable

RAS, CAS and WE define the operation

Refer function truth table for details

RAS, CAS, WE

DQM

Data Input/Output Mask

Data Input/Output

Controls output buffers in read mode and masks input data in write mode

Multiplexed data input / output pin

DQ0 ~ DQ3

VDD/VSS

VDDQ/VSSQ

NC

Power Supply/Ground

Data Output Power/Ground

No Connection

Power supply for internal circuits and input buffers

Power supply for output buffers

No connection

Rev. 1.7/Nov. 01

2

HY57V654020B

FUNCTIONAL BLOCK DIAGRAM

4Mbit x 4banks x 4 I/O Synchronous DRAM

Self refresh logic

& timer

Internal Row

counter

4Mx4 Bank3

4Mx4 Bank 2

4Mx4 Bank 1

4Mx4 Bank 0

CLK

Row

Pre

Row active

CKE

CS

Decoders

RAS

CAS

WE

DQ0

DQ1

DQ2

DQ3

Memory

Cell

refresh

Array

Column

Active

Column

Pre

DQM

Decoders

Y decoders

Column Add

Counter

Bank Select

A0

A1

Address

Registers

Burst

Counter

A11

BA0

BA1

CAS Latency

Pipe Line Control

Mode Registers

Data Out Control

Rev. 1.7/Nov. 01

3

HY57V654020B

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Rating

Unit

Ambient Temperature

TA

0 ~ 70

-55 ~ 125

-1.0 ~ 4.6

50

°C

Storage Temperature

TSTG

°C

Voltage on Any Pin relative to VSS

Voltage on VDD relative to VSS

Short Circuit Output Current

Power Dissipation

VIN, VOUT

V

VDD, VDDQ

IOS

V

mA

PD

1

W

Soldering Temperature Time

TSOLDER

260 10

°C Sec

Note : Operation at above absolute maximum rating can adversely affect device reliability

DC OPERATING CONDITION ^{(TA=0 to 70°C)}

Parameter

Symbol

Min

Typ.

Max

Unit

Note

Power Supply Voltage

Input High Voltage

Input Low Voltage

VDD, VDDQ

VIH

3.0

2.0

3.3

3.0

0

3.6

VDDQ + 2.0

0.8

V

1

1,2

1,3

VIL

VSSQ - 2.0

Note :

1.All voltages are referenced to VSS = 0V

2.VIH (max) is acceptable 5.6V AC pulse width with ≤3ns of duration

3.VIL (min) is acceptable -2.0V AC pulse width with ≤3ns of duration

AC OPERATING CONDITION ^{(TA=0 to 70°C, V}DD=3.3 ± 0.3V, VSS=0V)

Parameter

Symbol

Value

Unit

Note

AC Input High / Low Level Voltage

VIH / VIL

Vtrip

2.4/0.4

1.4

1

V

Input Timing Measurement Reference Level Voltage

Input Rise / Fall Time

tR / tF

Voutref

CL

ns

V

Output Timing Measurement Reference Level

Output Load Capacitance for Access Time Measurement

1.4

50

pF

1

Note :

1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)

For details, refer to AC/DC output circuit

Rev. 1.7/Nov. 01

4

HY57V654020B

CAPACITANCE ^{(TA=25°C, f=1MHz)}

Parameter

Symbol

Min

Max

Unit

Input capacitance

CLK

CI1

CI2

2

4

5

pF

A0 ~ A11, BA0, BA1, CKE, CS, RAS,

CAS, WE, DQM

2.5

Data input / output capacitance

DQ0 ~ DQ3

CI/O

2

6.5

pF

OUTPUT LOAD CIRCUIT

Vtt=1.4V

RT=250 Ω

Output

50pF

DC Output Load Circuit

AC Output Load Circuit

DC CHARACTERISTICS I ^{(TA=0 to 70°C, V}DD=3.3±0.3V)

Parameter

Symbol

Min.

Max

Unit

Note

Input Leakage Current

Output Leakage Current

Output High Voltage

Output Low Voltage

ILI

-1

2.4

-

1

uA

V

1

2

ILO

VOH

VOL

-

IOH = -4mA

IOL = +4mA

0.4

V

Note :

1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V

2.DOUT is disabled, VOUT=0 to 3.6V

Rev. 1.7/Nov. 01

5

HY57V654020B

DC CHARACTERISTICS II (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)

Speed

-8 -10P -10S

Parameter

Symbol

Test Condition

Unit Note

-6

-75

-10

Burst length=1, One bank active

Operating Current

IDD1

110

90

80

70

60

mA

1

tRC ≥ tRC(min), IOL=0mA

IDD2P

CKE ≤ VIL(max), tCK = min

CKE ≤ VIL(max), tCK = ∞

2

Precharge Standby Current

in Power Down Mode

IDD2PS

CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min

Input signals are changed one time during

2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V

IDD2N

15

mA

Precharge Standby Current

in Non Power Down Mode

CKE ≥ VIH(min), tCK = ∞

Input signals are stable.

IDD2NS

IDD3P

CKE ≤ VIL(max), tCK = min

CKE ≤ VIL(max), tCK = ∞

5

mA

Active Standby Current

in Power Down Mode

IDD3PS

CKE ≥ VIH(min), CS ≥ VIH(min), tCK = min

Input signals are changed one time during

2clks. All other pins ≥ VDD-0.2V or ≤ 0.2V

IDD3N

30

Active Standby Current

in Non Power Down Mode

CKE ≥ VIH(min), tCK = ∞

Input signals are stable.

IDD3NS

CL=3

140

90

120

90

110

90

mA

1

tCK ≥ tCK(min), IOL=0mA

Burst Mode Operating Current IDD4

All banks active

CL=2

Auto Refresh Current

Self Refresh Current

IDD5

IDD6

tRRC ≥ tRRC(min), All banks active

200

180

150

mA

uA

2

3

4

2

CKE ≤ 0.2V

500

Note :

1.IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open

2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II

3.HY57V654020BTC-6/75/8/10P/10S/10

4.HY57V654020BLTC-6/75/8/10P/10S/10

Rev. 1.7/Nov. 01

6

HY57V654020B

AC CHARACTERISTICS I ^{(AC operating conditions unless otherwise noted)}

-6

-75

-8

-10P

-10S

Max

-10

Parameter

Symbol

Unit

Note

Min

6

Max

Min

7.5

10

2.5

-

Max

Min

8

Max

Min

Max

Min

10

12

3

Min

10

12

3

Max

CAS Latency = 3 tCK3

CAS Latency = 2 tCK2

10

3

ns

System clock

cycle time

1000

10

2.5

-

10

3

Clock high pulse width

Clock low pulse width

tCHW

tCLW

-

1

-

3

CAS Latency = 3 tAC3

CAS Latency = 2 tAC2

tOH

5.4

-

6

-

6

-

6

-

8

-

Access time from

clock

2

-

6

-

6

-

Data-out hold time

2.7

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

1

-

2.7

1.5

0.8

1.5

0.8

1.5

0.8

1.5

0.8

1

-

3

2

1

2

1

2

1

2

1

3

2

1

2

1

2

1

2

1

3

Data-Input setup time

Data-Input hold time

Address setup time

Address hold time

tDS

-

2

-

3

-

1

tDH

-

1

-

1

-

tAS

-

2

-

3

-

tAH

-

1

-

1

-

CKE setup time

tCKS

tCKH

tCS

-

2

-

3

-

CKE hold time

-

1

-

1

-

Command setup time

Command hold time

CLK to data output in low Z-time

-

2

-

3

-

tCH

tOLZ

-

1

-

1

-

1

-

1

-

CAS Latency = 3 tOHZ3

CAS Latency = 2 tOHZ2

2.7

3

5.4

6

2.7

3

5.4

6

3

6

3

8

CLK to data output

in high Z-time

3

Note :

1.Assume tR / tF (input rise and fall time ) is 1ns

2.Access times to be measured with input signals of 1v/ns edge rate

Rev. 1.7/Nov. 01

7

HY57V654020B

AC CHARACTERISTICS II

-6

-75

-8

-10P

Max

-10S

Max

-10

Parameter

Symbol

Unit

Note

Min

60

18

42

18

12

1

Max

Min

65

20

45

20

15

1

Max

Min

68

20

48

20

16

1

Max

Min

70

20

50

20

1

Min

70

20

50

20

1

Min

80

96

30

50

30

20

1

Max

Operation

Auto Refresh

tRC

-

ns

RAS Cycle Time

tRRC

tRCD

tRAS

tRP

-

RAS to CAS Delay

RAS Active Time

-

ns

100K

ns

RAS Precharge Time

-

ns

RAS to RAS Bank Active Delay

CAS to CAS Delay

tRRD

tCCD

tWTL

tDPL

tDAL

tDQZ

tDQM

tMRD

ns

-

CLK

ms

Write Command to Data-In Delay

Data-In to Precharge Command

Data-In to Active Command

DQM to Data-Out Hi-Z

0

-

0

-

0

-

0

-

0

-

0

-

2

-

2

-

2

-

1

-

1

-

1

-

5

-

5

-

5

-

3

-

3

-

4

-

2

-

2

-

2

-

2

-

2

-

2

-

DQM to Data-In Mask

0

-

0

-

0

-

0

-

0

-

0

-

MRS to New Command

2

-

2

-

2

-

2

-

2

-

2

-

CAS Latency = 3 tPROZ3

CAS Latency = 2 tPROZ2

3

-

3

-

3

-

3

-

3

-

3

-

Precharge to

Data Output Hi-Z

2

-

2

-

2

-

2

-

2

-

2

-

Power Down Exit Time

Self Refresh Exit Time

Refresh Time

tPDE

tSRE

tREF

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

1

-

64

-

64

-

64

-

64

-

64

-

64

Note :

1. A new command can be given tRRC after self refresh exit

Rev. 1.7/Nov. 01

8

HY57V654020B

IBIS SPECIFICATION

IOH Characteristics (Pull-up)

66MHz and 100MHz Pull-up

100MHz

(Min)

100MHz

(Max)

66MHz

(Min)

Voltage

0

0.5

1

1.5

2

2.5

3

3.5

(V)

3.45

3.3

3.0

2.6

2.4

2.0

1.8

1.65

1.5

1.4

1.0

0

I(mA)

-2.4

I(mA)

0

-100

-200

-300

-400

-500

-600

-27.3

0

-74.1

-0.7

-7.5

-21.1

-34.1

-58.7

-67.3

-73

-129.2

-153.3

-197

-13.3

-27.5

-35.5

-41.1

-47.9

-52.4

-72.5

-93

-226.2

-248

Voltage (V)

-77.9

-80.8

-88.6

-93

-269.7

-284.3

-344.5

-502.4

I

^OHMin (100MHz)

^OHMin (66MHz)

I

^OHMax (66 /100MHz)

IOL Characteristics (Pull-down)

66MHz and 100MHz Pull-down

100MHz

(Min)

100MHz

(Max)

66MHz

(Min)

Voltage

250

200

150

100

50

(V)

0

I(mA)

0

I(mA)

0

I(mA)

0

0.4

27.5

41.8

51.6

58.0

70.7

72.9

75.4

77.0

77.6

80.3

81.4

70.2

17.7

26.9

33.3

37.6

46.6

48.0

49.5

50.7

51.5

54.2

54.9

0.65

0.85

1.0

107.5

133.8

151.2

187.7

194.4

202.5

208.6

212.0

219.6

222.6

1.4

1.5

0

1.65

1.8

0

0.5

1

1.5

Voltage (V)

^OLMin (100MHz)

^OLMin (66MHz)

^OLMax (100MHz)

2

2.5

3

3.5

1.95

3.0

I

3.45

Rev. 1.7/Nov. 01

9

HY57V654020B

DEVICE OPERATING OPTION TABLE

HY57V654020B(L)TC-6

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

166MHz(6ns)

133MHz(7.5ns)

125MHz(8ns)

3CLKs

7CLKs

6CLKs

10CLKs

9CLKs

3CLKs

5.4ns

6ns

2.7ns

3ns

HY57V654020B(L)TC-75

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

133MHz(7.5ns)

125MHz(8ns)

100MHz(10ns)

3CLKs

2CLKs

3CLKs

2CLKs

6CLKs

5CLKs

9CLKs

7CLKs

3CLKs

2CLKs

5.4ns

6ns

2.7ns

3ns

HY57V654020B(L)TC-8

CAS Latency

3CLKs

tRCD

tRAS

tRC

tRP

tAC

tOH

125MHz(8ns)

100MHz(10ns)

83MHz(12ns)

3CLKs

2CLKs

6CLKs

5CLKs

4CLKs

9CLKs

7CLKs

6CLKs

3CLKs

2CLKs

6ns

3ns

2CLKs

HY57V654020B(L)TC-10P

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

100MHz(10ns)

83MHz(12ns)

66MHz(15ns)

2CLKs

5CLKs

4CLKs

7CLKs

6CLKs

2CLKs

6ns

3ns

HY57V654020B(L)TC-10S

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

100MHz(10ns)

83MHz(12ns)

66MHz(15ns)

3CLKs

2CLKs

5CLKs

4CLKs

7CLKs

6CLKs

2CLKs

6ns

3ns

HY57V654020B(L)TC-10

CAS Latency

tRCD

tRAS

tRC

tRP

tAC

tOH

100MHz(10.0ns)

83MHz(12.0ns)

66MHz(15.0ns)

3CLKs

2CLKs

3CLKs

2CLKs

5CLKs

4CLKs

8CLKs

6CLKs

3CLKs

2CLKs

8ns

3ns

Rev. 1.7/Nov. 01

10

HY57V654020B

COMMAND TRUTH TABLE

A10/

AP

ADDR

Command

CKEn-1

CKEn

CS

RAS

CAS

WE

DQM

BA

Note

Mode Register Set

H

X

L

H

L

X

H

L

X

H

L

X

H

X

OP code

X

No Operation

X

Bank Active

L

RA

V

Read

L

H

L

H

L

CA

X

Read with Autoprecharge

Write

H

L

H

X

V

Write with Autoprecharge

Precharge All Banks

Precharge selected Bank

Burst Stop

H

X

V

X

L

H

L

H

X

L

X

V

X

DQM

X

Auto Refresh

H

X

L

H

L

A9 Pin High

(Other Pins OP code)

Burst-READ-Single-WRITE

Entry

H

L

X

L

H

L

X

H

X

H

X

H

X

V

L

X

H

X

H

X

H

X

V

H

X

H

X

H

X

H

X

V

1

X

Self Refresh

Exit

L

H

L

H

L

X

H

L

Entry

Precharge

power down

X

H

L

Exit

H

L

Entry

Clock

Suspend

Exit

H

L

X

H

X

Note :

1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high

2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,

Opcode = Operand Code, NOP = No Operation

Rev. 1.7/Nov. 01

11

HY57V654020B

PACKAGE INFORMATION

400mil 54pin Thin Small Outline Package

UNIT : mm(inch)

11.938(0.4700)

11.735(0.4620)

22.327(0.8790)

22.149(0.8720)

10.262(0.4040)

10.058(0.3960)

0.150(0.0059)

0.050(0.0020)

1.194(0.0470)

0.991(0.0390)

5deg

0deg

0.210(0.0083)

0.120(0.0047)

0.597(0.0235)

0.406(0.0160)

0.400(0.016)

0.80(0.0315)BSC

0.300(0.012)

Rev. 1.7/Nov. 01

12


型号：	HY57V654020BLTC-10
厂家：	ETC
描述：	x4 SDRAM 由x4 SDRAM\n 动态存储器
文件：	总12页 (文件大小：147K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HY57V654020BLTC-10 [ETC]

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