HY628100ALT1-70 [ETC]
x8 SRAM ; X8 SRAM\n
| 型号： | HY628100ALT1-70 |
| 厂家： | 
ETC |
| 描述： | x8 SRAM
|
| 文件： | 总9页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY628100A Series
128Kx8bit CMOS SRAM
DESCRIPTION
FEATURES
The HY628100A is a high speed, low power and
1M bit CMOS Static Random Access Memory
organized as 131,072 words by 8bit. The
HY628100A uses high performance CMOS
process technology and designed for high speed
low power circuit technology. It is particulary well
suited for used in high density low power system
application. This device has a data retention
mode that guarantees data to remain valid at a
minimum power supply voltage of 2.0V.
·
·
·
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup(L/LL-part)
- 2.0V(min) data retention
Standard pin configuration
·
- 32pin 525mil SOP
- 32pin 8x20mm TSOP-I(Standard)
Product
No
HY628100A
Voltage
(V)
Speed
(ns)
55/70/85
Operation
Current(mA)
10
Standby Current(uA)
Temperature
(°C)
L
100
LL
20
5.0
1mA
0~70
Comment : 50ns is available with 30pF test load.
PIN CONNECTION
NC
A16
A14
A12
A7
Vcc
A15
CS2
/WE
A13
A8
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A11
A9
32
1
2
3
4
5
6
7
8
9
3
/CS1
DQ8
DQ7
DQ6
DQ5
DQ4
Vss
30
29
28
27
26
25
24
4
A13
/WE
CS2
A15
Vcc
NC
5
A6
6
A5
A9
7
A11
/OE
A10
/CS1
I/O8
I/O7
I/O6
I/O5
I/O4
A4
8
A3
9
A2
10
11
12
13
14
15
16
A16
DQ3
A1
11
12
13
14
15
16
22
21
20
19
18
17
A0
A12
A7
A6
A5
A4
DQ1
A0
I/O1
I/O2
I/O3
Vss
A1
A2
A3
SOP
TSOP-I(Standard)
PIN DESCRIPTION
BLOCK DIAGRAM
Pin Name
Pin Function
Chip Select 1
Chip Select 2
ROW DECODER
I/O1
A0
/CS1
CS2
/WE
Write Enable
Output Enable
Address Input
Data Input/Output
Power(5.0V)
Ground
MEMORY ARRAY
1024x1024
/OE
A0 ~ A16
I/O1 ~ I/O8
Vcc
A16
I/O8
/CS1
CS2
/OE
Vss
/WE
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.05 /Feb.99
Hyundai Semiconductor
HY628100A Series
ORDERING INFORMATION
Part No.
HY628100AG
Speed
55/70/85
Power
Temp
Package
SOP
SOP
SOP
HY628100ALG
HY628100ALLG
HY628100AT1
HY628100ALT1
HY628100ALLT1
55/70/85
55/70/85
55/70/85
55/70/85
55/70/85
L-part
LL-part
TSOP-I(Standard)
TSOP-I(Standard)
TSOP-I(Standard)
L-part
LL-part
Comment : 50ns is available with 30pF test load.
ABSOLUTE MAXIMUM RATING (1)
Symbol
Vcc, VIN, VOUT
TA
TSTG
PD
Parameter
Power Supply, Input/Output Voltage
Operating Temperature
Storage Temperature
Power Dissipation
Rating
-0.5 to 7.0
0 to 70
-65 to 125
1.0
Unit
V
°C
°C
W
IOUT
Data Output Current
50
mA
TSOLDER
Lead Soldering Temperature & Time
260 ·10
°C·sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliablity.
RECOMMENDED DC OPERATING CONDITION
TA=0°C to 700°C /-400°C to 85°C
Symbol
Vcc
Vss
VIH
VIL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5(1)
Typ.
5.0
0
-
-
Max.
5.5
0
Vcc+0.5
0.8
Unit
V
V
V
V
Note :
1. VIL = -3.0V for pulse width less than 30ns
TRUTH TABLE
/CS1 CS2
/WE /OE
MODE
Standby
I/O OPERATION
High-Z
High-Z
H
X
L
L
L
X
L
H
H
H
X
X
H
H
L
X
X
H
L
Output Disabled High-Z
Read
Write
Data Out
Data In
X
Note :
1. H=VIH, L=VIL, X=don't care
Rev.05 /Feb.99
2
HY628100A Series
DC ELECTRICAL CHARACTERISTICS
Vcc = 5.0V±10%, TA = 0°C to 70°C, unless otherwise specified
Symbol
ILI
ILO
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Vss < VIN < Vcc
Vss < VOUT < Vcc, /CS1 = VIH or
CS2 = VIL or /OE = VIH or /WE = VIL
/CS1 = VIL, CS2 = VIH,
VIN = VIH or VIL, II/O = 0mA
/CS1 = VIL CS2 = VIH,
Min Duty Cycle = 100%, II/O = 0mA
/CS1 = VIH or CS2 = VIL
Min. Typ. Max.
Unit
uA
uA
-1
-1
-
-
1
1
Icc
Operating Power Supply
Current
Average Operating
Current
TTL Standby Current
(TTL Input)
-
-
-
5
30
1
10
50
2
mA
mA
mA
ICC1
ISB
ISB1
Standby Current
(CMOS Input)
/CS1 > Vcc - 0.2V
-
-
-
-
2
1
-
1
100
20
0.4
-
mA
uA
uA
V
CS2 > 0.2V or
CS2 > Vcc - 0.2V
IOL = 2.1Ma
L
LL
VOL
VOH
Output Low Voltage
Output High Voltage
-
IOH = -1mA
2.4
-
V
Note : Typical values are at Vcc = 5.0V, TA = 25°C
AC CHARACTERISTICS
Vcc = 5.0V±10%, TA = 0°C to 70°C (Normal), unless otherwise specified
-55
-70
-85
#
Symbol
Parameter
Unit
Min.
Max. Min.
Max. Min
Max.
READ CYCLE
1
2
3
4
5
6
7
8
9
TRC
tAA*
Read Cycle Time
Address Access Time
55
-
-
-
10
5
0
0
10
-
70
-
-
-
10
5
0
0
10
-
85
-
-
-
10
5
0
0
10
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
55
25
-
70
70
35
-
85
85
45
-
tACS* Chip Select Access Time
TOE
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Out Disable to Output in High Z
Output Hold from Address Change
TCLZ
TOLZ
tCHZ
tOHZ
tOH
-
-
-
20
20
-
25
25
-
30
30
-
WRITE CYCLE
10 tWC
11 tCW
12 tAW
13 tAS
14 tWP
15 tWR
16 tWHZ
17 tDW
18 tDH
19 tOW
Write Cycle Time
55
45
45
0
40
0
0
25
0
-
-
-
-
-
-
20
-
-
-
70
60
60
0
50
0
0
30
0
-
-
-
-
-
-
25
-
-
-
85
70
70
0
55
0
0
35
0
-
-
-
-
-
-
30
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
5
5
5
Comment : tAA* and tACS* can meet 50ns with 30pF test load.
Rev.05 /Feb.99
3
HY628100A Series
AC TEST CONDITIONS
TA = 0°C to 70°C (Normal), unless otherwise specified
PARAMETER
Input Pulse Level
Value
0.8V to 2.4V
Input Rise and Fall Time
Input and Output Timing Reference Level
Output Load
5ns
1.5V
CL = 100pF + 1TTL Load
CL* = 30pF + 1TTL Load
Comment
* : Test load is 30pF for 50ns
AC TEST LOADS
TTL
CL(1)
Note : Including jig and scope capacitance
CAPACITANCE
Temp = 25°C, f= 1.0MHz
Symbol Parameter
Condition
VIN = 0V
VI/O = 0V
Max.
6
8
Unit
pF
pF
CIN
COUT
Input Capacitance
Output Capacitance
Note : These parameters are sampled and not 100% tested
Rev.05 /Feb.99
4
HY628100A Series
TIMING DIAGRAM
READ CYCLE 1
tRC
ADDR
OE
tAA
tOE
tOLZ
tOH
CS1
CS2
tACS
tCLZ
tOHZ
tCHZ
High-Z
Data
Out
Data Valid
Note(READ CYCLE):
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are
not referenced to output voltage levels
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given
device and from device to device.
3. /WE is high for the read cycle.
READ CYCLE 2
tRC
ADDR
tAA
tOH
tOH
Data
Out
Previous Data
Data Valid
Note(READ CYCLE):
1. /WE is high for the read cycle.
2. Device is continuously selected /CS1 = VIL, CS2 = VIH.
3. /OE =VIL.
Rev.05 /Feb.99
5
HY628100A Series
WRITE CYCLE 1(/WE Controlled)
tWC
ADDR
CS1
tAW
tWR
tCW
CS2
tWP
tAS
WE
tDW
tDH
Data Valid
Data In
tOHZ
tOW
High-Z
Data
Out
Data Undefined
WRITE CYCLE 2 (/CS1 Controlled)
tWC
ADDR
tWR
tAS
tCW
CS1
tAW
CS2
WE
tWP
tDH
tDW
Data Valid
Data In
High-Z
tCLZ
tWHZ
Data
Out
High-Z
High-Z
Rev.05 /Feb.99
6
HY628100A Series
WRITE CYCLE 3 (CS2 Controlled)
tWC
ADDR
tAS
tWR
tCW
CS1
tAW
CS2
WE
tWP
tDW
Data Valid
tDH
Data In
High-Z
tCLZ
tWHZ
High-Z
Data
High-Z
Out
Notes(WRITE CYCLE):
1. A write occurs during the overlap of a low /CS1, CS2 and low /WE. A write begines at the latest transition
among /CS1 going low, CS2 going high and /WE going low: A write ends at the earliest transition among
/CS1 going high, CS2 low and /WE going high. tWP is measured from the beginning of write to the end of
write.
.
2. tCW is measured from the later of /CS1 going low or CS2 going high to the end of write .
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends as
/CS1, or /WE going high, and tWR is applied in case a write ends at CS2 going low.
5. If /OE, CS2 and /WE are in the read mode during this period, the I/O pins are in the output low-Z state,
input of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS1 goes low simultaneously with /WE going low, the outputs remain in high impedance state.
7. Dout is the read data of the new address.
8. When /CS1 is low and CS2 is high, I/O pins are in the output state. The input signals in the opposite
phase leading to the outputs should not be applied.
Rev.05 /Feb.99
7
HY628100A Series
DATA RETENTION ELECTRIC CHARACTERISTIC
SYM
VDR
Parameter
Vcc for Data Retention
Test Condition
/CS1 > Vcc - 0.2V
Min
2.0
Typ
-
Max Unit
-
V
CS2 < 0.2V or
> Vcc - 0.2V,
Vss<VIN<Vcc
ICCDR
Data Retention Current
Vcc = 3.0V, /CS1>Vcc - 0.2V
CS2< 0.2V or > Vcc - 0.2V,
Vss<VIN<Vcc
L
LL
-
-
2
1
50
10
uA
uA
tCDR
tR
Chip Deselect to Data Retention Time
Operating Recovery Time
0
-
-
-
-
ns
ns
tRC(2)
Notes:
1. Typical values are under the condition of TA = 25°C.
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM 1
DATA RETENTION MODE
VCC
4.5V
tCDR
tR
2.2V
VDR
CS1>VCC-0.2V
CS1
VSS
DATA RETENTION TIMING DIAGRAM 2
DATA RETENTION MODE
VCC
4.5V
tR
tCDR
CS2
VDR
0.4V
VSS
CS2<0.2V
Rev.05 /Feb.99
8
HY628100A Series
RELIABILITY SPEC.
TEST MODE
TEST SPEC.
> 2000V
> 250V
ESD
HBM
MM
LATCH - UP
< -100mA
> 100mA
PACKAGE INFORMATION
32pin 525mil Small Outline Package(G)
UNIT : INCH(mm)
0.444(11.278)
0.438(11.125)
0.564(14.326)
0.810(20.574)
0.804(20.422)
0.546(13.868)
0.109(2.769)
0.0125(0.318)
0.099(2.515)
0.011(0.279)
0.0061(0.155)
0.004(0.102)
0 deg
8 deg
0.0425(1.080)
0.0235(0.597)
0.020(0.508)
0.014(0.356)
0.050(1.27)BSC
32pin 8x20mm Thin Small Outline Package Standard(T1)
#1
#32
UNIT : INCH(mm)
0.319(8.103)
0.311(7.900)
#17
#16
0.728(18.491)
0.720(18.288)
0.792(20.117)
0.784(19.914)
0.041(1.05)
0.037(0.95)
0.006(0.15)
0.002(0.05)
0.020(0.50)
BSC
0.008(0.21)
0.004(0.10)
0.025(0.64)
0.021(0.54)
0.011(0.27)
0.007(0.17)
Rev.05 /Feb.99
9
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