HYM5V64404ATQG-50 [ETC]
x64 EDO Page Mode DRAM Module ; 64 EDO页模式DRAM模块\n
| 型号： | HYM5V64404ATQG-50 |
| 厂家： | 
ETC |
| 描述： | x64 EDO Page Mode DRAM Module
|
| 文件： | 总11页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HYM5V64404A Q-Series
SO DIMM 4Mx64 bit CMOS DRAM MODULE
based on 4Mx16 DRAM, EDO, 3.3V, 4K/8K-Refresh
DESCRIPTION
The HYM5V64404A Q-Series is a 4Mx64-bit EDO mode CMOS DRAM module consisting of four 4Mx16
TSOP and one 2048-bit EEPROM on a 144 pin glass-epoxy printed circuit board. 0.1mF and 0.01mF
decoupling capacitors are mounted for each DRAM. The HYM5V64404AQ G-series is gold plated socket
type Dual In-line Memory Module suitable for easy interchange and addition of 32M byte memory.
FEATURES
·
Max. Active Power Dissipation
·
·
·
·
Single power supply of 3.3V ± 10%
Read-Modify-Write Capability
LVTTL compatible inputs and outputs
/CAS-before-/RAS, /RAS-only, Hidden
and Self refresh capability
Speed
50
8K
4K
1.58W
1.30W
2.02W
1.73W
60
·
Refresh cycles
·
Fast access time and cycle time
Part No.
Ref.
Speed
50
tRAC
50ns
60ns
tCAC
13ns
15ns
tHPC
25ns
30ns
HYM5V64404A Q-Series
HYM5V64434A Q-Series
4K
60
8K£ ª
£ /ªCAS-before-/RAS refresh, Hidden refresh
mode : 4K cycles / 64ms
·
·
·
144-Pin SO DIMM
Serial Presence Detect with EEPROM
Extended Data Out Operation
PIN DISCRIPTION
/RAS0
/CAS0-CAS7,
/WE
Row Address Strobe
Column Address Strobe
Write Enable
/OE
Output Enable
A0 -A12
A0 -A11
DQ0-DQ63
SCL
Address Input(8K Product)
Address Input(4K Product)
Data Input / Output
Serial PD Clock Input
Serial PD Data Input/Output
Power (+3.3V)
SDA
VCC
VSS
Ground
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev.04 / May.98
1998 Hyundai Semiconductor
HYM5V64404A Q-Series
PIN NAME
#
NAME
#
NAME
#
NAME
#
NAME
1
3
Vss
2
Vss
73
75
/OE
74
76
NC
DQ0
DQ1
DQ2
DQ3
Vcc
4
DQ32
DQ33
DQ34
DQ35
Vcc
Vss
Vss
5
6
77
NC
78
NC
7
8
79
NC
80
NC
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
81
Vcc
82
Vcc
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
NOTE :
83
DQ16
DQ17
DQ18
DQ19
Vss
84
DQ48
DQ49
DQ50
DQ51
Vss
DQ4
DQ5
DQ6
DQ7
Vss
DQ36
DQ37
DQ38
DQ39
Vss
85
86
87
88
89
90
91
92
93
DQ20
DQ21
DQ22
DQ23
Vcc
94
DQ52
DQ53
DQ54
DQ55
Vcc
/CAS0
/CAS1
Vcc
/CAS4
/CAS5
Vcc
95
96
97
98
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
A0
A3
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
A1
A4
A6
A7
A2
A5
A8
A11
Vss
Vss
Vss
Vss
DQ8
DQ9
DQ10
DQ11
Vcc
DQ40
DQ41
DQ42
DQ43
Vcc
A9
*A12
NC
A10
Vcc
Vcc
/CAS2
/CAS3
Vss
/CAS6
/CAS7
Vss
DQ12
DQ13
DQ14
DQ15
Vss
DQ44
DQ45
DQ46
DQ47
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ56
DQ57
DQ58
DQ59
Vcc
NC
NC
NC
NC
DQ28
DQ29
DQ30
DQ31
Vss
DQ60
DQ61
DQ62
DQ63
Vss
NC
NC
Vcc
Vcc
NC
NC
/WE
/RAS0
NC
NC
NC
SDA
Vcc
SCL
NC
Vcc
1.A12 is used for 8K-Refresh Product (HYM5V64434A Q-Series)
2
HYM5V64404A Q-Series
SERIAL PRESENCE DETECT
BYTE NUMBER
FUNCTION DESCRIBED
FUNCTION
VALUE
BYTE0
# of Byte Written into Serial Memory
at Module Manufacturer
128 Bytes
80h
BYTE1
BYTE2
BYTE3
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
256 Bytes
EDO
08h
02h
0Ch
0Dh
0Ah
09h
01h
40h
00h
01h
32h
3Ch
# of Row Addresses on This Assembly
12(4K Ref)
13(8K Ref)
10(4K Ref)
9(8K Ref)
1 Bank
64 Bits
-
BYTE4
# of Column Addresses on This Assembly
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
# of Module Banks on This Assembly
Data Width of This Assembly
Data Width of This Assembly(Continued)
Voltage Interface Standard of This Assembly
tRAC
LVTTL
50ns
60ns
BYTE10
tCAC
13ns
15ns
0Dh
0Fh
BYTE11
BYTE12
DIMM Configuration Type
Refresh Rate/Type
None
00h
00h
83h
4K/8K Ref, Normal(15.6ms)
4K/8K Ref, SL-Part
(31.25ms)
BYTE13
BYTE14
Primary DRAM Width
Error Checking DRAM Width
Undefined
x16
None
10h
00h
FFh
00h
02h
0Eh
BYTE15-61
BYTE62
BYTE63
Undefined
Initial
4K/8K Ref.
SPD Data Revision Code
Checksum for Byte 0-62
50ns
60ns
Normal(15.6ms)
4K/8K Ref.
SL-Part(31.25ms)
50ns
60ns
85h
91h
BYTE64-125
BYTE126-127
BYTE128-255
NOTE :
Manufacturer Data Field
Reserved
HYUNDAI MFD
-
Reserved
FFh
FFh
Undefined
Undefinded
1.Serial PD interface is standard IIC architecture.
2.Pull-up resistors(4.7K typical value) are required on all open collector bus devices(SCL and SDA).
3.Current sink capability on SCL and SDA (Iol max) must be at least 3mA to maintain a valid low level.
4.Checksum can be obtained by adding the binary values in Byte 0-62, and eliminate all but low order byte.
The low order byte would be the `Checksum`.
5.Refer to HYUNDAI Manufacturer Data SPEC for Byte 64-125.
3
HYM5V64404A Q-Series
BLOCK DIAGRAM
NOTE :
1.A12 is used for 8K-Refresh Product (HYM5V64434A Q-Series)
4
HYM5V64404A Q-Series
ABSOLUTE MAXIMUM RATINGS
SYMBOL
TA
PARAMETER
RATING
0 to 70
-55 to 150
-0.5 to 4.6
-0.5 to 4.6
50
UNIT
°C
Ambient Temperature
TSTG
Storage Temperature
°C
VIN, VOUT
VCC
Voltage on Any Pin relative to VSS
Voltage on VCC relative to VSS
Short Circuit Output Current
Power Dissipation
V
V
IOS
mA
W
PD
4
TSOLDER
Soldering Temperature·Time
260·10
°C·sec
Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(TA=0°C to 70°C )
SYMBOL
VCC
VIH
PARAMETER
MIN.
3.0
TYP.
MAX.
3.6
UNIT
Power Supply Voltage
Input High Voltage
Input Low Voltage
3.3
V
V
V
2.0
-
-
VCC+0.3
0.8
VIL
-0.3
Note: All voltages are referenced to VSS.
5
HYM5V64404A Q-Series
DC CHARACTERISTICS
(TA=0°C to 70°C , VCC=3.3V ± 10%, VSS=0V, unless otherwise noted.)
Symbol
Parameter
Test Conditions
Speed
Max. Current
Unit
8K Product 4K Product
ICC1
Operating Current
/RAS, /CAS Cycling
tRC=tRC (min.)
50
60
440
360
560
480
mA
ICC2
ICC3
LVTTL Standby
Current
4
4
mA
mA
/RAS = /CAS ³ VIH
other inputs ³ VSS
/RAS-only Refresh
Current
/RAS cycling
/CAS = VIH
50
60
440
360
560
480
tRC = tRC (min.)
ICC4
EDO Mode Current
/CAS cycling
/RAS = VIL
50
60
480
400
520
440
mA
tHPC = tHPC (min.)
ICC5
ICC6
CMOS Standby
Current
2
1.2
2
1.2
mA
mA
/RAS = /CAS ³ VCC
- 0.2V
SL-part
/CAS-before-/RAS
Refresh Current
tRC=tRC (min.)
50
60
440
360
560
480
ICC7
ICC8
Battery Back-up
Current (SL-part)
VIH = VCC - 0.2V, VIL = 0.2V
/CAS = CBR cycling or 0.2V
/OE & /WE = VIH = VCC - 0.2V
Address = Don`t care
2.2
1.8
2.2
1.8
mA
mA
DQs = Open, tRC=31.25 ms
Self Refresh
/RAS & /CAS = 0.2V
Current (SL-part)
Other pins are same as ICC7
Symbol
Parameter
Test Condition
Min.
Max
Unit
ILI
Input Leakage
current(Any Input)
-20
20
VSS £ VIN £ VCC + 0.3,
All other pins not under
test=VSS
mA
ILO
Output Leakage
-5
5
VSS £ VOUT £ VCC
mA
current(Any Input)
/RAS & /CAS at VIH
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 2.0mA
IOH = -2.0mA
-
0.4
-
V
V
2.4
NOTE
1. ICC1, ICC3, ICC4 and ICC6 dependent on output loading and cycle rates(tRC and tHPC).
2. Specified values are obtained with outputs unloaded.
3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while
/RAS=VIL. In ICC4, address can be changed maximum once while /CAS=VIH within one EDO mode cycle
time tHPC.
4. Only /RAS(max.) = 1ms is applied to refresh of battery backup but tRAS(max.) = 10ms is applied to
normal functional operation.
5. ICC5(max.) = 1.2mA, ICC7 and ICC8 are applied to SL-part only.
6. VOH = 2.0V, VOL = 0.8V at AC Functional Test.
6
HYM5V64404A Q-Series
AC CHARACTERISTICS
(TA=0°C to 70°C , Vcc=3.3V ± 10%, Vss=0V, unless otherwise noted.)
HYH5V64404A / HYM5V64434A
-50 -60 -70
MIN. MAX. MIN. MAX. MIN. MAX.
#
SYMBOL
PARAMETER
UNIT NOTE
1 tRC
Random Read or Write Cycle Time
Read-Modify-Write Cycle Time
EDO Mode Cycle Time
90
128
25
67
-
-
-
110
153
30
73
-
-
-
ns
2 tRWC
3 tHPC
ns
-
-
ns
4 tHPRWC EDO Mode Read-Modify-Write Cycle Time
-
-
ns
5 tRAC
6 tCAC
7 tAA
Access Time from /RAS
50
13
25
28
-
60
15
30
35
-
ns 4,5,10,11
Access Time from /CAS
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4,5,10
Access Time from Column Address
Access Time from /CAS Precharge
/CAS to Output Low Impedance
Output Buffer Turn-off delay from /CAS
Transition Time (Rise and Fall)
/RAS Precharge Time
-
-
4,5,11
8 tCPA
9 tCLZ
10 tCEZ
11 tT
-
-
4
3
3
3
3
13
50
-
3
13
50
-
2
2
4
12 tRP
30
50
40
60
13 tRAS
14 tRASP
15 tRSH
16 tCSH
17 tCAS
18 tRCD
19 tRAD
20 tCRP
21 tCP
/RAS Pulse Width
10K
10K
/RAS Pulse Width (EDO Mode)
/RAS Hold Time
50 100K 60 100K
13
40
8
-
15
45
10
20
15
5
-
/CAS Hold Time
-
-
/CAS Pulse Width
10K
10K
/RAS to /CAS Delay
17
13
5
37
25
-
45
30
-
10
11
/RAS to Column Address Delay Time
/CAS to /RAS Precharge Time
/CAS Precharge Time
8
-
10
0
-
22 tASR
23 tRAH
24 tASC
25 tCAH
26 tAR
Row Address Set-up Time
Row Address Hold Time
0
-
-
8
-
10
0
-
Column Address Set-up Time
Column Address Hold Time
Column Address Hold Time from /RAS
Column Address to /RAS Lead Time
Read Command Set-up Time
0
-
-
8
-
10
50
30
0
-
45
25
0
-
-
27 tRAL
28 tRCS
29 tRCH
-
-
-
-
Read Command Hold Time Referenced to
/CAS
0
-
0
-
7
7
30 tRRH
Read Command Hold Time Referenced to
/RAS
0
-
0
-
ns
31 tWCH
32 tWCR
33 tWP
Write Command Hold Time
10
40
8
-
-
-
-
-
10
45
10
15
10
-
-
-
-
-
ns
ns
ns
ns
ns
Write Command Hold Time from /RAS
Write Command Pulse Width
34 tRWL
35 tCWL
Write Command to /RAS Lead Time
Write Command to /CAS Lead Time
15
8
7
HYM5V64404A Q-Series
AC CHARACTERISTICS
(Continued)
HYH5V64404A / HYM5V64434A
-50 -60 -70
MIN. MAX. MIN. MAX. MIN. MAX.
#
SYMBOL
PARAMETER
UNIT NOTE
36 tDS
Data-In Set-up Time
0
10
40
-
-
0
10
45
-
-
ns
ns
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8
8
37 tDH
38 tDHR
39 tREF
Data-In Hold Time
-
-
Data-In Hold Time Referenced to /RAS
Refresh Period (8192 cycles)
Refresh Period (4096 cycles)
Refresh Period (SL-part)
-
-
64
64
12,13
-
64
-
64
12
-
128
-
128
12,13
40 tWCS
41 tCWD
42 tRWD
43 tAWD
44 tCSR
45 tCHR
46 tRPC
47 tCPT
48 tROH
49 tOEA
50 tOED
51 tOEZ
52 tOEH
Write Command Set-up Time
/CAS to /WE Delay Time
0
-
-
0
-
-
9
9
9
9
34
70
45
5
36
80
50
5
/RAS to /WE Delay Time
-
-
Column Address to /WE Delay Time
/CAS Set-up Time (CBR Cycle)
/CAS Hold Time (CBR Cycle)
/RAS to /CAS Precharge Time
/CAS Precharge Time (CBR Counter Test)
/RAS Hold Time Referenced to /OE
/OE Access Time
-
-
-
-
10
5
-
10
5
-
-
-
25
0
-
30
0
-
-
-
-
13
-
-
15
-
/OE to Data Delay
13
0
15
0
Output Buffer Turn-Off Delay Time from /OE
/OE Command Hold Time
10
-
15
-
6
9
13
45
30
10
10
15
54
35
10
10
10
10
100K
100
-50
5
-
--
53 tCPWD /WE Delay Time from /CAS Precharge
54 tRHCP /RAS Hold Time from /CAS Precharge
-
-
-
-
55 tWRP
56 tWRH
57 tWTS
58 tWTH
59 tRASS
60 tRPS
61 tCHS
62 tDOH
63 tREZ
64 tWEZ
65 tWED
66 tOEP
67 tWPE
68 tOCH
69 tCHO
/WE to /RAS Precharge Time(CBR cycle)
/WE to /RAS Hold Time (CBR cycle)
-
-
-
-
Write Command Set-up Time (Test Mode In) 10
-
-
Write Command Hold Time (Test Mode In)
/RAS Pulse Width (Self Refresh)
/RAS Precharge Time (Self Refresh)
/CAS Hold Time (Self Refresh)
Output Data Hold Time
10
100K
100
-50
5
-
-
-
-
-
-
-
-
-
-
Output Buffer Turn-off Delay from /RAS
Output Buffer Turn-off Delay from /WE
/WE to Data Delay Time
0
10
10
-
0
15
15
-
6
6
0
0
15
5
15
5
/OE Precharge Time
-
-
/WE Pulse Width (EDO cycle)
/OE to /CAS Hold Time
5
-
5
-
5
-
5
-
/CAS Hold Time to /OE
5
-
5
-
8
HYM5V64404A Q-Series
NOTE
1. An initial pause of 200ms is required after power-up followed by 8 /RAS cycles before proper device
operation is achieved. In case of using internal refresh counter, a minimum of 8 /CAS-before-/RAS
initialization cycles instead of 8 /RAS-only refresh cycles are required. The device should be carefully
initialized to be prevented from being entered into multi bit test mode during initialization.
2. If /RAS=Vss during power-up, the HYM5V64404A / HYM5V64434A could begin an active cycle.
This condition results in higher current than necessary current which is demanded from the power
supply during power-up.
3. It is recommended that /RAS and /CAS track with Vcc during power-up or be held at a valid VIH in order
to minimize the power-up current.
4. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are
measured between VIH(min.) and VIL(max.), and are assumed to be 5ns for all inputs.
5. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 1 TTL loads and 100pF.
6. tWEZ, tREZ, tCEZ and tOEZ define the time at which the output achieves the open circuit condition and
is not referenced to output voltage levels.
7. Either tRCH or tRRH must be satisfied for a read cycle.
8. These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in
Read-Modify-Write cycles and late Write cycle.
9. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only. If tWCS ³ tWCS(min.), the cycle is an early write cycle
and data out pin will remain open circuit (high impedance) through the entire cycle. If tRWD ³
tRWD(min.), tCWD ³ tCWD(min.), tAWD ³ tAWD(min.), and tCPWD ³ tCPWD(min.), the cycle is a
Read-Modify-Write cycle and data out will contain data read from the selected cell. If neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.
10.Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a
reference point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is
controlled by tCAC.
11.Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a
reference point only. If tRAD is greater than the specified tRAD(max.) limit, then access time is
controlled by tAA.
12.tREF(max.)=128ms is applied to SL-parts.
13.A burst of 8192 /RAS-only refresh cycles must be executed within 64ms (128ms for SL-parts) after
exiting self refresh. (CBR refresh & Hidden refresh : 4K cycle/64ms)
CAPACITANCE
(TA=0°C to 70°C , Vcc=3.3V ± 10%, Vss=0V, f = 1MHz, unless otherwise noted.)
SYMBOL
CIN1
PARAMETER
TYP.
MAX.
28
UNIT
pF
Input Capacitance (A0 - A12)
Input Capacitance (/WE, /OE)
Input Capacitance (/RAS0)
Input Capacitance (/CAS0 - /CAS7)
Data Input /Output Capacitance (DQs)
-
-
-
-
-
CIN2
38
pF
CIN3
38
pF
CIN4
14
pF
CDQ
14
pF
9
HYM5V64404A Q-Series
PACKAGE INFORMATION
10
HYM5V64404A Q-Series
ORDERING INFORMATION
Part Number
Ref.
Power
Normal
SL-part
Normal
SL-part
Package
TSOP
TSOP
TSOP
TSOP
HYM5V64404ATQG
HYM5V64404ASLTQG
HYM5V64434ATQG
HYM5V64434ASLTQG
4K
4K
8K
8K
11
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