HYM71V16655AT6 [ETC]
16Mx64|3.3V|8/P/S|x8|SDR SDRAM - Unbuffered DIMM 128MB ; 16Mx64 | 3.3V | 8 / P / S | X8 | SDR SDRAM - 无缓冲DIMM 128MB\n型号: | HYM71V16655AT6 |
厂家: | ETC |
描述: | 16Mx64|3.3V|8/P/S|x8|SDR SDRAM - Unbuffered DIMM 128MB
|
文件: | 总14页 (文件大小:233K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
16Mx64 bits
PC100 SDRAM Unbuffered DIMM
based on 8Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM71V16655AT6 Series
DESCRIPTION
The Hynix HYM71V16655AT6 Series are 16Mx64bits Synchronous DRAM Modules. The modules are composed of eight 8Mx16bits
CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package, one 2Kbit EEPROM in 8pin TSSOP package on a 168pin glass-epoxy
printed circuit board. Two 0.33uF and one 0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.
The Hynix HYM71V16655AT6 Series are Dual In-line Memory Modules suitable for easy interchange and addition of 128Mbytes
memory. The Hynix HYM71V16655AT6 Series are fully synchronous operation referenced to the positive edge of the clock . All inputs
and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-
width.
FEATURES
•
•
•
•
PC100MHz support
•
•
•
•
•
SDRAM internal banks : four banks
Module bank : two physical bank
Auto refresh and self refresh
168pin SDRAM Unbuffered DIMM
Serial Presence Detect with EEPROM
1.25” (31.75mm) Height PCB with double sided com-
ponents
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4 or 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
•
•
Single 3.3±0.3V power supply
All device pins are compatible with LVTTL interface
Data mask function by DQM
•
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Clock
Internal
Bank
SDRAM
Part No.
Ref.
Power
Plating
Frequency
Package
HYM71V16M655AT6-8
HYM71V16M655AT6-P
HYM71V16M655AT6-S
HYM71V16M655ALT6-8
HYM71V16M655ALT6-P
HYM71V16M655ALT6-S
125MHz
100MHz
100MHz
125MHz
100MHz
100MHz
Normal
4 Banks
4K
TSOP-II
Gold
Low Power
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 1.5/Dec. 01
2
PC100 SDRAM Unbuffered DIMM
HYM71V16655AT6 Series
PIN DESCRIPTION
PIN
PIN NAME
Clock Inputs
Clock Enable
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CK0~CK3
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CKE0, CKE1
/S0 ~ /S3
Chip Select
Enables or disables all inputs except CK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
BA0, BA1
SDRAM Bank Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA9
Auto-precharge flag : A10
A0 ~ A11
Address
Row Address Strobe, Column
Address Strobe, Write Enable
/RAS, /CAS and /WE define the operation
Refer function truth table for details
/RAS, /CAS, /WE
DQM0~DQM7
DQ0 ~ DQ63
VCC
Data Input/Output Mask
Data Input/Output
Power Supply (3.3V)
Ground
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Ground
VSS
SCL
SPD Clock Input
Serial Presence Detect Clock input
Serial Presence Detect Data input/output
Serial Presence Detect Address Input
Write Protect for Serial Presence Detect on DIMM
No connection
SDA
SPD Data Input/Output
SPD Address Input
Write Protect for SPD
No Connection
SA0~2
WP
NC
Rev. 1.5/Dec. 01
3
PC100 SDRAM Unbuffered DIMM
HYM71V16655AT6 Series
PIN ASSIGNMENTS
FRONT SIDE
BACK SIDE
FRONT SIDE
BACK SIDE
PIN NO.
NAME
PIN NO.
NAME
PIN NO.
NAME
PIN NO.
NAME
1
2
3
4
5
6
7
8
9
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
85
86
87
88
89
90
91
92
93
94
VSS
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VCC
CK0
VSS
NC
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
*CK2
NC
VSS
CKE0
/S3
DQM6
DQM7
NC
VCC
NC
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
/S2
DQM2
DQM3
NC
VCC
NC
NC
NC
NC
VSS
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
NC
10
NC
NC
NC
Architecture Key
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
NC
95
96
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
NC
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
NC
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
NC
NC
NC
NC
NC
VSS
NC
NC
VSS
NC
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
CK1
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
*CK3
NC
NC
NC
VCC
/WE
DQM0
DQM1
/S0
NC
VSS
A0
A2
A4
A6
A8
VCC
/CAS
DQM4
DQM5
/S1
/RAS
VSS
A1
A3
A5
A7
A9
A10/AP
BA1
VCC
BA0
A11
VCC
NC
WP
SDA
SCL
VCC
SA0
SA1
SA2
VCC
Voltage Key
Note : * CK2 and CK3 are connected with termination R/C (Refer to the block diagram)
Rev. 1.5/Dec. 01
4
PC100 SDRAM Unbuffered DIMM
HYM71V16655AT6 Series
BLOCK DIAGRAM
CK2
CK3
Note : 1. The serial resistor values of DQs are 10ohms
Rev. 1.5/Dec. 01
5
PC100 SDRAM Unbuffered DIMM
HYM71V16655AT6 Series
SERIAL PRESENCE DETECT
FUNCTION
VALUE
BYTE
FUNCTION
NOTE
NUMBER
DESCRIPTION
-8
-P
-S
-8
-P
-S
# of Bytes Written into Serial Memory at Module
Manufacturer
BYTE0
128 Bytes
80h
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
BYTE10
BYTE11
Total # of Bytes of SPD Memory Device
256 Bytes
SDRAM
12
08h
04h
0Ch
09h
02h
40h
00h
01h
A0h
60h
00h
Fundamental Memory Type
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
1
9
2 Bank
64 Bits
-
Data Width of This Assembly (Continued)
Voltage Interface Standard of This Assembly
SDRAM Cycle Time @/CAS Latency=3
Access Time from Clock @/CAS Latency=3
DIMM Configuration Type
LVTTL
10ns
8ns
6ns
10ns
6ns
80h
60h
A0h
60h
6ns
None
15.625us
BYTE12
Refresh Rate/Type
80h
/ Self Refresh Supported
BYTE13
BYTE14
Primary SDRAM Width
x16
10h
00h
Error Checking SDRAM Width
None
Minimum Clock Delay Back to Back Random Column
BYTE15
tCCD = 1 CLK
01h
Address
BYTE16
BYTE17
BYTE18
BYTE19
BYTE20
BYTE21
Burst Lenth Supported
1,2,4,8,Full Page
4 Banks
8Fh
04h
06h
01h
01h
00h
2
# of Banks on Each SDRAM Device
SDRAM Device Attributes, /CAS Lataency
SDRAM Device Attributes, /CS Lataency
SDRAM Device Attributes, /WE Lataency
SDRAM Module Attributes
/CAS Latency=2,3
/CS Latency=0
/WE Latency=0
Neither Buffered nor Registered
+/- 10% voltage tolerence, Burst Read
Single Bit Write, Precharge All, Auto
Precharge, Early RAS Precharge
BYTE22
SDRAM Device Attributes, General
0Eh
BYTE23
BYTE24
BYTE25
BYTE26
BYTE27
BYTE28
BYTE29
BYTE30
BYTE31
BYTE32
BYTE33
BYTE34
BYTE35
SDRAM Cycle Time @/CAS Latency=2
Access Time from Clock @/CAS Latency=2
SDRAM Cycle Time @/CAS Latency=1
Access Time from Clock @/CAS Latency=1
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active Delay (tRRD)
Minimum /RAS to /CAS Delay (tRCD)
Minimum /RAS Pulse Width (tRAS)
Module Bank Density
8ns
6ns
-
10ns
6ns
-
12ns
6ns
-
A0h
60h
00h
00h
14h
10h
14h
30h
A0h
60h
00h
00h
14h
14h
14h
32h
10h
20h
10h
20h
10h
C0h
60h
00h
00h
14h
14h
14h
32h
-
-
-
20ns
16ns
20ns
48ns
20ns
20ns
20ns
50ns
64MB
2ns
1ns
2ns
1ns
20ns
20ns
20ns
50ns
Command and Address Signal Input Setup Time
Command and Address Signal Input Hold Time
Data Signal Input Setup Time
2ns
1ns
2ns
1ns
2ns
1ns
2ns
1ns
20h
10h
20h
10h
20h
10h
20h
10h
Data Signal Input Hold Time
BYTE36
Superset Information (may be used in future)
-
00h
~61
BYTE62
BYTE63
BYTE64
SPD Revision
Intel SPD 1.2B
12h
0Eh
ADh
3, 8
Checksum for Byte 0~62
Manufacturer JEDEC ID Code
-
E8h
2Eh
Hynix JEDED ID
BYTE65
....Manufacturer JEDEC ID Code
Unused
FFh
~71
HSI (Korea Area)
0*h
1*h
2*h
3*h
4*h
5*h
HSA (United States Area)
HSE (Europe Area)
HSJ (Japan Area)
Singapore
BYTE72
Manufacturing Location
10
ASIA Area
Rev. 1.5/Dec. 01
6
PC100 SDRAM Unbuffered DIMM
HYM71V16655AT6 Series
Continued
FUNCTION
VALUE
-P
BYTE
FUNCTION
NOTE
NUMBER
DESCRIPTION
-8
-P
-S
-8
-S
BYTE73
BYTE74
BYTE75
BYTE76
BYTE77
BYTE78
BYTE79
BYTE80
BYTE81
BYTE82
BYTE83
BYTE84
BYTE85
Manufacturer’s Part Number (Component)
Manufacturer’s Part Number (128Mb based)
Manufacturer’s Part Number (Voltage Interface)
Manufacturer’s Part Number (Memory Width)
....Manufacturer’s Part Number (Memory Width)
Manufacturer’s Part Number (Data Width)
....Manufacturer’s Part Number (Data Width)
Manufacturer’s Part Number (Refresh, SDRAM Bank)
Manufacturer’s Part Number (Generation)
Manufacturer’s Part Number (Package Type)
Manufacturer’s Part Number (Component Configuration)
Manufacturer’s Part Number (Hyphent)
7 (SDRAM)
37h
31h
56h
31h
36h
36h
35h
35h
41h
54h
36h
2Dh
50h
4, 5
4, 5
4, 5
4, 5
1
V (3.3V, LVTTL)
1
6
6
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
5
5 (4K Refresh, 4Banks)
A
T
6 (x16 based)
- (Hyphen)
P
Manufacturer’s Part Number (Min. Cycle Time)
8
S
38h
53h
BYTE86
Manufacturer’s Part Number
Blanks
20h
4, 5
~90
BYTE91
BYTE92
BYTE93
BYTE94
Revision Code (for Component)
....Revision Code (for PCB)
Manufacturing Date
Process Code
Process Code
Year
-
-
-
-
4, 6
4, 6
3, 6
3, 6
....Manufacturing Date
Work Week
BYTE95
Assembly Serial Number
Serial Number
None
-
6
~98
BYTE99
~125
Manufacturer Specific Data (may be used in future)
00h
BYTE126
System Frequency Support
100MHz
64h
FFh
7, 8
7, 8
BYTE127
Intel Specification Details for 100MHz Support
Refer to Note7
FFh
FDh
BYTE128
~256
Unused Storage Locations
-
00h
Note :
1. The bank address is excluded
2. 1, 2, 4, 8 for Interleave Burst Type
3. BCD adopted
4. ASCII adopted
5. Basically Hynix writes Part No. except for ‘HYM’ in Byte 73~90 to use the limited 18 bytes from byte 73 to byte 90
6. Not fixed but dependent
7. CK0, CK1 connected to DIMM, TBD junction temp, CL2(3) support, Intel defined Concurrent Auto Precharge support
8. Refer to Intel SPD Specification 1.2B
9. In the case of L-Part, character ‘L’ will be added between byte 81 and byte 82.
10. Refer to HSI Web site.
Rev. 1.5/Dec. 01
7
PC100 SDRAM Unbuffered DIMM
HYM71V16655AT6 Series
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
-55 ~ 125
-1.0 ~ 4.6
-1.0 ~ 4.6
50
°C
Storage Temperature
TSTG
°C
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Short Circuit Output Current
Power Dissipation
VIN, VOUT
V
VDD, VDDQ
IOS
V
mA
PD
8
W
Soldering Temperature Time
TSOLDER
260 10
°C Sec
Note : Operation at above absolute maximum rating can adversely affect device reliability.
DC OPERATING CONDITION (TA=0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
Power Supply Voltage
Input High voltage
Input Low voltage
VDD, VDDQ
VIH
3.0
2.0
3.3
3.0
0
3.6
VDDQ + 0.3
0.8
V
V
V
1
1,2
1,3
VIL
-0.3
Note :
1.All voltages are referenced to VSS = 0V
2.VIH(max) is acceptable 5.6V AC pulse width with <=3ns of duration.
3.VIL(min) is acceptable -2.0V AC pulse width with <=3ns of duration.
AC OPERATING TEST CONDITION (TA=0 to 70°C, VDD=3.3±0.3V, VSS=0V)
Parameter
Symbol
Value
Unit
Note
AC Input High / Low Level Voltage
VIH / VIL
Vtrip
2.4/0.4
1.4
1
V
V
Input Timing Measurement Reference Level Voltage
Input Rise / Fall Time
tR / tF
Voutref
CL
ns
V
Output Timing Measurement Reference Level Voltage
Output Load Capacitance for Access Time Measurement
1.4
50
pF
1
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (50pF). For details, refer to AC/DC output
load circuit
Rev. 1.5/Dec. 01
8
PC100 SDRAM Unbuffered DIMM
HYM71V16655AT6 Series
CAPACITANCE (TA=25°C, f=1MHz)
-8/P/S
Unit
Parameter
Pin
Symbol
Min
Max
CK0, CK1
CI1
CI2
CI3
CI4
CI5
CI6
CI/O
20
20
20
30
30
5
40
35
35
55
55
25
25
pF
pF
pF
pF
pF
pF
pF
CKE0, CKE1
/S0, /S1
Input Capacitance
A0~11, BA0, BA1
/RAS, /CAS, /WE
DQM0~DQM7
DQ0 ~ DQ63
Data Input / Output Capacitance
10
OUTPUT LOAD CIRCUIT
Vtt=1.4V
RT=250 Ω
Output
Output
50pF
50pF
DC Output Load Circuit
AC Output Load Circuit
Rev. 1.5/Dec. 01
9
PC100 SDRAM Unbuffered DIMM
HYM71V16655AT6 Series
DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)
Parameter
Symbol
Min.
Max
Unit
Note
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
ILI
-8
-1
2.4
-
8
1
uA
uA
V
1
2
ILO
VOH
VOL
-
IOH = -4mA
IOL = +4mA
0.4
V
Note :
1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2.DOUT is disabled, VOUT=0 to 3.6
DC CHARACTERISTICS II
Speed
Parameter
Symbol
Test Condition
Unit Note
-8
-P
-S
Burst length=1, One bank active
Operating Current
IDD1
800
800
800
mA
mA
1
tRC ≥ tRC(min), IOL=0mA
IDD2P
CKE ≤ VIL(max), tCK = 15ns
CKE ≤ VIL(max), tCK = ∞
16
16
Precharge Standby Current
in Power Down Mode
IDD2PS
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V
IDD2N
160
80
Precharge Standby Current
in Non Power Down Mode
mA
mA
mA
mA
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
IDD2NS
IDD3P
CKE ≤ VIL(max), tCK = 15ns
56
56
Active Standby Current
in Power Down Mode
IDD3PS CKE ≤ VIL(max), tCK = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
IDD3N
Input signals are changed one time during
320
320
Active Standby Current
in Non Power Down Mode
30ns. All other pins ≥ VDD-0.2V or ≤ 0.2V
CKE ≥ VIH(min), tCK = ∞
Input signals are stable.
IDD3NS
CL=3
880
800
800
800
1600
16
800
720
Burst Mode Operating
Current
tCK ≥ tCK(min), IOL=0mA
IDD4
IDD5
1
All banks active
CL=2
Auto Refresh Current
tRRC ≥ tRRC(min), All banks active
CKE ≤ 0.2V
mA
mA
2
3
Self Refresh Current
IDD6
Burst length=1, One bank active
tRC ≥ tRC(min), IOL=0mA
6.4
mA
4
Note :
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HYM71V16655AT6-8/P/S
4. HYM71V16655ALT6-8/P/S
Rev. 1.5/Dec. 01
10
PC100 SDRAM Unbuffered DIMM
HYM71V16655AT6 Series
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
-8
-P
-S
Parameter
Symbol
Unit
Note
Min
8
Max
Min
10
10
3
Max
Min
10
12
3
Max
CAS Latency = 3 tCK3
CAS Latency = 2 tCK2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
System Clock
Cycle Time
1000
1000
1000
10
3
Clock High Pulse Width
Clock Low Pulse Width
tCHW
tCLW
-
-
-
-
-
-
1
1
3
3
3
CAS Latency = 3 tAC3
CAS Latency = 2 tAC2
tOH
-
6
6
-
-
6
6
-
-
6
6
-
Access Time
From Clock
2
-
-
-
Data-Out Hold Time
3
3
3
Data-Input Setup Time
Data-Input Hold Time
Address Setup Time
Address Hold Time
tDS
2
-
2
-
2
-
1
1
1
1
1
1
1
1
tDH
tAS
1
-
1
-
1
-
2
-
2
-
2
-
tAH
1
-
1
-
1
-
CKE Setup Time
tCKS
tCKH
tCS
2
-
2
-
2
-
CKE Hold Time
1
-
1
-
1
-
Command Setup Time
Command Hold Time
CLK to Data Output in Low-Z Time
2
-
2
-
2
-
tCH
tOLZ
1
-
1
-
1
-
1
-
1
-
1
-
CAS Latency = 3 tOHZ3
CAS Latency = 2 tOHZ2
3
6
6
3
6
6
3
6
6
CLK to Data
Output in High-Z
Time
3
3
3
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Rev. 1.5/Dec. 01
11
PC100 SDRAM Unbuffered DIMM
HYM71V16655AT6 Series
AC CHARACTERISTICS II
-8
-P
-S
Parameter
Symbol
Unit
Note
Min
68
68
20
48
20
16
1
Max
Min
70
70
20
50
20
20
1
Max
Min
70
70
20
50
20
20
1
Max
Operation
Auto Refresh
tRC
-
-
-
ns
ns
RAS Cycle Time
tRRC
tRCD
tRAS
tRP
-
-
-
RAS to CAS Delay
RAS Active Time
-
-
-
ns
100K
100K
100K
ns
RAS Precharge Time
-
-
-
-
-
-
ns
RAS to RAS Bank Active Delay
CAS to CAS Delay
tRRD
tCCD
tWTL
tDPL
tDAL
tDQZ
tDQM
tMRD
ns
-
-
-
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
ms
Write Command to Data-In Delay
Data-In to Precharge Command
Data-In to Active Command
DQM to Data-Out Hi-Z
0
-
0
-
0
-
1
-
1
-
1
-
4
-
3
-
3
-
2
-
2
-
2
-
DQM to Data-In Mask
0
-
0
-
0
-
MRS to New Command
2
-
2
-
2
-
CAS Latency = 3 tPROZ3
CAS Latency = 2 tPROZ2
3
-
3
-
3
-
Precharge to Data
Output Hi-Z
2
-
2
-
2
-
Power Down Exit Time
Self Refresh Exit Time
Refresh Time
tPDE
tSRE
tREF
1
-
1
-
1
-
1
-
1
-
1
-
1
-
64
-
64
-
64
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 1.5/Dec. 01
12
PC100 SDRAM Unbuffered DIMM
HYM71V16655AT6 Series
DEVICE OPERATING OPTION TABLE
HYM71V16655A(L)T6-8
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
125MHz(8ns)
100MHz(10ns)
83MHz(12ns)
3CLKs
2CLKs
2CLKs
3CLKs
2CLKs
2CLKs
6CLKs
5CLKs
4CLKs
9CLKs
7CLKs
6CLKs
3CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
HYM71V16655A(L)T6-P
CAS Latency
2CLKs
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
83MHz(12ns)
66MHz(15ns)
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
2CLKs
2CLKs
HYM71V16655A(L)T6-S
CAS Latency
3CLKs
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
83MHz(12ns)
66MHz(15ns)
2CLKs
2CLKs
2CLKs
5CLKs
5CLKs
4CLKs
7CLKs
7CLKs
6CLKs
2CLKs
2CLKs
2CLKs
6ns
6ns
6ns
3ns
3ns
3ns
2CLKs
2CLKs
Rev. 1.5/Dec. 01
13
PC100 SDRAM Unbuffered DIMM
HYM71V16655AT6 Series
COMMAND TRUTH TABLE
A10/
ADDR
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA
Note
AP
Mode Register Set
H
X
L
H
L
L
X
H
L
L
X
H
H
L
X
H
H
X
OP code
No Operation
H
H
H
X
X
X
X
X
X
X
Bank Active
L
RA
V
V
Read
L
L
L
H
H
L
L
L
H
L
CA
CA
X
Read with Autoprecharge
Write
H
L
H
H
X
X
X
V
Write with Autoprecharge
Precharge All Banks
Precharge selected Bank
Burst Stop
H
H
X
V
X
X
L
L
H
H
L
L
L
H
H
H
H
X
L
X
V
X
X
DQM
X
X
Auto Refresh
H
X
L
L
L
L
L
H
L
A9 Pin High
(Other Pins OP code)
MRS
mode
Burst-Read-Single-WRITE
Entry
H
H
L
X
X
L
H
L
L
X
H
X
H
X
H
X
V
L
X
H
X
H
X
H
X
V
H
X
H
X
H
X
H
X
V
1
X
Self Refresh
Exit
L
H
L
H
L
X
X
X
H
L
Entry
Precharge
power down
X
X
H
L
Exit
H
H
L
Entry
Clock
Suspend
Exit
H
L
L
X
X
H
X
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don′t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
3. The burst read sigle write mode is entered by programming the Write burst mode bit (A9) in the mode register to a logic 1.
Rev. 1.5/Dec. 01
14
PC100 SDRAM Unbuffered DIMM
HYM71V16655AT6 Series
PACKAGE DEMENSION
Rev. 1.5/Dec. 01
15
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