HYS64V8301GU-8-C2 [ETC]
x64 SDRAM Module ; 64位SDRAM模块\n
| 型号： | HYS64V8301GU-8-C2 |
| 厂家： | 
ETC |
| 描述： | x64 SDRAM Module
|
| 文件： | 总12页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HYS 64V8301GU
SDRAM-Modules
3.3 V 8M × 64-Bit 1 Bank, 64MByte SDRAM Module
168-pin Unbuffered DIMM Modules
•
•
168 Pin unbuffered 8 Byte Dual-In-Line
SDRAM Modules for PC main memory
applications
•
Programmed Latencies:
Product Speed
CL
2
tRCD
2
tRP
2
-7
PC133
PC100-222, PC133-333 and PC133-222
versions
-7.5
-8
PC133
PC100
3
3
3
2
2
2
•
•
One bank 8M × 64 organization
Optimized for byte-write non-parity
applications
•
Programmable CAS Latency, Burst Length,
and Wrap Sequence
(Sequential & Interleave)
•
SDRAM Performance:
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh
Decoupling capacitors mounted on substrate
All inputs and outputs are LVTTL compatible
Serial Presence Detect with E2PROM
-7 /-7.5 -8
Unit
PC133 PC100
fCK Clock
Frequency
(max.)
133
100
MHz
ns
Utilizes four 8M × 16 SDRAMs in
TSOPII-54 packages with
4096 refresh cycles every 64 ms
tAC ClockAccess 5.4
6
Time
•
Single 3.3 V (± 0.3 V) power supply
•
133.35 mm × 29.21 mm × 3.00 mm card size
with gold contact pads.
(JEDEC MO-161)
The HYS 64V8301GU is an industry standard 168-pin 8-byte Dual in-line Memory Module (DIMM)
which is organized as 8M × 64 in an one bank high speed memory arrays designed with 128 Mbit
Synchronous DRAMs for non-parity applications. The DIMMs use -7. speed sorted 8M × 16
SDRAM devices in TSOP54 packages to meet the PC133-222 requirements, -7.5 speed sort for
PC133-333 and and -8 parts for the standard PC100 applications. Decoupling capacitors are
mounted on the PC board. The PC board design is according to INTEL’s module specification.
The DIMMs have a serial presence detect, implemented with a serial E2PROM using the 2-pin I2C
protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are
available to the end user.
All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm
long footprint.
INFINEON Technologies
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9.01
HYS 64V8301GU
SDRAM-Modules
Ordering Information
Type
Code
Package
Description
Module
Height
HYS 64V8301GU-7-C2
PC133-222-520 L-DIM-168-32 133 MHz 8M × 64 1 bank
1.15”
1.15”
1.15”
SDRAM module
HYS 64V8301GU-7.5-C2 PC133-333-520 L-DIM-168-32 133 MHz 8M × 64 1 bank
SDRAM module
HYS 64V8301GU-8-C2
PC100-222-620 L-DIM-168-32 100 MHz 8M × 64 1 bank
SDRAM module
Note: All part numbers end with a place code (not shown), designating the die revision. Consult
factory for current revision. Example: HYS64V4300GU-8-C2, indicating Rev.C2 dies are
used for SDRAM components.
Pin Definitions and Functions
A0 - A11
Address Inputs
(RA0 ~ RA11 / CA0 ~ CA7,
CA10)
CLK0 - CLK3
Clock Input
BA0, BA1
Bank Select
DQMB0 - DQMB7 Data Mask
DQ0 - DQ63 Data Input/Output
CS0 , CS2
Chip Select
CB0 - CB7
Check Bits (x72
VDD
Power (+ 3.3 V)
organization only)
RAS
CAS
WE
Row Address Strobe
Column Address Strobe
Read/Write Input
VSS
Ground
SCL
Clock for Presence Detect
Serial Data Out for Pres. Detect
No Connection
SDA
CKE0
Clock Enable
N.C./DU
Address Format
Part Number
Rows Columns Bank Select Refresh
Period
64 ms
Interval
8M × 64 HYS 64V8301GU 12
9
2
4k
15.6 µs
INFINEON Technologies
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HYS 64V8301GU
SDRAM-Modules
Pin Configuration
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
1
43
85
127
VSS
VSS
VSS
VSS
2
3
4
5
6
DQ0
DQ1
DQ2
DQ3
VDD
44
45
46
47
48
DU
86
87
88
89
90
DQ32
DQ33
DQ34
DQ35
VDD
128
129
130
131
132
CKE0
N.C.
CS2
DQMB2
DQMB3
DU
DQMB6
DQMB7
N.C.
7
DQ4
49
91
DQ36
133
VDD
VDD
8
DQ5
DQ6
DQ7
DQ8
VSS
50
51
52
53
54
N.C.
N.C.
N.C.
N.C.
VSS
92
93
94
95
96
DQ37
DQ38
DQ39
DQ40
VSS
134
135
136
137
138
N.C.
N.C.
CB6
CB7
VSS
9
10
11
12
13
14
15
16
17
DQ9
55
56
57
58
59
DQ16
DQ17
DQ18
DQ19
VDD
97
DQ41
DQ42
DQ43
DQ44
DQ45
139
140
141
142
143
DQ48
DQ49
DQ50
DQ51
VDD
DQ10
DQ11
DQ12
DQ13
98
99
100
101
18
60
DQ20
102
144
DQ52
VDD
VDD
19
20
21
22
DQ14
DQ15
N.C.
61
62
63
64
N.C.
DU
103
104
105
106
DQ46
DQ47
N.C.
145
146
147
148
N.C.
DU
N.C.
VSS
N.C.
VSS
N.C.
N.C.
23
65
DQ21
107
149
DQ53
VSS
VSS
24
25
26
N.C.
N.C.
VDD
66
67
68
DQ22
DQ23
VSS
108
109
110
N.C.
N.C.
VDD
150
151
152
DQ54
DQ55
VSS
27
28
29
30
31
WE
69
70
71
72
73
DQ24
DQ25
DQ26
DQ27
VDD
111
112
113
114
115
CAS
153
154
155
156
157
DQ56
DQ57
DQ58
DQ59
VDD
DQMB0
DQMB1
CS0
DQMB4
DQMB5
N.C.
DU
RAS
32
74
DQ28
116
158
DQ60
VSS
VSS
33
34
35
36
A0
A2
A4
A6
75
76
77
78
DQ29
DQ30
DQ31
VSS
117
118
119
120
A1
A3
A5
A7
159
160
161
162
DQ61
DQ62
DQ63
VSS
37
38
39
40
A8
79
80
81
82
CLK2
N.C.
WP
121
122
123
124
A9
163
164
165
166
CLK3
N.C.
SA0
SA1
A10
BA1
VDD
BA0
A11
VDD
SDA
41
42
83
84
SCL
125
126
CLK1
N.C.
167
168
SA2
VDD
CLK0
VDD
VDD
INFINEON Technologies
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HYS 64V8301GU
SDRAM-Modules
Functional Block Diagrams
CS0, CLK0
CS, CLK
CS, CLK
DQMB4
LDQM
DQMB5
LDQM
DQ32-DQ39
DQMB0
DQ0-DQ7
UDQM
DQ40-DQ47
DQMB1
DQ0-DQ7
UDQM
DQ0-DQ7
DQ8-DQ15
DQ8-DQ15
DQ8-DQ15
D0
D1
CS2, CLK2
CS, CLK
LDQM
CS, CLK
LDQM
DQMB6
DQMB7
DQ48-DQ55
DQMB2
DQ0-DQ7
UDQM
DQ56-DQ63
DQMB3
DQ0-DQ7
UDQM
DQ16-DQ23
DQ8-DQ15
DQ24-DQ31
DQ8-DQ15
D2
D3
E2PROM (256 word x 8 Bit)
A0-A11, BA0, BA1
D0-D3
D0-D3
D0-D3
D0-D3
D0-D3
SA0
SA0
SA1
SA2
SCL
V
CC
SA1
SA2
SCL
SDA
WP
C
V
SS
47 k
Ω
RAS, CAS, WE
CKE0
Clock Wiring
8 M x 64
CLK1, CLK3
CLK0
2 SDRAM+ 3.3 pF
Termination
2 SDRAM+ 3.3 pF
Termination
10 pF
CLK1
CLK2
CLK3
Notes:
1) All resistors are 10 Ohm except otherwise noted
BL04 7.8.00
Block Diagram: 8M x 64 one Bank SDRAM DIMM Modules (HYS 64V8301GU)
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HYS 64V8301GU
SDRAM-Modules
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
min.
– 1.0
– 1.0
-55
–
max.
4.6
Input / Output voltage relative to VSS
Power supply voltage on VDD
Storage temperature range
Power dissipation
VIN, VOUT
VDD
V
4.6
+150
8
V
TSTG
PD
oC
W
mA
Data out current (short circuit)
IOS
–
50
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD= 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
max.
Unit
min.
2.0
Input High Voltage
VIH
VIL
V
DD + 0.3
V
Input Low Voltage
– 0.5
2.4
0.8
–
V
Output High Voltage (IOUT = – 4.0 mA)
Output Low Voltage (IOUT = 4.0 mA)
VOH
VOL
II(L)
V
–
0.4
10
V
Input Leakage Current, any input
– 10
µA
(0 V < VIN < 3.6 V, all other inputs = 0 V)
Output Leakage Current
IO(L)
– 10
10
µA
(DQ is disabled, 0 V < VOUT < VDD
)
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
max.
Input Capacitance (A0 - A11, RAS, CAS, WE)
Input Capacitance (CS0 , CS2)
CI1
38
25
43
35
13
10
8
pF
pF
pF
pF
pF
pF
pF
pF
CI2
Input Capacitance (CLK0 - CLK3)
Input Capacitance (CKE0)
CICL
CI3
Input Capacitance (DQMB0 - DQMB7)
CI4
Input /Output Capacitance (DQ0 - DQ63, CB0 - CB7)
Input Capacitance (SCL, SA0-2)
CIO
CSC
CSD
Input /Output Capacitance
8
INFINEON Technologies
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HYS 64V8301GU
SDRAM-Modules
Operating Currents per SDRAM component
TA = 0 to 70 °C, VDD = 3.3 V ± 0.3 V
(Recommended Operating Conditions unless otherwise noted)
Parameter
Test Condition Symbol -7 /-7.5 -8
max.
150
Unit Note
1)
Operating current
RC = tRC(MIN.), tCK = tCK(MIN.)
–
ICC1
160
mA
t
Outputs open, Burst Length = 4, CL=3
All banks operated in random access,
all banks operated in ping-pong
manner to maximize gapless data
access
1)
Precharge standby current
in Power Down Mode
tCK = min
ICC2P
1.5
mA
CS = VIH (MIN.), CKE ≤ VIL(MAX.)
1)
Precharge stand-by current
in Non Power Down Mode
CS = VIH (MIN.), CKE ≥ VIH(MIN.)
tCK = min
ICC2N
40
35
mA
1)
CKE ≥ VIH(MIN.)
CKE ≤ VIL(MAX.)
No operating current
ICC3N
ICC3P
50
10
45
10
mA
tCK = min., CS = VIH (MIN.),
1)
mA
active state (max. 4 banks)
1, 2)
Burst Operating Current
–
ICC4
ICC5
ICC6
100
230
1.5
90
mA
tCK = min
Read command cycling
1)
Auto Refresh Current
–
210
1.5
mA
tCK = min
Auto Refresh command cycling
1)
Self Refresh Current
Self Refresh Mode
CKE = 0.2 V
mA
1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7 and
-7.5 and at 100 MHz for -8 modules. Input signals are changed once during tCK, excepts for ICC6
and for stand-by currents when tCK = infinity. All values are shown per memory component.
2. These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 are assumed and the data-out current is excluded.
INFINEON Technologies
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HYS 64V8301GU
SDRAM-Modules
AC Characteristics 3,4
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
-7.5
Unit Note
-8
-7
PC133-222 PC133-333 PC100-222
min. max. min. max. min. max.
Clock and Access Time
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
tCK
fCK
tAC
–
–
7.5
7.5
–
–
7.5
10
–
–
10
10
–
–
ns
ns
System Frequency
CAS Latency = 3
CAS Latency = 2
–
–
133
133
–
–
133
100
–
–
100
100
MHz
MHz
Access Time from Clock
CAS Latency = 3
4), 5)
–
–
5.4
5.4
–
–
5.4
6
–
–
6
6
ns
ns
CAS Latency = 2
6)
6)
Clock High Pulse Width
Clock Low Pulse Width
tCH
tCL
2.5
2.5
–
–
2.5
2.5
–
–
3
3
–
–
ns
ns
Setup and Hold Parameters
Input Setup Time
7)
7)
8)
9)
tCS
tCH
1.5
0.8
–
–
–
1
–
1.5
0.8
–
–
–
1
–
2
1
–
1
–
–
1
–
ns
Input Hold Time
ns
Power Down mode Entry Time tSB
CLK
CLK
Power Down Mode Exit Setup tPDE
1
1
Time
Mode Register Setup Time
Transition Time
tESC
tT
2
1
–
–
2
1
–
–
2
1
–
–
CLK
ns
–
Common Parameters
RAS to CAS Delay
Precharge Time
tRCD
tRP
tRAS
tRC
15
15
42
60
14
1
–
–
20
20
–
–
20
20
–
–
ns
ns
–
–
–
–
–
–
Active Command Period
Cycle Time
100k 45
100k 45
100k ns
–
–
–
67.5
–
–
–
70
16
1
–
–
–
ns
Bank to Bank Delay Time
tRRD
15
1
ns
CAS to CAS Delay Time (same tCCD
CLK
bank)
INFINEON Technologies
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HYS 64V8301GU
SDRAM-Modules
AC Characteristics (cont’d)3,4
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
-7.5
Unit Note
-8
-7
PC133-222 PC133-333 PC100-222
min. max. min. max. min. max.
Refresh Cycle
8)
Refresh Period (4096 cycles)
Self Refresh Exit Time
tREF
–
64
–
64
–
64
ms
10)
tSREX
1
–
1
–
1
–
CLK
Read Cycle
4)
Data Out Hold Time
tOH
tLZ
3
0
–
–
3
0
–
–
3
0
–
–
ns
ns
Data Out to Low Impedance
Time
–
11)
Data Out to High Impedance
Time
tHZ
3
7
2
3
7
2
3
8
2
ns
DQM Data Out Disable
Latency
tDQZ
–
–
CLK
–
Write Cycle
Data Input to Precharge
(write recovery)
tWR
2
0
–
–
2
0
–
–
2
0
–
–
CLK
CLK
–
–
DQM Write Mask Latency
tDQW
Notes
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up. Then a Precharge All Banks command must
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation
can begin.
4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between VIH and VIL. All AC measurements assume
tT = 1 ns with the AC output load circuit shown in Figure below. Specified tAC and tOH parameters
are measured with a 50 pF only, without any resistive termination and with a input signal of 1V/
ns edge rate between 0.8 V and 2.0 V.
5. If clock rising time is longer than 1 ns, a time (tT/2 − 0.5) ns must be added to this parameter.
6. Rated at 1.4 V.
7. If tT is longer than 1 ns, a time (tT − 1) ns must be added to this parameter.
8. Whenever the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up” the device.
INFINEON Technologies
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HYS 64V8301GU
SDRAM-Modules
9. Timing is a asynchronous. If setup time is not met by rising edge of the clock then the CKE signal
is assumed latched on the next cycle.
10.Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
after the Self Refresh Exit command is registered.
11.This is referenced to the time at which the output achieved the open circuit condition, not to
output voltage levels.
tCH
2.4 V
0.4 V
CLOCK
tT
tCL
tHOLD
tSETUP
INPUT
1.4 V
tAC
tAC
I/O
tLZ
tOH
50 pF
OUTPUT
1.4 V
Measurement conditions for
AC and tOH
tHZ
t
SPT03404
A serial presence detect storage device - E2PROM - is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E2PROM device during module
production using a serial presence detect protocol (I2C synchronous 2-wire bus).
INFINEON Technologies
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HYS 64V8301GU
SDRAM-Modules
SPD-Table for HYS64V8301
Byte# Description
SPD Entry
Value
Hex
8M × 64 8M × 64 8M × 64
-7
-7.5
80
08
04
0C
09
01
40
00
01
75
54
00
80
-8
0
Number of SPD bytes
128
80
08
04
0C
09
01
40
00
01
75
54
00
80
80
08
04
0C
09
01
40
00
01
A0
60
00
80
1
Total Bytes in Serial PD
Memory Type
256
2
SDRAM
3
Number of Row Addresses
Number of Column Addresses
Number of DIMM Banks
Module Data Width
12
4
9
5
1
6
64
7
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL = 3
SDRAM Access Time at CL = 3
DIMM Config (Error Det/Corr.)
Refresh Rate/Type
0
8
LVTTL
7.5 / 10.0 ns
5.4 / 6.0 ns
none
9
10
11
12
Self-Refresh,
15.6 µs
13
14
15
SDRAM Width, Primary
x16
n/a
10
00
01
10
00
01
10
00
01
Error Checking SDRAM Data Width
Minimum Clock Delay for Back-to-
Back Random Column Address
tCCD = 1 CLK
16
17
18
19
20
21
22
Burst Length Supported
Number of SDRAM Banks
Supported CAS Latencies
CS Latencies
1, 2, 4, & 8
4
0F
04
06
01
01
00
0E
0F
04
06
01
01
00
0E
0F
04
06
01
01
00
0E
CL = 2 & 3
CS latency = 0
WL = 0
WE Latencies
SDRAM DIMM Module Attributes
SDRAM Device Attributes: General
unbuffered
V
DD tol. ± 10%
INFINEON Technologies
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HYS 64V8301GU
SDRAM-Modules
SPD-Table for HYS64V8301
(cont’d)
Byte# Description
SPD Entry
Value
Hex
8M × 64 8M × 64 8M × 64
-7
-7.5
-8
23
SDRAM Cycle Time at CL = 2
10.0 ns
75
A0
A0
CAS Latency = 2
24
25
26
27
28
SDRAM Access Time at CL = 2
SDRAM Cycle Time at CL = 1
SDRAM Access Time at CL = 1
Minimum Row Precharge Time
6.0 ns
54
FF
FF
0F
0E
60
FF
FF
14
0F
60
FF
FF
14
10
not supported
not supported
15 / 20 ns
Minimum Row Active to Row Active
14 / 15 / 16 ns
Delay tRRD
29
30
31
32
33
34
35
Minimum RAS to CAS Delay tRCD
Minimum RAS Pulse Width tRAS
Module Bank Density (per bank)
SDRAM Input Setup Time
15 / 20 ns
42 / 45 ns
64 MByte
1.5 / 2 ns
0.8 / 1 ns
1.5 / 2 ns
0.8 / 1 ns
–
0F
2A
10
15
08
15
08
FF
12
C5
14
2D
10
15
08
15
08
FF
12
0A
14
2D
10
20
10
20
10
FF
12
68
SDRAM Input Hold Time
SDRAM Data Input Setup Time
SDRAM Data Input Hold Time
36-61 Superset Information
62
63
SPD Revision
Revision 1.2
–
Checksum for bytes 0 - 62
64-125 Manufacturers Information
–
126
Frequency Specification
100 MHz Details
64
AF
FF
64
AF
FF
64
AF
FF
127
–
–
128+
Unused Storage Locations
INFINEON Technologies
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HYS 64V8301GU
SDRAM-Modules
Package Outlines
L-DIM-168-32 (JEDEC MO-161)
SDRAM DIMM Module Package
133.35+- 0.15
127.35
3 max.
3
1
10
11
6.35
40
41
6.35
84
1.27 -+ 0.1
3
1.27
42.18
91 x 1.27 = 115.57
124 125
66.68
2
85 94
95
168
3 min.
Detail of Contacts
L-DIM-168-32
1
1.27
Note: All tolerances according to JEDEC standard
Dimensions in mm
INFINEON Technologies
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