HYS72V32301GR-7.5 [ETC]
x72 SDRAM Module ; X72 SDRAM模块\n
| 型号： | HYS72V32301GR-7.5 |
| 厂家： | 
ETC |
| 描述： | x72 SDRAM Module
|
| 文件： | 总19页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
3.3 V 168-pin Registered SDRAM Modules
PC133 128 MByte Module
PC133 256 MByte module
PC133 512 MByte Module
PC133 1 GByte Module
• 168-pin Registered 8 Byte Dual-In-Line
SDRAM Module for PC and Server main
memory applications
• Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
• One bank 16M × 72, 32M x 72 and 64M × 72 • Auto Refresh (CBR) and Self Refresh
two bank 128M × 72 organization
• All inputs and outputs are LVTTL compatible
• Optimized for ECC applications with very low
• Serial Presence Detect with E2PROM
input capacitances
• Utilizes SDRAMs in TSOPII-54 packages
• JEDEC standard Synchronous DRAMs
with registers and PLL.
(SDRAM) Programmable CAS Latency, Burst
Length and Wrap Sequence (Sequential &
Interleave)
• Card Size: 133.35 mm × 43.18 mm × 3.99/
8.13 mm with Gold contact pads
(JEDEC MO-161)
• Single + 3.3 V (± 0.3 V) power supply
• These modules all fully compatible with the
current industry standard PC133
specifications
• Performance:
-7.5
Unit
MHz
ns
fCK
tCK
tAC
Clock Frequency (max.) @ CL = 3 133
Clock Cycle Time (min.) @ CL = 3 7.5
Clock Access Time (min.)
CAS Latency = 3
5.4
ns
The HYS 72Vxx3xxGR-7.5 are industry standard 168-pin 8-byte Dual in-line Memory Modules
(DIMMs) organized as 16M × 72, 32M x 72, 64M × 72 and 128M × 72 high speed memory arrays
designed with Synchronous DRAMs (SDRAMs) for ECC applications. The 32M x 72 (256Mbyte)
registered DIMM module is available in two versions (12 or 13 row addresses). All control and
address signals are registered on-DIMM and the design incorporates a PLL circuit for the Clock
inputs. Use of an on-board register reduces capacitive loading on the input signals but are delayed
by one cycle in arriving at the SDRAM devices. Decoupling capacitors are mounted on the PC
board. The DIMMs use a serial presence detects scheme implemented via a serial E2PROM using
the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second
128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance,
flexible 8-byte interface in a 133.35 mm long footprint.
Data Book
1
1.00
HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
Ordering Information
Type
Compliance Code
Description
SDRAM
Technology
HYS 72V16300GR-7.5 PC133R-333-542-B2 one bank 128 MB Reg. DIMM 64 MBit
HYS 72V16301GR-7.5 PC133R-333-542-B2 one bank 128 MB Reg. DIMM 128 MBit
HYS 72V32301GR-7.5 PC133R-333-542-B2 one bank 256 MB Reg. DIMM 128 Mbit
HYS 72V32300GR-7.5 PC133R-333-542-AA one bank 256 MB Reg. DIMM 256 Mbit
HYS 72V64300GR-7.5 PC133R-333-542-B2 one bank 512 MB Reg. DIMM 256 MBit
HYS 72V128320GR-7.5 PC133R-333-542-B2 two banks 1 GByte Reg. DIMM 256 MBit
(stacked)
Note: HYS 72V32301GR-7.5All part numbers end with a place code (not shown), designating the
die revision. Consult factory for current revision. Example: HYS 64V16300GR-7.5-C2,
indicating Rev.C2 dies are used for SDRAM components.
Pin Definitions and Functions
A0 - A11, A12 Address Inputs (A12 is used for
256Mbit based modules only)
DQMB0 - DQMB7 Data Mask
BA0, BA1
Bank Selects
CS0 - CS3
REGE
VDD
Chip Select
DQ0 - DQ63 Data Input/Output
Register Enable
Power (+ 3.3 V)
Ground
CB0 - CB7
RAS
Check Bits
Row Address Strobe
Column Address Strobe
Read/Write Input
Clock Enable
VSS
CAS
SCL
Clock for Presence Detect
Serial Data Out
No Connection
–
WE
SDA
N.C.
–
CKE0
CLK0 - CLK3 Clock Input
Address Format
Density Organization Memory SDRAMs # of
# of row/bank/ Refresh Period Interval
Banks
SDRAMs columns bits
128 MB 16M × 72
128 MB 16M × 72
256 MB 32M x 72
256 MB 32M x 72
512 MB 64M × 72
1
1
1
1
1
2
16M × 4
16M x 8
32M x 4
32M x 8
64M × 4
64M × 4
18
9
12/2/10
12/2/10
12/2/11
13/2/10
13/2/11
13/2/11
4k
4k
4k
8k
8k
8k
64 ms 15.6 µs
64 ms 15.6 µs
64 ms 15.6 µs
64 ms 7.8 µs
64 ms 7.8 µs
64 ms 7.8 µs
18
9
18
36
1 GB
128M × 72
Data Book
2
1.00
HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
Pin Configuration
PIN# Symbol
PIN# Symbol
PIN# Symbol
PIN# Symbol
1
VSS
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
VSS
85
VSS
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
VSS
2
DQ0
DQ1
DQ2
DQ3
VDD
DU
86
DQ32
DQ33
DQ34
DQ35
VDD
CKE0
CS3
3
CS2
87
4
DQMB2
DQMB3
DU
88
DQMB6
DQMB7
N.C.
5
89
6
90
7
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
VDD
91
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
VDD
8
N.C.
N.C.
CB2
92
N.C.
9
93
N.C.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
94
CB6
CB3
95
CB7
VSS
96
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ16
DQ17
DQ18
DQ19
VDD
97
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ48
DQ49
DQ50
DQ51
VDD
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
DQ20
N.C.
DU
DQ52
N.C.
DQ14
DQ15
CB0
CB1
VSS
DQ46
DQ47
CB4
DU
N.C.
VSS
REGE
VSS
CB5
DQ21
DQ22
DQ23
VSS
VSS
DQ53
DQ54
DQ55
VSS
N.C.
N.C.
VDD
N.C.
N.C.
VDD
WE
DQ24
DQ25
DQ26
DQ27
VDD
CAS
DQ56
DQ57
DQ58
DQ59
VDD
DQMB0
DQMB1
CS0
DU
DQMB4
DQMB5
CS1
RAS
VSS
DQ28
DQ29
VSS
DQ60
DQ61
A0
A1
Data Book
3
1.00
HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
Pin Configuration (cont’d)
PIN# Symbol PIN# Symbol
PIN# Symbol
PIN# Symbol
34
35
36
37
38
39
40
41
42
A2
76
77
78
79
80
81
82
83
84
DQ30
DQ31
VSS
118
119
120
121
122
123
124
125
126
A3
160
161
162
163
164
165
166
167
168
DQ62
DQ63
VSS
A4
A5
A6
A7
A8
CLK2
N.C.
WP
A9
CLK3
N.C.
SA0
SA1
SA2
VDD
A10 (AP)
BA1
VDD
BA0
A11
VDD
CLK1
A12
SDA
SCL
VDD
VDD
CLK0
Data Book
4
1.00
HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
RCS0
RDQMB0
RDQMB4
DQM
CS
DQM
CS
DQ0-DQ3
DQ4-DQ7
DQ32-DQ35
DQ0-DQ3
DQ0-DQ3
D0
D8
DQM
DQM
DQ0-DQ3
CS
CS
DQ36-DQ39
DQ0-DQ3
D1
D9
RDQMB1
RDQMB5
DQM
DQ0-DQ3
DQM
DQ0-DQ3
CS
DQ8-DQ11
DQ40-DQ43
D2
D3
D10
CS
DQ0-DQ3
CS
DQM
DQM
DQ12-DQ15
CB0-CB3
DQ44-DQ47
CB4-CB7
DQ0-DQ3
D11
DQM
CS
DQM
CS
DQ0-DQ3
D17
DQ0-DQ3
D16
RCS2
RDQMB2
RDQMB6
DQM
DQ0-DQ3
CS
DQM
DQ0-DQ3
D12
CS
DQ16-DQ19
DQ20-DQ23
DQ48-DQ51
D4
CS
DQ0-DQ3
CS
DQ0-DQ3
D13
DQM
DQM
DQ52-DQ55
D5
RDQMB3
RDQMB7
CS
DQ0-DQ3
CS
DQ0-DQ3
D14
DQM
DQM
DQ24-DQ27
DQ56-DQ59
D6
CS
DQ0-DQ3
CS
DQ0-DQ3
D15
DQM
DQM
DQ28-DQ31
DQ60-DQ63
D7
E2PROM
(256 word x 8 Bit)
CLK0
12 pF
PLL
SDRAMs D0-D17
CLK1, CLK2, CLK3
SA0
SA1
SA2
SCL
SA0
SA1 SDA
SA2
SCL
12 pF
CS0/CS2
DQMB0-7
BA0, BA1
A0-A11, A12
RAS
CAS
CKE0
WE
RCS0/RCS2
WP
RDQMB0-7
RBA0, RBA1
RA0-RA11, RA12
RRAS
RCAS
RCKE0
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
47 kΩ
VCC
VSS
D0-D17, Reg., DLL
D0-D17, Reg., DLL
C
RWE
REGE
1) DQ wirding may differ from that decribed
in this drawing; however DQ/DQB relationship
must be maintained as shown
10 kΩ
VCC
2) All resistors are 10 Ω unless otherwise noted
SPB04135
Block Diagram: One Bank 16M × 72, 32M × 72 and 64M × 72 SDRAM DIMM Modules
HYS72V16300GR, HYS72V32301GR and HYS 72V64300GR using x4 organized SDRAMs
Data Book
5
1.00
HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
RCS0
CS
DQM
DQ0-DQ7
D0
CS
DQM
RDQMB0
DQ0-DQ7
RDQMB4
DQ32-DQ39
DQ0-DQ7
D4
CS
DQM
DQ0-DQ7
D1
CS
DQM
DQ0-DQ7
D5
RDQMB1
RDQMB5
DQ8-DQ15
DQ40-DQ47
CS WE
DQM
DQ0-DQ7
D8
RCB0-RCB7
RCS2
CS
DQM
DQ0-DQ7
D2
CS
DQM
DQ0-DQ7
D6
RDQMB2
RDQMB4
DQ16-DQ23
DQ48-DQ55
CS
DQM
DQ0-DQ7
D3
CS
DQM
DQ0-DQ7
D7
RDQMB3
RDQMB7
DQ24-DQ31
DQ56-DQ63
E2PROM
(256 word x 8 Bit)
VCC
VSS
D0-D8, Reg., DLL
D0-D8, Reg., DLL
SA0
SA1
SA2
SCL
SA0
SA1 SDA
C
SA2
SCL
WP
47 kΩ
CLK0
12 pF
PLL
SDRAMs D0-D8
Notes:
1) DQ wirding may differ from that
decribed in this drawing;
however DQ/DQB relationship
must be maintained as shown
2) All resistors are 10 Ω unless
otherwise noted
CS0/CS2
DQMB0-7
BA0, BA1
A0-A11,12*)
RAS
CAS
CKE0
RCS0/RCS2
RDQMB0-7
RBA0, RBA1
RA0-11,12
RRAS
SDRAMs D0-D8
SDRAMs D0-D8
SDRAMs D0-D8
SDRAMs D0-D8
SDRAMs D0-D8
SDRAMs D0-D8
RCAS
*) A12 is only for 32 M x 72
organisation
RCKE0
WE
RWE
CLK1, CLK2, CLK3
12 pF
REGE
10 kΩ
VCC
SPB04130
Block Diagram: One Bank 16Mx72 and 32M × 72 Modules
HYS72V16301 & HYS72V32300GR using x8 organized SDRAMs
Data Book
6
1.00
HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
RCS0
RCS1
RDQMB0
RDQMB4
CS
DQ0-DQ3
CS
DQ0-DQ3
CS
DQ0-DQ3
CS
DQ0-DQ3
DQM
DQM
DQM
DQM
DQ0-DQ3
DQ4-DQ7
DQ32-DQ35
D0
D0
D8
D8
DQM
DQ0-DQ3
CS DQM
DQ0-DQ3
CS
DQM CS
DQ0-DQ3
DQM
CS
DQ36-DQ39
DQ0-DQ3
D1
D1
D9
D9
RDQMB1
RDQMB5
DQM
DQ0-DQ3
CS DQM
DQ0-DQ3
CS
DQM CS
DQ0-DQ3
DQM
DQ0-DQ3
CS
DQ8-DQ11
DQ40-DQ43
D2
D2
D3
D10
D10
CS
CS
DQ0-DQ3
CS
DQ0-DQ3
CS
DQ0-DQ3
DQM
DQ0-DQ3
DQM
DQM
DQM
DQ12-DQ15
CB0-CB3
DQ44-DQ47
CB4-CB7
D3
D11
D11
CS
CS
DQM
DQ0-DQ3
DQM
DQM CS
DQ0-DQ3
DQM
DQ0-DQ3
D17
CS
DQ0-DQ3
D16
D16
D17
RCS2
RCS3
RDQMB2
RDQMB6
DQM
DQ0-DQ3
CS DQM
CS
DQM CS
DQ0-DQ3
DQM
DQ0-DQ3
D12
CS
DQ16-DQ19
DQ48-DQ51
DQ0-DQ3
D4
D4
D12
CS
CS
DQ0-DQ3
D13
DQM
DQ0-DQ3
DQM
DQ0-DQ3
DQM
DQM
CS
CS
DQ20-DQ23
DQ52-DQ55
DQ0-DQ3
D13
D5
D5
RDQMB3
RDQMB7
CS
DQ0-DQ3
D14
CS
DQ0-DQ3
D14
DQM
DQ0-DQ3
DQM
DQ0-DQ3
DQM
DQM
CS
CS
DQ24-DQ27
DQ56-DQ59
D6
D6
DQM
DQ0-DQ3
CS DQM
CS
DQM CS
DQ0-DQ3
DQM
DQ0-DQ3
CS
DQ28-DQ31
DQ61-DQ63
DQ0-DQ3
D7
D7
D15
D15
E2PROM
(256 word x 8 Bit)
CLK0
12 pF
PLL
Stacked SDRAMs D0-D17
CLK1, CLK2, CLK3
SA0
SA1
SA2
SCL
SA0
SA1 SDA
SA2
SCL
12 pF
CS0-CS3
DQMB0-7
BA0, BA1
A0-A11, A12* )
RAS
CAS
CKE0
WE
RCS0-RCS3
WP
RDQMB0-7
RBA0, RBA1
RA0-RA11
RRAS
RCAS
RCKE0
Stacked SDRAMs D0-D17
Stacked SDRAMs D0-D17
Stacked SDRAMs D0-D17
Stacked SDRAMs D0-D17
Stacked SDRAMs D0-D17
Stacked SDRAMs D0-D17
47 kΩ
VCC
VSS
D0-D17, Reg. DLL
D0-D17, Reg. DLL
C
RWE
REGE
1.) DQ wirding may differ from that decribed
in this drawing; however DQ/DQB relationship
must be maintained as shown
*) A12 is only used for
128 M x 72 organisation
10 kΩ
VCC
2.) All resistors are 10 Ω unless otherwise noted
SPB04136
Block Diagram: Two Bank 128M × 72 SDRAM DIMM Modules
HYS 72V128320GR Using Stacked x4 Organized SDRAMs
Data Book
7
1.00
HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
DC Characteristics
TA = 0 to 70 °C 1); VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
max.
Unit
min.
2.0
Input High Voltage
VIH
VIL
V
DD + 0.3
V
Input Low Voltage
– 0.5
2.4
0.8
–
V
Output High Voltage (IOUT = – 4.0 mA)
Output Low Voltage (IOUT = 4.0 mA)
VOH
VOL
II(L)
V
–
0.4
10
V
Input Leakage Current, any input
– 10
µA
(0 V < VIN < 3.6 V, all other inputs = 0 V)
Output Leakage Current
IO(L)
– 10
10
µA
(DQ is disabled, 0 V < VOUT < VDD)
Capacitance
TA = 0 to 70 °C 1); VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values (max.)
Unit
One Bank
modules
Two Bank
Modules
Input Capacitance
CIN
10
20
pF
(all inputs except CLK and CKE)
Input Capacitance (CLK)
Input Capacitance (CKE)
CCLK
CCKE
CIO
30
17
10
30
30
17
pF
pF
pF
Input/Output Capacitance
(DQ0 - DQ63, CB0 - CB7)
Input Capacitance (SCL, SA0 - 2)
Input/Output Capacitance (SDA)
CSC
CSD
8
8
8
8
pF
pF
Data Book
8
1.00
HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
Operating Currents per SDRAM Component
TA = 0 to 70 °C 1), VDD = 3.3 V ± 0.3 V
(Recommended Operating Conditions unless otherwise noted)
Parameter
Test Condition Symbol 64 Mb 128
256 M Unit Note
b
Mb
max.
2)
Operating current
–
ICC1
tRC = tRC(MIN.), tCK = tCK(MIN.)
x4 100
120
270
mA
Outputs open, Burst Length = 4,
CL = 3
All banks operated in random
access,
all banks operated in ping-pong
manner to maximize gapless
data access
2)
2)
Precharge stand-by current
in Power Down Mode
t
CK = min.
ICC2P
2
2
2
mA
mA
CS = VIH(MIN.), CKE ≤ VIL(MAX.)
Precharge Stand-by Current
in Non-Power Down Mode
tCK = min.
ICC2N
35
40
35
CS = VIH (MIN.), CKE ≥ VIH(MIN.)
2)
2)
No operating current
CKE ≥ VIH(MIN.) ICC3N
CKE ≤ VIL(MAX.) ICC3P
45
8
50
10
50
10
mA
mA
tCK = min., CS = VIH(MIN.),
active state (max. 4 banks)
2), 3)
Burst operating current
–
–
–
ICC4
ICC5
ICC6
tCK = min.,
x4 60
130
120
180
270
240
mA
mA
Read command cycling
2)
Auto refresh current
tCK = min.,
Auto Refresh command cycling
2)
Self refresh current
Self Refresh Mode,
CKE = 0.2 V
1
1.5
2.5
mA
Data Book
9
1.00
HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
4), 5)
AC Characteristics (SDRAM Device Specification)
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
-7.5
Unit Note
min.
max.
Clock and Access Time
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2 (64Mb & 128Mb based mod.)
CAS Latency = 2 (256Mb based modules)
tCK
fCK
tAC
–
7.5
10
12
–
–
–
ns
ns
ns
Clock Frequency
CAS Latency = 3
CAS Latency = 2 (64Mb & 128Mb based mod.)
CAS Latency = 2 (256Mb based modules)
–
MHz
–
–
–
133
100
83
MHz
MHz
Access Time from Clock
CAS Latency = 3
–
ns
–
–
5.4
6
CAS Latency = 2
ns
Clock High Pulse Width
Clock Low Pulse Width
Transition Time
tCH
tCL
tT
2.5
2.5
0.5
–
ns
ns
ns
–
–
–
–
10
Setup and Hold Parameters
Input Setup Time
tIS
1.5
0.8
–
–
–
1
–
–
ns
–
–
–
–
–
Input Hold Time
tIH
ns
Power Down Mode Entry Time
Power Down Mode Exit Setup Time
Mode Register Setup Time
tSB
tPDE
tRCS
CLK
CLK
CLK
1
2
Common Parameters
Row to Column Delay Time
Row Precharge Time
tRCD
tRP
tRAS
tRC
tRRD
tCCD
20
20
45
67.5
2
–
ns
–
–
–
–
–
–
–
ns
Row Active Time
100k
ns
Row Cycle Time
–
–
–
ns
Activate (a) to Activate (b) Command Period
CAS(a) to CAS(b) Command Period
CLK
CLK
1
Data Book
10
1.00
HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
AC Characteristics (SDRAM Device Specification) (cont’d) 4), 5)
TA = 0 to 70 °C 1); VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
-7.5
Unit Note
min.
max.
Refresh Cycle
Refresh Period
64&128MBit SDRAM Based Modules
256 MBit SDRAM Based Modules
tREF
–
µs
µs
–
–
15.6
7.8
6)
Self Refresh Exit Time
tSREX
1
–
CLK
Read Cycle
Data Out Hold Time
tOH
tLZ
3
0
3
–
–
–
7
2
ns
–
7)
Data Out to Low Impedance Time
Data Out to High Impedance Time
DQM Data Out Disable Latency
ns
7)
tHZ
ns
tDQZ
CLK
–
Write Cycle
Data Input to Precharge
(write recovery)
tWR
2
0
–
–
CLK
CLK
–
–
DQM Write Mask Latency
tDQW
Data Book
11
1.00
HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
Notes
1. The registered DIMM modules are designed to operate under system operating conditions
between 0-55 deg C ambient, maximum sustained bandwidth and 0 LFM airflow.
2. These parameters depend on the cycle rate. All values are measured at 133 MHz operation
frequency. Input signals are changed once during tck excepts for Icc6 and for standby currents
when tck = infinity.
3. These parameters are measured with continous data stream during read access and all DQ
toggling. CL=3 and BL=4 is assumed and the Vcc current is excluded.
4. An initial pause of 100 µs is required after power-up. Then a Precharge All Banks command must
be given followed by eight Auto Refresh (CBR) cycles before the Mode Register Set Operation
can begin. Also the on-DIMM PLL must be given enough clock cycles to stabilize (tSTAB) before
any operation can be guaranteed.
5. AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between VIH and VIL. All AC measurements assume
tT = 1 ns with the AC output load circuit shown. Specified tAC and tOH parameters are measured
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate
between 0.8 V and 2.0 V.
6. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
after the Self Refresh Exit command is registered.
7. Referenced to the time at which the output achieves the open circuit condition, not to output
voltage levels.
tCH
2.4 V
0.4 V
CLOCK
tT
tCL
tHOLD
tSETUP
INPUT
1.4 V
tAC
tAC
I/O
tLZ
tOH
50 pF
OUTPUT
1.4 V
Measurement conditions for
AC and tOH
tHZ
t
SPT03404
A serial presence detect storage device - E2PROM 34C02 - is assembled onto the module.
Information about the module configuration, speed, etc. is written into the E2PROM device during
module production using a serial presence detect protocol (I2C synchronous 2-wire bus).
Data Book
12
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HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
SPD-Table for -7.5 Registered DIMM Modules with PLL
Byte# Description
SPD Entry
Value
Hex
0
1
2
3
Number of SPD Bytes
128
80
08
04
Total Bytes in Serial PD
256
Memory Type
SDRAM
12/13
Number of Row Addresses
(without BS bits)
0C
0C
0C
0D
0D
0D
4
Number of Column Addresses 10/11
0A
01
0A
01
0B
01
0A
01
0B
01
0B
02
5
Number of DIMM Banks
Module Data Width
1/2
6
72
48
7
Module Data Width (cont’d)
Module Interface Levels
Cycle Time at CL = 3
Access Time from Clock at
CL = 3
0
00
01
75
54
8
LVTTL
7.5 ns
5.4 ns
9
10
11
12
13
14
DIMM Config (Error Det/Corr.) ECC
02
Refresh Rate/Type
15.6/7.8 µs
x4 / x8
80
80
80
04
04
82
82
04
04
82
04
04
SDRAM Width, Primary
04 08
04 08
08
08
Error Checking SDRAM Data x4 / x8
Width
15
16
Minimum tCCD
Burst Length Supported
1 CLK
01
0F
1, 2, 4, 8 &
(full page)
4
8F
0F
0F
0F
0F
17
18
Number of SDRAM Banks
04
SDRAM Supported CAS
Latencies
2 & 3
06
19
20
21
SDRAM CS Latencies
SDRAM WE Latencies
SDRAM DIMM Module
Attributes
0
01
01
1F
0
with PLL
22
23
24
25
26
SDRAM Device Attributes
V
10%
DD tol +/–
0E
Min. Clock Cycle Time at
CL = 2
10/12 ns
A0
60
A0
60
A0
60
C0
60
00
00
C0
60
C0
60
Max. Data Access Time from 6.0
Clock for CL = 2
Min. Clock Cycle Time at
CL = 1
not supported
Max. Data Access Time from not supp.
Clock at CL = 1
Data Book
13
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HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
SPD-Table for -7.5 Registered DIMM Modules with PLL (cont’d)
Byte# Description
SPD Entry
Value
Hex
27
28
29
30
31
SDRAM Minimum tRP
SDRAM Minimum tRRD
SDRAM Minimum tRCD
SDRAM Minimum tRAS
Module Bank Density (per
bank)
20 ns
15 ns
14
0F
14
2D
20 ns
45 ns
128 MByte/
256 Mbyte
512 MByte
1.5 ns
20
20
40
40
80
80
32
33
34
SDRAM Input Setup Time
SDRAM Input Hold Time
SDRAM Data Input Setup
Time
15
08
15
0.8 ns
1.5 ns
35
SDRAM Data Input Hold Time 0.8 ns
08
36-61 Superset Information
(may be used in future)
–
00
62
63
SPD Revision
JEDEC 2
02
Checksum for Bytes 0 - 62
–
–
–
–
–
C8
50
69
93
CC
CD
64-125 Manufacturer’s Information
126
Frequency Specification
Details of Clocks
64
8D
FF
127
8F
FF
8F
FF
8F
FF
8D
FF
8D
FF
128+
Unused Storage Locations
1) HYS72V16300GR-7.5
2) HYS72V16301GR-7.5
*) HYS72V32301GR-7.5
**) HYS72V32300GR-7.5
Data Book
14
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HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
Package Outlines
Module Package
JEDEC MO-161
Registered DIMM Modules Raw Card AA L-DIM168-44
256MB modules
Front
Side
3.99
0.157 max.
1.5" (nominal)
Front
Back
1.27
0.050
±
0.10
± 0.004
note: all outline dimensions and tolerances are in accordance with the JEDEC standard
Data Book
15
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HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
Package Outlines
Module Package
JEDEC MO-161
Registered DIMM Modules Raw Card B L-DIM168-37-2
128MB, 256MB & 512MB modules
Front
Side
3.99
0.157 max.
1.7" (nominal)
Front
Back
1.27
0.050
±
0.10
± 0.004
note: all outline dimensions and tolerances are in accordance with the JEDEC standard
Data Book
16
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HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
Package Outlines
Module Package
JEDEC MO-161
Registered DIMM Modules Raw Card B L-DIM168-37-2
1 GByte module
Front
Side
8 max.
1.7" (nominal)
Front
Back
1.27
0.050
±
0.10
± 0.004
note: all outline dimensions and tolerances are in accordance with the JEDEC standard
Data Book
17
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HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
Functional Description
All these PC133 168-pin Registered DIMMs conform to a compatible set of timing and operation
characteristics intended to comply with the 133 MHz standards. The Registered DIMMs achieve
high speed data transfer rate up to 133 MHz.
All control and address signals are synchronized with the positive edge of externally supplied clocks
and are registered on-DIMM and hence delayed by one clock cycle in arriving at the SDRAM
devices. The use of the on-board register reduces the capacitive loading of the DIMM on input
control and address signals. The SDRAM device data lines (DQ) are connected directly to the DIMM
tabs through 10 Ohm series resistors. All the following timing diagrams and explanations show
DIMM operation at the tabs, not SDRAM operation.
The picture below depicts an overview of the effect of the Registered Mode on the data outputs
(DQs) for a Read operation. Without the registers, the data is delayed according to the device CAS
latency, in the case two clocks. With the register, the data is delayed according to the device CAS
latency plus an additional clock cycle. This is know as the DIMM CAS latency, and in this example
is four three. The data path can be thought of as a pipeline in which the register effectively lengthens
the pipe by one clock cycle.
Registered DIMM Burst Read Operation (BL = 4)
T0
T1
T2
T3
T4
T5
T6
CLK
Command
Read A
NOP
NOP
NOP
NOP
NOP
NOP
Device
CAS latency = 2
DOUT A0 DOUT A1 DOUT A2 DOUT A3
t
CK2, DQ’s
DIMM
CAS latency = 3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
Added for on-DIMM pipeline register
t
CK3, DQ’s
One Clock
Reg-DIMM Latency = 1
SPT03968
In case of a Burst Write Command the data-in is delayed one clock due the op-DIMM pipeline
register also. Therefore, data for the first Burst Write cycle must be applied on the DQ pins on the
next clock cycle after the Write command is issued. the remaining data inputs must be supplied on
each subsequent rising clock edge until the burst length is completed. When the burst has finished,
any additional data supplied to the DQ pins will be ignored.
Data Book
18
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HYS 72Vxx3xxGR-7.5
PC133 Registered SDRAM-Modules
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
DQ’s
NOP
Write A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
don’t care
DIN A0
DIN A1
DIN A2
DIN A3
The first data element and the Write
are registered on the next clock edge
Reg-DIMM Latency = 1 CLK
Extra data is ignored after
termination of a Burst.
SPT03969
Registered DIMM Burst Write Operation (BL = 4)
Data Book
19
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