ICX411AQ [ETC]
Diagonal 8.98mm(Type 1/1.8) Frame Readout CCDImage Sensor with a Square Pixel for Color Cameras ; 对角线8.98毫米（类型1 / 1.8 ）帧读取CCDImage传感器采用方形像素的彩色摄像机\n
| 型号： | ICX411AQ |
| 厂家： | 
ETC |
| 描述： | Diagonal 8.98mm(Type 1/1.8) Frame Readout CCDImage Sensor with a Square Pixel for Color Cameras
|
| 文件： | 总32页 (文件大小：440K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICX411AQ
Diagonal 8.98mm (Type 1/1.8) Frame Readout CCD Image Sensor with a Square Pixel for Color Cameras
Description
The ICX411AQ is a diagonal 8.98mm (Type 1/1.8)
interline CCD solid-state image sensor with a square
pixel array and 3.98M effective pixels. Frame readout
allows all pixels' signals to be output independently
within approximately 1/4.28 second.
20 pin DIP (Plastic)
Also, number of vertical pixels decimation allows
output of 30 frames per second in high frame rate
readout mode.
This chip features an electronic shutter with
variable charge-storage time.
R, G, B primary color mosaic filters are used as the
color filters, and at the same time high sensitivity and
low dark current are achieved through the adoption
of Super HAD CCD technology.
This chip is suitable for applications such as
electronic still cameras, etc.
1
2
Features
• Supports frame readout
V
• High horizontal and vertical resolution
• Supports high frame rate readout mode: 30 frames/s, 25 frames/s,
AF1 mode: 60 frames/s, 50 frames/s,
AF2 mode: 120 frames/s, 100 frames/s
• Square pixel
12
16
H
56
11
• Horizontal drive frequency: 24MHz
• No voltage adjustments (reset gate and substrate bias are not adjusted.)
• R, G, B primary color mosaic filters on chip
• High sensitivity, low dark current
Optical black position
(Top View)
• Continuous variable-speed shutter
• Excellent anti-blooming characteristics
• Exit pupil distance recommended range –20 to –100mm
• 20-pin high-precision plastic package
Device Structure
• Interline CCD image sensor
• Total number of pixels:
2384 (H) × 1734 (V) approx. 4.13M pixels
• Number of effective pixels: 2312 (H) × 1720 (V) approx. 3.98M pixels
• Number of active pixels:
• Number of recommended recording pixels:
2308 (H) × 1712 (V) approx. 3.95M pixels diagonal 8.980mm
2272 (H) × 1704 (V) approx. 3.87M pixels diagonal 8.875mm aspect ratio 4:3
8.1mm (H) × 6.6mm (V)
• Chip size:
• Unit cell size:
• Optical black:
3.125µm (H) × 3.125µm (V)
Horizontal (H) direction: Front 16 pixels, rear 56 pixels
Vertical (V) direction:
Horizontal 28
Front 12 pixels, rear 2 pixels
• Number of dummy bits:
• Substrate material:
Vertical 1 (even fields only)
Silicon
Super HAD CCD is a trademark of Sony Corporation. The Super HAD CCD is a version of Sony's high performance CCD HAD (Hole-
Accumulation Diode) sensor with sharply improved sensitivity by the incorporation of a new semiconductor technology developed by
Sony Corporation.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E01Y32B33
ICX411AQ
Block Diagram and Pin Configuration
(Top View)
10
9
8
7
6
5
4
3
2
1
Gb
R
B
Gr
B
Gb
R
B
Gr
B
Gb
R
Gb
R
Gr
B
Gr
B
Gb
R
Gb
R
Gr
Gr
11
12
13
14
15
16
17
18
19 20
Pin Description
Pin No. Symbol
Description
Pin No. Symbol
Description
Supply voltage
Reset gate clock
1
2
Vφ4
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
11
12
13
14
15
16
17
18
19
20
VDD
φRG
Hφ2
Vφ3A
Vφ3B
Vφ2
3
Horizontal register transfer clock
Horizontal register transfer clock
GND
4
Hφ1
5
Vφ1A
Vφ1B
TEST
TEST
GND
VOUT
GND
φSUB
CSUB
VL
6
Substrate clock
1
2
7
Test pin
Substrate bias
1
8
Test pin
Protective transistor bias
9
GND
Hφ1
Horizontal register transfer clock
Horizontal register transfer clock
10
Signal output
Hφ2
1
2
Leave this pin open
DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance
of 0.1µF.
– 2 –
ICX411AQ
Absolute Maximum Ratings
Item
Ratings
–40 to +12
–50 to +15
–50 to +0.3
–40 to +0.3
–25 to
Unit Remarks
VDD, VOUT, φRG – φSUB
Vφ1A, Vφ1B, Vφ3A, Vφ3B – φSUB
Vφ2, Vφ4, VL – φSUB
V
V
V
V
V
V
V
V
V
V
Against φSUB
Hφ1, Hφ2, GND – φSUB
CSUB – φSUB
VDD, VOUT, φRG, CSUB – GND
Vφ1A, Vφ1B, Vφ2, Vφ3A, Vφ3B, Vφ4 – GND
Hφ1, Hφ2 – GND
–0.3 to +22
–10 to +18
–10 to +6.5
–0.3 to +28
–0.3 to +15
to +15
Against φGND
Against φVL
Vφ1A, Vφ1B, Vφ3A, Vφ3B – VL
Vφ2, Vφ4, Hφ1, Hφ2, GND – VL
Voltage difference between vertical clock input pins
Hφ1 – Hφ2
1
V
Between input
clock pins
–6.5 to +6.5
–10 to +16
–30 to +80
–10 to +60
–10 to +75
V
V
Hφ1, Hφ2 – Vφ4
Storage temperature
°C
°C
°C
Guaranteed temperature of performance
Operating temperature
1
+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
+16V (Max.) is guaranteed for turning on or off power supply.
– 3 –
ICX411AQ
Bias Conditions
Item
Symbol
VDD
Min.
Typ.
Max.
Unit Remarks
V
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
1
14.55
15.0
15.45
1
2
2
VL
φSUB
φRG
VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply for
the V driver should be used.
2
Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Symbol
Min.
3.0
Typ.
7.0
Max.
10.0
Unit Remarks
mA
Supply current
IDD
Clock Voltage Conditions
Waveform
Diagram
Item
Symbol
Min.
Typ.
Max. Unit
Remarks
Readout clock voltage VVT
14.55 15.0 15.45
V
V
V
1
2
2
VVH1, VVH2
–0.05
–0.2
0
0
0.05
0.05
VVH = (VVH1 + VVH2)/2
VVH3, VVH4
VVL1, VVL2,
VVL3, VVL4
–8.0
–7.5
7.5
–7.0
V
2
VVL = (VVL3 + VVL4)/2
VφV
6.8
8.05
0.1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
2
2
2
2
2
2
2
3
3
3
4
4
4
5
Vφ = VVHn – VVLn (n = 1 to 4)
V
Vertical transfer clock
voltage
VVH3 – VVH
VVH4 – VVH
VVHH
–0.25
–0.25
0.1
0.9
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
VVHL
0.9
VVLH
0.9
VVLL
0.7
VφH
4.75
–0.05
0.8
5.0
0
5.25
0.05
Horizontal transfer
clock voltage
VHL
VCR
2.5
3.3
Cross-point voltage
VφRG
3.0
5.25
0.4
Reset gate clock
voltage
VRGLH – VRGLL
VRGL – VRGLm
Low-level coupling
Low-level coupling
0.5
Substrate clock voltage VφSUB
21.5
22.5
23.5
– 4 –
ICX411AQ
Clock Equivalent Circuit Constants
Item
Symbol
CφV1A, CφV3A
CφV1B, CφV3B
CφV2, CφV4
Min.
Typ.
1200
4700
3300
470
560
150
220
39
Max.
Unit Remarks
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Capacitance between vertical transfer
clock and GND
CφV1A2, CφV3A4
CφV1B2, CφV3B4
CφV23A, CφV41A
CφV23B, CφV41B
CφV1A3A
Capacitance between vertical transfer
clocks
CφV1B3B
220
56
CφV1A3B, CφV1B3A
CφV24
82
CφV1A1B, CφV3A3B
68
Capacitance between horizontal transfer
clock and GND
CφH1, CφH2
CφHH
33
82
pF
pF
pF
pF
Ω
Capacitance between horizontal transfer
clocks
Capacitance between reset gate clock
and GND
CφRG
8
Capacitance between substrate clock
and GND
CφSUB
1000
62
R1A, R1B, R2,
R3A, R3B, R4
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
RGND
18
12
Ω
Ω
RφH
Vφ2
R2
CφV24
CφV1A2
CφV1A3A
CφV23A
CφV23B
Vφ1A
Vφ3A
RφH
RφH
R1A
R3A
Hφ1
Hφ2
CφV1B2
CφV1A
CφV1A1B
CφV1B3A
CφV1B
CφV41A
CφV2
CφV3A
CφV3A3B
Rφ
H
RφH
CφHH
Hφ1
Hφ2
CφV1A3B
CφV3B
CφH2
CφH1
R1B
CφV4
CφV41B
R3B
CφV3A4
CφV3B4
Vφ1B
Vφ3B
R
GND
CφV1B3B
R4
Vφ4
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
– 5 –
ICX411AQ
Drive Clock Waveform Conditions
(1) Readout clock waveform
100%
90%
φM
VVT
φM
2
10%
0%
0V
tr
twh
tf
(2) Vertical transfer clock waveform
Vφ1A, Vφ1B
Vφ3A, Vφ3B
V
VHH
V
VH1
V
VHH
V
VH
V
VH
VVHH
V
VHH
V
VHL
V
VHL
V
VHL
V
VH3
V
VHL
V
VL1
V
VL3
V
VLH
V
VLH
V
VLL
V
VLL
V
VL
V
VL
Vφ2
Vφ4
V
VHH
V
VHH
V
VHH
V
VHH
V
VH
V
VH
V
VHL
V
VH2
VHL
VVHL
V
VHL
V
V
VH4
V
VLH
VL2VVLH
V
V
VLL
V
VLL
V
VL
V
VL4
V
VL
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
– 6 –
ICX411AQ
(3) Horizontal transfer clock waveform
tr
twh
tf
Hφ2
90%
VCR
VφH
twl
VφH
2
10%
Hφ1
VHL
two
Cross-point voltage for the Hφ1 rising side of the horizontal transfer clocks Hφ1 and Hφ2 waveforms is VCR.
The overlap period for twh and twl of horizontal transfer clocks Hφ1 and Hφ2 is two.
(4) Reset gate clock waveform
tr
twh
tf
V
RGH
RG
twl
VφRG
A
V
RGLH
V
RGL
V
V
RGLL
RGLm
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from
Point A in the above diagram until the rising edge of RG.
In addition, VRGL is the average value of VRGLH and VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval with twh, then:
VφRG = VRGH – VRGL
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
100%
90%
φM
VφSUB
φM
2
10%
V
SUB
0%
tr
twh
tf
– 7 –
ICX411AQ
Clock Switching Characteristics (Horizontal drive frequency: 24MHz)
twh
twl
tr
tf
Item
Symbol
VT
Unit Remarks
Min. Typ. Max.Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
During
Readout clock
3.10 3.33
0.5
0.5
µs
readout
Vφ1A, Vφ1B,
Vφ2, Vφ3A,
Vφ3B, Vφ4
Vertical transfer
clock
When using
CXD3400N
15
250 ns
Hφ1
Hφ2
10.5 14.6
10.5 14.6
10.5 14.6
10.5 14.6
6.4 10.5
6.4 10.5
6.4 10.5
6.4 10.5
Horizontal
transfer clock
ns tf ≥ tr – 2ns
Reset gate clock φRG
Substrate clock φSUB
6
8
37
4
3
ns
During drain
charge
1.6 2.7
0.5
0.5 µs
two
Min. Typ. Max.
Item
Symbol
Unit Remarks
ns
Horizontal transfer clock Hφ1, Hφ2 10.5 14.6
Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics)
1.0
G
B
0.9
R
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
400
450
500
550
600
650
700
Wave Length [nm]
– 8 –
ICX411AQ
Image Sensor Characteristics (horizontal drive frequency: 24MHz)
(Ta = 25°C)
Measurement
method
Item
Symbol Min.
Typ.
Max. Unit
Remarks
G Sensitivity
Sg
180
0.35
0.40
380
220
0.50
0.55
285
0.65
0.70
mV
1
1
1
2
1/30s accumulation
Rr
R
B
Sensitivity
comparison
Rb
Vsat
Saturation signal
Smear
mV
dB
Ta = 60°C
1
–90
–79
–81.2
–70.1
20
Frame readout mode
High frame rate readout mode
Zone 0 and I
Sm
3
4
Video signal shading SHg
%
25
Zone 0 to II'
Vdt
∆Vdt
Lcg
Lcr
mV
mV
%
5
6
7
7
7
8
Dark signal
Dark signal shading
Line crawl G
Line crawl R
Line crawl B
Lag
12
Ta = 60°C, 4.28 frame/s
2
6
Ta = 60°C, 4.28 frame/s,
3.8
3.8
3.8
0.5
%
Lcb
Lag
%
%
1
After closing the mechanical shutter, the smear can be reduced to below the detection limit by performing
vertical register sweep operation.
2
Excludes vertical dark signal shading caused by vertical register high-speed transfer.
Zone Definition of Video Signal Shading
2312 (H)
2
2
4
V
10
H
8
H
8
1720 (V)
0, I
4
II, II
V
10
Measurement System
CCD
[ A]
CCD
C.D.S
AMP
Gr Gb
[ B]
S/H
S/H
R
B
[ C]
Note) Adjust the amplifier gain so that the gain between [ A] and [ B], and between [ A] and [ C] equals 1.
– 9 –
ICX411AQ
Image Sensor Characteristics Measurement Method
Measurement conditions
(1) In the following measurements, the device drive conditions are at the typical values of the bias and clock
voltage conditions, and the frame readout mode is used.
(2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb
channel signal output or the R/B channel signal output of the measurement system.
Color coding of this image sensor & Readout
The primary color filters of this image sensor are arranged in
Gb
R
B
Gr
B
Gb
R
B
Gr
B
B2
B1
the layout shown in the figure on the left (Bayer arrangement).
Gr and Gb denote the G signals on the same line as the R
signal and the B signal, respectively.
A2
A1
Gb
R
Gb
R
For frame readout, the A1 and A2 lines are output as signals in
the A field, and the B1 and B2 lines in the B field.
Gr
Gr
Horizontal register
Color Coding Diagram
– 10 –
ICX411AQ
Readout modes
1. Readout modes list
Mode name
Frame rate
4.28 frame/s
4.17 frame/s
30 frame/s
25 frame/s
60 frame/s
50 frame/s
120 frame/s
100 frame/s
Number of effective output lines
NTSC mode
PAL mode
1720 (Odd 860, Even 860)
Frame readout mode
1720 (Odd 860, Even 860)
NTSC mode
PAL mode
287
287
123
153
41
High frame rate readout
mode
NTSC mode
PAL mode
AF1 mode
AF2 mode
NTSC mode
PAL mode
55
2. Frame readout mode, high frame rate readout mode
Frame readout mode
High frame rate readout mode
1st field
2nd field
R
Gb
R
17
16
15
14
13
12
11
10
9
Gr
B
17
16
15
14
13
12
11
10
9
R
Gb
R
Gr
B
17
16
15
14
13
12
11
10
9
R
Gb
R
Gr
B
Gr
B
Gr
B
Gr
B
Gb
R
Gb
R
Gb
R
Gr
B
Gr
B
Gr
B
Gb
R
Gb
R
Gb
R
Gr
B
Gr
B
Gr
B
Gb
R
Gb
R
Gb
R
Gr
B
Gr
B
Gr
B
8
Gb
R
8
Gb
R
8
Gb
R
7
Gr
B
7
Gr
B
7
Gr
B
6
Gb
R
6
Gb
R
6
Gb
R
5
Gr
B
5
Gr
B
5
Gr
B
4
Gb
R
4
Gb
R
4
Gb
R
3
Gr
B
3
Gr
B
3
Gr
B
2
Gb
R
2
Gb
R
2
Gb
R
1
Gr
1
Gr
1
Gr
VOUT
VOUT
VOUT
Note) Blacked out portions in the diagram indicate pixels which are not read out.
1. Frame readout mode
In this mode, all pixel signals are divided into two fields and output.
All pixel signals are read out independently, making this mode suitable for high resolution image capturing.
2. High frame rate readout mode
Output is performed at 30 frames per second by reading out 4 pixels for every 12 vertical pixels and adding
2 pixels in the horizontal CCD.
The number of output lines is 287 lines.
This readout mode emphasizes processing speed over vertical resolution.
– 11 –
ICX411AQ
3. AF1 mode, AF2 mode
The AF modes increase the frame rate by cutting out a portion of the picture through high-speed elimination of
the top and bottom of the picture in high frame rate readout mode. AF1 allows 1/60s and 1/50s output, and
AF2 allows 1/120s and 1/100s output, so these modes are effective for raising the auto focus (AF) speed.
287
– 12 –
ICX411AQ
Definition of standard imaging conditions
(1) Standard imaging condition I:
Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject.
(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR
cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined
as the standard sensitivity testing luminous intensity.
(2) Standard imaging condition II:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
(3) Standard imaging condition III:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens (exit pupil distance –33mm) with CM500S (t = 1.0mm) as an IR cut filter. The
luminous intensity is adjusted to the value indicated in each testing item by the lens diagram.
1. G Sensitivity, sensitivity comparison
Set to the standard imaging condition I. After setting the electronic shutter mode with a shutter speed of
1/100s, measure the signal outputs (VGR, VGb, VR and VB) at the center of each Gr, Gb, R and B channel
screen, and substitute the values into the following formulas.
VG = (VGr + VGb)/2
100
Sg = VG ×
[mV]
30
Rr = VR/VG
Rb = VB/VG
2. Saturation signal
Set to the standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with
the average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B
signal outputs.
3. Smear
Set to the standard imaging condition II. With the lens diaphragm at F5.6 to F8, first adjust the average
value of the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal
output, R signal output and B signal output (Gra, Gba, Ra, Ba), and then adjust the luminous intensity to
500 times the intensity with the average value of the Gr signal output, 150mV.
After the readout clock is stopped and the charge drain is executed by the electronic shutter at the
respective H blankings, measure the maximum value (Vsm [mV]) independent of the Gr, Gb, R and B
signal outputs, and substitute the values into the following formula.
Gra + Gba + Ra + Ba
4
1
500
1
10
Sm = 20 × log Vsm ÷
×
×
[dB] (1/10V method conversion value)
(
)
– 13 –
ICX411AQ
4. Video signal shading
Set to the standard imaging condition III. With the lens diaphragm at F5.6 to F8, adjusting the luminous
intensity so that the average value of the Gr signal output is 150mV. Then measure the maximum value
(Grmax [mV]) and minimum value (Grmin [mV]) of the Gr signal output and substitute the values into the
following formula.
SHg = (Grmax – Grmin)/150 × 100 [%]
5. Dark signal
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature of 60°C
and the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
6. Dark signal shading
After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark
signal output and substitute the values into the following formula.
∆Vdt = Vdmax – Vdmin [mV]
7. Line crawl
Set to the standard imaging condition II. Adjusting the luminous intensity so that the average value of the
Gr signal output is 150mV, and then insert R, G and B filters and measure the difference between G signal
lines (∆Glr, ∆Glg, ∆Glb [mV]) as well as the average value of the G signal output (Gar, Gag, Gab).
Substitute the values into the following formula.
∆Gli
Gai
Lci =
× 100 [%] (i = r, g, b)
8. Lag
Adjust the Gr signal output value generated by the strobe light to 150mV. After setting the strobe light so
that it strobes with the following timing, measure the residual signal amount (Vlag). Substitute the value
into the following formula.
Lag = (Vlag/150) × 100 [%]
VD
V1A/V1B
Gr
150mV
Vlag
– 14 –
ICX411AQ
–7.5V 15V
Drive Circuit
3.3V
100k
0.1
1/35V
1
2
20
19
18
17
16
15
14
13
12
11
XSUB
XV3
3
0.1
XSG3B
XSG3A
XV1
4
5
CXD3400N
6
0.1
XSG1B
XSG1A
XV4
7
8
9
XV2
10
2SC4250
CCD OUT
1
2
3
4
5
6
7
8
9 10
4.7k
ICX411
(BOTTOM VIEW)
VR1 (2.7k)
3.3/20V
VSUB Cont.
0.01
20 19 18 17 16 15 14 13 12 11
Hφ2
Hφ1
φRG
0.1
200k
0.1
0.1
3.3/16V
VSUB Cont.
GND
tf 4ms
tr 2ms
φSUB
VSUB
Notes) Substrate bias control
1. The saturation signal level decreases when exposure is performed using the mechanical shutter,
so control the substrate bias.
2. A saturation signal level equivalent to that for continuous exposure can be assured by connecting
a 2.7kΩ grounding registor to the CCD CSUB pin.
Drive timing precautions
1. Blooming occurs in modes (high frame rate readout, etc.) that do not use the mechanical shutter,
so do not ground the connected 2.7kΩ resistor.
2. tf is slow, so the internally generated voltage VSUB may not drop to a sufficiently low level if the
substrate bias control signal is not set to high level 20ms before entering the exposure period
and the 2.7kΩ resistor connected to the CSUB pin is not grounded.
3. The blooming signal generated during exposure in mechanical shutter mode is swept by
providing two fields or more of idle transfer through vertical register high-speed sweep transfer
from the time the mechanical shutter closes until sensor readout is performed. However, note that
the VL potential and the φSUB pin DC voltage sag at this time.
– 15 –
Drive Timing Chart (Vertical Sequence) High Frame Rate Readout Mode → Frame Readout Mode/Electronic Shutter Normal Operation
Act.
VD
V1A
V1B
V2
V3A
V3B
V4
A
B
B
C
D
E
SUB
TRG
CLOSE
OPEN
OPEN
VSUB
Cont.
CCD
OUT
A
A
B
B
C
(ODD)
C
(EVEN)
D
E
Note) The B output signals contain a blooming component and should therefore not be used.
Apply 20 or more electronic shutter pulses at the start of exposure for the recording image.
If less than 20 pulses are applied, the electronic shutter may occur a discharge error.
Drive Timing Chart (Vertical Sync)
NTSC/PAL Frame Readout Mode
NTSC: 4.28 frame/s, PAL: 4.17 frame/s
VD
HD
NTSC
PAL
c
a
c
b
V1A/V1B
V2
V3A/V3B
V4
SUB
TRG
CLOSE
OPEN
OPEN
VSUB
Cont.
CCD
OUT
Note) The 1044 and 2088H horizontal period in NTSC mode are 938clk, the 1073H, 1074H, 2147H and 2148H horizontal period in PAL mode are 1376clk.
Drive Timing Chart (Readout)
"a" Enlarged
NTSC/PAL Frame Readout Mode
NTSC: #91
PAL: #91
NTSC: #92
PAL: #92
H1
1200 1280
1314
196
V1A/V1B
162
264
V2
230
V3A/V3B
1098
1202
128
298
V4
"b" Enlarged
NTSC: #1134
PAL: #1164
NTSC: #1135
PAL: #1165
1132
V1A/V1B
V2
V3A/V3B
V4
1166
Drive Timing Chart (High-speed Sweep Operation)
"c" Enlarged
NTSC/PAL Frame Readout Mode
236192clk = 88 lines
HD
1
60
V1A/V1B
V2
V3A/V3B
V4
34343434343434343434343434343434
34 34 34 34
#1736
#1
#2
#3
#4
Drive Timing Chart (Horizontal Sync)
NTSC/PAL Frame Readout Mode
2
2
CLK
H1
H2
RG
SHP
SHD
1
34
1
136
68
V1A/V1B
1
102
1
1
102
102
V2
1
1
170
V3A/V3B
1
102
34
170
1
1
1
68
V4
1
65
1
SUB
121
1
86
Drive Timing Chart (Vertical Sync)
NTSC/PAL High Frame Rate Readout Mode
NTSC: 30 frame/s, PAL: 25 frame/s
VD
HD
NTSC
PAL
d
d
V1A
V1B
V2
V3A
V3B
V4
CCD
OUT
Note) The 294H horizontal period in NTSC mode are 1968clk, the 353H in PAL mode is 1152clk.
Drive Timing Chart (Readout)
"d" Enlarged
NTSC/PAL High Frame Rate Readout Mode, AF1 Mode, AF2 Mode
#1
#2
H1
1382 1462
1132
1280
73
73
V1A
V1B
V2
1202
1348
99
1200
1098
1314
V3A
60
V3B
V4
60
1166
1384
86
Drive Timing Chart (Horizontal Sync)
NTSC/PAL High Frame Rate Readout Mode, AF1 Mode, AF2 Mode
2
2
CLK
H1
H2
RG
SHP
SHD
V1A/V1B
V2
V3A/V3B
V4
1
65
1
121
126
1
SUB
Drive Timing Chart (Vertical Sync)
NTSC/PAL AF1 Mode
NTSC: 60 frame/s, PAL: 50 frame/s
VD
HD
NTSC
PAL
f
d
e
f
d
e
V1A
V1B
V2
V3A
V3B
V4
NTSC
PAL
CCD
OUT
Note) The 147H horizontal period in NTSC mode are 2346clk, the 177H in PAL mode is 576clk.
Drive Timing Chart
"e" Enlarged
NTSC/PAL AF1 Mode
27240clk = 10 lines
HD
1
60
V1A/V1B
V2
V3A/V3B
V4
#1
#2
#3
#4
#246
1313131313131313
Drive Timing Chart
"f" Enlarged
NTSC/PAL AF1 Mode, AF2 Mode
27240clk = 10 lines
NTSC: 137H
PAL: 167H
NTSC: 147H
PAL: 177H
NTSC: 1H
PAL: 1H
HD
1
60
V1A/V1B
V2
V3A/V3B
V4
#1
#2
#3
#4
#246
1313131313131313
Drive Timing Chart (Vertical Sync)
NTSC/PAL AF2 Mode
NTSC: 120 frame/s, PAL: 100 frame/s
VD
HD
NTSC
PAL
h
d
g
h
d
g
V1A
V1B
V2
V3A
V3B
V4
NTSC
PAL
CCD
OUT
Note) The 74H horizontal period in NTSC mode are 1173clk, the 88H and 89H in PAL mode is 1506clk.
Drive Timing Chart
"g" Enlarged
NTSC/PAL AF2 Mode
38136clk = 14 lines
HD
1
60
V1A/V1B
V2
V3A/V3B
V4
#1
#2
#3
#4
#360
1313131313131313
Drive Timing Chart
"h" Enlarged
NTSC/PAL AF2 Mode
40860clk = 15 lines
NTSC: 59H
PAL: 73H
NTSC: 73H
PAL: 87H
NTSC: 1H
PAL: 1H
HD
1
60
V1A/V1B
V2
V3A/V3B
V4
#1
#2
#3
#4
#381
1313131313131313
ICX411AQ
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensors.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 30W
soldering iron with a ground wire and solder each pin in less than 2 seconds. For repairs and remount,
cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero-cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operations as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load
more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to
limited portions. (This may cause cracks in the package.)
50N
50N
1.2Nm
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for
installation, use either an elastic load, such as a spring plate, or an adhesive.
– 30 –
ICX411AQ
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to other locations as a precaution.
d) The notch of the package is used for directional index, and that can not be used for reference of fixing.
In addition, the cover glass and seal resin may overlap with the notch of the package.
e) If the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be
generated by the fragments of resin.
f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-
acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives.
(reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods, as color filters will be discolored. When high
luminous objects are imaged with the exposure level controlled by the electronic iris, the luminance of
the image-plane may become excessive and discoloring of the color filter will possibly be accelerated. In
such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the
power-off mode should be properly arranged. For continuous using under cruel condition exceeding the
normal using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
c) Brown stains may be seen on the bottom or side of the package. But this does not affect the CCD
characteristics.
d) This package has 2 kinds of internal structure. However, their package outline, optical size, and strength
are the same.
A
B
The cross section of lead frame can be seen on the side of the package for structure A.
– 31 –
Package Outline
Unit: mm
20 pin DIP
A
6.9
D
20
11
20
11
C
1.7
B
1.7
V
H
1
10
1
10
12.7
0.8
13.8 ± 0.1
'
B
10.0
2.5
1. “A” is the center of the effective image area.
~
2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.
3. The bottom “C” of the package, and the top of the cover glass “D”
1.27
are the height reference.
0.3
4. The center of the effective image area relative to “B” and “B'”
M
is (H, V) = (6.9, 6.0) ± 0.075mm.
0.3
5. The rotation angle of the effective image area relative to H and V is ± 1˚.
PACKAGE STRUCTURE
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm.
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
Plastic
The height from the top of the cover glass “D” to the effective image area is 1.49 ± 0.15mm.
GOLD PLATING
7. The tilt of the effective image area relative to the bottom “C” is less than 50µm.
The tilt of the effective image area relative to the top “D” of the cover glass is less than 50µm.
42 ALLOY
0.95g
8. The thickness of the cover glass is 0.5mm, and the refractive index is 1.5.
PACKAGE MASS
DRAWING NUMBER
9. The notches on the bottom of the package are used only for directional index, they must
not be used for reference of fixing.
AS-B6-04(E)
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