IDT54FCT373ATLB [ETC]
LATCH|SINGLE|8-BIT|FCT/PCT-CMOS|LLCC|20PIN|CERAMIC ;型号: | IDT54FCT373ATLB |
厂家: | ETC |
描述: | LATCH|SINGLE|8-BIT|FCT/PCT-CMOS|LLCC|20PIN|CERAMIC PC |
文件: | 总7页 (文件大小:88K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
FAST CMOS OCTAL
IDT54/74FCT373AT/CT
TRANSPARENT LATCH
FEATURES:
DESCRIPTION:
• A and C grades
TheFCT373Tisanoctaltransparentlatchbuiltusinganadvanceddual
metalCMOStechnology. Theseoctallatcheshave3-stateoutputsandare
intendedforbusorientedapplications. Theflip-flopsappeartransparentto
thedatawhenLatchEnable(LE)ishigh. WhenLEislow,thedatathatmeets
theset-uptimeislatched. DataappearsonthebuswhentheOutputEnable
(OE)islow. WhenOEishigh,thebusoutputisinthehigh-impedancestate.
• Low input and output leakage ≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility:
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High Drive outputs (-15mA IOH, 48mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
• Power off disable outputs permit "live insertion"
• Available in the following packages:
– Industrial: SOIC, SSOP, QSOP, TSSOP
– Military: CERDIP, LCC, CERPACK
FUNCTIONALBLOCKDIAGRAM
D0
D1
D2
D3
D4
D5
D6
D7
D
D
D
D
D
D
D
D
O
O
O
O
O
O
O
O
G
G
G
G
G
G
G
G
LE
OE
O2
O3
O6
O7
O0
O1
O4
O5
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
MAY 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-5496/2
IDT54/74FCT373AT/CT
FASTCMOSOCTALTRANSPARENTLATCH
MILITARYANDINDUSTRIALTEMPERATURERANGES
PINCONFIGURATION
VCC
20
19
18
17
16
15
14
13
12
11
1
2
3
4
INDEX
OE
O0
D0
D1
O1
O7
D7
D6
O6
O5
3
2
20 19
1
4
5
6
7
8
18
17
16
15
14
D1
D7
D6
O6
O5
D5
O1
5
O2
D2
D3
O2
D2
D3
O3
6
D5
D4
O4
LE
7
9
10 11 12 13
8
9
GND
10
LCC
TOP VIEW
CERDIP/ SOIC/ SSOP/ QSOP/ TSSOP/ CERPACK
TOP VIEW
ABSOLUTEMAXIMUMRATINGS(1)
PINDESCRIPTION
Symbol
Description
Max
Unit
V
Pin Names
Description
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +7
Dx
LE
Data Inputs
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
3-State Outputs
TSTG
IOUT
Storage Temperature
DC Output Current
–65 to +150
–60 to +120
°C
mA
OE
Ox
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
FUNCTIONTABLE(1)
Inputs
Outputs
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
Dx
H
L
LE
H
OE
L
Ox
H
H
L
L
X
X
H
Z
CAPACITANCE (TA = +25°C, F = 1.0MHz)
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High Impedance
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
Typ.
Max. Unit
CIN
VIN = 0V
6
8
10
12
pF
pF
COUT
VOUT = 0V
NOTE:
1. This parameter is measured at characterization but not tested.
2
IDT54/74FCT373AT/CT
MILITARYANDINDUSTRIALTEMPERATURERANGES
FASTCMOSOCTALTRANSPARENTLATCH
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%; Military: TA = –55°C to +125°C, VCC = 5.0V ±10%
Symbol
VIH
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2
Typ.(2)
—
Max.
—
Unit
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
VCC = Max.
—
—
—
—
—
—
—
—
—
—
0.8
±1
±1
±1
±1
±1
–1.2
—
V
IIH
Input HIGH Current(4)
Input LOW Current(4)
High Impedance Output Current
(3-State output pins)(4)
Input HIGH Current(4)
ClampDiodeVoltage
Input Hysteresis
VI = 2.7V
VI = 0.5V
VO = 2.7V
VO = 0.5V
—
µA
µA
µA
IIL
VCC = Max.
—
IOZH
IOZL
VCC = Max
—
—
II
VCC = Max., VI = VCC (Max.)
VCC = Min, IIN = -18mA
—
µA
V
VIK
VH
ICC
–0.7
200
0.01
—
mV
µA
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
1
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min
VIN = VIH or VIL
IOH = –6mA MIL
IOH = –8mA IND
IOH = –12mA MIL
IOH = –15mA IND
IOL = 32mA MIL
IOL = 48mA IND
2.4
3.3
—
V
2
3
—
VOL
Output LOWVoltage
VCC = Min
VIN = VIH or VIL
VCC = Max., VO = GND(3)
VCC = 0V, VIN or VO ≤ 4.5V
—
0.3
0.5
V
IOS
Short Circuit Current
Input/Output Power Off Leakage(5)
–60
—
–120
—
–225
±1
mA
µA
IOFF
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
3
IDT54/74FCT373AT/CT
FASTCMOSOCTALTRANSPARENTLATCH
MILITARYANDINDUSTRIALTEMPERATURERANGES
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
—
0.5
2
mA
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
OE = GND
VIN = VCC
VIN = GND
—
0.15
0.25
mA/
MHz
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
Outputs Open
fi = 10MHz
VIN = VCC
VIN = GND
—
—
1.5
1.8
3.5
4.5
mA
mA
50% Duty Cycle
OE = GND
LE = VCC
One Bit Toggling
VIN = 3.4V
VIN = GND
VCC = Max.
Outputs Open
fi = 2.5MHz
VIN = VCC
VIN = GND
—
—
3
5
6(5)
50% Duty Cycle
OE = GND
VIN = 3.4V
VIN = GND
14(5)
LE = VCC
Eight Bits Toggling
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of ∆ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2+ fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Output Frequency
Ni = Number of Outputs at fi
All currents are in milliamps and all frequencies are in megahertz.
4
IDT54/74FCT373AT/CT
MILITARYANDINDUSTRIALTEMPERATURERANGES
FASTCMOSOCTALTRANSPARENTLATCH
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE-INDUSTRIAL
FCT373AT
Min.(2)
FCT373CT
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Parameter
PropagationDelay
Dx to Ox
Condition(1)
CL = 50pF
RL = 500Ω
Max.
Min.(2)
Max.
Unit
1.5
5.2
1.5
4.2
ns
PropagationDelay
LE to Ox
2
8.5
6.5
5.5
2
5.5
5.5
5
ns
ns
ns
OutputEnableTime
1.5
1.5
1.5
1.5
OutputDisableTime
Set-up Time HIGH or LOW, Dx to LE
Hold Time HIGH or LOW, Dx to LE
LE Pulse Width HIGH(3)
2
1.5
5
—
—
—
2
1.5
5
—
—
—
ns
ns
ns
tH
tW
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE-MILITARY
FCT373AT
Min.(2)
FCT373CT
Symbol
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Parameter
PropagationDelay
Dx to Ox
Condition(1)
CL = 50pF
RL = 500Ω
Max.
Min.(2)
Max.
Unit
1.5
5.6
1.5
5.1
ns
PropagationDelay
LE to Ox
2
9.8
7.5
6.5
2
8
ns
ns
ns
OutputEnableTime
1.5
1.5
1.5
1.5
6.3
5.9
OutputDisableTime
Set-up Time HIGH or LOW, Dx to LE
Hold Time HIGH or LOW, Dx to LE
LE Pulse Width HIGH(3)
2
1.5
6
—
—
—
2
1.5
6
—
—
—
ns
ns
ns
tH
tW
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
5
IDT54/74FCT373AT/CT
FASTCMOSOCTALTRANSPARENTLATCH
MILITARYANDINDUSTRIALTEMPERATURERANGES
TESTCIRCUITSANDWAVEFORMS
VCC
SWITCHPOSITION
7.0V
Test
Switch
Closed
Open
500Ω
Open Drain
Disable Low
Enable Low
VOUT
VIN
Pulse
Generator
D.U.T
.
All Other Tests
50pF
500Ω
T
R
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
L
C
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Octal link
Test Circuits for All Outputs
3V
DATA
1.5V
INPUT
0V
LOW-HIGH-LOW
tH
tSU
1.5V
PULSE
3V
1.5V
0V
TIMING
INPUT
ASYNCHRONOUS CONTROL
tW
tREM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
3V
Octal link
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
Pulse Width
Octal link
Set-Up, Hold, and Release Times
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
VOH
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
Octal link
0V
Octal link
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT54/74FCT373AT/CT
MILITARYANDINDUSTRIALTEMPERATURERANGES
FASTCMOSOCTALTRANSPARENTLATCH
ORDERINGINFORMATION
XXXX
XX
X
IDT
XX
FCT
Package
Process
Device Type
Temp. Range
Blank
Industrial
B
MIL-STD-883, Class B
Industrial Options
Small Outline IC
SO
PY
Q
Shrink Small Outline Package
Quarter-size Small Outline Package
Thin Shrink Small Outline Package
PG
Military Options
CERDIP
CERPACK
D
E
L
Leadless Chip Carrier
Fast CMOS Octal Transparent Latch
373AT
373CT
54
74
– 55°C to +125°C
– 40°C to +85°C
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logichelp@idt.com
(408) 654-6459
www.idt.com
7
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