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IDT71V6S85PFI [ETC]

256K x 36, 512K x 18 3.3V Synchronous ZB TM SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs; 256K ×36 ， 512K ×18的3.3V同步ZB TM SRAM的2.5VI / O，突发流量计数器，通过输出
IDT71V6S85PFI
型号： IDT71V6S85PFI
厂家： ETC    ETC
描述：

256K x 36, 512K x 18 3.3V Synchronous ZB TM SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs
256K ×36 ， 512K ×18的3.3V同步ZB TM SRAM的2.5VI / O，突发流量计数器，通过输出

计数器 静态存储器
文件： 总26页 (文件大小：495K)
中文：  中文翻译
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256K x 36, 512K x 18  
IDT71V65702  
IDT71V65902  
3.3VSynchronousZBT™SRAMs  
2.5V I/O, Burst Counter  
Flow-ThroughOutputs  
Features  
◆
256K x 36, 512K x 18 memory configurations  
Supports high performance system speed - 100 MHz  
(7.5 ns Clock-to-Data Access)  
occurs,beitreadorwrite.  
◆
◆
◆
TheIDT71V65702/5902containaddress,data-inandcontrolsignal  
registers.Theoutputsareflow-through(nooutputdataregister).Output  
enable is the only asynchronous signal and can be used to disable the  
outputsatanygiventime.  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
4-word burst capability (Interleaved or linear)  
Individual byte write (BW1-BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
2.5V (±5%) I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA).  
AClockEnable(CEN)pinallowsoperationoftheIDT71V65702/5902  
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored  
whenCENishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot  
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.  
Thedatabuswilltri-stateonecycleafterthechipisdeselectedorawrite  
isinitiated.  
TheIDT71V65702/5902haveanon-chipburstcounter.Intheburst  
mode,theIDT71V65702/5902canprovidefourcyclesofdataforasingle  
address presented to the SRAM. The order of the burst sequence is  
defined by the LBO input pin. The LBO pin selects between linear and  
interleaved burst sequence. The ADV/LD signal is used to load a new  
externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter  
(ADV/LD = HIGH).  
TheIDT71V65702/5902SRAMsutilizeIDT’slatesthigh-performance  
CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm  
100-pin plasticthinquadflatpack(TQFP)aswellasa119 ballgridarray  
(BGA) and 165 fine pitch ball grid array (fBGA).  
◆
◆
◆
◆
◆
◆
◆
◆
Description  
The IDT71V65702/5902 are 3.3V high-speed 9,437,184-bit  
(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x  
18.Theyaredesignedtoeliminatedeadbuscycleswhenturningthe  
busaroundbetweenreadsandwrites,orwritesandreads.Thusthey  
TM  
havebeengiventhenameZBT ,orZeroBusTurnaround.  
AddressandcontrolsignalsareappliedtotheSRAMduringone  
clock cycle, and on the next clock cycle the associated data cycle  
PinDescriptionSummary  
0
18  
A -A  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/ O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
1
2
2
CE , CE , CE  
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
1
2
3
4
Individual Byte Write Selects  
Clock  
BW , BW , BW , BW  
CLK  
ADV/LD  
Advance Burst Address/Load New Address  
Linear/Interleaved Burst Order  
Sleep Mode  
Synchronous  
Static  
LBO  
ZZ  
Asynchronous  
Synchronous  
Static  
I/ O0-I/O31, I/OP1-I/OP4  
Data Input/Output  
Co re Powe r, I/O Powe r  
Ground  
DD DDQ  
V
, V  
Supply  
Supply  
SS  
V
Static  
5315 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
OCTOBER 2004  
1
©2004IntegratedDeviceTechnology,Inc.  
DSC-5315/08  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
Pin Definitions(1)  
Symbol  
Pin Function  
I/O Active  
Description  
A -A  
Address Inputs  
I
N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of  
0
18  
CLK, ADV/LD low, CEN low, and true chip enables.  
ADV/LD  
Advance / Load  
I
N/A ADV/LD is a synchronous input that is used to load the internal registers with new address and control  
when it is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with  
the chip deselected, any burstin progress is terminated. When ADV/LD is sampled high then the  
internal burst counter is advanced for any burst that was in progress. The external addresses are  
ignored when ADV/LD is sampled high.  
R/W  
Read / Write  
Clock Enable  
I
I
N/A R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or  
Write access to the memory array. The data bus activity for the current cycle takes place one clock  
cycle later.  
LOW Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including  
clock are ignored and outputs remain unchanged. The effect of CEN sampled high on the device  
outputs is as if the low to high clock transition did not occur. For normal operation, CEN must be  
sampled low at rising edge of clock.  
CEN  
Individual Byte  
Write Enables  
I
I
LOW Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load  
write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW1-BW4)  
must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write  
signals are ignored when R/W is sampled high. The appropriate byte(s) ofdata are written into the  
device one cycle later. BW1-BW4 can all be tied low if always doing write to the entire 36-bit word.  
-
BW1 BW4  
Chip Enables  
LOW Synchronous active low chip enable. CE1 and CE2 are used with CE2 to enable the IDT71V65702/5902  
(CE1 or CE2 sampled high or CE2 sampled low) and ADV/LD low atthe rising edge of clock, initiates  
CE1, CE2  
TM  
a deselect cycle. The ZBT has a one cycle deselect, i.e., the data bus will tri-state one clock cycle  
after deselect is initiated.  
CE2  
Chip Enable  
Clock  
I
I
HIGH Synchronous active high chip enable. CE2 is used with CE1 and CE2 to enable the chip. CE2 has  
inverted polarity but otherwise identical to CE1 and CE2.  
CLK  
N/A This is the clock input to the IDT71V65702/5902. Except for OE, all timing references for the device are  
made with respect to the rising edge of CLK.  
I/O0-I/O31 Data Input/Output I/O  
I/OP1-I/OP4  
N/A Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The  
data outputpath is flow-through (no output register).  
Linear Burst  
Order  
I
I
I
LOW Burstorder selection input. When LBO is high the Interleaved burst sequence is selected. When LBO  
is low the Linear burst sequence is selected. LBO is a static input, and it must not change during  
device operation.  
LBO  
OE  
ZZ  
Output Enable  
Sleep Mode  
LOW Asynchronous output enable. OE must be low to read data from the 71V65702/5902. When OE is HIGH  
the I/O pins are in a high-impedance state. OE does not need to be actively controlled for read and  
write cycles. In normal operation, OE can be tied low.  
HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the  
IDT71V65702/5902 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode.  
VDD  
Power Supply  
Power Supply  
Ground  
N/A  
N/A  
N/A  
N/A 3.3V core power supply.  
N/A 2.5V I/O supply.  
VDDQ  
V
SS  
N/A Ground.  
5315 tbl 02  
NOTE:  
1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.  
6.422  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
Functional Block Diagram — 256K x 36  
LBO  
256K x 36 BIT  
MEMORY ARRAY  
Address A [0:17]  
D
D
Q
Q
Address  
CE1, CE2  
2
CE  
R/W  
Control  
CEN  
ADV/  
LD  
DI  
DO  
BWx  
D
Q
Control Logic  
Clk  
Mux  
Sel  
Clock  
Gate  
OE  
Data I/O [0:31], I/O P[1:4]  
,
5315 drw 01  
6.42  
3
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
Functional Block Diagram — 512K x 18  
LBO  
512K x 18 BIT  
MEMORY ARRAY  
Address A [0:18]  
D
D
Q
Q
Address  
CE1, CE2  
2
CE  
R/  
W
Control  
CEN  
ADV/  
LD  
DI  
DO  
BWx  
D
Q
Control Logic  
Clk  
Mux  
Sel  
Clock  
Gate  
OE  
Data I/O [0:15], I/O P[1:2]  
,
5315 drw 01a  
RecommendedDCOperating  
Conditions  
Symbol  
VDD  
VDDQ  
VSS  
Parameter  
Core Supply Voltage  
I/O Supply Voltage  
Ground  
Min.  
3.135  
2.375  
0
Typ.  
Max.  
Unit  
V
3.3  
3.465  
2.5  
2.625  
V
0
0
V
____  
VIH  
Input High Voltage - Inputs  
Input High Voltage - I/O  
Input Low Voltage  
1.7  
VDD + 0.3  
VDDQ + 0.3  
0.7  
V
____  
____  
VIH  
1.7  
V
(1)  
VIL  
-0.3  
V
5315 tbl 03  
NOTE:  
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.  
6.442  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
RecommendedOperating  
TemperatureandSupplyVoltage  
Grade  
Ambient  
VSS  
VDD  
VDDQ  
Temperature(1)  
Commercial  
Industrial  
0°C to +70°C  
0V  
0V  
3.3V±5%  
3.3V±5%  
2.5V±5%  
-40°C to +85°C  
2.5V±5%  
5315 tbl 05  
NOTES:  
1. During production testing, the case temperature equals the ambient temperature.  
Pin Configuration — 256K x 36  
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
1
80  
79  
78  
77  
I/OP3  
I/O16  
I/O17  
VDDQ  
VSS  
I/O18  
I/O19  
I/O20  
I/O21  
VSS  
I/OP2  
I/O15  
I/O14  
VDDQ  
VSS  
I/O13  
I/O12  
I/O11  
I/O10  
VSS  
2
3
4
5
76  
75  
74  
73  
6
7
8
9
72  
71  
70  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
VDDQ  
I/O22  
I/O23  
VDDQ  
I/O9  
I/O8  
69  
68  
67  
66  
(1)  
VSS  
VSS  
(1)  
VDD  
VSS  
(2)  
65  
64  
VDD  
VDD  
ZZ  
VSS  
I/O24  
I/O25  
VDDQ  
VSS  
I/O26  
I/O27  
I/O28  
I/O29  
VSS  
63  
62  
I/O7  
I/O6  
VDDQ  
VSS  
I/O5  
I/O4  
I/O3  
I/O2  
VSS  
VDDQ  
I/O1  
I/O0  
I/OP1  
61  
60  
59  
58  
57  
56  
55  
VDDQ  
I/O30  
I/O31  
I/OP4  
54  
53  
,
52  
51  
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
5315 drw 02  
Top View  
100TQFP  
NOTES:  
1. Pins 14 and 66 do not have to be connected directly to VSS as long as the input voltage is ≤ VIL.  
2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is > VIH.  
3. Pins 84 is reserved for a future 16M.  
4. DNU = Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK. The  
current die revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).  
6.42  
5
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
Pin Configuration — 512K x 18  
AbsoluteMaximumRatings(1)  
Commercial &  
Industrial  
Symbol  
Rating  
Unit  
(2)  
VTERM  
Terminal Voltage with  
Respect to GND  
-0.5 to +4.6  
V
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81  
1
80  
NC  
NC  
NC  
DDQ  
10  
A
(3,6)  
VTERM  
Terminal Voltage with  
Respect to GND  
-0.5 to VDD  
V
V
V
2
79  
78  
77  
NC  
NC  
3
4
V
DDQ  
V
V
5
SS  
V
76  
75  
74  
73  
SS  
(4,6)  
VTERM  
Terminal Voltage with  
Respect to GND  
-0.5 to VDD +0.5  
-0.5 to VDDQ +0.5  
6
NC  
NC  
NC  
7
P1  
I/O  
8
8
I/O  
7
I/O  
9
9
I/O  
72  
71  
70  
6
I/O  
(5,6)  
VTERM  
Terminal Voltage with  
Respect to GND  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
SS  
V
DDQ  
V
SS  
V
V
DDQ  
5
69  
68  
67  
66  
10  
I/O  
I/O  
Commercial  
0 to +70  
-40 to +85  
-55 to +125  
-55 to +125  
2.0  
oC  
oC  
oC  
oC  
W
11  
I/O  
4
I/O  
(1)  
SS  
V
SS  
V
V
V
(7)  
TA  
(1)  
DD  
(2)  
SS  
V
DD  
Industrial  
65  
64  
DD  
V
SS  
V
ZZ  
I/O  
I/O  
63  
62  
12  
I/O  
3
TBIAS  
TSTG  
PT  
Temperature Under Bias  
Storage Temperature  
Power Dissipation  
DC Output Current  
13  
I/O  
2
61  
60  
59  
58  
57  
56  
55  
DDQ  
V
DDQ  
V
V
SS  
14  
V
I/O  
SS  
1
I/O  
15  
I/O  
0
I/O  
NC  
NC  
P2  
I/O  
NC  
IOUT  
50  
mA  
SS  
V
SS  
V
V
54  
53  
DDQ  
V
DDQ  
5315 tbl 06  
NC  
NC  
NC  
NC  
NC  
NC  
,
NOTES:  
52  
51  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may  
cause permanent damage to the device. This is a stress rating only and functional  
operation of the device at these or any other conditions above those indicated  
in the operational sections of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect reliability.  
2. VDD terminals only.  
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  
5315 drw 02a  
3. VDDQ terminals only.  
4. Input terminals only.  
5. I/O terminals only.  
6. This is a steady-state DC parameter that applies after the power supply has  
reached its nominal operating value. Power sequencing is not necessary;  
however, the voltage on any input or I/O pin cannot exceed VDDQ during power  
supply ramp up.  
Top View  
100TQFP  
NOTES:  
1. Pins 14 and 66 do not have to be connected directly to VSS as long as the  
input voltage is < VIL.  
2. Pin 16 does not have to be connected directly to VDD as long as the input  
voltage is >VIH.  
7. During production testing, the case temperature equal TA.  
3. Pin 84 is reserved for a future 16M.  
4. DNU = Do not use. Pins 38, 39, 42 and 43 are reserved for respective  
JTAG pins: TMS, TDI, TDO and TCK. The current die revision allows  
these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).  
119BGACapacitance(1)  
(TA = +25°C, f = 1.0MHz)  
100TQFPCapacitance(1)  
(TA = +25°C, f = 1.0MHz)  
Symbol  
Parameter(1)  
Input Capacitance  
I/O Capacitance  
Conditions  
VIN = 3dV  
VOUT = 3dV  
Max. Unit  
Symbol  
CIN  
Parameter(1)  
Input Capacitance  
I/O Capacitance  
Conditions  
VIN = 3dV  
VOUT = 3dV  
Max. Unit  
CIN  
5
7
pF  
7
7
pF  
CI/O  
pF  
CI/O  
pF  
5315 tbl 07  
5315 tbl 07a  
165 fBGA Capacitance(1)  
(TA = +25°C, f = 1.0MHz)  
Symbol  
CIN  
Parameter(1)  
Input Capacitance  
I/O Capacitance  
Conditions  
VIN = 3dV  
VOUT = 3dV  
Max. Unit  
TBD pF  
CI/O  
TBD pF  
5315 tbl 07b  
NOTE:  
1. This parameter is guaranteed by device characterization, but not production tested.  
6.462  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
Pin Configuration — 256K x 36, 119 BGA  
1
2
3
4
5
6
7
DDQ  
6
4
8
16  
DDQ  
V
A
B
C
D
E
F
V
A
A
A
A
A
A
NC(3)  
ADV/LD  
2
3
2
9
A
NC  
NC  
CE  
NC  
NC  
CE2  
15  
7
A
DD  
V
12  
A
A
16  
I/O  
P3  
I/O  
SS  
SS  
SS  
SS  
SS  
SS  
P2  
I/O  
15  
I/O  
V
V
V
NC  
V
V
V
17  
I/O  
18  
I/O  
13  
I/O  
14  
I/O  
1
CE  
OE  
A17  
DDQ  
19  
I/O  
12  
I/O  
DDQ  
V
V
V
V
V
V
20  
I/O  
21  
23  
11  
I/O  
10  
I/O  
I/O  
G
H
J
BW  
2
3
BW  
22  
I/O  
SS  
SS  
9
I/O  
8
I/O  
I/O  
V
V
R/W  
DDQ  
24  
DD  
DD  
V
DD  
V
DDQ  
DD(2)  
SS(1)  
V
V
V
26  
I/O  
SS  
SS  
6
I/O  
7
I/O  
I/O  
V
CLK  
NC  
V
K
L
25  
I/O  
27  
I/O  
4
I/O  
5
I/O  
4
BW  
1
BW  
DDQ  
29  
28  
I/O  
SS  
SS  
SS  
SS  
SS  
SS  
3
I/O  
DDQ  
V
V
V
V
V
V
M
N
P
R
T
CEN  
30  
I/O  
1
0
2
I/O  
1
I/O  
I/O  
A
A
P1  
I/O  
0
I/O  
31  
P4  
I/O  
I/O  
NC  
NC  
,
5
A
DD  
VSS(1)  
14  
13  
A
NC  
ZZ  
V
A
LBO  
10  
11  
NC  
DNU  
A
A
NC  
DNU  
(4)  
(4)  
(4)  
(4)  
(4)  
DDQ  
V
DDQ  
V
DNU  
DNU  
DNU  
U
5315 drw 13a  
Top View  
Pin Configuration — 512K x 18, 119 BGA  
1
2
3
4
5
6
7
DDQ  
6
4
8
16  
DDQ  
V
V
A
A
A
A
A
A
A
A
B
C
D
E
F
NC(3)  
3
2
9
NC  
NC  
CE2  
NC  
NC  
NC  
CE2  
17  
ADV/LD  
7
DD  
V
13  
A
A
A
8
SS  
SS  
SS  
SS  
SS  
SS  
SS  
P1  
I/O  
I/O  
NC  
NC  
V
V
V
NC  
V
V
V
V
9
I/O  
7
I/O  
1
CE  
OE  
A18  
NC  
DDQ  
6
I/O  
DDQ  
V
NC  
V
10  
I/O  
5
I/O  
G
H
J
NC  
NC  
BW  
2
11  
I/O  
SS  
SS  
4
I/O  
NC  
DD  
V
V
V
V
NC  
W
R/  
DD(2)  
SS(1)  
SS  
DDQ  
DD  
V
DD  
DDQ  
V
V
V
V
V
12  
I/O  
SS  
3
NC  
V
CLK  
NC  
NC  
I/O  
NC  
DDQ  
K
L
13  
I/O  
SS  
2
I/O  
NC  
V
V
V
V
BW1  
DDQ  
14  
I/O  
SS  
SS  
SS  
SS  
SS  
SS  
V
V
V
V
NC  
V
M
N
P
R
T
CEN  
15  
I/O  
1
1
I/O  
NC  
A
A
NC  
P2  
I/O  
0
0
I/O  
NC  
NC  
5
DD  
V
12  
NC  
A
VSS(1)  
14  
A
A
NC  
LBO  
15  
10  
11  
NC  
A
A
NC  
A
ZZ  
,
(4)  
(4)  
(4)  
(4)  
DNU  
(4)  
DNU  
DDQ  
DNU  
DDQ  
V
5315 drw 13b  
DNU  
DNU  
U
V
Top View  
NOTES:  
1. R5 and J5 do not have to be directly connected to VSS as long as the input voltage is < VIL.  
2. J3 does not have to be connected directly to VDD as long as the input voltage is ≥ VIH.  
3. A4 is reserved for future 16M.  
4. DNU = Do not use; Pin U2, U3, U4, U5 and U6 are reserved for respective JTAG pins: TMS, TDI, TCK, TDO and TRST. The current die revision allows  
these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).  
6.42  
7
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
Pin Configuration — 256K x 36, 165 fBGA  
1
2
3
4
5
6
7
8
ADV/LD  
OE  
9
10  
11  
(3)  
A
B
C
D
E
F
NC  
NC  
A
7
A
17  
A
8
NC  
CE  
BW  
BW  
CE  
2
CEN  
R/W  
1
3
2
(3)  
(3)  
A
6
CE  
CLK  
NC  
A
9
NC  
2
BW  
BW  
1
4
I/O  
NC  
I/O  
V
V
V
V
V
V
V
NC  
I/O  
I/O  
P3  
DDQ  
SS  
SS  
SS  
SS  
SS  
DDQ  
P2  
I/O  
17  
V
DDQ  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
V
DDQ  
I/O  
14  
16  
15  
I/O  
19  
I/O  
18  
V
DDQ  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
V
DDQ  
I/O  
13  
I/O  
12  
I/O  
I/O  
20  
V
DDQ  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
V
DDQ  
I/O  
11  
I/O  
10  
21  
G
H
J
I/O  
I/O  
V
V
V
V
V
V
V
I/O  
I/O  
8
23  
22  
DDQ  
DD  
SS  
SS  
SS  
DD  
DDQ  
9
(1)  
(2)  
V
SS  
V
DD  
NC  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
NC  
NC  
I/O  
ZZ  
I/O  
I/O  
25  
I/O  
24  
V
DDQ  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
V
DDQ  
7
6
K
L
M
N
P
I/O  
I/O  
V
V
V
V
V
V
V
I/O  
I/O  
4
27  
26  
DDQ  
DD  
SS  
SS  
SS  
DD  
DDQ  
5
I/O  
29  
I/O  
28  
V
DDQ  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
V
DDQ  
I/O  
3
I/O  
2
I/O  
31  
I/O  
30  
V
DDQ  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
V
DDQ  
I/O  
1
I/O  
0
(3)  
(1)  
I/O  
P4  
NC  
V
DDQ  
V
SS  
DNU  
NC  
V
SS  
V
SS  
V
DDQ  
NC  
I/O  
P1  
(3)  
(3)  
(4)  
NC  
LBO  
NC  
A
A
DNU  
A
DNU  
A
10  
A
A
14  
NC  
5
2
1
13  
(3)  
(4)  
(4)  
R
NC  
A
A
DNU  
A
DNU  
A
A
A
15  
A
16  
4
3
0
11  
12  
5315 tbl 25a  
Pin Configuration — 512K x 18, 165 fBGA  
1
2
3
4
5
6
7
8
ADV/LD  
OE  
9
10  
11  
(3)  
A
B
C
D
E
F
NC  
NC  
NC  
NC  
NC  
NC  
NC  
A
NC  
A
18  
A
8
A
10  
7
CE  
BW  
CE  
2
CEN  
R/W  
1
2
(3)  
(3)  
A
6
CE  
2
NC  
CLK  
NC  
A
9
NC  
BW  
1
NC  
I/O  
V
DDQ  
V
SS  
V
SS  
V
SS  
V
SS  
V
SS  
V
NC  
NC  
NC  
NC  
NC  
NC  
I/O  
P1  
DDQ  
V
DDQ  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
V
I/O  
7
8
DDQ  
I/O  
V
DDQ  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
V
I/O  
6
9
DDQ  
I/O  
10  
V
DDQ  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
V
I/O  
5
DDQ  
G
H
J
I/O  
V
DDQ  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
V
I/O  
4
11  
DDQ  
(1)  
(2)  
V
V
DD  
NC  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
NC  
ZZ  
NC  
NC  
NC  
NC  
NC  
NC  
SS  
I/O  
NC  
NC  
NC  
NC  
NC  
V
DDQ  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
V
I/O  
3
12  
DDQ  
K
L
M
N
P
I/O  
V
DDQ  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
V
I/O  
2
13  
DDQ  
I/O  
V
DDQ  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
V
I/O  
1
14  
DDQ  
I/O  
V
DDQ  
V
DD  
V
SS  
V
SS  
V
SS  
V
DD  
V
I/O  
0
15  
DDQ  
(4)  
(1)  
I/O  
V
DDQ  
V
SS  
DNU  
NC  
V
V
SS  
V
DDQ  
NC  
P2  
SS  
(4)  
(4)  
(3)  
NC  
LBO  
NC  
A
5
A
2
DNU  
A
1
DNU  
A
11  
A
14  
A
15  
(4)  
(4)  
(3)  
R
NC  
A4  
A
3
DNU  
A
0
DNU  
A
12  
A
13  
A
16  
A
17  
5315 tbl25b  
NOTES:  
1. Pins H1 and N7 do not have to be directly connected to VSS as long as the input voltage is < VIL.  
2. Pin H2 does not have to be connected directly to VDD as long as the input voltage is ≥ VIH.  
3. Pins B9, B11, A1, R2 and P2 are reserved for future 18M, 36M, 72M, 144 and 288M respectively.  
4. DNU = Do not use. Pins P5, R5, P7, R7 and N5 are reserved for respective JTAG pins: TDI, TMS, TDO, TCK and TRST on future revisions. The current  
die revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).  
6.482  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
SynchronousTruthTable(1)  
CEN  
CE ,CE (5 )  
1
2
R/W  
ADV/LD  
BWx  
ADDRESS  
USED  
PREVIOUS CYCLE  
CURRENT CYCLE  
I/O  
(One cycle later)  
(7 )  
L
L
L
L
H
X
L
L
X
L
L
H
Valid  
X
External  
External  
Internal  
X
X
LOAD WRITE  
LOAD READ  
D
(7 )  
Q
(7 )  
Valid  
LOAD WRITE /  
BURST WRITE  
BURST WRITE  
D
(Advance burst counter)(2 )  
(7 )  
L
X
X
H
X
Internal  
LOAD READ /  
BURST READ  
BURST READ  
Q
(Advance burst counter)(2 )  
L
L
H
X
X
X
H
X
X
L
H
X
X
X
X
X
X
X
X
DESELECT or STOP(3 )  
NOOP  
HIZ  
HIZ  
DESELECT / NOOP  
X
(4 )  
SUSPEND  
Previous Value  
5315 tbl 08  
NOTES:  
1. L = VIL, H = VIH, X = Don’t Care.  
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of  
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.  
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will  
tri-state one cycle after deselect is initiated.  
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the  
I/Osremainsunchanged.  
5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.  
6. Device Outputs are ensured to be in High-Z during device power-up.  
7. Q - data read from the device, D - data written to the device.  
Partial Truth Table for Writes(1)  
(3 )  
(3 )  
BW1  
X
BW2  
X
BW3  
BW4  
OPERATION  
R/W  
H
L
READ  
X
L
X
L
WRITE ALLBYTES  
WRITE BYTE 1 (I/O[0:7], I/OP1)  
L
L
(2 )  
(2 )  
L
L
H
H
H
L
H
H
H
L
WRITE BYTE 2 (I/O[8:15], I/OP2)  
L
H
L
(2,3)  
WRITE BYTE 3 (I/O[16:23], I/OP3)  
L
H
H
(2,3)  
WRITE BYTE 4 (I/O[24:31], I/OP4)  
NO WRITE  
L
H
H
H
H
L
H
H
H
5315 tbl 09  
NOTES:  
1. L = VIL, H = VIH, X = Don’t Care.  
2. Multiple bytes may be selected during the same cycle.  
3. N/A for x18 configuration.  
Interleaved Burst Sequence Table (LBO=VDD)  
Sequence 1  
Sequence 2  
Sequence 3  
Sequence 4  
A1  
A0  
0
A1  
A0  
1
A1  
A0  
0
A1  
1
A0  
First Address  
0
0
1
1
0
0
1
1
1
1
0
0
1
Second Address  
Third Address  
1
0
1
1
0
0
1
0
0
1
Fourth Address(1)  
1
0
1
0
0
5315 tbl 10  
NOTE:  
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.  
6.42  
9
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
LinearBurstSequenceTable(LBO=VSS)  
Sequence 1  
Sequence 2  
Sequence 3  
Sequence 4  
A1  
A0  
0
A1  
0
A0  
1
A1  
A0  
0
A1  
A0  
First Address  
0
0
1
1
1
1
0
0
1
0
0
1
1
Second Address  
Third Address  
1
1
0
1
0
0
1
1
0
1
Fourth Address(1)  
1
0
0
1
0
5315 tbl 11  
NOTE:  
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.  
FunctionalTimingDiagram(1)  
CYCLE  
n+29  
n+30  
n+31  
n+32  
n+33  
n+34  
n+35  
n+36  
n+37  
CLOCK  
(2)  
(2)  
ADDRESS  
A29  
C29  
A30  
C30  
A31  
C31  
A32  
C32  
A33  
C33  
A34  
C34  
A35  
C35  
A36  
C36  
A37  
C37  
(A0 - A17  
)
CONTROL  
(R/W, ADV/LD, BWx)  
(2)  
DATA  
D/Q28  
D/Q29  
D/Q30  
D/Q31  
D/Q32  
D/Q33  
D/Q34  
D/Q35  
D/Q36  
I/O [0:31], I/O P[1:4]  
,
5315 drw 03  
NOTES:  
1. This assumes CEN, CE1, CE2 and CE2 are all true.  
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data  
delay from the rising edge of clock.  
6.1402  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles(2)  
(1 )  
CEN  
BWx  
OE  
Cycle  
Address  
R/W  
ADV/LD  
I/O  
Comments  
CE1  
n
A0  
X
H
X
H
X
X
H
X
X
L
L
H
L
L
H
L
H
L
L
H
L
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
L
X
L
D1  
Q0  
Load read  
Burst read  
n+1  
X
L
n+2  
A1  
X
L
Q0+1 Load read  
n+3  
H
X
L
L
Q1  
Z
Deselect or STOP  
n+4  
X
X
X
L
NOOP  
n+5  
A2  
X
Z
Load read  
Burst read  
n+6  
X
H
L
Q2  
n+7  
X
L
Q2+1 Deselect or STOP  
n+8  
A3  
X
X
X
X
X
X
X
X
L
Z
Load write  
Burst write  
n+9  
X
L
X
L
L
D3  
n+10  
n+11  
n+12  
n+13  
n+14  
n+15  
n+16  
n+17  
n+18  
n+19  
A4  
X
L
D3+1 Load write  
X
X
L
H
X
L
X
X
L
D4  
Z
Deselect or STOP  
X
NOOP  
A5  
A6  
A7  
X
Z
Load write  
Load read  
Load write  
Burst write  
H
L
L
X
L
D5  
Q6  
D7  
L
X
H
X
L
X
L
L
X
X
L
A8  
X
X
X
L
D7+1 Load read  
Q8 Burst read  
Q8+1 Load write  
X
L
A9  
L
5315 tbl 12  
NOTES:  
1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.  
2. H = High; L = Low; X = Don't Care; Z = High Impedence.  
6.42  
11  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
ReadOperation(1)  
(2 )  
CEN  
BWx  
OE  
Cycle  
Address  
R/W  
ADV/LD  
I/O  
Comments  
CE1  
n
A0  
X
H
X
L
L
L
X
X
X
L
X
Address and Control meet setup  
Contents of Address A0 Read Out  
n+1  
X
X
X
Q0  
5315 tbl 13  
NOTES:  
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.  
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.  
Burst Read Operation(1)  
(2 )  
CEN  
BWx  
OE  
Cycle  
Address  
R/W  
ADV/LD  
I/O  
Comments  
CE1  
n
A0  
X
H
X
X
X
X
H
X
H
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
X
Address and Control meet setup  
Address A0 Read Out, Inc. Count  
Address A0+1 Read Out, Inc. Count  
Address A0+2 Read Out, Inc. Count  
Address A0+3 Read Out, Load A1  
Address A0 Read Out, Inc. Count  
Address A1 Read Out, Inc. Count  
Address A1+1 Read Out, Load A2  
n+1  
n+2  
n+3  
n+4  
n+5  
n+6  
n+7  
X
X
X
X
L
Q0  
X
Q0+1  
Q0+2  
Q0+3  
Q0  
X
X
A1  
X
H
L
X
L
Q1  
A2  
Q1+1  
5315 tbl 14  
NOTES:  
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.  
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.  
Write Operation(1)  
(2 )  
CEN  
BWx  
OE  
Cycle  
Address  
R/W  
ADV/LD  
I/O  
Comments  
CE1  
n
A0  
X
L
L
L
L
L
L
X
X
X
Address and Control meet setup  
Write to Address A0  
n+1  
X
X
X
X
D0  
5315 tbl 15  
NOTES:  
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.  
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.  
Burst Write Operation(1)  
(2 )  
CEN  
BWx  
OE  
Cycle  
Address  
R/W  
ADV/LD  
I/O  
Comments  
CE1  
n
A0  
X
L
X
X
X
X
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
Address and Control meet setup  
Address A0 Write, Inc. Count  
Address A0+1 Write, Inc. Count  
Address A0+2 Write, Inc. Count  
Address A0+3 Write, Load A1  
Address A0 Write, Inc. Count  
Address A1 Write, Inc. Count  
Address A1+1 Write, Load A2  
n+1  
n+2  
n+3  
n+4  
n+5  
n+6  
n+7  
X
X
X
X
L
D0  
X
D0+1  
D0+2  
D0+3  
D0  
X
X
A1  
X
X
L
H
L
X
L
D1  
A2  
D1+1  
5315 tbl 16  
NOTES:  
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.  
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.  
6.1422  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
Read Operation with Clock Enable Used(1)  
(2 )  
CEN  
BWx  
OE  
Cycle  
Address  
R/W  
ADV/LD  
I/O  
Comments  
CE1  
n
A0  
X
H
X
H
X
X
H
H
H
L
X
L
X
X
L
L
L
L
L
H
L
H
H
L
L
L
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
X
X
AddressA0 and Control meet setup  
Clock n+1 Ignored  
n+1  
n+2  
n+3  
n+4  
n+5  
n+6  
n+7  
X
L
A1  
X
Q0  
Q0  
Q0  
Q1  
Q2  
Q3  
Address A0 Read out, Load A1  
Clock Ignored. Data Q0 is on the bus.  
Clock Ignored. Data Q0 is on the bus.  
Address A1 Read out, Load A2  
Address A2 Read out, Load A3  
Address A3 Read out, Load A4  
X
X
L
X
A2  
A3  
A4  
L
L
5315 tbl 17  
NOTES:  
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.  
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.  
Write Operation with Clock Enable Used(1)  
(2 )  
CEN  
BWx  
OE  
Cycle  
Address  
R/W  
ADV/LD  
I/O  
Comments  
CE1  
n
A0  
X
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
L
H
L
H
H
L
L
L
L
X
L
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
Address A0 and Control meet setup.  
Clock n+1 Ignored.  
n+1  
n+2  
n+3  
n+4  
n+5  
n+6  
n+7  
X
L
A1  
X
D0  
X
Write data D0, Load A1.  
Clock Ignored.  
X
X
L
X
X
Clock Ignored.  
A2  
A3  
A4  
D1  
D2  
D3  
Write Data D1, Load A2  
Write Data D2, Load A3  
Write Data D3, Load A4  
L
L
5315 tbl 18  
NOTES:  
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.  
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.  
6.42  
13  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
Read Operation with Chip Enable Used(1)  
(2 )  
(3 )  
CEN  
BWx  
OE  
Cycle  
Address  
R/W  
ADV/LD  
Comments  
CE1  
H
H
L
I/O  
n
X
X
X
X
H
X
H
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
L
?
Z
Deselected.  
n+1  
n+2  
n+3  
n+4  
n+5  
n+6  
n+7  
n+8  
n+9  
Deselected.  
A0  
X
Z
Address A0 and Control meet setup.  
Address A0 read out, Deselected.  
Address A1 and Control meet setup.  
Address A1 read out, Deselected.  
Deselected.  
H
L
Q0  
Z
A1  
X
X
L
H
H
L
Q1  
Z
X
X
X
L
A2  
X
Z
Address A2 and Control meet setup.  
Address A2 read out, Deselected.  
Deselected.  
H
H
Q2  
Z
X
X
5315 tbl 19  
NOTES:  
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.  
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.  
3. Device outputs are ensured to be in High-Z during device power-up.  
Write Operation with Chip Enable Used(1)  
CE(2 )  
H
H
L
CEN  
BWx  
OE  
Cycle  
Address  
R/W  
ADV/LD  
I/O  
Comments  
n
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
?
Z
Deselected.  
n+1  
n+2  
n+3  
n+4  
n+5  
n+6  
n+7  
n+8  
n+9  
Deselected.  
A0  
X
Z
Address A0 and Control meet setup  
Data D0 Write In, Deselected.  
Address A1 and Control meet setup  
Data D1 Write In, Deselected.  
Deselected.  
X
L
H
L
X
L
D0  
Z
A1  
X
X
X
L
H
H
L
X
X
L
D1  
Z
X
A2  
X
Z
Address A2 and Control meet setup  
Data D2 Write In, Deselected.  
Deselected.  
X
X
H
H
X
X
D2  
Z
X
5315 tbl 20  
NOTES:  
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.  
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.  
6.1442  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
DC Electrical Characteristics Over the Operating  
Temperature and Supply Voltage Range (VDD = 3.3V±5%)  
Symbol  
Parameter  
Input Leakage Current  
Test Conditions  
Min.  
Max.  
Unit  
___  
|ILI|  
VDD = Max., VIN = 0V to VDD  
5
µA  
(1 )  
___  
___  
___  
LBO Input Leakage Current  
|ILI|  
VDD = Max., VIN = 0V to VDD  
VOUT = 0V to VCC  
30  
5
µA  
µA  
V
|ILO|  
VOL  
VOH  
Output Leakage Current  
Output Low Voltage  
Output High Voltage  
IOL = +6mA, VDD = Min.  
IOH = -6mA, VDD = Min.  
0.4  
___  
2.0  
V
5001 tbl 21  
NOTE:  
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.  
DC Electrical Characteristics Over the Operating  
Temperature and Supply Voltage Range(1) (VDD = 3.3V±5%)  
7.5ns  
8ns  
8.5ns  
Unit  
Symbol  
Parameter  
Operating Power  
Test Conditions  
Device Selected, Outputs Open,  
Com'l  
Ind  
Com'l  
Ind  
Com'l  
Ind  
IDD  
Supply Current  
ADV/LD = X, VDD = Max.,  
VIN > VIH or < VIL, f = fMAX  
275  
295  
250  
270  
225  
245  
mA  
mA  
mA  
mA  
(2)  
CMOS Standby Power  
Supply Current  
Device Deselected, Outputs Open,  
VDD = Max., VIN > VHD or < VLD,  
f = 0(2,3)  
ISB1  
ISB2  
ISB3  
IZZ  
40  
105  
40  
60  
125  
60  
40  
100  
40  
60  
120  
60  
40  
95  
40  
40  
60  
115  
60  
Clock Running Power  
Supply Current  
Device Deselected, Outputs Open,  
VDD = Max., VIN > VHD or < VLD,  
(2,3)  
f = fMAX  
Idle Power  
Supply Current  
Device Selected, Outputs Open,  
CEN > VIH, VDD = Max.,  
VIN > VHD or < VLD, f = fMAX  
(2,3)  
Full Sleep Mode  
Supply Current  
Device Selected, Outputs Open  
CEN  
IL DD  
≤ V , V = Max., ZZ ≥ V  
HD  
40  
60  
40  
60  
60  
mA  
(2,3)  
IN  
V
≥
HD  
V
≤
LD  
MAX  
or V , f = f  
5315 tbl 22  
NOTES:  
1. All values are maximum guaranteed values.  
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.  
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.  
V
DDQ/2  
AC Test Conditions  
AC Test Load  
50  
Ω
Input Pulse Levels  
0 to 2.5V  
2ns  
I/O  
0
Z = 50Ω  
Input Rise/Fall Times  
Input Timing Reference Levels  
Output Reference Levels  
Output Load  
,
5315 drw 04  
6
5
4
VDDQ/2  
VDDQ/2  
Figure 1  
Figure 1. AC Test Load  
•
3
5315 tbl 23  
∆tCD  
(Typical, ns)  
2
•
•
1
•
•
20 30 50  
80 100  
Capacitance (pF)  
200  
5315 drw 05  
,
Figure 2. Lumped Capacitive Load, Typical Derating  
6.42  
15  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
AC Electrical Characteristics  
(VDD = 3.3V±5%, Commercial and Industrial Temperature Ranges)  
7.5ns  
8ns  
8.5ns  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
____  
____  
____  
____  
____  
____  
tCY C  
Clock Cycle Time  
10  
2.5  
2.5  
10.5  
2.7  
11  
3.0  
3.0  
ns  
ns  
ns  
(1)  
Clock High Pulse Width  
Clock Low Pulse Width  
tCH  
____  
____  
____  
(1)  
2.7  
tCL  
Output Parameters  
____  
____  
____  
tCD  
Clock High to Valid Data  
7.5  
8
8.5  
ns  
ns  
ns  
____  
____  
____  
tCDC  
Clock High to Data Change  
Clock High to Output Active  
Clock High to Data High-Z  
Output Enable Access Time  
2
2
2
____  
____  
____  
(2,3,4)  
3
3
3
tCL Z  
____  
____  
____  
(2,3,4)  
5
5
5
ns  
ns  
ns  
ns  
tCHZ  
____  
____  
____  
tOE  
5
5
5
____  
____  
____  
(2,3)  
Output Enable Low to Data Active  
Output Enable High to Data High-Z  
0
0
0
tOLZ  
____  
____  
____  
(2,3)  
5
5
5
tOHZ  
Set Up Times  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
tSE  
Clock Enable Setup Time  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
2.0  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSA  
Address Setup Time  
tSD  
Data In Setup Time  
tSW  
Read/Write (R/W) Setup Time  
Advance/Load (ADV/LD) Setup Time  
Chip Enable/Select Setup Time  
Byte Write Enable (BWx) Setup Time  
tSADV  
tSC  
tSB  
Hold Times  
tHE  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
Clock Enable Hold Time  
Address Hold Time  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
0.5  
ns  
ns  
ns  
ns  
ns  
ns  
tHA  
tHD  
Data In Hold Time  
tHW  
Read/Write (R/W) Hold Time  
Advance/Load (ADV/LD) Hold Time  
Chip Enable/Select Hold Time  
tHADV  
tHC  
tHB  
Byte Write Enable ( x) Hold Time  
BW  
ns  
5315 tbl 24  
NOTES:  
1. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.  
2. Transition is measured ±200mV from steady-state.  
3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.  
4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.  
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,  
which is a Max. parameter (worse case at 70 deg. C, 3.135V).  
6.1462  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
Timing Waveform of Read Cycle(1,2,3,4)  
,
6.42  
17  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
Timing Waveform of Write Cycles(1,2,3,4,5)  
,
6.1482  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
Timing Waveform of Combined Read and Write Cycles(1,2,3)  
,
6.42  
19  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
Timing Waveform of CEN Operation(1,2,3,4)  
,
6.2402  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
Timing Waveform of CS Operation(1,2,3,4)  
,
,
6.42  
21  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
100-Pin Thin Quad Plastic Flatpack (TQFP) Package Diagram Outline  
6.2422  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
119 Ball Grid Array (BGA) Package Diagram Outline  
6.42  
23  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline  
6.2442  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
Timing Waveform of OE Operation(1)  
OE  
tOE  
tOHZ  
tOLZ  
DATAOUT  
Q
Q
,
5315 drw 11  
NOTE:  
1. A read operation is assumed to be in progress.  
OrderingInformation  
XX  
IDT  
XXXX  
S
XX  
XX  
Package  
Process/Temp  
Range  
Device  
Type  
Power Speed  
,
Blank  
I
Commercial (0°C to +70°C)  
Industrial (-40°C to +85°C)  
100-pin Plastic Thin Quad Flatpack (TQFP)  
119 Ball Grid Array (BGA)  
165 Fine Pitch Ball Grid Array (fBGA)  
PF  
BG  
BQ  
75  
80  
85  
Access time (tCD) in tenths of nanoseconds  
IDT71V65702  
IDT71V65902  
256Kx36 Flow-Through ZBT SRAM  
512Kx18 Flow-Through ZBT SRAM  
5315 drw 12  
6.42  
25  
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with  
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs  
Commercial and Industrial Temperature Range  
DatasheetDocumentHistory  
12/31/99  
04/20/00  
Creatednewdatasheetfromobsoletedevices IDT71V657andIDT71V659  
Pg.5,6  
AddedJTAGtestpinstoTQFPpinconfiguration;removedfootnote  
AddclarificationnotetoRecommendedOperatingTemperaturesandAbsoluteMaxRatingtable  
AddnotetoBGApinconfiguration;correctedtypowithinpinout  
InsertTQFPpackageDiagramOutline  
Pg. 7  
Pg. 21  
05/23/00  
07/28/00  
Addednewpackageoffering:13mmx15mm,165fBGA  
Correctionon119BGAPackageDiagramOutline  
Remove JTAG pins from TQFP, BG119 and BQ165 pinouts refer to IDT71V656xx and  
IDT71V658xx Device errata sheet  
Pg. 23  
Pg. 5-8  
Pg. 7,8  
Pg. 23  
Pg. 8  
Correct error in pinout, B2 on BG119 and B1 on BQ165 pinout  
UpdateBG119PackageDiagramDimensions  
Add reference note to pin N5, BQ165 pinout, reserved for JTAG TRST  
AddIzztoDCElectricalCharacteristics  
11/04/00  
Pg. 15  
08/08/02  
12/04/02  
Pg.5,6,15,16,25 AddedIndustrialinformationtodatasheet.  
Pg. 1-26  
Pg. 6  
Pg. 1,2,5,6,7,8  
Pg. 7  
Pg. 5& 6  
Pg. 7  
ChangeddatasheetfromPrelininarytofinalrelease.  
CorrectedAbsolute Max. table (AddedItemptoheadingintable)  
RemovedJTAGfunctionalityforcurrentdierevision.  
Correctedpinconfigurationx36,119BGA. SwitchedI/O0andI/OP1.  
UpdatedtemperatureTanote.  
12/18/02  
10/15/04  
Updated pin configuration 512K x 18 for the 119 BGA - reordered I/O signals on P7, N6, L6, K7,  
H6, G7, F6, E7, D6.  
CORPORATE HEADQUARTERS  
2975StenderWay  
Santa Clara, CA 95054  
for SALES:  
for Tech Support:  
sramhelp@idt.com  
800-544-7726  
800-345-7015 or 408-727-6116  
fax: 408-492-8674  
www.idt.com  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
6.2462  

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IDT

IDT71V802S150BQI

 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect
IDT

IDT71V802S150PF

 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect
IDT

IDT71V802S150PFI

 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect
IDT
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