ILC7082AIM5-47 [ETC]
Positive Fixed Voltage Regulator ; 正固定电压稳压器\n
| 型号： | ILC7082AIM5-47 |
| 厂家： | 
ETC |
| 描述： | Positive Fixed Voltage Regulator
|
| 文件： | 总15页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
www.fairchildsemi.com
ILC7082
150mA SOT-23 Ultra Low Noise CMOS RF-LDO™
Regulator
Features
Description
• Ultra low 1mV dropout per 1mA load
• 1% output voltage accuracy
• Only 30mVRMS noise
• Uses low ESR ceramic output capacitor to minimize noise
and output ripple
• Only 100mA ground current at 100mA load
• Ripple rejection up to 85dB at 1kHz, 60dB at 1MHz
• Excellent line and load transient response
• Over current / over temperature protection
• Guaranteed to 150mA output current
• Industry standard five lead SOT-23 package
• Fixed 2.8V, 3.0V, 3.3V,3.6V, 4.7V, 5.0V and adjustable
output voltage options
The ILC7082 is a 150mA low dropout (LDO) voltage
regulator designed to provide a high performance solution
to low power systems. The device offers a typical
combination of low dropout and low quiescent current
expected of CMOS parts, while uniquely providing the low
noise and high ripple rejection characteristics usually only
associated with bipolar LDO regulators.
The device has been optimized to meet the needs of modern
wireless communications design; Low noise, low dropout,
small size, high peak current, high noise immunity.
The ILC7082 is designed to make use of low cost ceramic
capacitors while outperforming other devices that require
tantalum capacitors.
• Metal mask option available for custom voltages between
2.5V and 10V
Applications
• Cellular phones
• Wireless communicators
• PDAs / palmtops / organizers
• Battery powered portable electronics
Typical Applications
VOUT
5
1
4
SOT-23-5
ILC7082
2
COUT
CNOISE
3
VIN
ON
CIN
OFF
Rev. 1.4
©2001 Fairchild Semiconductor Corporation
ILC7082
Pin Assignments
VOUT
CNOISE
VOUT
VADJ
5
4
5
4
SOT-23-5
SOT-23-5
ILC7082-xx
ILC7082-xx
1
2
3
1
2
3
VIN
VIN
GND
ON/OFF
GND
ON/OFF
FixedVoltage option
Adjustable Voltage option
PIN DESCRIPTION ILC7082-xx (fixed voltage version)
Pin Number
Pin Name
VIN
Pin Description
1
2
Connect directly to supply
Ground pin. Local ground for CNOISE and COUT
GND
.
3
4
ON/OFF
CNOISE
By applying less than 0.4V to this pin the device will be turned off.
Optional noise bypass capacitor may be connected between this pin and
GND (pin 2). Do not connect CNOISE directly to the main power ground plane.
Output Voltage. Connect COUT between this pin and GND (pin 2).
5
VOUT
PIN DESCRIPTION ILC7082-AIK-XX (SOIC fixed voltage version)
Pin Num-
ber
Pin Name
Pin Description
1
2
GND
Connect directly to supply
ON/OFF
Ground pin. Local ground for CNOISE and COUT
.
3
VIN
Connect directly to supply
4
5
6
N/C
N/C
No Connection
No Connection
VOUT
Output Voltage. Connect COUT between this pin and GND (pin 2).
7
8
N/C
N/C
No Connection
No Connection
©2001 Fairchild Semiconductor Corporation
2
ILC7082
PIN DESCRIPTION ILC7082-ADJ (adjustable voltage version)
Pin Number
Pin Name
VIN
Pin Description
1
2
Connect directly to supply
Ground pin. Local ground for CNOISE and COUT
By applying less than 0.4V to this pin the device will be turned off.
GND
.
3
4
ON/OFF
VADJ
Voltage feedback pin to set the adjustable output voltage. Do not connect a capacitor to
this pin.
5
VOUT
Output Voltage. Connect COUT between this pin and GND (pin 2).
Internal Block Diagram
VIN
CNOISE
INTERNAL
V
DD
BANDGAP
REFERENCE
TRANS-
V
ERROR AMPLIFIER
REFD
CONDUCTANCE
AMPLIFIER
VOUT
FEEDBACK
GND
ON/OFF
Absolute Maximum Ratings
Parameter
Input Voltage
Symbol
Ratings
-0.3 to +13.5
-0.3 to VIN
Units
VIN
V
VON/OFF
On/Off Input Voltage
Output Current
Short circuit protected
-0.3 to VIN+0.3
250 (Internally Limited)
-40~+150
IOUT
VOUT
PD
mA
V
Output Voltage
Package Power Dissipation (SOT-23-5)
Maximum Junction Temp Range
Storage Temperature
mW
°C
TJ(max)
TSTG
TA
-40~+125
°C
Operating Ambient Temperature
Package Thermal Resistance
-40 to +85
°C
333
°C/W
θJA
©2001 Fairchild Semiconductor Corporation
3
ILC7082
ELECTRICAL CHARACTERISTICS ILC7082AIM5
Unless otherwise specified, all limits are at TA=25°C; VIN = VOUT(NOM) +1V, IOUT = 1mA, COUT = 1µF, VON/OFF = 2V..
The • denotes specifications which apply over the specified operating temperature range.
Parameter
Symbol
Conditions
Min
Typ
Max Units
Input Voltage Range
2
13
V
•
VIN
Iout = 1mA
-1
VOUT(NOM)
VOUT(NOM)
+1
1mA < IOUT < 100mA
1mA < IOUT < 100mA
1mA < IOUT < 150mA
1mA < IOUT < 150mA
-1.5
-2.5
+1.5
+2.5
%VOUT
•
•
VOUT
Output Voltage
(NOTM)
-2.5
-3.5
VOUT(NOM)
+2.5
+3.5
Feedback Voltage
(ADJ version)
1.215
1.202
1.240
0.007
1.265
1.278
0.014
0.032
V
VADJ
•
•
%/V
V
∆
/
OUT
VOUT(NOM) +1V < VIN < 12V
Line Regulation
(VOUT* V )
∆
IN
0.1
10
1
2
IOUT= 0mA (Note 4)
•
•
•
•
•
•
•
•
•
25
35
IOUT = 10mA
IOUT = 50mA
Dropout Voltage
(Note 3)
50
75
V
IN - VOUT
mV
100
150
200
225
300
200
220
220
240
220
240
240
260
260
280
2
100
150
95
IOUT = 100mA
I
OUT = 150mA
IOUT = 0mA
OUT = 10mA
IOUT = 50mA
100
100
100
115
0.1
I
IGND
Ground Pin Current
µA
I
I
OUT = 100mA
OUT = 150mA
•
•
Shutdown (OFF) Current
ON/OFF Input Voltage
VON/OFF = 0V
µA
µA
ION/OFF
High = Regulator On
Low = Regulator Off
1.5
13
0.6
•
•
VON/OFF
ON/OFF Pin Input
Current (Note 5)
VON/OFF = 0.6V, regulator OFF
0.3
1
IIN( ON/OFF)
VON/OFF = 2V, regulator ON
Peak Output Current
(Note 4)
VOUT > 0.95VOUT(NOM)
tpw = 2ms
,
400
500
mA
IOUT(peak)
eN
Output Noise Voltage
(RMS)
BW = 300Hz to 50kHz, CIN = 1µF
NOISE = 0.01µF, COUT = 2.2µF,
30
µVRMS
C
IOUT = 10mA
Ripple Rejection
COUT = 4.7µF,
Freq. = 1kHz
Freq. = 10kHz
Freq. = 1MHz
85
70
60
14
V
/ V
∆
IN
∆
OUT
dB
I
OUT = 100mA
Dynamic Line Regulation
VIN: VOUT(NOM) + 1V to
OUT(NOM) + 2V,
mV
V
∆
OUT(line)
V
tr/tf = 2ms; IOUT = 150mA
Dynamic Load Regulation
Short Circuit Current
IOUT: 1mA to 150mA; tr < 5µS
40
mV
mA
V
∆
OUT(load)
VOUT = 0V
600
ISC
©2001 Fairchild Semiconductor Corporation
4
ILC7082
Notes:
1: Absolute maximum ratings indicate limits which when exceeded may result in damage to the component. Electrical specifica-
tions do not apply when operating the device outside of its rated operating conditions.
2: Specified Min/Max limits are production tested or guaranteed through correlation based on statistical control methods. Mea-
surements are taken at constant junction temperature as close to ambient as possible using low duty pulse testing.
3: Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the nominal
value measured with an IV differential.
4: Guaranteed by design
5: The device’s shutdown pin includes a 2MΩ internal pulldown resistor connected to ground.
OPERATION
DOMINANT POLE
The ILC7082 LDO design is based on an advanced circuit
85 dB
configuration for which patent protection has been applied.
Typically it is very difficult to drive a capacitive output with
an amplifier. The output capacitance produces a pole in the
feedback path, which upsets the carefully tailored dominant
pole of the internal amplifier. Traditionally the pole of the
OUTPUT POLE
output capacitor has been “eliminated” by reducing the
output impedance of the regulator such that the pole of the
output capacitor is moved well beyond the gain bandwidth
COMPENSATING
ZERO
product of the regulator. In practice, this is difficult to do and
UNITY GAIN
still maintain high frequency operation. Typically the output
impedance of the regulator is not simply resistive, such that
the reactive output impedance interacts with the reactive
FREQUENCY
impedance of the load resistance and capacitance. In
addition, it is necessary to place the dominant pole of the
circuit at a sufficiently low frequency such that the gain of
the regulator has fallen below unity before any of the
complex interactions between the output and the load occur.
The ILC7082 does not try to eliminate the output pole, but
incorporates it into the stability scheme. The load and output
capacitor forms a pole, which rolls off the gain of the
regulator below unity. In order to do this the output
impedance of the regulator must be high, looking like a
current source. The output stage of the regulator becomes a
transconductance amplifier, which converts a voltage to a
current with a substantial output impedance. The circuit
which drives the transconductance amplifier is the error
amplifier, which compares the regulator output to the band
gap reference and produces an error voltage as the input to
the transconductance amplifier. The error amplifier has a
dominant pole at low frequency and a “zero” which cancels
out the effects of the pole. The zero allows the regulator to
have gain out to the frequency where the output pole
continues to reduce the gain to unity. The configuration of
the poles and zero are shown in figure 1. Instead of
powering the critical circuits from the unregulated input
voltage, the CMOS RF LDO powers the internal circuits
such as the bandgap, the error amplifier and most of the
transconductance amplifier from the boot strapped regulated
output voltage of the regulator. This technique offers
extremely high ripple rejection and excellent line transient
response.
Figure 1: ILC7082 RF LDO frequency response
VIN
INTERNAL
V
DD
CNOISE
BANDGAP
REFERENCE
TRANS-
V
ERROR AMPLIFIER
REFD
CONDUCTANCE
AMPLIFIER
VOUT
FEEDBACK
GND
ON/OFF
Figure 2: ILC7082 RF LDO regulator block diagram
The ILC7082 is designed in a CMOS process with some
minor additions, which allow the circuit to be used at input
voltages up to 13V. The resulting circuit exceeds the fre-
quency response of traditional bipolar circuits. The ILC7082
is very tolerant of output load conditions with the inclusion
of both short circuit and thermal overload protection. The
device has a very low dropout voltage, typically a linear
response of 1mV per milliamp of load current, and none of
the quasi-saturation characteristics of a bipolar output
devices. All the good features of the frequency response and
regulation are valid right to the point where the regulator
goes out of regulation in a 4 millivolt transition region.
Because there is no base drive, the regulator is capable of
providing high current surges while remaining in regulation.
This is shown in the high peak current of 500mA which
allows for the ILC7082 to be used in systems that require
short burst mode operation.
A block diagram of the regulator circuit used in the ILC7082
is shown in figure 2, which shows the input-to-output
isolation and the cascaded sequence of amplifiers that
implement the pole-zero scheme outlined above.
©2001 Fairchild Semiconductor Corporation
5
ILC7082
For best results, a resistor value of 470kΩ or less may be
used for R2. The output voltage can be programmed from
2.5V to 12V
Shutdown (ON/OFF) Operation
The ILC7082 output can be turned off by applying 0.4V or
less to the device’s ON/OFF pin (pin 3). In shutdown mode,
the ILC7082 draws less than 1mA quiescent current. The
output of the ILC7081 is enabled by applying 1.5V to 13V at
the ON/OFF pin. In applications were the ILC7082 output
will always remain enabled, the ON/OFF pin may be
connected to VIN (pin 1). The ILC7082’s shutdown circuitry
includes hysteresis, as such the device will operate properly
even if a slow moving signal is applied to the ON/OFF pin.
The device’s shutdown pin includes a 2m Ω internal pull
down resistor connected to ground.
Note that an external capacitor should not be connected
to the adjustable feedback pin (pin 4). Connecting an
external capacitor to pin 4 may cause regulator instabil-
ity and lead to oscillations.
Maximum Output Current
The maximum output current available from the ILC7082 is
limited by the maximum package power dissipation as well
as the device’s internal current limit. For a given ambient
temperature, TA, the maximum package power dissipation is
given by:
Short Circuit Protection
The ILC7082 output can withstand momentary short circuit
to ground. Moreover, the regulator can deliver very high
output peak current due to its 1A instantaneous short circuit
current capability.
PD(MAX) = (TJ(MAX) - TA) / θJA
where TJ(MAX) = 150°C is the maximum junction tempera-
ture and qJA = 333°C/W is the package thermal resistance.
For example at
mum package power dissipation is;
= 85°C ambient temperature, the maxi-
A
Thermal Protection
The ILC7082 also includes a thermal protection circuit
which shuts down the regulator when die temperature
exceeds 170°C due to overheating. In thermal shutdown,
once the die temperature cools to below 160°C, the regulator
is enabled. If the die temperature is excessive due to high
package power dissipation, the regulator’s thermal circuit
will continue to pulse the regulator on and off. This is called
thermal cycling.
PD(MAX) = 195mΩ.
The maximum output current can be calculated from the fol-
lowing equation:
IOUT(MAX) < PD(MAX) / (VIN - VOUT
)
For example at VIN = 6V, VOUT = 5V and TA = 85°C, the
maximum output current is IOUT(MAX) < 195mA. At higher
output current, the die temperature will rise and cause the
thermal protection circuit to be enabled.
Excessively high die temperature may occur due to high
differential voltage across the regulator or high load current
or high ambient temperature or a combination of all three.
Thermal protection protects the regulator from such fault
conditions and is a necessary requirement in today’s designs.
In normal operation, the die temperature should be limited to
under 150°C.
APPLICATION HINTS
Figure 4 shows the typical application circuit for the
ILC7082.
Adjustable OutputVoltage
Figure 5 shows how an adjustable output voltage can be
easily achieved using ILC7082-ADJ. The output voltage,
VOUT is given by the following equation:
VOUT
SOT23-5
5
1
4
3
CNOISE
ILC7082
COUT
VIN
CIN
VOUT = 1.24V x (R1/R2 + 1)
2
R1
R2
ON
VOUT
OFF
VADJ
SOT23-5
5
1
4
3
Figure 4: Basic application circuit for
fixed output voltage versions
ILC7082-ADJ
COUT
VIN
2
CIN
ON
OFF
Fig. 3: Application circuit for adjustable output voltage
©2001 Fairchild Semiconductor Corporation
6
ILC7082
Noise bypass capacitors with a value as low as 470pF may
be used. However, for optimum performance, use a 0.01mF
or larger, ceramic chip capacitor. Note that the turn on and
turn off response of the ILC7082 is inversely proportional to
the value of the noise bypass capacitor. For fast turn on and
turn off, use a small value noise bypass capacitor. In applica-
tions were exceptionally low output noise is not required,
consider omitting the noise bypass capacitor altogether.
Input Capacitor
An input capacitor CIN of value 1mF or larger should be con-
nected from VIN to the main ground plane. This will help to
filter supply noise from entering the LDO. The input capaci-
tor should be connected as close to the LDO regulator input
pin as is practical. Using a high-value input capacitor will
offer superior line transient response as well as better power
supply ripple rejection. A ceramic or tantalum capacitor may
be used at the input of the LDO regulator.
The Effects of ESR (Equivalent Series Resistance)
The ESR of a capacitor is a measure of the resistance due to
the leads and the internal connections of the component.
Typically measured in m Ω (milli-ohms) it can increase to
ohms in some cases.
Note that there is a parasitic diode from the LDO regulator
output to the input. If the input voltage swings below the reg-
ulator’s output voltage by a couple of hundred milivolts then
the regulator may be damaged. This condition must be
avoided. In many applications a large value input capacitor,
CIN, will hold VIN higher than VOUT and decay slower than
Wherever there is a combination of resistance and current,
voltages will be present. The control functions of LDOs use
two voltages in order to maintain the output precisely; VOUT
VOUT when the LDO is powered off.
and VREF
.
Output Capacitor Selection
Fairchild strongly recommends the use of low ESR (equiva-
With reference to the block diagram in figure 4, VOUT is fed
back to the error amplifier and is used as the supply voltage
for the internal components of the ILC7082. So any change
in VOUT will cause the error amplifier to try to compensate to
maintain VOUT at the set level and noise on V OUT will be
reflected into the supply of each internal components of the
ILC7082. So any change in VOUT will cause the error ampli-
fier to try to compensate to maintain VOUT at the set level
and noise on VOUT will be reflected into the supply of each
internal circuit. The reference voltage, VREF, is influenced by
the CNOISE pin. Noise into this pin will add to the reference
voltage and be fed through the circuit. These factors will not
cause a problem if some simple steps are taken. Figure 5
shows where these added ESR resistances are present in the
typical LDO circuit.
lent series resistance) ceramic capacitors for C
and
OUT
CNOISE The ILC7082 is stable with low ESR capacitor (as
low as zero Ω). The value of the output capacitor should be
1mF or higher. Either ceramic chip or a tantalum capacitor
may be used at the output.
Use of ceramic chip capacitors offer significant advantages
over tantalum capacitors. A ceramic capacitor is typically
cheaper than a tantalum capacitor, it usually has a smaller
footprint, lower height, and lighter weight than a tantalum
capacitor. Furthermore, unlike tantalum capacitors which are
polarized and can be damaged if connected incorrectly,
ceramic capacitors are non-polarized. Low value ceramic
chip capacitors with X5R or X7R dielectric are available in
the 100pF to 4.7mF range. Beware of using ceramic capaci-
tors with Y5V dielectric since their ESR increases signifi-
cantly at cold temperatures. Figure 12 shows a list of
recommended ceramic capacitors for use at the output of
ILC7082.
IOUT
VOUT
R*
IC
RC
SOT-23-5
ILC7082
2
5
1
4
3
COUT
CNOISE
Note: If a tantalum output capacitor is used then for stable
operation Impala recommends a low ESR tantalum capacitor
with maximum rated ESR at or below 0.4W. Low ESR tanta-
lum capacitors, such as the TPS series from AVX Corpora-
tion (www.avxcorp.com) or the T495 series from Kemet
(www.kemet.com) may be used.
VIN
RF LDOTM
Regulator
ON
R*
In applications where a high output surge current can be
expected, use a high value but low ESR output capacitor for
superior load transient response. The ILC7082 is stable with
no load.
CIN
OFF
Figure 5: ESR present in COUT and CNOISE
Noise Bypass Capacitor
In low noise applications, the self noise of the ILC7082 can
be decreased further by connecting a capacitor from the
noise bypass pin (pin 4) to ground (pin 2). The noise bypass
pin is a high impedance node as such care should be taken in
printed circuit board layout to avoid noise pick-up from
external sources. Moreover, the noise bypass capacitor
should have low leakage.
With this in mind low ESR components will offer better per-
formance where the LDO may be subjected to large load
transients current. ESR is less of a problem with CIN as the
voltage fluctuations at the input will be filtered by the LDO.
©2001 Fairchild Semiconductor Corporation
7
ILC7082
VOUT
However, being aware of these current flows, there is also
another potential source of induced voltage noise from the
resistance inherent in the PCB trace. Figure 6 shows where
the additive resistance of the PCB can manifest itself. Again
these resistances may be very small, but a summation of
several currents can develop detectable voltage ripple and
will be amplified by the LDO. Particularly the accumulation
of current flows in the ground plane can develop significant
voltages unless care is taken. With a degree of care, the
ILC7082 will yield outstanding performance.
5
1
4
ILC7082
SOT-23-5
COUT
2
3
VIN
CIN
ON/OFF
GND2
ICOUT
Printed Circuit Board Layout Guidelines
GND1
GND3
GND4
ILOAD
GND5
As was mentioned in the previous section, to take full advan-
tage of any high performance LDO regulator requires paying
careful attention to grounding and printed circuit board
(PCB) layout.
ILOAD
ILOAD
ILOAD
True GND
(0V)
+ICOUT
+ICOUT
+ICOUT
+ICNOISE
+ICNOISE
+IGND
Figure 7: Effects of poor circuit layout
IOUT
VOUT
RPCB
ESR
Figure 8 shows an optimum schematic. In this schematic,
high output surge current has little effect on the ground cur-
rent and noise bypass current return of the LDO regulator
Note that the key difference here is that COUT and CNOISE are
directly connected to the LDO regulator’s ground pin. The
LDO is then separately connected to the main ground plane
and returned to a single point system ground.
RPCB
I1
COUT
SOT-23-5
5
1
4
3
CNOISE
ILC7082
VIN
CIN
2
RPCB
The layout of the LDO and its external components are also
based on some simple rules to minimize EMI and output
voltage ripple.
RPCB
ON
OFF
Figure 6: Inherent PCB resistance
Figure 7 shows the effects of poor grounding and PCB layout
magnified by the ESR and PCB resistances and the accumu-
lation of current flows.
Note thatparticularly during high output load current, the
LDO regulator’s ground pin and the ground return for COUT
and C NOISE are not at the same potential as the system
ground. This is due to high frequency impedance caused by
PCB’s trace inductance and DC resistance. The current loop
between COUT, CNOISE and the LDO regulator’s ground pin
will degrade performance of the LDO.
©2001 Fairchild Semiconductor Corporation
8
ILC7082
VOUT
CNOISE
5
1
4
3
COUT
ILC7082
SOT-23-5
ESR<0.5
Ω
2
VIN
CIN
ON/OFF
DC/DC
Converter
VBATT
+
GND
Ground Plane
Ground Plane
Ground Plane
Ground Plane
Fairchild Semiconductor - Eval. Board
Figure 8: Recommended application circuit schematic.
Figure 9: Recommended application circuit layout
( not drawn to scale)
Note, ground plane is bottom layer of PCB and
connects to top layer ground connections through
vias.
Evaluation Board Parts List For Printed Circuit Board Shown Above
Label
Part Number
Manufacturer
Description
TM
U1
ILC7082AIM5-30
Fairchild Semiconductor
150mA RF LDO regulator
J1
Cin
69190-405
Berg
Connector, four position header
GRM40 Y5V 105Z16
ECU-V1H103KBV
GRM42-6X5R475K10
muRata
Panasonic
muRata
Ceramic capacitor, 1µF,16V, SMT ( size 0805 )
Ceramic capacitor, 0.01µF,16V, SMT ( size 0603 )
Ceramic capacitor, 4.7µF,16V, SMT ( size 1206)
Cnoise
Cout
GROUNDING RECOMMENDATIONS
1. Connect CIN between VIN of the ILC7082 and the “GROUND PLANE”.
2. Keep the ground side of COUT and CNOISE connected to the “LOCAL GROUND” and not directly to the “GROUND
PLANE”.
3. On multilayer boards use component side copper for grounding around the ILC7082 and connect back to a “GROUND
PLANE” using vias.
4. If using a DC-DC converter in your design, use a star grounding system with separate traces for the power ground and the
control signals. The star should radiate from where the power supply enters the PCB.
LAYOUT CONSIDERATIONS
1. Place all RF LDO related components; ILC7082, input capacitor CIN, noise bypass capacitor CNOISE and output capacitor
C
OUT as close together as possible.
2. Keep the output capacitor COUT as close to the ILC7082 as possible with very short traces to the VOUT and GND pins.
3. The traces for the related components; ILC7082, input capacitor CIN, noise bypass capacitor CNOISE and output capacitor
C
OUT can be run with minimum trace widths close to the LDO.
4. Maintain a separate “LOCAL GROUND” remote from the “GROUND PLANE” to ensure a quiet ground near the LDO.
Figure 9 shows how this circuit can be translated into a PCB layout.
©2001 Fairchild Semiconductor Corporation
9
ILC7082
Recommended Ceramic Output Capacitors
COUT Capacitor Size
IOUT
Dielectric
X5R
Part Number
C2012X5R1A105KT
GRM40X7R105K010
LMK212BJ105KG
GRM42-6X7R105K016
EMK316BJ105KL
TMK316BJ105KL
Capacitor Vendor
1µF
0805
0805
0805
1206
1206
1206
0 to 150mA
TDK
“
“
“
“
“
“
“
“
“
“
X7R
muRata
X7R
Taiyo-Yuden
muRata
X7R
X7R
Taiyo-Yuden
Taiyo-Yuden
X5R
2.2µF
0805
0805
1206
0 to 150mA
X5R
X5R
X5R
GRM40X5R225K 6.3
C2012X5R0J225KT
EMK316BJ225ML
muRata
TDK
“
“
“
“
Taiyo-Yuden
4.7µF
1206
1206
0 to 150mA
“
X5R
X7R
GRM42-6X5R475K010
LMK316BJ475ML
muRata
“
Taiyo-Yuden
©2001 Fairchild Semiconductor Corporation
10
ILC7082
TYPICAL PERFORMANCE CHARACTERISTICS ILC7082
Unless otherwise specified: TA = 25°C, VIN = VOUT(NOM) + 1V, ON/OFF pin tied to VIN
Dropout Characteristics
Output Voltage vsTemperature
3.4
3.3
3.2
3.1
3.015
VOUT = 3.3V
VOUT = 3.0V
COUT = 1µF (Ceramic)
COUT = 1µF (Ceramic)
3.01
3.005
3
IOUT = 0mA
IOUT = 10mA
IOUT = 50mA
2.995
2.99
IOUT = 100mA
IOUT = 150mA
3
2.985
3
3.2
3.4
3.6
-50
0
50
Temperature (°C)
100
150
VIN (V)
Dropout Voltage vs Temperature
Dropout Voltage vs IOUT
250
200
250
200
IOUT = 150mA
VOUT = 3.0V
VOUT = 3.0V
TA = 85°C
TA = 25°C
IOUT = 100mA
IOUT = 50mA
150
100
50
150
100
50
TA = –40°C
IOUT = 0mA
0
0
–40
25
85
0
50
100
150
Temperature (°C)
Output Current (mA)
Line Transient Response
Ground Current vs Input Voltage
6
5
150
VIN: tr/tf < 1 µs
VOUT = 3.0V
COUT = 2.2 µF (Ceramic
VOUT = 3.0 V
COUT = 1µF (Ceramic)
IOUT = 50mA
IOUT = 10mA
125
100
75
IOUT = 150mA
IOUT = 100 mA
IOUT = 0mA
4
3.01
3.00
2.99
2.98
IOUT = 100mA
50
2
4
6
8
10
12
14
5µs/div
V
IN (V)
©2001 Fairchild Semiconductor Corporation
11
ILC7082
TYPICAL PERFORMANCE CHARACTERISTICS ILC7082
Unless otherwise specified: TA = 25°C, VIN = VOUT(NOM) + 1V, ON/OFF pin tied to VIN
Load Transient Response
VOUT = 3.0V
Short Circuit Current
3.15
3.10
Thermal Cycling
VIN = 4V
Output Shorted to Gnd
COUT = 1 µF || 0.47 µF (Ceramic)
t = 0
at time,
1.5
1.0
3.05
3.00
2.95
0.5
0
100
1
100µs/div
t = 0
5ms/div
On/OffTransient Response
On/Off Transient Response
15
15
10
5
VOUT = 2.8V
VOUT = 2.8V
OUT = 150mA
COUT = 1µF
I
OUT = 10mA
I
10
5
Without CNOISE Capacitor
Without CNOISE Capacitor
COUT = 1µF
0
0
3
3
2
2
1
1
0
0
100µS/div
100µS/div
On/OffTransient Response
On/OffTransient Response
15
15
10
5
VOUT = 2.8V
IOUT = 10mA
CNOISE = 0.01µF, C OUT = 1µF
VOUT = 2.8V
OUT = 150mA
CNOISE = 0.01µF, C OUT = 1µF
I
10
5
0
0
3
3
2
2
1
1
0
0
5mS/div
5mS/div
©2001 Fairchild Semiconductor Corporation
12
ILC7082
TYPICAL PERFORMANCE CHARACTERISTICS ILC7082
Unless otherwise specified: TA = 25°C, VIN = VOUT(NOM) + 1V, ON/OFF pin tied to VIN
Spectral Noise Density
Spectral Noise Density
10
10
VOUT = 2.8V
VOUT = 2.8V
I
OUT = 50mA
COUT = 2.2µF
CNOISE = 0.01µF
CNOISE = 0.01µ
1
0.1
1
0.1
COUT = 1µF (Ceramic
IOUT = 50mA, 100mA or 150 mA
COUT = 2.2µF or 4.7µF (Ceramic)
COUT = 10µF (Ceramic)
0.01
0.01
IOUT = 1 mA
0.001
0.001
10M
10
100
1K
10K
Frequency (Hz)
1M
100K
1M
10
100
1K
10K
100K
Frequency (Hz)
Output Noise Voltage vs. CNOISE
Output Noise Voltage vs. CNOISE
90
90
80
70
VOUT = 3V
IOU = 10mA
COUT = 2.2µF(Ceramic)
CNOISE = 1.2nF
VOUT = 3V
80
70
CNOISE = 1.2nF
I
OUT = 10mA
COUT = 4.7µF(Ceramic)
5.6nF
8.2nF
60
50
40
30
60
50
40
30
5.6nF
8.2nF
0.039µF
0.047µF
0.039µF
0.047µF
0.022µF
0.022µF
20
10
0
20
10
0
0.01µF
0.016µ
100 Hz–
50 KHz
100 Hz–
100 KHz
300 Hz–
50 KHz
300 Hz–
100 KHz
100 Hz–
50 KHz
100 Hz–
100 KHz
300 Hz–
50 KHz
300 Hz–
100 KHz
Freq Band
Ripple Rejection vs. Frequency
Freq Band
Ripple Rejection vs. Frequency
80
70
60
50
40
30
120
VOUT = 2.8V
IOUT = 150mA
VOUT = 3V
IOUT = 10mA
COUT = 2.2µF
100
80
60
40
20
0
COUT = 4.7µF
COUT = 4.7µF
COUT = 10µF
COUT = 10µF
COUT = 1µF
COUT = 1µF
20
COUT = 2.2µF
10
0
10M
10
100
1K
10K
Frequency (Hz)
1M
100K
10M
10
100
1K
10K
Frequency (Hz)
1M
100K
©2001 Fairchild Semiconductor Corporation
13
ILC7082
Package Outline Dimensions Dimensions shown in mm and (inches).
8-Lead plastic surface mount (SOIC)
5.0 (.196)
4.8 (.189)
6.2 (.2440)
5.8 (.2284)
4.0 (.157)
3.8 (.150)
PIN 1
0.127 bsc
(.050 bsc)
0.25 (.0098)
0.19 (.0075)
0° - (8°)
1.27 (.050)
0.40 (0.16)
1.75 (.0688)
1.35 (.0532)
Seating Plane
0.51 (.020)
0.33 (0.13)
3.8 (.150)
4.0 (.157)
Package Outline Dimensions Dimensions shown in inches and (mm).
5-Lead plastic surface mount (SOT-23-5)
0.122 (3.10)
0.106 (2.70)
0.071 (1.80)
0.055 (1.40)
0.118 (3.00)
0.102 (2.60)
PIN 1
0.037 (0.95) BSC
0.055 (1.40)
0.0393 (1.0)
0.057 (1.45)
0.035 (0.90)
10°
0°
0.0217 (0.55)
0.0138 (0.35)
0.0078 (0.2)
0.0031 (0.08)
SEATING
PLANE
0.0059 (0.15)
0.0019 (0.05)
0.019 (0.50)
0.0138 (0.35)
©2001 Fairchild Semiconductor Corporation
14
ILC7082
SOT-23PACKAGE MARKINGS - ILC7082AIM5-XX
Output
Voltage (V)
*
Package
Marking
Order
Information
Grade
Supplied as:
2.8
2.85
3.0
A
A
A
A
A
A
A
A
A
ILC7082AIM5-28
ILC7082AIM5-285
ILC7082AIM5-30
ILC7082AIM5-31
ILC7082AIM5-33
ILC7082AIM5-36
ILC7082AIM5-47
ILC7082AIM5-50
ILC7082AIM5-ADJ
EAXX
EJXX
EBXX
EHXX
ECXX
EDXX
EGXX
EEXX
EFXX
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3k Units on Tape and Reel
3.1
3.3
3.6
4.7
5.0
ADJ
* Note: First two characters identify the product and the last two characters identify the date code
SOIC PACKAGE MARKINGS - ILC7082AIK-xx
Output
Voltage (V) Grade
Order
Information
Package Marking
7082AIK285-XX
7082AIK33-XX
Supplied as:
2.85
3.3
A
A
ILC7082AIK-285
ILC7082AIK-33
2,500 Units on Tape and Reel
2,500 Units on Tape and Reel
Ordering Information
Ordering Information (TA = -40°C to +85°C)
ILC7082AIM5-xx
ILC7082AIM5-ADJ
ILC7082AIK-xx
150mA, fixed voltage
150mA, adjustable voltage
150mA, fixed voltage (soic-8)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
10/15/01 0.0m 001
Stock#DSxxxxxxxx
2001 Fairchild Semiconductor Corporation
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