IMIC9850A [ETC]
Clocks and Buffers ; 时钟和缓冲器\n
| 型号： | IMIC9850A |
| 厂家： | 
ETC |
| 描述： | Clocks and Buffers
|
| 文件： | 总19页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
Product Features
Product Description
This device is an advanced performance single
package clock solution for high end Pentium III designs
using Rambus memory system architectures. It
provides all of the system motherboard’s clocks
needed to support the CPU, memory and peripheral
devices. Included in the frequency table are specific
+5% margin test frequencies to assist designers in
verification of adequate timing margins in designs. All
CPU (Host) clocks are deferential and comply with Intel
specified timing requirements.
•
•
•
•
•
•
•
Four differential host clocks
Two 3V Mref single ended for DRCG
Four 3V, 66 MHz clocks
Ten 3V, 33 MHz PCI clocks
Two 48 MHz clocks
Two 14.318 MHz reference clocks
Select logic for Differential Swing Control, Test
mode, Hi-Z, Power-down, Spread spectrum, and
frequency selection
External resistor for CPU current reference
56 Pin SSOP and TSSOP Package
•
•
Frequency Selection Table
SEL 100/133 SELA SELB
CPU(1:4),
CPU# (1:4)
100 MHz
105 MHz
200 MHz
High Z
3VMRef/
3VMRef_b
50 MHz
3V66
(0:3)
66.7 MHz
70.0 MHz
66.7 MHz
High Z
PCI (0:9)
48 M (0:1)
REF (1:2)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
33.3 MHz
35.0 MHz
33.3 MHz
High Z
48 MHz
48 MHz
48 MHz
High Z
14.318 MHz
14.318 MHz
14.318 MHz
High Z
52.5 MHz
50 MHz
High Z
133.3 MHz
126.7 MHz
200 MHz
XIN/2
66.7 MHz
63.3 MHz
66.7 MHz
XIN/4
66.7 MHz
63.3 MHz
66.7 MHz
XIN/4
33.3 MHz
31.7 MHz
33.3 MHz
XIN/8
48 MHz
48 MHz
48 MHz
XIN/2
14.318 MHz
14.318 MHz
14.318 MHz
XIN
Block Diagram
Pin Configuration
VSSR
Ref1/MultSel0
Ref2/MultSel1
VDDR
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDM
VDDR
3VMRef
3VMRef_b
VSSM
Spread#
CPU1
CPU1#
VDDC
CPU2
CPU2#
VSSC
CPU3
CPU3#
VDDC
CPU4
Sel1
Sel2
XIN
Ref1/MultSel0
OSC
XOUT
XIN
XOUT
VSSP
PCI0
PCI1
VDDP
PCI2
PCI3
VSSP
PCI4
PCI5
VDDP
PCI6
PCI7
VSSP
PCI8
Ref2/MultSel1
VSSR
9
3VMRef
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
3VMRef_b
I_REF
Spread#
VDDC
CPU(1:4)
VCO1
SEL100/133
PwrDwn#
CPU#(1:4)
CPU4#
VSSC
I_Ref
VDD
VSS
VSSC
VDDL
3V66(0:3)
VSSL
VDDP
PCI9
VDDP
VDD
3V66_0
3V66_1
VSS
PCI (0:9)
VSSP
SEL100/133
VSSU
48M0/SelA
48M1/SelB
VDDU
VSSL
VDDU
VCO2
3V66_2
3V66_3
VDDL
48M(0:1)/Sel(A:B)
VSSU
SELA/B
PwrDwn#
2
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07067 Rev. *A
12/22/2002
Page 1 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
Pin Description
PIN No.
Pin Name
I/O Description
55
3VMRef
O
3V reference to memory clock driver. It is synchronous to the CPU clock. See table 1, pg
1 for spread selection.
54
3VMRef_b
Spread#
O
I
3V reference to memory clock driver (180° out of phase with 3VMref).
52*
Invokes Spread Spectrum functionality on the Differential Host clocks. MRef/MRef_b
clocks, 66 MHz clocks, and 33 MHz PCI clocks. Active Low.
51
50
48
47
45
44
42
41
39
CPU1
CPU1#
CPU2
CPU2#
CPU3
CPU3#
CPU4
CPU4#
I_Ref
O
O
O
O
CPU clock pair. These two clocks are 180o out of phase with each other. See the table on
page 1 of this data sheet for the frequency selections.
CPU clock pair. These two differential clocks are 180o out of phase with each other. See
the table on page 1 of this data sheet for the frequency selections.
CPU clock pair. These two differential clocks are 180o out of phase with each other. See
the table on page 1 of this data sheet for the frequency selections.
CPU clock pair. These two differential clocks are 180o out of phase with each other. See
the table on page 1 of this data sheet for the frequency selections.
This pin is the reference current input for the CPU pairs. This pin takes a fixed precision
resistor tied to ground in order to establish the appropriate current. See pg. 9.
35, 34,
31, 30
28*
25*
26*
23*
3V66 (0:3)
O
I
66.67 MHz 3.3 Volt outputs. These clocks are differential to the CPU clocks.
PwrDwn#
48 M0/SelA
48 M1/SelB
SEL100/133
Invokes power-down mode. Active Low. Sets all clocks low.
SelA and SelB inputs are sensed on power-up and then internally latched prior to
the pin being used for output of 3V 48 MHz clocks.
I
CPU frequency select pin. See the table on page 1 of this data sheet for the frequency
selections.
21, 20,
18, 17,
15, 14,
12, 11, 9,
8
PCI (0:9)
O
3.3V 33 MHz PCI output clocks. See the table on page 1 of this data sheet for the
frequency selections.
6
5
2
3
XOUT
XIN
O
I
14.318 MHz crystal output.
14.318 MHz crystal input.
Ref1/MultSel (0)
Ref2/MultSel (1)
I
MultSel0 and MultSel1 inputs are sensed on power-up and then internally
latched prior to the pin being used for output of 3V 14.318 MHz clocks. They sel
I_Ref values, see pg. 9.
56
53
49
VDDM
VSSM
VDDC
VSSC
VDD
VSS
VDDL
VSSL
P
P
P
P
P
P
P
P
Power pin recommended 3 Vmref and 3Vmref_b dedicated use.
Ground pin recommended for 3Vmref and 3Vmref_b dedicated use.
Power pin recommended for CPU/CPU# dedicated use.
Ground pin recommended for CPU/CPU# dedicated use.
Power pin recommended for dedicated core use.
Ground pin recommended for dedicated core use.
Power pins recommended for 3V66 dedicated use.
Ground pin recommended for 3V66 dedicated use.
46
38, 36
37, 33
29
32
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07067 Rev. *A
12/22/2002
Page 2 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
Pin Description (cont.)
PIN No.
Pin Name
VDDU
VSSU
I/O Description
27
24
P
P
P
P
P
P
Power pin recommended for 48 MHz dedicated use.
Ground pin recommended for 48 MHz dedicated use.
Power pins recommended for PCI dedicated use.
Ground pins recommended for PCI dedicated use.
Power pin recommended for Ref clock and Xtal dedicated use.
22, 16, 10
19, 13, 7
VDDP
VSSP
VDDR
4
1
VSSR
Ground pin recommended for Ref clock and Xtal dedicated use.
Note: All pin numbers that are followed with an astirik (*) contain internal pull-up resistors. These internal devices are
sufficient enough to guarantee a logic 1 will be sensed internally of no external circuitry is connected.
Power on Bi-Directional Pins
Power Up Condition:
Pins 2, 3, 25, and 26 are Power up bi-directional pins and are used for different features in this device (see Pin
description, Page 2). During power-up, these pins are in input mode (see Fig 2, below), therefore, they are considered
input select pins internal to the IC. After a settling time, the Selection data is latch into internal control registers and
these pins become toggling clock outputs.
VDD Rail
Power Supply
Ramp
Ref1/MultSel0
Ref2/MultSel1
-
Hi-Z Inputs
Toggle Outputs
48M0/SelA
48M1/SelB
Select Data is latched into register then pin becomes clock output signal.
Fig. 1
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07067 Rev. *A
12/22/2002
Page 3 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
Vdd
Strapping Resistor Options for pins with internal
Pull-ups:
Rup
The power up bidirectional pins have a large value pull-
up each (250KΩ), therefore, a selection “1” is the
default. If the system uses a slow power supply (over
3mS settling time), then it is recommended to use an
external Pullup (Rup) in order to insure a high
50K
IMI C9850
Rd
Load
Bidirectional
JP1
JUMPER
selection. In this case, the designer may choose one of
two configurations, see Fig. 2A and Fig. 2B.
Fig.2A
Fig. 2A represents an additional pull up resistor 50KΩ
connected from the pin to the power line, which allows
a faster pull to a high level.
Rdn
5K
If a selection “0” is desired, then a jumper is placed on
JP1 to a 5KΩ resistor as implemented as shown in
Fig.2A. Please note the selection resistors (Rup, and
Rdn) are placed before the Damping resistor (Rd)
close to the pin.
JP2
Vdd
3 Way Jumper
Fig. 2B represent a single resistor 10KΩ connected to a
3 way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads1 and 3. When a “0”
selection is desired, a jumper is placed between leads
1 and 2.
Rsel
10K
IMI C9850
Rd
Load
Bidirectional
Fig.2B
Maximum Ratings1
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Maximum Input Voltage:
Maximum Input Voltage:
Storage Temperature:
Operating Temperature:
Maximum ESD protection
Maximum Power Supply:
VSS - 0.5V
VDD + 0.7V
-65°C to + 150°C
0°C to +85°C
2000V
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD)
5.5V
1 Note: 1. The voltage on any input or I/O cannot exceed the
power pin during power-up. Power supply sequencing is
NOT required.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07067 Rev. *A
12/22/2002
Page 4 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
DC Parameters
Characteristic
Symbol
VDD3
Vih3
Vil3
Min
TYP
Max
3.465
VDD +0.3
0.8
Units
V
Conditions
Supply Voltage
3.135
Input High Voltage
Input Low Voltage
Input Leakage Current
2.0
V
Note 1
Note 1
VSS – 0.3
V
IiL
-5
-
+5
0 < Vin < VDD
µA
µA
µA
Tri-State leakage Current
Ioz
-
-
±10
Input Low Current (@Vin =
VSS)
IIL
-66
-5
For pins with internal Pull
up resistors, Note 3
Input High Current (@Vin =
VDD)
IIH
Idd
5
µA
Dynamic Supply Current
-
250
mA
475Ω current reference at
lout=*Iref, CPU=133MHz,
Msel0 = 0, Msel1 = 1
Power Down Current (VDD)
Input Pin Capacitance
IddPD
Cin
-
-
60
5
mA
pF
PwrDwn# pin = low
Except XIN and XOUT
Crystal Pin capacitance
Cxtal
34
36
38
pF
Present between both Pin
5 and 6 to Ground.
Crystal DC Bias Voltage
Crystal Startup time
VBIAS
Txs
0.3Vdd
-
Vdd/2
-
0.7Vdd
40
V
From Stable 3.3V power
supply.
µS
Ambient Temperature
Ta
0
70
oC
No Airflow
Notes
1. All inputs are specified when using a 3.3V power supply.
2. Although internal pull-up resistors have a typical value of 250K, this value may vary between 200K and 500K.
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07067 Rev. *A
12/22/2002
Page 5 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
AC Parameters
133 MHz CPU
100 MHz CPU
Characteristic
Symbol
TPeriod
Units
nS
nS
mA
(V)
V
Notes
11
Min
Max
7.65
N/A
14.9
(0.76)
0.05
Min
10.0
9.85
12.9
(0.66)
VSS =
0.0
45%
Voh
Max
10.2
N/A
14.9
(0.75)
0.05
CPU CLK period - average
Absolute minimum CPU CLK Period Abs/MinPeriod
Output Current (CPU)
(Voltage at given load)
7.5
7.35
12.9
(0.66)
VSS=
0.0
11
11
Ioh
(Voh)
Vol
11
11
Vcrossover
Vcrossover
45%
Voh
55%
Voh
55%
Voh
V
Host/CPU CLK rise time
Host/CPU CLK fall time
Rise time and fall time matching
TRISE
TFALL
Rise/Fall
Matching
175
175
700
700
20%
175
175
700
700
20%
pS
pS
11, 12
11, 12
11
Overshoot
Voh +
0.2V
Voh +
0.2V
11
Undershoot
TJcc
-0.2
-0.2
V
11
13
Cycle to Cycle jitter
CPU to CPU clock skew
Duty Cycle
200 pS
150
55
200 pS
150
55
pS
pS
%
Tskew
Tdc
45
15.0
5.25
5.05
0.4
45
20.
7.5
7.3
0.4
0.4
45
11
2, 9
5, 10
6, 10
8
Mref, Mref_b CLK period
Mref, Mref_b CLK high time
Mref, Mref_b CLK low time
Mref, Mref_b CLK rise time
Mref, Mref_b, CLK fall time
Mref and Mref_b Duty Cycle
Mref & Mref_b Cycle to Cycle jitter
REF CLK rise time
REF CLK fall time
REF Duty Cycle
REF Cycle to Cycle jitter
48M CLK rise time
48M CLK fall time
TPeriod
THIGH
TLOW
TRISE
TFALL
Tdc
15.3
N/A
N/A
1.6
1.6
55
20.4
N/A
N/A
1.6
1.6
55
nS
nS
nS
nS
nS
%
pS
nS
nS
%
0.4
45
8
11
12
8
TJcc
250 pS
250 pS
TRISE
TFALL
Tdc
2.0
2.0
45
2.0
2.0
45
8
55
1.0
55
1.0
11
12
8
8
11
12
TJcc
nS
nS
nS
%
TRISE
TFALL
Tdc
2.0
2.0
45
2.0
2.0
45
48M Duty Cycle
48M Cycle to Cycle jitter
55
350
55
350
TJcc
pS
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07067 Rev. *A
12/22/2002
Page 6 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
AC Parameters (Cont.)
133 MHz CPU
100 MHz CPU
Characteristic
Symbol
TPeriod
Units
nS
nS
nS
nS
nS
%
Notes
2, 9
Min
15.0
5.25
5.05
0.5
Max
16.0
N/A
N/A
2.0
Min
15.0
5.25
5.05
0.5
Max
15.2
N/A
N/A
2.0
3V66 CLK period
3V66 CLK high time
3V66 CLK low time
3V66 CLK rise time
3V66 CLK fall time
3V66 Duty Cycle
THIGH
TLOW
TRISE
TFALL
Tdc
5, 10
6, 10
8
0.5
45
2.0
55
0.5
45
2.0
55
11
3V66 to 3V66 clock skew
3V66 Cycle to Cycle jitter
PCI CLK period
PCI CLK high time
PCI CLK low time
PCI CLK rise time
PCI CLK fall time
PCI Duty Cycle
Tskew
TJcc
250
300 pS
250
300 pS
pS
pS
nS
nS
nS
nS
nS
%
12
8
2, 9
5, 10
6, 10
8
TPeriod
THIGH
TLOW
TRISE
TFALL
Tdc
30.0
12.0
12.0
0.5
0.5
45
30.0
12.0
12.0
0.5
0.5
45
2.0
2.0
55
2.0
2.0
55
11
PCI to PCI clock skew
PCI Cycle to Cycle jitter
Output enable delay (all outputs)
Output disable delay (all outputs)
Tskew
TJcc
500
500
10.0
10.0
3
500
500
10.0
10.0
3
pS
pS
nS
nS
nS
12
7
tpZL, tpZH
tpLZ, tpZH
Tstable
1.0
1.0
1.0
1.0
All clock Stabilization from power-up
Notes:
1. All output drivers have monotonic rise/fall times through the specified VOL/VOH levels.
2. Period, jitter, offset and skew measured on rising edge @ 1.25V for 2.5V clocks and @1.5V for 3.3V clocks.
3. The PCI clock is the Host clock divided by four at Host = 133 MHz. PCI clock is the host clock divided by three at
Host = 100 MHz.
4. 3V66 is internal VCO frequency divided by four for Host = 133 MHz. 3V66 clock is internal VCO frequency divided
by three for Host = 100 MHz.
5. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
6. TLOW is measured at 0.4V for all outputs.
7. The time specified is measured from when VDD achieves its nominal operating level (typical condition VDD = 3.3V)
till the frequency output is stable and operating within specification.
8. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V
9. The average period over any 1 uS period of time is greater than the minimum specified period.
10. Calculated at minimum edge-rate (1V/nS) to guarantee 45/55% duty-cycle.
11. CPU clock test load is Rs=33.2 Ohms, Rp = 49.9.
12. 20% and 80%
13. Measured at 1.25 Volts
14. Measured at 1.50 Volts
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07067 Rev. *A
12/22/2002
Page 7 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
Group to Group Offset Limits
Groups
3V66 to PCI
Notes:
1. All offsets are to be measured at rising edges.
Offset
Measurement Loads (Lumped) Measure Point
1.5-3.5 nS 3V66 leads
3V66@ 30 pF, PCI @ 30 pF
3V66@ 1.5V, PCI @ 1.5 V
Lumped Capacitive Test Loads for Single Ended Outputs
Clock
Max Load
30
20
30
Units
pF
pF
PCI Clocks (PCLK)
Mref, Mref_b
3V66
pF
48 MHz Clock
REF
20
20
pF
pF
CPU (1:4), (1:4)#
Rs = 33.2, Rp = 49.9
Ohm
Test and Measurement Setup
For Differential Output Signals
The following shows lumped test load configurations for the differential Host Clock Outputs. Multsel(0:1) = (0, 1)
Rs
Rs
Rp
Test Nodes
Rp
Figure 3. Lumped Test Load Configuration
Cypress Semiconductor Corporation
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Document#: 38-07067 Rev. *A
12/22/2002
Page 8 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
For Single Ended Output Signals
Output under Test
Probe
Load Cap
3.3V signals
2.5V signals
tDC
tDC
-
-
-
-
3.3V
2.5V
2.4V
1.5V
2.0V
1.25V
0.4V
0.4V
0V
0V
Tr
Tf
Tr
Tf
Spectrum Spread Clocking Description
Spread Spectrum is a modulation technique for distributing clock period over a certain bandwidth (called Spread
Bandwidth). This technique allows the distribution of the energy (EMI) over a range of frequencies therefore reducing
the radiation generated from clocks. As the spread is a percentage of the rested (non-spread) frequency, it is effective
at the fundamental and all its harmonics.
In this device Spread Spectrum is enabled through pin 52 (Spread#). As the name suggests, spread spectrum is
enabled when Spread# is low. This pin has a 250KΩ internal pull up, therefore, defaults to a high (Spread Spectrum
disabled) unless externally forced to a low.
When Spread# is forced low, the device will be down spread (fig.5B) mode at –0.5%, and the center frequency is shifted
down from its rested (non-spread) value by -0.25%. (ex.: assuming the center frequency is 100MHz in non-spread
mode; when down spread is enabled, the center frequency shifts to 99.75MHz.), see fig.4 below.
Cypress Semiconductor Corporation
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Document#: 38-07067 Rev. *A
12/22/2002
Page 9 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
Spread off
Spread on
Center
Center
Frequency,
Frequency,
Fig.4
Spectrum Spreading Selection Table
Unspread
Frequency in
MHz
Down Spreading
F Min
(MHz)
99.5
F Center
(MHz)
99.75
F Max
(MHz)
100.0
133.3
Spread
(%)
.5
Desired
100.0
133.3
132.2
132.6
.5
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07067 Rev. *A
12/22/2002
Page 10 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
Host Swing Select Functions
MultSel0 MultSel1
Board Target
Trace/TermZ
Reference Rr, Iref =
Vdd/(3*Rr)
Output Current
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
Voh @Z, Iref =
2.32mA
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
60 Ohms
Rf = 475 1%,
Iref = 2.32mA
Rr = 475 1%,
Iref = 2.32mA
Rr = 475 1%,
Iref = 2.32mA
Rr = 475 1%,
Iref = 2.32mA
Rr = 475 1%,
Iref = 2.32mA
Rr = 475 1%,
Iref = 2.32mA
Rr = 475 1%,
Iref = 2.32mA
Rr = 475 1%,
Iref = 2.32mA
0.7V @ 60
0.59V @ 50
0.85V @ 60
0.71V @ 50
0.56V @ 60
0.47V @ 50
0.99V @ 60
0.82V @ 50
0.75V @ 30
0.62V @ 20
0.90V @ 30
0.75V @ 20
0.60V @ 30
0.5V @ 20
50 Ohms
60 Ohms
50 Ohms
60 Ohms
50 Ohms
60 Ohms
50 Ohms
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5Ma
1.05V @ 30
0.84V @ 20
Note: The entries in boldface are the primary system configurations of interest. The outputs should be optimized for
these configurations.
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Document#: 38-07067 Rev. *A
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Page 11 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
Buffer Characteristics
Current Mode CPU Clock Buffer Characteristics
The current mode output buffer detail and current reference circuit details are contained in the previous table of this
data sheet. The following parameters are used to specify output buffer characteristics:
1. Output impedance of the current mode buffer circuit - Ro (see Figure 5).
2. Minimum and maximum required voltage operation range of the circuit – Vop (see Figure 5).
3. Series resistance in the buffer circuit – Ros (see Figure 5).
4. Current accuracy at given configuration into nominal test load for given configuration.
VDD3 (3.3V +/- 5%)
Ro
Iout
Ros
0V
1.2V
Iout
Vout = 1.2V max
Vout
Figure 5
Host Clock (HCSL) Buffer Characteristics
Characteristic
Minimum
Maximum
Ro
3000 Ohms (recommended)
N/A
Ros
Vout
N/A
1.2V
Iout is selectable depending on implementation. The parameters above apply to all configurations. Vout is the voltage at
the pin of the device.
The various output current configurations are shown in the host swing select functions table. For all configurations, the
deviation from the expected output current is +/- 7% as shown in the table current accuracy (page 13).
Cypress Semiconductor Corporation
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Page 12 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
Current Accuracy
Conditions
Configuration
Load
Min
Max
Iout
VDD = nominal (3.30V) All combinations of M0, M1
and Rr shown in host Swing
Nominal test load for
given configuration
-7% Inom
+ 7% Inom
Select Function Table
Iout
VDD = 3.30 +/- 5%
All combinations of M0, m1
Nominal test load for
-12% Inom + 12% Inom
and Rr shown in Host Swing given configuration
Select Function Table
Note: Inom refers to the expected current based on the configuration of the device.
Buffer Characteristics for 48 MHz and REF
Characteristic
Symbol Min Typ Max
Units Conditions
Pull-Up Current Min
IOHmin
IOHmax
IOLmin
IOLmax
Trh
-12
-27
9
26
0.5
0.5
20
-53
-92
27
79
2.0
2.0
60
mA
mA
mA
mA
VOH=VDDmin-0.5V (2.64V)
VOH=VDDmin/2 (1.56V)
VOL=0.4V
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
3.3V Output Rise Edge Rate
3.3V Output Fall Edge Rate
Output Impedance
VOL=VDDmin/2 (1.56V)
-
-
40
V/nS 3.3V +/- 5% @ 0.4V – 2.4 V
V/nS 3.3V +/- 5% @ 2.4V – 0.4 V
Tfh
Zo
Ω
Buffer Characteristics for PCI, 3V66, MRef, MRef_b
Characteristic
Symbol Min Typ Max
Units Conditions
Pull-Up Current Min
IOHmin
IOHmax
IOLmin
IOLmax
Trh
-11
-30
9
28
1/1
1/1
-83
-184
38
148
4/1
4/1
55
mA
mA
mA
mA
VOH=VDD-0.5V (2.64V)
V OH=VDD/2 (1.56V)
VOL=0.4V
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
3.3V Output Rise Edge Rate
3.3V Output Fall Edge Rate
Output Impedance
VOL=VDD/2 (1.56V)
-
-
30
V/nS 3.3V +/- 5% @ 0.4V – 2.4 V
V/nS 3.3V +/- 5% @ 2.4V – 0.4 V
Tfh
Zo
12
Ω
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Document#: 38-07067 Rev. *A
12/22/2002
Page 13 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
Suggested Oscillator Crystal Parameters
Characteristic
Symbol
Min
Typ
Max
Units
MHz
PPM
PPM
Conditions
Frequency
Fo
14.17
14.31818
14.46
Tolerance
TC
-
-
-
-
-
-
-
+/-100
Note 1
Frequency Stability
Operating Mode
Load Capacitance
TS
+/- 100
Stability (TA -10 to +60C) Note 1
Parallel Resonant, Note 1
The crystal’s rated load. Note 1
Note 2
-
-
-
-
-
CXTAL
RESR
20
40
pF
Effective Series
Ohms
Resistance (ESR)
Note1: For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen
crystal meets or exceeds these specifications
Note 2: Larger values may cause this device to exhibit oscillator startup problems
To obtain the maximum accuracy, the total circuit loading capacitance should be equal to CXTAL. This loading capacitance is the
effective capacitance across the crystal pins and includes the clock generating device pin capacitance (CFTG), any circuit trace
capacitance (CPCB), and any onboard discrete load capacitance (CDISC).
The following formula and schematic illustrates the application of the loading specification of a crystal (CXTAL)for a design.
CL = (CXINPCB + CXINFTG + CXINDISC) X (CXOUTPCB + CXOUTFTG + CXOUTDISC
(CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB + CXOUTFTG + COUTDISC
)
)
Where:
CXTAL
= the load rating of the crystal
CXOUTFTG = the clock generators XIN pin effective device internal capacitance to ground
CXOUTFTG = the clock generators XOUT pin effective device internal capacitance to ground
CXINPCB
CXOUTPCB = the effective capacitance to ground of the crystal to device PCB trace
CXINDISC = any discrete capacitance that is placed between the XIN pin and ground
= the effective capacitance to ground of the crystal to device PCB trace
CXOUTDISC = any discrete capacitance that is placed between the XOUT pin and ground
XIN
CXINPCB
CXINDISC
CXINFTG
CXOUTPCB
CXOUTDISC
CXOUTFTG
XOUT
Clock Generator
As an example, and using this formula for this datasheet’s device, a design that has no discrete loading capacitors (CDISC) and each
of the crystal to device PCB traces has a capacitance (CPCB) to ground of 4pF (typical value) would calculate as:
CL = (4pF + 36pF + 0pF) X (4pF + 36pF + 0pF) = 40 X 40
(4pF + 36pF + 0pF) + (4pF + 36pF + 0pF) 40 + 40
= 1600
80
= 20pF
Therefore to obtain output frequencies that are as close to this data sheets specified values as possible, in this design example, you
should specify a parallel cut crystal that is designed to work into a load of 20pF
Cypress Semiconductor Corporation
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Page 14 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
Package Drawing and Dimensions (56 Pin TSSOP)
Cypress Semiconductor Corporation
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Document#: 38-07067 Rev. *A
12/22/2002
Page 15 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
Package Drawing and Dimensions (Cont.)
56 Pin TSSOP Dimensions
INCHES
MILLIMETERS
SYMBOL
MIN
-
NOM
-
MAX
MIN
NOM
MAX
A
0.2794
-
-
0.10
0.90
0.10
-
1.10
0.15
0.95
A1
0.0013 0.0025 0.0038
0.0216 0.0229 0.0241
0.00254
0.05
0.85
A2
000
b
0.0043
-
0.0069
0.17
0.17
0.27
0.23
b1
0.0043 0.0051 0.0058
0.0020
0.20
0.08
-
bbb
c
0.0023
-
0.0051
0.09
0.09
0°
0.20
0.16
8°
c1
0.0023 0.0032 0.0041
0.127
-
-
θ
0°
8°
e
0.0127 BSC
0.0206
0.50 BSC
8.10 BSC
H
D
0.3531 0.3556 0.3581 13.90 14.00 14.10
E
L
0.1524 0.1549 0.1575
0.0127 0.0152 0.0191
6.00
0.50
6.10
0.60
6.20
0.75
NOTES:
1. Die thickness allowable is 0.279 +/- 0.0127 (0.0110 +/-
.005 inches)
2. Dimensions & tolerance per ASME. Y14, 5M-1994.
3. Datum Plane H located at mold parting line and
coincident with lead. Where lead exits plastic body at
bottom of parting line.
4. Datums A-B and D to be determined where centerline
between leads exits plastic body at Datum Plane H.
5. “D” and “E” are reference datums and do not include
mode flash or protrusions, and are measured at the
bottom parting line. Mold flash or protrusions shall not
exceed 0.15mm on D and 0.25mm on E per side.
6. Dimension is the length of terminal for soldering to a
substrate.
7. Terminal positions are shown for reference only.
8. Formed leads shall be planar with respect to one another
within 0.076mm at seating plane.
9. The lead width dimension does not include Dambar
protrusion. Allowable Dambar protrusion shall be
0.08mm total in excess of the lead width dimension
located on the lower radius or the foot. Minimum space
between protrusions and an adjacent lead to be 0.08mm
for 0.50mm pitch.
10. Section “C-C” to be determined at 0.10 to 0.25mm from
the lead tip.
11. This part is compliant with JEDEC specification MO-153,
variations DB, DC, DE ED, EE, and FE.
Cypress Semiconductor Corporation
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Document#: 38-07067 Rev. *A
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Page 16 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
Package Drawing and Dimensions (56 Pin SSOP)
56 Pin SSOP Outline Dimensions
INCHES
MILLIMETERS
SYMBOL
A
MIN
NOM
MAX
MIN
2.41
NOM
2.59
MAX
2.79
C
0.095
0.102
0.012
0.090
0.010
-
0.110
L
A1
A2
B
C
D
E
e
0.008
0.088
0.008
0.005
.720
0.016
0.092
0.0135
0.010
.730
0.20
2.24
0.31
2.29
0.41
2.34
H
E
0.203 0.254 0.343
0.127 0.254
18.29 18.42 18.54
-
.725
a
D
0.292
0.296
0.025 BSC
0.406
0.013
0.032
5º
0.299
7.42
7.52
7.59
0.635 BSC
A2
A
H
a
0.400
0.10
0.024
0º
0.410
0.016
0.040
8º
10.16 10.31 10.41
A1
0.25
0.61
0º
0.33
0.81
5º
0.41
1.02
8º
e
B
L
a
X
0.085
0.093
0.100
2.16
2.36
2.54
Ordering Information
Part Number
C9850AY
Package Type
56 Pin SSOP
56 Pin TSSOP
Production Flow
Commercial, 0ºC to +70ºC
Commercial, 0ºC to +70ºC
C9850AT
Marking: Example: Cypress
C9850
Date Code, Lot #
C9850AY
Package
Y = SSOP
T = TSSOP
Revision
Device Number
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07067 Rev. *A
12/22/2002
Page 17 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
Notice
Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design,
performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in
life supporting and medical applications where the failure or malfunction of the product could cause failure of the life
supporting and medical systems. Products are not authorized for use in such applications unless a written approval is
requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of
its products in the life supporting and medical applications
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07067 Rev. *A
12/22/2002
Page 18 of 19
ADVANCED INFORMATION
C9850
High Performance Pentium III Clock Generator
Document Title: C9850 High Performance Pentium® III Clock Generator
Document Number: 38-07067
Rev. ECN
No.
Issue
Date
Orig. of Description of Change
Change
**
*A
107122 06/11/01 IKA
122752 12/22/02 RBI
Convert from IMI to Cypress
Add power up requirements to maximum ratings
information
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07067 Rev. *A
12/22/2002
Page 19 of 19
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