IMIZ9973 [ETC]
Clocks and Buffers ; 时钟和缓冲器\n
| 型号： | IMIZ9973 |
| 厂家： | 
ETC |
| 描述： | Clocks and Buffers
|
| 文件： | 总9页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Z9973
3.3V, 125-MHz, Multi-Output Zero Delay Buffer
Table 1. Frequency Table[1]
Features
VC0_SEL
FB_SEL2
FB_SEL1
FB_SEL0
F
VC0
• Output frequency up to 125 MHz
• 12 clock outputs: frequency configurable
• 350 ps max output-to-output skew
• Configurable output disable
• Two reference clock inputs for dynamic toggling
• Oscillator or PECL reference input
• Spread spectrum-compatible
• Glitch-free output clocks transitioning
• 3.3V power supply
• Pin-compatible with MPC973
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
8x
12x
16x
20x
16x
24x
32x
40x
4x
6x
8x
• Industrial temperature range: –40°C to +85°C
• 52-pin TQFP package
10x
8x
12x
16x
20x
Note:
1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz.
.
Block Diagram
Pin Configuration
PECL_CLK
PECL_CLK#
VCO_SEL
PLL_EN
REF_SEL
Sync
Frz
D Q
QA0
0
1
Phase
Detector
VCO
TCLK0
TCLK1
0
1
QA1
QA2
QA3
LPF
TCLK_SEL
FB_IN
52 51 50 49 48 47 46 45 44 43 42 41 40
39
Sync
Frz
VSS
VSS
MR#/OE
SCLK
QB0
QB1
D
Q
1
QB0
2
38
37
36
35
34
33
32
31
30
29
28
27
VDDC
QB1
3
QB2
QB3
SDATA
4
FB_SEL2
VSS
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
5
QB2
6
VDDC
QB3
7
Z9973
8
MR#/OE
Sync
Frz
D
Q
QC0
QC1
FB_IN
VSS
9
Power-On
Reset
10
11
12
13
TCLK1
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
FB_OUT
VDDC
FB_SEL0
PECL_CLK
PECL_CLK#
VDD
Sync
Frz
2
QC2
D
D
SELA(0,1)
Q
Q
QC3
2
2
SELB(0,1)
SELC(0,1)
14 15 16 17 18 19 20 21 22 23 24 25 26
0
1
Sync
Frz
FB_OUT
/4, /6, /8, /10
Sync Pulse
/2
Sync
Frz
2
SYNC
D Q
FB_SEL(0,1)
Data Generator
SCLK
Output Disable
Circuitry
12
SDATA
INV_CLK
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07089 Rev. *D
Revised December 21, 2002
Z9973
Pin Description [2]
Pin Number
Pin Name
PWR I/O Type
Pin Description
11
PECL_CLK
PECL_CLK#
TCLK0
I
I
PU PECL Clock Input.
PD PECL Clock Input.
12
9
I
PU External Reference/Test Clock Input.
10
TCLK1
I
PU External Reference/Test Clock Input.
44, 46, 48, 50
32, 34, 36, 38
16, 18, 21, 23
29
QA(3:0)
VDDC
VDDC
VDDC
VDDC
O
O
O
O
Clock Outputs. See Table 2 for frequency selections.
Clock Outputs. See Table 2 for frequency selections.
Clock Outputs. See Table 2 for frequency selections.
QB(3:0)
QC(3:0)
FB_OUT
Feedback Clock Output. Connect to FB_IN for normal operation. The
divider ratio for this output is set by FB_SEL(0:2). See Table 1. A bypass
delay capacitor at this output will control Input Reference/ Output Banks
phase relationships.
25
SYNC
VDDC
O
Synchronous Pulse Output. This output is used for system synchroni-
zation. The rising edge of the output pulse is in sync with both the rising
edges of QA (0:3) and QC(0:3) output clocks regardless of the divider ratios
selected.
42, 43
SELA(1,0)
SELB(1,0)
SELC(1,0)
FB_SEL(2:0)
VCO_SEL
FB_IN
I
I
I
I
I
I
I
I
I
I
PU Frequency Select Inputs. These inputs select the divider ratio at QA(0:3)
outputs. See Table 2.
40, 41
PU Frequency Select Inputs. These inputs select the divider ratio at QB(0:3)
outputs. See Table 2.
19, 20
PU Frequency Select Inputs. These inputs select the divider ratio at QC(0:3)
outputs. See Table 2.
5, 26, 27
PU Feedback Select Inputs. These inputs select the divide ratio at FB_OUT
output. See Table 1.
52
31
6
PU VCO Divider Select Input. When set LOW, the VCO output is divided by
2. When set HIGH, the divider is bypassed. See Table 1.
PU Feedback Clock Input. Connect to FB_OUT for accessing the
phase-locked loop (PLL).
PLL_EN
PU PLL Enable Input. When asserted HIGH, PLL is enabled. And when LOW,
PLL is bypassed.
7
REF_SEL
TCLK_SEL
MR#/OE
PU Reference Select Input. When HIGH, the crystal oscillator is selected. And
when LOW, TCLK (0,1) is the reference clock.
8
PU TCLKSelectInput. WhenLOW, TCLK0isselectedandwhenHIGHTCLK1
is selected.
2
PU Master Reset/Output Enable Input. When asserted LOW, resets all of the
internal flip-flops and also disables all of the outputs. When pulled HIGH,
releases the internal flip-flops from reset and enables all of the outputs.
14
INV_CLK
I
PU InvertedClockInput. Whenset HIGH, QC(2,3)outputs areinverted. When
set LOW, the inverter is bypassed.
3
4
SCLK
I
I
PU Serial Clock Input. Clocks data at SDATA into the internal register.
SDATA
PU Serial Data Input. Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in power
management.
17, 22, 28,
VDDC
3.3V Power Supply for Output Clock Buffers.
33,37, 45, 49
13
VDD
VSS
3.3V Supply for PLL.
Common Ground.
1, 15, 24, 30,
35, 39, 47, 51
Note:
2. A bypass capacitor (0.1 µF) should be placed as close as possible to each positive power (< 0.2”). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.
Document #: 38-07089 Rev. *D
Page 2 of 9
Z9973
inputs (see Table 1). The VCO frequency is then divided to
provide the required output frequencies. These dividers are
set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs (see
Table 2). For situations in which the VCO needs to run at
relatively low frequencies and hence might not be stable,
assert VCO_SEL LOW to divide the VCO frequency by 2. This
will maintain the desired output relationships, but will provide
an enhanced PLL lock range.
Functional Description
The Z9973 has an integrated PLL that provides low-skew and
low-jitter clock outputs for high-performance microprocessors.
Three independent banks of four outputs as well as an
independent PLL feedback output, FB_OUT, provide excep-
tional flexibility for possible output configurations. The PLL is
ensured stable operation given that the VCO is configured to
run between 200 MHz to 480 MHz. This allows a wide range
of output frequencies up to125 MHz.
The Z9973 is also capable of providing inverted output clocks.
When INV_CLK is asserted HIGH, QC2 and QC3 output
clocks are inverted. These clocks could be used as feedback
outputs to the Z9973 or a second PLL device to generate early
or late clocks for a specific design. This inversion does not
affect the output to output skew.
The phase detector compares the input reference clock to the
external feedback input. For normal operation, the external
feedback input, FB_IN, is connected to the feedback output,
FB_OUT. The internal VCO is running at multiples of the input
reference clock set by FB_SEL(0:2) and VCO_SEL select
Table 2. Frequency Select Inputs
VCO_SEL
SELA1
SELA0
QA
SELB1
SELB0
QB
SELC1
SELC0
QC
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO/8
VCO/12
VCO/16
VCO/24
VCO/4
VCO/6
VCO/8
VCO/12
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO/8
VCO/12
VCO/16
VCO/20
VCO/4
VCO/6
VCO/8
VCO/10
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VCO/4
VCO/8
VCO/12
VCO/16
VCO/2
VCO/4
VCO/6
VCO/8
1. contain short or “runt” clock periods. These are clock cycles
in which the cycle(s) are shorter in period than either the
old or new frequency to which it is being transitioned.
Zero Delay Buffer
When used as a zero delay buffer, the Z9973 will likely be in a
nested clock tree application. For these applications the
Z9973 offers a low-voltage PECL clock input as a PLL
reference. This allows the user to use LVPECL as the primary
clock distribution device to take advantage of its far superior
skew performance. The Z9973 can then lock onto the LVPECL
reference and translate with near-zero delay to low-skew
outputs.
2. contain stretched clock periods. These are clock cycles in
which the cycle(s) are longer in period than either the old
or new frequency to which it is being transitioned.
This device specifically includes logic to guarantee that runt
and stretched clock pulses do not occur if the device logic
levels of any or all of the following pins changed “on the fly”
while it is operating: SELA, SELB, SELC, and VCO_SEL.
By using one of the outputs as a feedback to the PLL, the
propagation delay through the device is eliminated. The PLL
works to align the output edge with the input reference edge
thus producing near-zero delay. The reference frequency
affects the static phase offset of the PLL and thus the relative
delay between inputs and outputs. Because the static phase
offset is a function of the reference clock, the Tpd of the Z9973
is a function of the configuration used.
SYNC Output
In situations where output frequency relationships are not
integer multiples of each other, the SYNC output provides a
signal for system synchronization. The Z9973 monitors the
relationship between the QA and the QC output clocks. It
provides a low-going pulse, one period in duration, one period
prior to the coincident rising edges of the QA and QC outputs.
The duration and the placement of the pulse depend on the
higher of the QA and QC output frequencies. The following
timing diagram illustrates various waveforms for the SYNC
output (see Figure 1). Note. The SYNC output is defined for
all possible combinations of the QA and QC outputs even
though under some relationships the lower frequency clock
could be used as a synchronizing signal.
Glitch-Free Output Frequency Transitions
Customarily, when output buffers have their internal counters
changed “on the fly,” their output clock periods will:
Document #: 38-07089 Rev. *D
Page 3 of 9
Z9973
VCO
1:1 Mode
2:1 Mode
QA
QC
SYNC
QA
QC
SYNC
3:1 Mode
QC
QA
SYNC
3:2 Mode
4:1 Mode
QA
QC
SYNC
QC
QA
SYNC
4:3 Mode
6:1 Mode
QA
QC
SYNC
QA
QC
SYNC
Figure 1. Sync Output Waveforms
Document #: 38-07089 Rev. *D
Page 4 of 9
Z9973
serial data. An output is frozen when a logic “0” is programmed
and enabled when a logic “1” is written. The enabling and
freezing of individual outputs is done in such a manner as to
eliminate the possibility of partial “runt” clocks.
Power Management
The individual output enable/freeze control of the Z9973
allows the user to implement unique power management
schemes into the design. The outputs are stopped in the logic
“0” state when the freeze control bits are activated. The serial
input register contains one programmable freeze enable bit for
12 of the 14 output clocks. The QC0 and FB_OUT outputs
cannot be frozen with the serial port, which avoids any
potential lock-up situation should an error occur in loading the
The serial input register is programmed through the SDATA
input by writing a logic “0” start bit followed by 12 NRZ freeze
enable bits (see Figure 2). The period of each SDATA bit
equals the period of the free-running SCLK signal. The SDATA
is sampled on the rising edge of SCLK.
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively
D4-D7 are the control bits for QB0-QB3, respectively
D8-D10 are the control bits for QC1-QC3, respectively
D11 is the control bit for SYNC
Figure 2. SDATA Input Register
Document #: 38-07089 Rev. *D
Page 5 of 9
Z9973
Maximum Ratings[3]
Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V
Maximum Input Voltage Relative to VDD:.............VDD + 0.3V
Storage Temperature: ................................–65°C to + 150°C
Operating Temperature:................................–40°C to +85°C
Maximum ESD protection ...............................................2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current:..................................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to
the range:
VSS < (VIN or VOUT) < VDD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters (VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C)
Parameter
VIL
Description
Input LOW Voltage
Conditions
Min.
VSS
2.0
Typ.
Max.
0.8
Unit
V
VIH
Input HIGH Voltage
VDD
1000
V
VPP
Peak-to-Peak Input Voltage
PECL_CLK
300
mV
VCMR
IIL
Common Mode Range PECL_CLK[9]
Input Low Current[10]
VDD – 2.0
VDD – 0.6
–120
120
V
µA
µA
V
IIH
Input High Current[10]
VOL
VOH
IDDQ
IDDA
IDD
Output Low Voltage[11]
Output High Voltage[11]
Quiescent Supply Current
PLL Supply Current
IOL = 20 mA
0.5
IOH = –20 mA
2.4
V
10
15
15
20
mA
mA
mA
VDD only
Dynamic Supply Current
QA and QB @ 60 MHz,
225
QC @ 120 MHz, CL = 30 pF
QA and QB @ 25 MHz,
QC @ 50 MHz, CL = 30 pF
125
4
CIN
Input Pin Capacitance
pF
[4]
AC Parameters (VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C)
Parameter Description Conditions
Tr / Tf TCLK Input Rise / Fall
Min.
Typ.
Max.
3.0
Units
ns
Fref
Reference Input Frequency
Reference Input Duty Cycle
PLL VCO Lock Range
Note 5
25
Note 5
75
MHz
%
FrefDC
Fvco
200
480
10
MHz
ms
Tlock
Maximum PLL Lock Time
Output Clocks Rise/Fall Time[6]
Tr / Tf
0.8V to 2.0V
0.15
1.2
ns
Notes:
3. The voltage on any input or I/O pic cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Parameters are guaranteed by design and characterization. Not 100% tested in production.
5. Maximum and minimum input reference is limited by VC0 lock range.
6. Outputs loaded with 30 pF each.
Document #: 38-07089 Rev. *D
Page 6 of 9
Z9973
AC Parameters (VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C) (Continued)[4]
Parameter
Fout
Description
Conditions
Min.
Typ.
Max.
Units
Maximum Output Frequency
Q (÷2)
Q (÷4)
Q (÷6)
Q (÷8)
125
120
80
MHz
60
FoutDC
Output Duty Cycle[6]
TCYCLE
/2 – 750
TCYCLE
/2 + 750
ps
tpZL, tpZH
tpLZ, tpHZ
TCCJ
Output Enable Time[6](all outputs)
Output Disable Time[6](all outputs)
Cycle to Cycle Jitter (peak to peak)[6]
Any Output to Any Output Skew[6,7]
Propagation Delay[7,8]
2
2
10
8
ns
ns
ps
ps
ps
± 100
250
–25
130
70
TSKEW
350
175
330
270
–225
–70
Tpd
QFB = (÷8)
–130
Ordering Information
Part Number
IMIZ9973BA
IMIZ9973BAT
Package Type
52-pin TQFP
52-pin TQFP–Tape and Reel
Production Flow
Industrial, –40°C to +85°C
Industrial, –40°C to +85°C
Notes:
7. 50Ω transmission line terminated into VDD/2.
8. Tpd is specified for a 50-MHz input reference. Tpd does not include jitter.
9. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR
range and the input lies within the VPP specification.
10. Inputs have pull-up/pull-down resistors that effect input current.
11. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
Document #: 38-07089 Rev. *D
Page 7 of 9
Z9973
Package Drawing and Dimensions
52-lead Thin Plastic Quad Flat Pack (10 × 10 × 1.4 mm) A52
51-85131-**
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-07089 Rev. *D
Page 8 of 9
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Z9973
Document Title: Z9973 3.3V, 125 MHz Multi-Output Zero Delay Buffer
Document Number: 38-07089
Orig. of
Rev.
**
ECN No. Issue Date
Change
Description of Change
Convert from IMI to Cypress
Changed Commercial to Industrial
107125
108067
111799
06/06/01
07/03/01
02/06/02
IKA
*A
NDP
*B
BRK
Convert from Word Doc to Adobe Framemaker Cypress Format
Changed the Timing Diagram and the operating voltage condition
*C
*D
116452
122774
07/30/02
12/21/02
HWT
RBI
Corrected the Ordering Information to match the DevMaster.
Add power up requirements to maximum ratings information.
Document #: 38-07089 Rev. *D
Page 9 of 9
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