IMSSG559AYB [ETC]
CPU System Clock Generator ; CPU的系统时钟发生器\n
| 型号： | IMSSG559AYB |
| 厂家： | 
ETC |
| 描述： | CPU System Clock Generator
|
| 文件： | 总8页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SG559
Mobile Pentium Processor Application Clock Generator with SSCG, USB and Power
Management Support
Approved Product
FREQUENCY TABLE
CPU
PRODUCT FEATURES
SEL100/66#
PCI
33.3 Mhz
33.2 MHz
Supports clock requirements for Mobile Pentium®
Processor
0
1
66.4 Mhz*
99.8 Mhz**
*Down Spread 1.25% (total); **Down Spread .5% (total)
2 Host and 5 PCI clocks
Separate supply pins for mixed (3.3/2.5V) voltage
application.
<175ps skew among CPU clocks.
< 250ps skew among PCI clocks.
48mhz for USB.
CONNECTION DIAGRAM
28-pin SSOP package for minimum board space.
Power management capabilities
28
1
XIN
XOUT
VSS
VSS
2
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDR
REF
BLOCK DIAGRAM
3
4
PCI_F
PCI1
VDDP
PCI2
PCI3
VDDP
PCI4
PCI5
VSS
VDDC
CPU0
VDDR
XIN
XOUT
REF
5
OSC
6
CPU1
7
VSS
VDDC
CPUCLK (0:1)
8
VDD
CPU_STOP#
PLL
9
VSS
PCI_STOP#
SEL1066#
VDDP
10
11
12
13
14
PCI_STOP#
CPU_STOP#
PWR_DWN#
48M
PCI (1:5)
PCI_F
PWR_DWN#
VDD
VSS
48 MHz
SEL100/ 66#
PLL
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/12/1999
Page 1 of 8
SG559
Mobile Pentium Processor Application Clock Generator with SSCG, USB and Power
Management Support
Approved Product
PIN DESCRIPTION
PIN No.
1
Pin Name
PWR
VDD
I/O
I
TYPE
Description
OSC1 On-chip reference oscillator input pin. Requires either an
external parallel resonant crystal (nominally 14.318 MHz) or
externally generated reference signal
XIN
2
VDD
O
OSC1 On-chip reference oscillator output pin. Drives an external
parallel resonant crystal. When an externally generated
reference signal is used at Xin, this pin is left unconnected
PADI4 Frequency select input pins. See frequency select table on
XOUT
15
23, 24
4
-
I
SEL100/66#
PU
page 1.This pin has internal pull-up.
VDDC
VDDP
O
O
BUF1 Clock outputs. CPU frequency table specified on page 1.
CPUCLK
(0:1)
PCI_F
BUF4 Free running PCI clock. When PCI_STP# = 0, this clock does
NOT stop.
16
5, 7, 8,
10, 11
26
VDD48
VDDP
O
O
BUF3 48 MHz fixed clock.
BUF4 PCI bus clocks. See frequency select table on page 1.
48M
PCI(1:5)
VDDR
-
O
I
BUF3 Buffered outputs of on-chip reference oscillator.
REF
PCI_STOP#
19
PAD
PU
PAD
PU
PAD
PU
-
When driven to a logic low level, this pin will synchronously stop
all PCI clocks (except PCI_F) at a logic low level.
When driven to a logic low level, this pin will synchronously stop
all CPU clocks at a logic low level.
This pin is active low. When asserted low, the device is in
shutdown mode. VCO’s, Crystal, and outputs are turned off.
3.3 volt power supply for core logic.
18
17
-
-
I
I
CPU_STOP#
PWR_DWN#
13, 21
3, 12,
14, 20,
22, 28
9, 6
-
-
P
P
VDD
VSS
-
Ground pins for the device.
-
P
-
-
3.3 Volt power supply pins for PCI (1:5) and PCI_F clock output
buffers.
3.3 or 2.5 Volt power supply for CPUCLK (0:1) outputs.
3.3 Volt power supply pins for reference clock output buffers
and crystal circuit.
VDDP
25
27
-
-
P
P
VDDC
VDDR
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/12/1999
Page 2 of 8
SG559
Mobile Pentium Processor Application Clock Generator with SSCG, USB and Power
Management Support
Approved Product
POWER MANAGEMENT FUNCTIONS
All PCI (excluding PCI_F) and CPU clocks can be enabled or stopped via the PCI_STOP# and CPU_STOP# input pins.
All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped and
on transitions from stopped to running when the chip was not powered down. On power up, the VCOs will stabilize to
the correct pulse widths within 0.2 mS. The CPU and PCI clocks transition between running and stopped by waiting for
one positive edge on PCI_F followed by a negative edge on the clock of interest, after which high levels of the output are
either enabled or disabled.
PWR_DWN#
CPU_STOP#
PCI_STOP#
CPUCLK
PCICLK
OTHER CLKs
XTAL & VCOs
1
1
1
1
0
0
1
1
0
1
0
1
LOW
LOW
RUNNING
RUNNING
LOW
RUNNING
LOW
RUNNING
RUNNING
RUNNING
RUNNING
RUNNING
RUNNING
RUNNING
RUNNING
RUNNING
0
x (don’t care)
x (don’tcare)
LOW
LOW
LOW
OFF
POWER MANAGEMENT TIMING
PCI_F
PCI_STOP#
PCICLK(1:5)
CPU_STOP#
CPUCLK(0:1)
POWER MANAGEMENT TIMING
Signal State
Latency
Signal
No. of rising edges of free
running PCICLK (PCIF)
CPU_ST0P#
PCI_ST0P#
0 (disabled)
1 (enabled)
0 (disabled)
1 (enabled)
1
1
1
1
NOTES:
1. Clock on/off latency is defined in the number of rising edges of free running PCI CLOCK between the clock disable
goes low/high to the first valid clock comes out of the device.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/12/1999
Page 3 of 8
SG559
Mobile Pentium Processor Application Clock Generator with SSCG, USB and Power
Management Support
Approved Product
SPECTRUM SPREAD CLOCKING
Down Spread
Amplitude
(dB)
Without Spectrum Spread
With Spectrum Spread
Frequency (MHz)
Center
Spectrum Analysis
MAXIMUM RATINGS
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Voltage Relative to VSS:
Voltage Relative to VDD:
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
-0.3V
0.3V
-65ºC to + 150ºC
-40ºC to +85ºC
7V
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/12/1999
Page 4 of 8
SG559
Mobile Pentium Processor Application Clock Generator with SSCG, USB and Power
Management Support
Approved Product
ELECTRICAL CHARACTERISTICS
Characteristic
Symbol Min
Typ
Max
0.8
Units
Conditions
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
VIL
VIH
IIL
-
-
-
Vdc
Vdc
µA
-
-
2.0
-
-66
5
IIH
µA
Output Low Voltage
IOL = 4mA
VOL
-
-
-
0.4
Vdc
All Outputs (see buffer spec)
Output High Voltage
IOH = 4mA
VOH
2.4
-
Vdc
All Outputs Using 3.3V Power
(see buffer spec)
Tri-State leakage Current
Dynamic Supply Current
Static Supply Current
Short Circuit Current
Ioz
Idd
-
-
-
-
-
-
10
140
70
-
µA
mA
µA
CPU = 66.6 MHz, PCI = 33.3 MHz
pwr_dwn# (PIN17) = 0
Isdd
ISC
-
25
mA
1 output at a time - 30 seconds
VDD = VDDP=VDDR =3.3V ±5%, VDDC = 2.5V ±5%,, TA = -40ºC to +85ºC
SWITCHING CHARACTERISTICS
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Measured at 1.5V
Output Duty Cycle
CPU to PCI Offset
-
45
1
50
3
55
4
%
ns
ps
tOFF
tSKEW
15 pf Load Measured at 1.5V
15 pf Load Measured at 1.5V
Buffer out Skew All CPU
and PCI Buffer Outputs
-
-
250
-
-
+250
500
ps
-
∆Period Adjacent Cycles
∆P
Jitter Spectrum 20 dB
Bandwidth from Center
BWJ
KHz
VDD = VDDP =VDDR =3.3V ±5%, VDDC = 2.5V ±5%,, TA = -40ºC to +85ºC
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/12/1999
Page 5 of 8
SG559
Mobile Pentium Processor Application Clock Generator with SSCG, USB and Power
Management Support
Approved Product
BUFFER 1 CHARACTERISTICS FOR CPUCLK(0:1)
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current Min
IOHmin
IOHmax
IOLmin
IOLmax
Zo
-27
-
-
-
-
-
-
-
-
mA
mA
Vout = 1.0 V
Vout = 2.6 V
Vout = 1.2 V
Vout = 0.3 V
66 and 100 MHz
20 pF Load
Pull-Up Current Max
-27
Pull-Down Current Min
Pull-Down Current Max
Dynamic Output Impedance
27
-
-
mA
27
15
1.6
mA
10
0.4
Ohms
nS
Rise Time Between
0.4 V and 2.0 V
TR
Fall Time
TF
0.5
-
1.6
nS
20 pF Load
Between 0.4 V and 2.0 V
VDD = VDDP= VDDR =3.3V ±5%, VDDC = 2.5V ±5%,, TA = -40ºC to +85ºC
BUFFER 3 CHARACTERISTICS FOR REF, 48M
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current Min
IOHmin
IOHmax
IOLmin
IOLmax
Zo
-29
-
-
-
-
-
-
-
-
mA
mA
Vout = 1.0 V
Vout = 3.135 V
Vout = 1.95 V
Vout = 0.4 V
Pull-Up Current Max
-23
Pull-Down Current Min
Pull-Down Current Max
Dynamic Output Impedance
29
-
-
mA
27
25
2.0
mA
18
0.5
Ohms
nS
66 and 100 MHz
20 pF Load
Rise Time
TR
Between 0.4 V and 2.4 V
Fall Time
TF
0.5
-
2.0
nS
20 pF Load
Between 0.4 V and 2.4 V
VDD = VDDP= VDDR =3.3V ±5%, VDDC = 2.5V ±5%,, TA = -40ºC to +85ºC
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/12/1999
Page 6 of 8
SG559
Mobile Pentium Processor Application Clock Generator with SSCG, USB and Power
Management Support
Approved Product
BUFFER 4 CHARACTERISTICS FOR PCI_F, PCI(1:5)
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Pull-Up Current Min
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
IOHmin
IOHmax
IOLmin
IOLmax
-33
-
-
-
-
-
-
mA
mA
mA
mA
Vout = 1.0 V
Vout = 3.135 V
Vout = 1.95 V
Vout = 0.4 V
-33
30
-
-
38
Dynamic Output Impedance
Rise Time
Zo
TR
14
0.5
-
-
20
2.0
Ohms
nS
66 and 100 MHz
30 pF Load
Between 0.4 V and 2.4 V
Fall Time
TF
0.5
-
2.0
nS
30 pF Load
Between 0.4 V and 2.4 V
VDDP= VDDR =3.3V ±5%, VDDC = 2.5V ±5%,, TA = -40ºC to +85ºC
CRYSTAL AND REFERENCE OSCILLATOR PARAMETERS
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Frequency
Tolerance
Fo
TC
TS
12.00
14.31818
16.00
+/-100
+/- 100
5
MHz
PPM
PPM
PPM
-
-
-
-
-
Calibration note 1
-
Stability (Ta -10 to +60C) note 1
Aging (first year @ 25C) note 1
Parallel Resonant
TA
-
Mode
OM
CP
VBIAS
Ts
-
-
Pin Capacitance
DC Bias Voltage
Startup time
5
pF
V
Capacitance of XIN and Xout pins
0.3Vdd
Vdd/2
0.7Vdd
-
-
-
-
20
-
30
-
µS
Load Capacitance
CL
pF
note 1
Effective Series
resonant
R1
40
Ohms
resistance
Power Dissipation
Shunt Capacitance
X1 and X2 Load
DL
CO
CL
-
-
-
0.10
7
mW
pF
note 1
--
17
pF
internal crystal loading capacitors on
each pin (to ground)
For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the
effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit
traces, the clock generator and any onboard discrete load capacitors.
Budgeting Calculations
Typical trace capacitance, (< half inch) is 4 pF, Load to the crystal is therefore
Clock generator internal pin capacitance of 36 pF, Load to the crystal is therefore
the total parasitic capacitance would therefore be
2.0 pF
18.0 pF
= 20.0 pF(matching CL)
Note 1: It is recommended but not mandatory that a crystal meets these specifications.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/12/1999
Page 7 of 8
SG559
Mobile Pentium Processor Application Clock Generator with SSCG, USB and Power
Management Support
Approved Product
PACKAGE DRAWING AND DIMENSIONS
28 PIN SSOP OUTLINE DIMENSIONS
C
L
INCHES
MILLIMETERS
SYMBOL
MIN
NOM
MAX
MIN
NOM
MAX
H
E
A
A1
A2
B
0.068
0.002
0.066
0.010
0.005
0.397
0.205
0.073
0.005
0.078 1.73
0.008 0.05
0.070 1.68
0.015 0.25
0.009 0.13
0.407 10.07
0.212 5.20
1.86
0.13
1.99
0.21
1.78
0.38
0.22
10.33
5.38
0.068
1.73
D
a
0.012
0.30
A2
C
D
E
0.006
0.15
A
0.402
10.20
5.30
A1
0.209
e
B
e
0.0256 BSC
0.307
0.65 BSC
7.80
H
a
0.301`
0°
0.311 7.65
7.90
8°
4°
8°
0°
4°
L
0.022
0.030
0.037 0.55
0.75
0.95
ORDERING INFORMATION
Part Number
Package Type
Production Flow
Commercial, -40ºC to +85ºC
IMISG559AYB
28 PIN SSOP
Note:
The ordering part number is formed by a combination of device number, device revision, package style, and
screening as shown below.
Marking: Example: IMI
SG559AYB
Date Code, Lot #
IMISG559AYB
Flow
B = Commercial, -40ºC to + 85ºC
Package
Y = SSOP
Revision
IMI Device Number
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Rev. 1.0
4/12/1999
Page 8 of 8
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