INDT166B [ETC]
Long Distance Digital Display Link Transmitter & Receiver; 远程数字显示链接发送接收
| 型号： | INDT166B |
| 厂家： | 
ETC |
| 描述： | Long Distance Digital Display Link Transmitter & Receiver |
| 文件： | 总40页 (文件大小：1567K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INDT/R166B
INDT/R331B
Preliminary Data Sheet
Order this document by Q_DS_IND166-331
Long Distance Digital Display
Link Transmitter & Receiver
The GigaSTaR Digital Display Link 166/331-series is an
innovative high-speed link featuring simultaneous
transmission of digital video, audio and bi-directional
sideband data over one standard shielded twisted pair
cable up to 50 m (500 m with fiber optics). It supports
VGA…UXGA as well as Digital TV (DTV) and High-
Definition TV (HDTV) formats up to 720p or HDTV1080i
with up to 16.7 million colors. The sideband channels
provide bandwidth up to 264 Mbps to connect peripheral
components like keyboard, mouse, disc drive and audio
devices.
VESA Format
VESA Format
at 24bit/60Hz
VGA…XGA
at 18bit/60Hz
INDT/R166B
INDT/R331B
VGA…WXGA
VGA…UXGA
HDTV (24 bit)
480p (60fps), 720p (30fps)
480p (60fps), 720p (60fps), 1080i (30fps)
VGA…SXGA
Compared to the 165/330-series the 166/331 offer
additional features like a tristate pixel interface (Rx only)
and an integrated pixel buffer to reducing pixel clock
variations. The 166/331 may be used as direct drop-in
replacement for the 165/330 under specified conditions.
INDT/R166B
INDT/R331B
Features:
Applications:
• Long distance multimedia consoles
• High resolution industrial remote terminals
• Video broadcast systems
• Parallel graphics controller and LC-display interfaces:
− 18- / 24-bit (1 pixel/clock)
− 36- / 48-bit (2 pixel/clock)
• Pixel data clocking on rising/falling/both clock edges
• Long distance camera links
• Machine vision systems
• Pixel Clock frequency: 24 – 161 MHz
• Direct adaptation to DVI and LDI/LVDS standard interface
devices
• Digital TV equipment
• 4 channel audio interface (IEC958 compliant S/P-DIF)
• High- and low-speed bi-directional sideband data channels
• Single + 3.3 V power supply
• Video Projectors and Home Cinemas
• DVI Extension products
• Extended temperature range: -40 – +85 °C
Typical Application:
PC
TFT
LC-Display
Transmitter
Receiver
VIDEO
Graphics
VIDEO
Controller
Camera
DVD
DATA
STP-cable
INDT166B
or
INDR166B
or
DATA
INDT331B
INDR331B
AUDIO
AUDIO
HDTV
Date: 2005-03-14 Revision: 0.1
Page 1 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
Index
1
General Description ............................................................................................................................ 3
1.1
1.1.1
1.2
1.2.1
Link Interface ....................................................................................................................................3
Link Interface Bandwidth ............................................................................................................3
Pixel Interface ...................................................................................................................................4
General Information....................................................................................................................4
Pixel Interface Modes.................................................................................................................5
Pixel Clock Sampling Modes ......................................................................................................5
Pixel Data I/O Color Bit Mapping ................................................................................................7
1.2.2
1.2.3
1.2.4
1.3
Sideband Interface............................................................................................................................8
1.3.1
General Information....................................................................................................................8
Low-speed Upstream Sideband Data Channel (SB0)..................................................................9
High-speed Upstream Sideband Data Channel (SB1).................................................................9
Low-speed Downstream Sideband Data Channel (SB2) .............................................................9
High-speed Downstream Sideband Data Channel (SB3, SB4)....................................................9
Sideband Interface Signals.......................................................................................................10
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.4
Audio Interface................................................................................................................................11
2
3
Device Configuration ........................................................................................................................ 12
2.1
Pixel Clock Conditioning (Rx only)...................................................................................................12
Configuration Vectors and Configuration Data .................................................................................13
Configuration Process and Timing...................................................................................................14
Interface Configuration Scheme ......................................................................................................15
Error Handling and Reset ................................................................................................................15
2.2
2.3
2.4
2.5
Electrical Specification ..................................................................................................................... 16
3.1 External Circuits..............................................................................................................................16
3.1.1
External Loop Filter Specification..............................................................................................16
Serial Transmission Cable Interconnect....................................................................................16
Serial Transmission Cable Termination.....................................................................................17
Receiver Equalizer ...................................................................................................................17
Reference Clock.......................................................................................................................17
VREF Reference Circuitry...........................................................................................................17
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Power Supply..................................................................................................................................17
Absolute Maximum Ratings.............................................................................................................18
Recommended Operating Conditions ..............................................................................................18
AC–Characteristics (under recommended operating conditions, Reference Clock Freq. = 66 MHz)..19
DC–Characteristics (under recommended operating conditions) ......................................................19
Reference Clock Specification (Ta = -40 to 85° C; Vcc = 3.15 to 3.45 V)..........................................19
Timing Specification ........................................................................................................................20
4
5
6
Signals............................................................................................................................................... 27
4.1
INDT166B Transmitter Signal Description........................................................................................27
INDR166B Receiver Signal Description...........................................................................................28
INDT331B Transmitter Signal Description........................................................................................30
INDR331B Receiver Signal Description...........................................................................................32
4.2
4.3
4.4
Pin Assignment................................................................................................................................. 34
5.1
INDT166B Transmitter ....................................................................................................................34
INDR166B Receiver........................................................................................................................35
INDT331B Transmitter ....................................................................................................................36
INDR331B Receiver........................................................................................................................37
5.2
5.3
5.4
Package Information......................................................................................................................... 38
6.1
6.2
INDT/R166B....................................................................................................................................38
INDT/R331B....................................................................................................................................39
7
8
Ordering and Product Availability.................................................................................................... 40
Revision History................................................................................................................................ 40
Date: 2005-03-14 Revision: 0.1
Page 2 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
1 General Description
The GigaSTaR Digital Display Link is a high-speed serial and long distance link for video, audio and digital data, which
supports the popular VESA and Digital TV standards as well as proprietary video formats from VGA to UXGA with color
depth up to 24 bits.
1.1 Link Interface
The INDT/R166B link requires one single twisted pair cable for the high-speed downlink. The INDT/R331B provides double
bandwidth by using two twisted pairs. Both devices offer an uplink connection using a twisted pair. The downlink must be
established before the uplink can be activated.
D
VIDEO
AUDIO
VIDEO
AUDIO
Downlink
E
M
U
X
M
U
X
Only INDT/R330
SIDEBAND
DATA
SIDEBAND
DATA
Uplink
Figure 1.1: GigaSTaR Digital Display Link Interfaces
The transmitter’s and receiver’s generic parallel RGB interfaces (CMOS/TTL compatible) support direct connection to the
parallel data port of any graphic controller or to any flat panel display with a parallel pixel data port. The bit width of the
pixel data path can be scaled to support the 18- or 24-bit mode with 1 pixel/clock, the 36- or 48-bit mode with 2 pixel/clock.
Pixel data can be clocked into the transmitter on the rising, falling or on both edges (18-, 24-bit mode) of the pixel clock.
Pixel data are provided at the receiver on the rising, falling or on both edges (18-, 24-bit mode) of the pixel clock.
1.1.1 Link Interface Bandwidth
The bandwidth of the downlink is shared between video, audio and sideband data. Disabling audio and/or sideband
channels, even partially, increases the available bandwidth for the video data. The video configuration required for VESA
or Digital TV (DTV) / High-Definition TV (HDTV) standard compatible video resolutions is shown in Table 1.1 and Table
1.2.
INDT/R166B configurations
Up to
Mode
High-speed
Sideband
Low-speed
Sideband
VESA-/DTV-Mode
Audio
1
2
3
4
X
–
–
X
X
X
–
X/–
X
XGA 18 color bits
XGA 18 color bits
–
XGA 24 color bits
X
X
480p(60fps), 720p (30fps)
Table 1.1: INDT/R166B Video Configuration
Date: 2005-03-14 Revision: 0.1
Page 3 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
INDT/R331B configurations
Up to
Mode
High-speed
Sideband
Low-speed
Sideband
VESA-/DTV-Mode
Audio
1
2
3
4
5
X
–
X
X
–
X/–
X
SXGA 24 color bits
UXGA 18 color bits
UXGA 18 color bits
720p (60fps)
–
–
X
X
X
X
X
X
1080i (30fps)
Table 1.2: INDT/R331B Video Configuration
Note: Implementation of video modes other than VESA or DTV/HDTV is possible. Special modes may need evaluation.
1.2 Pixel Interface
1.2.1 General Information
The pixel interface is designed to support direct interfacing to any digital graphics device with a parallel data port such as
graphic-cards/controllers, CCD cameras or flat panel TFT displays. With standard interface devices the data port can also
be adapted to systems with non-generic parallel interfaces such as DVI or LVDS/OpenLDI.
PX_CLK_IN
PX_CLK_OUT
PX_CLK+
PX_CLK–
Downstream
Video
Video
PX_CLK
PX_D[47:0]
PX_D[47:0]
48
48
PX_HSYNC
PX_VSYNC
PX_DE
PX_HSYNC
PX_VSYNC
PX_DE
INDT
INDR
Receiver
Transmitter
Figure 1.2: Pixel Interface
Signal
Tx1
IN
Rx
Description
PX_D[47:0]
PX_CLK+
OUT Configurable parallel pixel data interface
IN
OUT Tx Pixel clock 24 – 161 MHz, diff + or single-ended
OUT Tx Pixel clock 24 – 161 MHz, diff –
OUT Rx Pixel clock 24 – 161 MHz
PX_CLK–
PX_CLK
PX_CLK_OUT
PC_CLK_IN
PX_HSYNC
PX_VSYNC
PX_DE
IN
OUT Rx Pixel clock 24 – 161 MHz, de-jitter
IN
Rx Pixel clock 24 – 161 MHz, de-jitter
IN
IN
IN
OUT Pixel data framing – Horizontal sync pulse
OUT Pixel data framing – Vertical sync pulse
OUT Pixel data framing – Data enable
Table 1.3: Pixel Interface Signals
1 Configurable to 3.3V or 1.8V input levels via VREF-pin.
Date: 2005-03-14 Revision: 0.1
Page 4 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
The transmitter’s pixel interface accepts pixel data with a pixel clock frequency of 24 – 161 MHz (full pixel mode). For the
Tx side in single-ended mode, PX_CLK+ is the clock input and PX_CLK– has to be tied to GND. A differential pixel clcok
mode on the Rx side is not available. All pixel data and pixel clock inputs of the transmitter can be selected through the
VREF-pin to either work with conventional graphic controllers with 3.3 V output voltage swing or to work with latest
controllers with low voltage swing (1.0 – 2.0 V, see Figure 3.3: VREF Reference Circuitry). The pixel data and pixel
clock outputs of the receiver provide a 3.3 V CMOS compliant output.
1.2.2 Pixel Interface Modes
The pixel interface is configurable to accommodate all the various graphic interface standards in the market. The width of
the pixel interface is a function of the selected operating mode.
• In full-pixel mode the bit width of the pixel interface can be set to support an 18- or 24-bit wide parallel video interface.
1 pixel per sampling edge is transmitted.
• In double-pixel mode the bit width of the pixel interface can be set to support a 36- or 48-bit wide parallel video
interface. 2 pixels per sampling edge are transmitted.
1.2.3 Pixel Clock Sampling Modes
The pixel interface can be set to support data sampling at the rising, falling or at both edges of the pixel clock,
depending on the selected mode.
Table 1.4 and , Figure 1.4, Figure 1.5 summarize the various options for configuring the pixel interface.
Clock
Pixel Mode
PX_CLK+
PX_CLK-
Description
Edge
rising
falling
both
18 bits of pixel(n) sampled at rising edge of PX_CLK+
18 bits of pixel(n) sampled at falling edge of PX_CLK+
18 bits of pixel(n) sampled at both edges of PX_CLK+
24 bits of pixel(n) sampled at rising edge of PX_CLK+
24 bits of pixel(n) sampled at falling edge of PX_CLK+
24 bits of pixel(n) sampled at both edges of PX_CLK+
–
–
–
–
–
–
↑
↓
↑↓
↑
↓
↑↓
18-bit
(Full Pixel)
rising
falling
both
24-bit
(Full Pixel)
18 bits of pixel(n) and
rising
falling
rising
falling
–
–
–
–
36-bit
(Double
Pixel)
↑
↓
↑
↓
18 bits of pixel(n+1) sampled at rising edge of PX_CLK+
18 bits of pixel(n) and
18 bits of pixel(n+1) sampled at falling edge of PX_CLK+
24 bits of pixel(n) and
48-bit
(Double
Pixel)
24 bits of pixel(n+1) sampled at rising edge of PX_CLK+
24 bits of pixel(n) and
24 bits of pixel(n+1) sampled at falling edge of PX_CLK+
Table 1.4: Overview – Pixel Interface Configurations
Date: 2005-03-14 Revision: 0.1
Page 5 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
PX_DE
18/24-bit Mode
(Full Pixel)
P0
P1
P2
P3
P4
P5
P6
PX_D[23:0]
PX_CLK+
PX_CLK+
PX_CLK+
rising edge clock mode
falling edge clock mode
both edge clock mode
Figure 1.4: Pixel Interface – Full Pixel Modes
PX_DE
Odd pixel
P1
P0
P3
P2
P5
P4
P7
P6
PX_D[47:24]
PX_D[23:0]
PX_CLK+
PX_CLK+
36/48-bit Mode
(Double Pixel)
Even pixel
rising edge clock mode
falling edge clock mode
Figure 1.5: Pixel Interface – Double Pixel Modes
Date: 2005-03-14 Revision: 0.1
Page 6 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
1.2.4 Pixel Data I/O Color Bit Mapping
The color bits are mapped to the parallel I/Os as a function of the selected pixel clock (R = Red, G = Green, B = Blue, O = Odd,
E = Even).
Full Pixel
Double Pixel
36-bit Mode
Data
18-bit Mode
24-bit Mode
48-bit Mode
RO[7]
RO[6]
RO[5]
RO[4]
RO[3]
RO[2]
RO[1]
RO[0]
GO[7]
GO[6]
GO[5]
GO[4]
GO[3]
GO[2]
GO[1]
GO[0]
BO[7]
BO[6]
BO[5]
BO[4]
BO[3]
BO[2]
BO[1]
BO[0]
RE[7]
RE[6]
RE[5]
RE[4]
RE[3]
RE[2]
RE[1]
RE[0]
GE[7]
GE[6]
GE[5]
GE[4]
GE[3]
GE[2]
GE[1]
GE[0]
BE[7]
BE[6]
BE[5]
BE[4]
BE[3]
BE[2]
BE[1]
BE[0]
PX_D47
PX_D46
PX_D45
PX_D44
PX_D43
PX_D42
PX_D41
PX_D40
PX_D39
PX_D38
PX_D37
PX_D36
PX_D35
PX_D34
PX_D33
PX_D32
PX_D31
PX_D30
PX_D29
PX_D28
PX_D27
PX_D26
PX_D25
PX_D24
PX_D23
PX_D22
PX_D21
PX_D20
PX_D19
PX_D18
PX_D17
PX_D16
PX_D15
PX_D14
PX_D13
PX_D12
PX_D11
PX_D10
PX_D9
–
–
–
–
RO[5]
RO[4]
RO[3]
RO[2]
RO[1]
RO[0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
GO[5]
GO[4]
GO[3]
GO[2]
GO[1]
GO[0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
BO[5]
BO[4]
BO[3]
BO[2]
BO[1]
BO[0]
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
R[5]
R[4]
R[3]
R[2]
R[1]
R[0]
–
R[7]
R[6]
R[5]
R[4]
R[3]
R[2]
R[1]
R[0]
G[7]
G[6]
G[5]
G[4]
G[3]
G[2]
G[1]
G[0]
B[7]
B[6]
B[5]
B[4]
B[3]
B[2]
B[1]
B[0]
RE[5]
RE[4]
RE[3]
RE[2]
RE[1]
RE[0]
–
–
–
G[5]
G[4]
G[3]
G[2]
G[1]
G[0]
–
GE[5]
GE[4]
GE[3]
GE[2]
GE[1]
GE[0]
–
PX_D8
–
–
PX_D7
B[5]
B[4]
B[3]
B[2]
B[1]
B[0]
–
BE[5]
BE[4]
BE[3]
BE[2]
BE[1]
BE[0]
–
PX_D6
PX_D5
PX_D4
PX_D3
PX_D2
PX_D1
PX_D0
–
–
Table 1.5: Pixel Interface Bit Mapping
Date: 2005-03-14 Revision: 0.1
Page 7 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
1.3 Sideband Interface
1.3.1 General Information
The sideband interfaces provide a bi-directional data path subdivided into several logical data streams with different
bandwidth in both directions:
Downstream: Data direction from Transmitter (INDT) -->
Upstream: Data direction to Transmitter (INDT) <--
to Receiver (INDR)
from Receiver (INDR)
Activating the upstream sideband data transmission necessitates an additional pair of wires to establish the physical uplink
(see 1.1 Link Interface). STP cables usually contain 4 pairs of wires; thus this extra connection is available in most cases.
If the upstream sideband data channel is not used, it has to be disabled. The downstream sideband data channels can be
partially disabled to provide extra bandwidth for the pixel data transmission.
SB4_CLKI
SB4_CLK
SB4_CLKO
SB4
SB4
SB4_D[1:0]
SB4_D[1:0]
High Speed
High Speed
2
2
SB3_CLKI
SB3_CLKO
SB3_D[1:0]
SB3
SB3
SB3_CLK
Downstream
Upstream
High Speed
High Speed
SB3_D[1:0]
2
4
2
4
SB2
SB2
SB2_CLK
SB2_CLK
Low Speed
Low Speed
SB2_D[3:0]
SB2_D[3:0]
SB1_CLKI
SB1_CLKO
SB1_D[1:0]
SB1_CLK
SB1
SB1
SB1_D[1:0]
High Speed
High Speed
2
4
2
SB0
SB0
SB0_CLK
SB0_CLK
Low Speed
Low Speed
SB0_D[3:0]
SB0_D[3:0]
4
INDT
INDR
Receiver
Figure 1.6: Sideband Data Interfaces
Note: SB4 available at INDT/R331B only.
Date: 2005-03-14 Revision: 0.1
Page 8 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
Signals (D+Clk)
Interface
Speed
Direction
Width
[bit]
Bandwidth
[Mbps]
Asynchro-
nous
Synchro-
nous
Samp-
ling
INDT
INDR
SB0
SB2
SB1
SB3
SB42
4+1
4+1
2+1
2+2
2+2
4+1
4+1
2+2
2+1
2+1
Low speed
Low speed
High speed
High speed
High speed
Upstream
Downstream
Upstream
Downstream
Downstream
4
4
2
2
2
4.125
4.26
–
–
X
X
X
X
X
–
–
111.375
132
132
X
X
X
–
X
X
Table 1.6: Transfer Capabilities Sideband Data Interface Signals
1.3.2 Low-speed Upstream Sideband Data Channel (SB0)
The low-speed upstream sideband data channel consists of one 4 Mbps data channel with a 4-bit parallel interface (or 4
individual 1 Mbps data channels, each consisting of a 1-bit serial interface) and one synchronous clock output (SB0_CLK).
1.3.3 High-speed Upstream Sideband Data Channel (SB1)
The high-speed upstream sideband data channel has a 2-bit wide data interface. Different operating modes can be
selected. The maximum bandwidth is 111 Mbps. This can be used for any generic data link e.g. a low-resolution graphics
channel or a CMOS image sensor.
In asynchronous clocking mode an external clock can be applied into SB1_CLKI of the INDR. The range of the external
acceptable clock frequency is 0 – 55 MHz. In synchronous mode data are read into the INDR using the synchronous clock
frequency of 55 MHz being output at SB1_CLKO. In both cases the transferred data are available at the INDT with a fixed
clock of 55 MHz.
1.3.4 Low-speed Downstream Sideband Data Channel (SB2)
The low-speed downstream sideband data channel consists of one 4 Mbps data channel with a 4-bit parallel interface (or 4
individual 1 Mbps data channels, each consisting of a 1-bit serial interface) and one synchronous clock output (SB2_CLK).
1.3.5 High-speed Downstream Sideband Data Channel (SB3, SB42).
The INDT/R166B (INDT/R331B) features one (two) high-speed downstream sideband data channels, each with a 2-bit
wide data interface. Different operating modes can be selected. The maximum bandwidth is 132 Mbps (2 x 132 Mbps).
In asynchronous clocking mode an external clock can be feed into SB3_CLKI (and SB4_CLKI2) of the INDT. The range of
the external acceptable clock frequency is 0 – 66 MHz. In synchronous mode data are read into the INDT using the
synchronous clock frequency of 66 MHz being output at SB3_CLKO (and SB4_CLKO2). In both cases the transferred data
are available at the INDR with a fixed clock of 66 MHz. In sampling mode, the sideband data are sampled with an internal
sampling clock at 66 MHz.
2 Sideband Data Channel 4 (SB4) only available with INDT/R330B
Date: 2005-03-14 Revision: 0.1
Page 9 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
1.3.6 Sideband Interface Signals
Sideband
SB0
Signal
Dir
OUT
OUT
OUT
OUT
OUT
IN
Description
Sideband Data Channel 0 Upstream Synchronous Clock Output. Data
is provided aligned to rising edge.
SB0_CLK
SB0_D[3:0]
SB1_CLK
SB1_D[1:0]
SB2_CLK
SB2_D[3:0]
SB3_CLKI
SB0
Sideband Data Channel 0 Upstream Output
Sideband Data Channel 1 Upstream Synchronous Clock Output. Data
is provided aligned to rising edge.
SB1
SB1
Sideband Data Channel 1 Upstream Output
Sideband Data Channel 2 Downstream Synchronous Clock Output.
Data is registered at rising edge.
SB2
SB2
Sideband Data Channel 2 Downstream Input
Sideband Data Channel 3 Downstream Asynchronous Clock Input.
Data is registered at rising edge.
SB3
IN
Sideband Data Channel 3 Downstream Synchronous Clock Output.
Data is registered at rising edge.
SB3
SB3
SB3_CLKO
SB3_D[1:0]
SB4_CLKI
OUT
IN
Sideband Data Channel 3 Downstream Input
Sideband Data Channel 4 Downstream Asynchronous Clock Input.
Data is registered at rising edge.
SB43
IN
Sideband Data Channel 4 Downstream Synchronous Clock Output.
SB43
SB43
SB4_CLKO
SB4_D[1:0]
OUT
IN
Data is registered at rising edge.
Sideband Data Channel 4 Downstream Input.
Table 1.7: Sideband Interface Signals (INDT, Transmitter)
Sideband
SB0
Signal
Dir
OUT
IN
Description
Sideband Data Channel 0 Upstream Synchronous Clock Output. Data
is registered at rising edge.
SB0_CLK
SB0_D[3:0]
SB1_CLKI
SB0
Sideband Data Channel 0 Upstream Input
Sideband Data Channel 1 Upstream Asynchronous Clock Input. Data
is registered at rising edge.
SB1
IN
Sideband Data Channel 1 Upstream Synchronous Clock Output. Data
is registered at rising edge.
SB1
SB1
SB2
SB2
SB3
SB3
SB43
SB43
SB1_CLKO
SB1_D[1:0]
SB2_CLK
OUT
IN
Sideband Data Channel 1 Upstream Input
Sideband Data Channel 2 Downstream Synchronous Clock Output.
Data is provided aligned to rising edge.
OUT
OUT
OUT
OUT
OUT
OUT
SB2_D[3:0]
SB3_CLK
Sideband Data Channel 2 Downstream Output
Sideband Data Channel 3 Downstream Synchronous Clock Output.
Data is provided aligned to rising edge.
SB3_D[1:0]
SB4_CLK
Sideband Data Channel 3 Downstream Output
Sideband Data Channel 4 Downstream Synchronous Clock Output.
Data is provided aligned to rising edge.
SB4_D[1:0]
Sideband Data Channel 4 Downstream Output.
Table 1.8: Sideband Interface Signals (INDR, Receiver)
3 Sideband Data Channel 4 (SB4) only available with INDT/R330B
Date: 2005-03-14 Revision: 0.1
Page 10 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
1.4 Audio Interface
The audio interface provides four serial audio channels, which are compliant to the Standard IEC958 Digital audio interface
from the EBU (European Broadcasting Union), also known as S/P-DIF Interface. It supports sampling frequencies of 44,1
kHz and 48,0 kHz. The audio data interface can be disabled to free up bandwidth for pixel data transmission.
AI_C0
AI_C1
AI_C2
AI_C3
AI_C0
AI_C1
AI_C2
AI_C3
Audio
Audio
Downstream
S/P DIF
S/P DIF
INDR
Reveiver
INDT
Transmitter
Figure 1.7: Audio Interface
Signal
AI_C0
AI_C1
AI_C2
AI_C3
Tx
IN
IN
IN
IN
Rx
Description
OUT S/P-DIF Audio Channel 0
OUT S/P-DIF Audio Channel 1
OUT S/P-DIF Audio Channel 2
OUT S/P-DIF Audio Channel 3
Table 1.9: Audio Interface Signals
Date: 2005-03-14 Revision: 0.1
Page 11 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
2 Device Configuration
The GigaSTaR Digital Display Link allows for configuring the pixel-, sideband- and audio-interface.
2.1 Pixel Clock Conditioning (Rx only)
In order to allow for interfacing with devices being susceptible to any clock variations the Rx device provides the capability
to compensate for that.
PX_CLK_OUT holds the pixel clock signal as it has been created from the embedded clock in the data stream. Those
signals are typically afflicted with jitter, which may cause invalid data on interfacing devices dependent on its PLL
performance. By feeding back the PX_CLK_OUT via an external PLL into the PX_CLK_IN, the PX_CLK signal can be de-
jittered. As soon the PX_CLK_IN receives a valid frequency of 20MHz or higher the pixel data outputs are enabled and the
PX_CLK provides the valid and jitter-free pixel clock accordingly.
PLL
PX_CLK_OUT
PX_CLK_IN
INDR
PX_CLK
Receiver
PX_D0…47
Figure 2.1: Pixel Clock conditioning
When PX_CLK_IN is tied to logic HIGH the pixel data outputs PX_D0…D47 are tri-stated.
When PX_CLK_IN is tied to logic LOW the Rx166/Rx331 operates as Rx165/Rx330, with the restriction that the PX_CLK-
(signal provided by Rx165/Rx330) is not available. In this case the PX_CLK holds the pixel clock signal as it has been
created from the embedded clock in the data stream. Though the 166/331series can be used in applications designed for
165/330-series, other combinations than pairs (Tx and Rx) of the same series are not compatible.
Note: The external PLL shall have an integrating characteristic to prepare the PX_CLK signal for proper and stable
interfacing with devices (DVI/LVDS) whose internal PLL performance may cause data loss especially at higher frequencies
and resolutions.
Date: 2005-03-14 Revision: 0.1
Page 12 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
2.2 Configuration Vectors and Configuration Data
Four configuration vectors (cfg0 – cfg3, 4-bit each) must be loaded into the device through the low-speed sideband data
interfaces SB0 and SB2. The Tx and the Rx device must be connected via the downlink.
SB0 and SB2 sideband data are multiplexed and are also used for device configuration. After de-assertion of RESET#,
CFG_CYC is automatically being driven high and enables the configuration process.
The configuration select signals (CFG_SEL[3:0]) are provided sequentially at SB0 (INDT) respectively at SB2 (INDR).
These select signals enable e.g. an external logic which provides the configuration vectors (cfg0 – cfg3) via the
configuration signals CFG_D[3:0]. These are read at SB2 (INDT) respectively at SB0 (INDR).
Vector
name
cfg0
cfg1
cfg2
cfg3
Configuration Select Signals
CFG_SEL[3:0]
Sequence
Configuration vector
1
2
3
4
0001
0010
0100
1000
Requests configuration vector 0
Requests configuration vector 1
Requests configuration vector 2
Requests configuration vector 3
Table 2.1: Configuration Vector Sequence
Transmitter
Receiver
CFG_SEL[3:0]
Configuration mode
(CFG_CYC = 1)
CFG_SEL[3:0]
SB0_D[3:0]
CFG_D[3:0]
SB2_D[3:0]
CFG_D[3:0]
SB0_D[3:0]
Normal mode
SB2_D[3:0]
(CFG_CYC = 0)
Table 2.2: Pin Naming Multiplex Matrix
CFGEN
SYNC1/0
SB0_D[3…0]
SB1_D[1…0]
CFGDATA
LOW
LOW
>1ms
SDB
>1ms
For proper initialization of the upstream channel, the side band data input at the Rx needs to be kept low for >1ms after the
SYNC1/0 went high.
Figure 2.2 shows how to perform the configuration with external logic.
Date: 2005-03-14 Revision: 0.1
Page 13 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
CFG_CYC
CFG_CYC
0
1
0
1
2
SB0
2
3
CFG_SEL[3:0]
(SB2_D[3:0])
CFG_SEL[3:0]
(SB0_D[3:0])
SB2
EN1
BUF
EN2
EN2
EN2
EN2
EN1
BUF
EN2
EN2
EN2
cfg0
cfg1
cfg2
cfg3
cfg0
cfg1
4
4
4
4
4
4
4
4
4
4
4
4
4
EN1
BUF
EN1
BUF
INDT
INDR
EN1
EN1
BUF
BUF
cfg2
4
EN1
BUF
0
1
2
0
1
2
3
CFG_D[3:0]
(SB0_D[3:0])
CFG_D[3:0]
(SB2_D[3:0])
SB0
SB2
3
Figure 2.2: Configuration Logic
Each configuration vector’s default setting is “1111”. This popular operating mode (see light gray lines on following tables)
can easily be established with pull-up resistors from the configuration inputs to VCC instead of tri-state buffers. All
configuration vectors are valid for transmitter and receiver, unless otherwise noted.
2.3 Configuration Process and Timing
Figure 2.3 shows the configuration process.
RESET#
CFG_CYC
CFG_SEL[3:0]
CFG_D[3:0]
0x0
0x1
0x0
0x2
0x0
0x4
0x0
0x8
0x0
cfg0
cfg1
cfg2
cfg3
Internal clock
registers
config data
Figure 2.3: Timing of Configuration Process
Date: 2005-03-14 Revision: 0.1
Page 14 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
2.4 Interface Configuration Scheme
Note: The low-speed downstream sideband is automatically enabled, when high-speed downstream sideband OR audio is
enabled. INDT and INDR must be configured within the same group.
Vector
Name
Vector
Interface
Pixel Interface
Description
Group
Bits
1111
0100
0101
24-bit
24-bit
24-bit
24 bits of pixel(n) sampled at rising edge of PX_CLK+
24 bits of pixel(n) sampled at falling edge of PX_CLK+
24 bits of pixel(n) sampled at both edges of PX_CLK+
V1
24 bits of pixel(n) and
1001
48-bit
24 bits of pixel(n+1) sampled at rising edge of PX_CLK+
24 bits of pixel(n) and
1010
48-bit
24 bits of pixel(n+1) sampled at falling edge of PX_CLK+
Pixel
cfg0
Interface
0000
0001
0010
18-bit
18-bit
18-bit
18 bits of pixel(n) sampled at rising edge of PX_CLK+
18 bits of pixel(n) sampled at falling edge of PX_CLK+
18 bits of pixel(n) sampled at both edges of PX_CLK+
18 bits of pixel(n) and
V2
S1
0110
36-bit
18 bits of pixel(n+1) sampled at rising edge of PX_CLK+
18 bits of pixel(n) and
0111
36-bit
18 bits of pixel(n+1) sampled at falling edge of PX_CLK+
Disable high-speed downstream sideband data channel
0000
4
SB3 and SB4
Enable high-speed downstream sideband data channel
11XX
1100
1111
1110
4
SB3 and SB4
Sideband
Interface
Clocking: Asynchronous mode at downstream sideband
cfg1
cfg2
data channels SB3 and SB44
S2
A
Tx
Clocking: Synchronous mode at downstream sideband
data channels SB3 and SB44
Clocking: Sampling mode at downstream sideband data
Tx only
channels SB3 and SB44
X100
X111
01XX
11XX
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Disable upstream sideband data
Enable upstream sideband data
Disable Audio
Audio +
High Speed
Upstream
SB1
Enable Audio
Inom = x1.0, Ipre = x1.3, algorithm 1
Inom = x1.0, Ipre = x1.3, algorithm 2
Inom = x1.0, Ipre = x1.6, algorithm 1
Inom = x1.0, Ipre = x1.6, algorithm 2
Inom = x1.0, Ipre = x1.9, algorithm 1
Inom = x1.0, Ipre = x1.9, algorithm 2
Inom = x1.3, Ipre = x1.6, algorithm 1
Inom = x1.3, Ipre = x1.6, algorithm 2
Inom = x1.3, Ipre = x1.9, algorithm 1
Inom = x1.3, Ipre = x1.9, algorithm 2
Inom = x1.6, Ipre = x1.9, algorithm 1
Inom = x1.6, Ipre = x1.9, algorithm 2
Inom = Ipre = x1.9
Pre-
Emphasis
For
Serial
cfg3
Rx only
Upstream
Trans-
mission
Inom = Ipre = x1.3
Inom = Ipre = x1.0
Inom = Ipre = x1.6
Note: others than the above mentioned vector bit combinations are not allowed
Table 2.3: Configuration of the Pixel Interface Mode
2.5 Error Handling and Reset
The chips provide an error detection signal (ERROR pin) indicating incorrect video timings. It is recommended to reset the
chip after the ERROR pin went high.
4 Sideband Data Channel 4 (SB4) only available with INDT/R330B
Date: 2005-03-14 Revision: 0.1
Page 15 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
3 Electrical Specification
3.1 External Circuits
3.1.1 External Loop Filter Specification
The internal PLLs of the INDT166B/331B and the INDR166B/331B devices require an external RC loop filter (Figure 3.1).
R1
C
R2
CAPx
CAPy
Figure 3.1: External Loop Filter Circuit
It is recommended to implement the 0-Ohm resistors R1 and R2 for the transmitter as real components, because their
values may change in future versions. Table 3.1 shows the optimal values for the INDT/R166B, Table 3.2 for the
INDT/R331B. It is recommended to use SMD ceramic chip capacitors and chip resistors.
Value Tx
Value Rx
Link
Signals
Pins
Parameter
Symbol
(INDT166B)
(INDR166B)
Loop Filter Capacitor
Loop Filter Resistor 1
Loop Filter Resistor 2
C
R1
R2
1µF
0 Ω
0 Ω
1µF
47 Ω
47 Ω
CAP1
CAP2
C11
C12
PLL0
Table 3.1: External Loop Filter Specification for INDT/R166B
Value Tx
Value Rx
Link
Signals
Pins
Parameter
Symbol
(INDT331B)
1µF
(INDR331B)
Loop Filter Capacitor
Loop Filter Resistor 1
Loop Filter Resistor 2
Loop Filter Capacitor
Loop Filter Resistor 1
Loop Filter Resistor 2
C
R1
R2
C
R1
R2
1µF
47 Ω
47 Ω
1µF
47 Ω
47 Ω
CAP1
CAP2
A15
B15
PLL0
0 Ω
0 Ω
1µF
CAP3
CAP4
A8
B8
PLL1
0 Ω
0 Ω
Table 3.2: External Loop Filter Specification for INDT/R331B
3.1.2 Serial Transmission Cable Interconnect
The serial lines have to be AC-coupled through 100 nF capacitors; RF ceramic capacitors shall be used. Values for R and
L are dependent on the type of cable.
Decoupling capacitor
Cable termination
TX0+
RX0+
R
L
TX0–
TX1+
RX0–
RX1+
Downstream
R
L
INDT
INDR
TX1–
RX1–
Only INDT/R 330
RX2+
RX2–
TX2+
TX2–
R
L
Upstream
Figure 3.2: Decoupling and Cable Termination
Date: 2005-03-14 Revision: 0.1
Page 16 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
3.1.3 Serial Transmission Cable Termination
Besides the AC coupling capacitors, a dedicated cable termination has to be provided on the receiver input (Figure 3.2).
The termination values have to be matched for the type of cable and length.
3.1.4 Receiver Equalizer
The equalizer inside the receiver device compensates the frequency-dependant cable attenuation. For cable lengths5
above 10m, it is recommended to activate the equalizer function (pin EQ = HIGH) to achieve optimum transmission
performance.
3.1.5 Reference Clock
The internal data clock frequency is 1320 MHz and is generated by internal PLLs. Both, transmitter and receiver require an
external clock oscillator or reference clock of 66.0 MHz with a stability of ± 100 ppm. To enable the INDT/R166 supporting
VESA Standard XGA24, the clock frequency must be 66.6667 MHz. However, the use of 66.6667 MHz clock frequency
disables the transmission of audio data of 44.1 kHz sampling frequency. Transmission of audio data of 48 kHz sampling
frequency is still possible as long as there is sufficient bandwidth left.
3.1.6 VREF Reference Circuitry
The VREF-pin at the transmitter device has two modes to set the threshold level at the input pixel interface. For standard
3.3 V LVTTL input level, it must be tied to VCC (3.3 V). For low swing voltage levels (VDD = 1.0 – 2.0 V), VREF must be tied
to half the supply voltage (VDD/2 = 0.5 – 1.0 V) of the driver (graphics controller). Figure 3.3 shows the input thresholds at
different VREF levels:
VREF MIN
VREF MAX
- 0.1
+ 0.1
- 0.1
+ 0.1
Low Voltage Swing
0.5 < VREF < 1.0 V
L
H
L
H
Voltage [V]
3.3
0
0.5
1
1.5
2
2.5
3.0
LVTTL
L
H
VREF = 3.3 V
0.8
2.0
Figure 3.3: VREF Reference Circuitry
3.2 Power Supply
Each GigaSTaR Digital Display Link chip consists of a separate Bipolar and CMOS die. Therefore, the device provides
multiple power planes to minimize EMI. It is suggested to use an own 3.3 V regulator6 for the whole chip to implement
optimal decoupling of the power supply lines. Table 3.3 shows the current consumption of the devices.
Typical7 Current
Device
Die
Consumption [mA]
CMOS
Bipolar
CMOS
Bipolar
400
230
400
540
INDT/R166B
INDT/R331B
Table 3.3: Current Consumption
5 Refers to the GORE reference cable GGSC1608-X, other cable types may differ.
6 Do not use two separate regulators to avoid chip damage due to latch-up.
7 Depending on video operating modes and external circuitry
Date: 2005-03-14 Revision: 0.1
Page 17 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
Table 3.4 shows, which planes can be tied together.
Pin Name
Type
Description
VCC Plane No.
1A
GND Plane No.
1B
VCC_CORE
POWER
CMOS core supply
GND_CORE GROUND
VCC_IO
GND_IO
VCC_CML
GND_CML
VCC_SX
GND_SX
VCC_IA
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
CMOS digital I/O
supply
1A
2A
1B
2B
CMOS chip-to-chip
interface supply
CMOS uplink I/O
supply
4A (1A)8
4B (1B)
2B
Bipolar Chip-to-chip
interface supply
2A
GND_IA
VCC_A0
GND_A0
VCC_A1
GND_A1
Bipolar downlink I/O
supply
3A
3B
Bipolar PLL supply
3A
3B
Table 3.4: Power Supply Planes
3.3 Absolute Maximum Ratings
The absolute maximum ratings define values beyond which damage may occur to the device. Inova Semiconductors may
not be held liable for any product degradation or damage caused by a violation of the absolute maximum ratings. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability. Functional operation of the device
at these or any other conditions above those indicated in the recommended operating conditions is not guaranteed.
Parameter
Symbol
VCC
Min.
-0.5
-0.5
-20
Max.
Units
V
Note
DC Supply Voltage
+4.2
See keynote (6)
Input Voltage
VIN
VCC+0.5
+20
V
I/O Current (DC or transient any pin)
Junction Temperature (under bias)
Storage Temperature
Soldering Temp./Time
Static Discharge Voltage
ID
mA
° C
° C
° C / sec
V
See keynote (6)
Tj
-45
+140
Tstg
-55
+150
TSLD / tSLD
VESD1
220 / 10
± 2000
Human Body Model
Table 3.5: Absolute Maximum Ratings
3.4 Recommended Operating Conditions
Parameter
Symbol
VCC
Min.
Max.
+3.45
Vcc
Units
V
Note
DC Supply Voltage
Input Voltage
+3.15
Vcc typ. = 3.3 V
VIN
0
V
VCC =3.3V ± 0.15V
CML Output Current
CMOS Output Current
Junction Temperature (under bias)
Ambient Temperature
IOUTCML
IOUTCMOS
Tj
-10
-10
0
+10
mA
mA
° C
° C
+10
+125
+85
Ta
-40
Table 3.6: Recommended Operating Conditions
8 Plane #4 may be connected to plane #1, if this plane is adequately noise-free.
Date: 2005-03-14 Revision: 0.1
Page 18 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
3.5 AC–Characteristics (under recommended operating conditions, Reference Clock Freq. = 66 MHz)
Parameter
Min.
Typ.
1.5
1.32
757.6
5
Max.
3
Units
pF
Input capacitance, any pin (@ 66 MHz)
Serial Transmission Data Rate (Downstream, per Link)
Serial Bit Width (Downstream)
Gbit/s
ps
CMOS Output Rise / Fall Time (CL = 10 pF)
10
ns
Table 3.7: AC–Characteristics
3.6 DC–Characteristics (under recommended operating conditions)
Parameter
Symbol
VIH
VIL
Test Condition
Min.
2.6
Typ.
Max.
Unit
V
V
CMOS Input High Voltage
CMOS Input Low Voltage
CMOS Input High Current
CMOS Input Low Current
EQLSEL/OSC Pin High Current
EQLSEL/OSC Pin Low Current
CMOS Output High Voltage
CMOS Output Low Voltage
CMOS Output High Current
CMOS Output Low Current
LOCK Output High Current
LOCK Output Low Current
INDT166B Supply Current
0.7
1
IIH
VIN = Vcc
-1
-1
µA
µA
µA
µA
V
IIL
VIN = 0 V
1
IIH
IIL
VIN = Vcc
-10
40
10
VIN = 0 V
-10
VOH
VOL
IOH
IOH = -0.5 mA
0,95Vcc
IOL = 1.5 mA
0,05 Vcc
V
VOH = 0.9Vcc
-3
3.5
-1
1.5
-
-5
6
mA
mA
mA
mA
mA
IOL
VOL = 0.1Vcc
ILH
VOH = 0.9Vcc
-2.5
3
ILL
VOL = 0.1Vcc
ICCTX166
CMOS output load = 10 pF
@ Vcc typ. = 3.3 V
CMOS output load = 10 pF
@ Vcc typ. = 3.3 V
CMOS output load = 10 pF
@ Vcc typ. = 3.3 V
CMOS output load = 10 pF
@ Vcc typ. = 3.3 V
635
675
665
985
975
INDR166B Supply Current
INDT331B Supply Current
INDR331B Supply Current
ICCRX166
ICCTX331
ICCRX331
-
-
-
620
955
935
mA
mA
mA
Table 3.8: DC–Characteristics
Note: Floating CMOS inputs can result in excessive supply current. Therefore unused inputs should be tied to Vcc or Gnd.
3.7 Reference Clock Specification (Ta = -40 to 85° C; Vcc = 3.15 to 3.45 V)
Parameter
Symbol
fOSC
Min.
Typ.
66.0
Max.
Unit
Note
66,6667 MHz
possible, see 3.1.5
Nominal Frequency (INDT/R166)
MHz
Nominal Frequency (INDT/R331)
Frequency Tolerance
Duty Cycle
fOSC
FTOL
66.0
MHz
ppm
%
-100
40
+100
60
Table 3.9: Reference Clock Specification
Date: 2005-03-14 Revision: 0.1
Page 19 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
3.8 Timing Specification
(a) Transmitter pixel interface
t1
PCLK+
PX_D[47:0],
PX_DE,
PX_HSYNC,
PX_VSYNC
t2
Figure 3.4: Pixel Interface Timing Diagram At Rising Edge At Tx
Parameter
t1
t2
Description
Min.
0.5
1.0
Typ.
0.9
1.3
Max.
-
-
Unit
ns
ns
Pixel data and ctrl signal setup time to pixel clock at Tx
Pixel data and ctrl signal hold time to pixel clock at Tx
Table 3.10: Pixel Interface Timing Table At Rising Edge At Tx
t3
PCLK+
PX_D[47:0],
PX_DE,
PX_HSYNC,
PX_VSYNC
t4
Figure 3.5: Pixel Interface Timing Diagram At One Pixel Per Clock At Falling Edge At Tx
Parameter
t3
t4
Description
Min.
0.5
0.5
Typ.
0.9
1.3
Max.
-
-
Unit
ns
ns
Pixel data and ctrl signal setup time to pixel clock at Tx
Pixel data and ctrl signal hold time to pixel clock at Tx
Table 3.11: Pixel Interface Timing Table At One Pixel Per Clock At Falling Edge At Tx
Date: 2005-03-14 Revision: 0.1
Page 20 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
(b) Receiver pixel interface
t5/6
PX_CLK
PX_D[47:0],
PX_DE,
PX_HSYNC,
PX_VSYNC
t7
Figure 3.6: Pixel Interface Timing Diagram At Rising Edge At Rx
Parameter
Description
Min.
1.8
1.6
0.5
Typ.
4.0
Max.
4.4
Unit
t5
t6
t7
Pixel data and ctrl signal setup time to pixel clock at Rx (SXGA)
Pixel data and ctrl signal setup time to pixel clock at Rx (UXGA)
Pixel data and ctrl signal hold time to pixel clock at Rx
ns
3.0
4.2
ns
ns
1.2
1.4
Table 3.12: Pixel Interface Timing Table At Rising Edge At Rx
t8/9
PX_CLK
PX_D[47:0],
PX_DE,
PX_HSYNC,
PX_VSYNC
t10
Figure 3.7: Pixel Interface Timing Diagram At Falling Edge At Rx
Parameter
Description
Min.
2.2
1.0
0.5
Typ.
3.8
Max.
4.7
Unit
t8
Pixel data and ctrl signal setup time to pixel clock at Rx (SXGA)
Pixel data and ctrl signal setup time to pixel clock at Rx (UXGA)
Pixel data and ctrl signal hold time to pixel clock at Rx
ns
ns
ns
t9
t10
2.9
3.7
1.2
1.3
Table 3.13: Pixel Interface Timing Table At Falling Edge At Rx
Date: 2005-03-14 Revision: 0.1
Page 21 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
(c) Transmitter sideband interface
t11
t13
SB2_CLK
SB2_D[3:0]
t12
t14
Figure 3.8: Tx Sideband Data Interface; Low Speed Downstream
Parameter
Description
Min.
40
Typ.
200
100
30
Max.
-
Unit
ns
t11
t12
t13
t14
Low speed downstream sideband data setup time to clock output at Tx
Low speed downstream sideband data hold time to clock output at Tx
Low speed downstream sideband data clock high time at Tx
Low speed downstream sideband data clock low time at Tx
0
-
ns
29,3
900
31,7
916
ns
ns
909
Table 3.14: Tx Sideband Data Interface; Low Speed Downstream
t15 t16
t19
t20
SB3_CLKO
SB3_D[1:0]
SB3_CLKI
t17
t18
Figure 3.9: Tx Sideband Data Interface; High Speed Downstream
Parameter
t15
Description
Min.
6
Typ.
Max. Unit
High speed downstream sideband data setup time to clock output (synchronous
8.6
2.0
6.0
1.0
-
-
-
-
ns
ns
ns
ns
mode) at Tx
t16
t17
t18
High speed downstream sideband data hold time to clock output (synchronous
mode) at Tx
0
2
2
High speed downstream sideband data setup time to clock input (asynchronous
mode) at Tx
High speed downstream sideband data hold time to clock input (asynchronous
mode) at Tx
t19
t20
High speed downstream sideband data clock output high time at Tx
High speed downstream sideband data clock output low time
6,1
8,6
6.3
9.5
6,5
10,1
ns
ns
Table 3.15: Tx Sideband Data Interface; High Speed Downstream
Date: 2005-03-14 Revision: 0.1
Page 22 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
t21
t24
SB0_CLK
SB0_D[3:0]
t22
t23
Figure 3.10: Tx Sideband Data Interface; Low Speed Upstream
Parameter
Description
Min.
420
520
532
430
Typ.
430
530
534
435
Max.
440
540
536
442
Unit
ns
t21
t22
t23
t24
Low speed upstream sideband data setup time to clock output at Tx
Low speed upstream sideband data hold time to clock output at Tx
Low speed upstream sideband data clock high time at Tx
Low speed upstream sideband data clock low time at Tx
ns
ns
ns
Table 3.16: Tx Sideband Data Interface; Low Speed Upstream
t25
t28
SB1_CLK
SB1_D[1:0]
t26
t27
Figure 3.11: Tx Sideband Data Interface; High Speed Upstream
Parameter
Description
Min.
9,4
4,4
9,6
3,8
Typ.
10,2
5.5
10.5
9.7
Max.
11,5
6,0
11,5
10,2
Unit
ns
t25
t26
t27
t28
High speed upstream sideband data setup time to clock output at Tx
High speed upstream sideband data hold time to clock output at Tx
High speed upstream sideband data clock high time at Tx
High speed upstream sideband data clock low time at Tx
ns
ns
ns
Table 3.17: Tx Sideband Data Interface; High Speed Upstream
Date: 2005-03-14 Revision: 0.1
Page 23 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
(d) Receiver sideband interface
t29
t31
SB2_CLK
SB2_D[3:0]
t30
t32
Figure 3.12: Rx Sideband Data Interface; Low Speed Downstream
Parameter
Description
Min.
478
450
450
480
Typ.
484
455
454
484
Max.
490
460
458
490
Unit
ns
t29
t30
t31
t32
Low speed downstream sideband data setup time to clock output at Rx
Low speed downstream sideband data hold time to clock output at Rx
Low speed downstream sideband data clock high time at Rx
Low speed downstream sideband data clock low time at Rx
ns
ns
ns
Table 3.18: Rx Sideband Data Interface; Low Speed Downstream
t33
t35
SB3_CLK
SB3_D[1:0]
t34
t36
Figure 3.13: Rx Sideband Data Interface; High Speed Downstream
Parameter
Description
Min.
5,5
7,2
9,8
5,5
Typ.
6.0
Max.
6,4
Unit
ns
t33
t34
t35
t36
High speed downstream sideband data setup time to clock output at Rx
High speed downstream sideband data hold time to clock output at Rx
High speed downstream sideband data clock high time at Rx
High speed downstream sideband data clock low time at Rx
7,5
8,4
ns
10.6
6.4
11,1
6,8
ns
ns
Table 3.19: Rx Sideband Data Interface; High Speed Downstream
Date: 2005-03-14 Revision: 0.1
Page 24 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
t37
t39
SB0_CLK
SB0_D[3:0]
t38
t40
Figure 3.14: Rx Sideband Data Interface; Low Speed Upstream
Parameter
Description
Min.
20
Typ.
100
10
48,8
922
Max.
-
Unit
ns
t37
t38
t39
t40
Low speed upstream sideband data setup time to clock output at Rx
Low speed upstream sideband data hold time to clock output at Rx
Low speed upstream sideband data clock high time at Rx
Low speed upstream sideband data clock low time at Rx
0
-
ns
47,9
912
49,7
932
ns
ns
Table 3.20: Rx Sideband Data Interface; Low Speed Upstream
t41 t42
t45
t46
SB1_CLKO
SB1_D[1:0]
SB1_CLKI
t43
t44
Figure 3.15: Rx Sideband Data Interface; High Speed Upstream
Parameter
t41
Description
Min.
4,0
Typ.
6,0
Max.
-
Unit
High speed upstream sideband data setup time to clock output
ns
(synchronous mode) at Rx
t42
t43
t44
High speed upstream sideband data hold time to clock output
(synchronous mode) at Rx
0
0
1,0
2,5
2,5
-
ns
ns
ns
High speed upstream sideband data setup time to clock output
(asynchronous mode) at Rx
High speed upstream sideband data hold time to clock output
(asynchronous mode) at Rx
1,0
t45
t46
High speed upstream sideband data clock high time at Rx
High speed upstream sideband data clock low time at Rx
7,2
9,7
10,1
10,1
11,3
10,6
ns
ns
Table 3.21: Rx Sideband Data Interface; High Speed Upstream
Date: 2005-03-14 Revision: 0.1
Page 25 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
t49
RESET#
CFG_CYC
CFG_SEL[3:0]
CFG_D[3:0]
0000
0001
cfg0
0000
0010
cfg1
0000
0100
cfg2
0000
1000
cfg3
0000
t47
configuration data
sideband data
t48
Figure 3.16: Configuration Interface Timing
Parameter
Description
Min.
Typ.
350
100
0
Max.
Unit
ns
t47
t48
t49
Configuration Select High Phase
-
-
-
-
-
-
Configuration Select High to Configuration Data valid
Configuration data valid after Configuration Select high to low
transition
ns
ns
Table 3.22: Configuration Interface Timing
Date: 2005-03-14 Revision: 0.1
Page 26 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
4 Signals
4.1 INDT166B Transmitter Signal Description
Pin Name
Link Interface
TX0+
Pin
Dir
Type
Description
B8
B9
A5
A4
B6
B2
OUT
OUT
IN
CML
CML
Serial Data Output (Downlink)
Serial Data Input (Uplink)
TX0–
RX2+
CML
RX2–
IN
CML
LOCK0
OUT
OUT
LVTTL
LVTTL
Lock Indicator. HIGH when PLL of Downlink is properly locked
HIGH when the Uplink is frame synchronous
SYNC2
Pixel Interface
PX_CLK+
PX_CLK–
K14
J14
IN
IN
LVTTL*
LVTTL*
Pixel clock 24 – 161 MHz, diff + or single-ended
Pixel clock 24 – 161 MHz, diff – pull to GND in single ended mode
(see Table
4.3)
PX_D[47:0]
IN
LVTTL*
Configurable parallel pixel data interface
PX_HSYNC
PX_VSYNC
PX_DE
J13
IN
IN
IN
IN
LVTTL*
LVTTL*
LVTTL*
A
Pixel data framing – Horizontal sync pulse (active HIGH)
Pixel data framing – Vertical sync pulse (active HIGH)
Pixel data framing – Data enable (active HIGH)
Configures the input level of the pixel interface
H13
H14
VREF
G13
Sideband Interface
Sideband Data Channel 0 Upstream Synchronous Clock Output. Data is
provided aligned to rising edge.
SB0_CLK
A13
OUT
OUT
OUT
LVTTL
LVTTL
SB0_D[3:0]
A11,B11,A
12,B12
If CFG_CYC=0: Sideband Data Channel 0 Upstream Output
If CFG_CYC=1: Configuration vector output
(CFG_SEL[3:0])
Sideband Data Channel 1 Upstream Synchronous Clock Output. Data is
provided aligned to rising edge.
SB1_CLK
SB1_D[1:0]
SB2_CLK
E14
LVTTL
LVTTL
LVTTL
D14,D13 OUT
Sideband Data Channel 1 Upstream Output
Sideband Data Channel 2 Downstream Synchronous Clock Output. Data is
registered at rising edge.
C13
OUT
SB2_D[3:0]
A14,B14,B
13,C14
If CFG_CYC=0: Sideband Data Channel 2 Downstream Input
If CFG_CYC=1: Configuration data input
IN
LVTTL
LVTTL
(CFG_D[3:0])
Sideband Data Channel 3 Downstream Asynchronous Clock Input. Data is
registered at rising edge.
SB3_CLKI
G14
IN
Sideband Data Channel 3 Downstream Synchronous Clock Output. Data is
registered at rising edge.
SB3_CLKO
F13
OUT
IN
LVTTL
LVTTL
SB3_D[1:0]
Audio Interface
AI_C0
E13,F14
Sideband Data Channel 3 Downstream Input
C2
C1
D2
D1
IN
IN
IN
IN
LVTTL
LVTTL
LVTTL
LVTTL
S/P-DIF Audio Channel 0
S/P-DIF Audio Channel 1
S/P-DIF Audio Channel 2
S/P-DIF Audio Channel 3
AI_C1
AI_C2
AI_C3
Other Signals
RESET#
ERROR
CFG_CYC
OSC
B3
A2
IN
OUT
OUT
IN
LVTTL
LVTTL
LVTTL
LVTTL
A
Asynchronous Hardware Reset (active LOW)
Pixel Buffer Overrun
A1
Indicates that the configuration process is active
Reference Oscillator Input (see chapter 3.7)
Loop filter pin of Downlink
A6
CAP1
C11
C12
B1
IN
CAP2
NC
IN
–
A
Loop filter pin of Downlink
Not connected
–
Table 4.1: INDT166B Transmitter Signals
* Configurable to LVTTL or Low Voltage Swing via VREF-pin
Date: 2005-03-14 Revision: 0.1
Page 27 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
Pin Name
Pin
Dir
Type
Description
Power Supply
C3,D3,E4,G7,G8,G10,H3,H8,J3,J4,J8,J11,L5,L6,L10,M3,M8,M11,
VCC_CORE
GND_CORE
VCC_IO
IN
IN
IN
IN
POWER
GROUND
POWER
M12
CMOS core supply
D5,E5,E11,F4,F6,F11,G4,G6,H5,H6,H10,H12,J10,K3,K7,K8,K11,
L3,L11,M9
C4,D4,E2,E3,G9,G11,H4,H7,H11,J7,J12,K5,K6,K9,K10,L9,L12,M4,
M7
CMOS digital I/O
supply
A3,C5,E12,F3,F5,F12,G3,G5,G12,H9,J5,J6,J9,K4,K12,L4,L7,L8,M5,
GND_IO
GROUND
M6,M10
VCC_CML
GND_CML
VCC_SX
GND_SX
VCC_IA
F7,F8
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
CMOS chip-to-chip
interface supply
F9,F10
B4
CMOS uplink I/O
supply
B5
E8,E10
Bipolar Chip-to-chip
interface supply
GND_IA
E7,E9
VCC_A0
GND_A0
VCC_A1
GND_A1
A7,A10,C6,C7,C10,D6,D12
A8,A9,B7,B10,C8,C9,D11,E6
D9,D10
Bipolar downlink I/O
supply
Bipolar PLL supply
D7,D8
Table 4.2: INDT166B Transmitter Power Supply
Pin Name
Pin
K13
L14
L13
M14
M13
N14
N13
P14
P13
P12
N12
P11
Pin Name
PX_D35
PX_D34
PX_D33
PX_D32
PX_D31
PX_D30
PX_D29
PX_D28
PX_D27
PX_D26
PX_D25
PX_D24
Pin
N11
P10
N10
P9
Pin Name
PX_D23
PX_D22
PX_D21
PX_D20
PX_D19
PX_D18
PX_D17
PX_D16
PX_D15
PX_D14
PX_D13
PX_D12
Pin
N5
P4
N4
P3
N3
P2
P1
N1
N2
M1
M2
L1
Pin Name
PX_D11
PX_D10
PX_D9
PX_D8
PX_D7
PX_D6
PX_D5
PX_D4
PX_D3
PX_D2
PX_D1
PX_D0
Pin
L2
PX_D47
PX_D46
PX_D45
PX_D44
PX_D43
PX_D42
PX_D41
PX_D40
PX_D39
PX_D38
PX_D37
PX_D36
K1
K2
J1
N9
J2
P8
H1
H2
G1
G2
F1
F2
E1
N8
P7
N7
P6
N6
P5
Table 4.3: INDT166B Transmitter Pixel Data Pin Numbers
4.2 INDR166B Receiver Signal Description
Pin Name
Link Interface
RX0+
Pin
Dir
Type
Description
B8
B9
A5
A4
B6
B2
C5
IN
IN
OUT
OUT
OUT
OUT
IN
CML
CML
Serial Data Input (Downlink 0)
Serial Data Output (Uplink)
RX0–
TX2+
CML
TX2–
CML
LOCK0
LVTTL
LVTTL
LVTTL
Lock Indicator. HIGH when PLL of Downlink is properly locked
High, when the Downlink is frame synchronous
Selects the Downlink equalizer (LOW=OFF; HIGH=ON)
SYNC0
EQ
Pixel Interface
PX_CLK
PX_CLK_IN
PX_CLK_OUT
J14
A3
OUT
IN
LVTTL
LVTTL
LVTTL
Pixel clock 24 – 161 MHz,
Pixel clock 24 – 161 MHz, de-jitter feedback
Pixel clock 24 – 161 MHz, de-jitter feedback
H14
OUT
(see Table
4.6)
PX_D[47:0]
OUT
LVTTL
Configurable parallel pixel data interface
PX_HSYNC
PX_VSYNC
PX_DE
G13
OUT
OUT
OUT
LVTTL
LVTTL
LVTTL
Pixel data framing – Horizontal sync pulse (active HIGH)
Pixel data framing – Vertical sync pulse (active HIGH)
Pixel data framing – Data enable (active HIGH)
H13
J13
Sideband Interface
Sideband Data Channel 0 Upstream Synchronous Clock Output. Data is
registered at rising edge.
If CFG_CYC=0: Sideband Data Channel 0 Upstream Input
If CFG_CYC=1: Configuration data input
SB0_CLK
A13
OUT
IN
LVTTL
LVTTL
SB0_D[3:0]
A11,B11,A
12,B12
(CFG_D[3:0])
Date: 2005-03-14 Revision: 0.1
Page 28 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
Pin Name
Pin
Dir
Type
Description
Sideband Data Channel 1 Upstream Asynchronous Clock Input. Data is
registered at rising edge.
SB1_CLKI
E13
IN
LVTTL
Sideband Data Channel 1 Upstream Synchronous Clock Output. Data is
registered at rising edge.
SB1_CLKO
SB1_D[1:0]
SB2_CLK
E14
D14,D13
C13
OUT
IN
LVTTL
LVTTL
LVTTL
Sideband Data Channel 1 Upstream Input
Sideband Data Channel 2 Downstream Synchronous Clock Output. Data is
provided aligned to rising edge.
OUT
SB2_D[3:0]
A14,B14,B
13,C14
If CFG_CYC=0: Sideband Data Channel 2 Downstream Output
If CFG_CYC=1: Configuration vector output
OUT
LVTTL
(CFG_SEL[3:0])
Sideband Data Channel 3 Downstream Synchronous Clock Output. Data is
provided aligned to rising edge.
SB3_CLK
G14
OUT
OUT
LVTTL
LVTTL
SB3_D[1:0]
Audio Interface
AI_C0
F14,F13
Sideband Data Channel 3 Downstream Output
C2
C1
D2
D1
OUT
OUT
OUT
OUT
LVTTL
LVTTL
LVTTL
LVTTL
S/P-DIF Audio Channel 0
S/P-DIF Audio Channel 1
S/P-DIF Audio Channel 2
S/P-DIF Audio Channel 3
AI_C1
AI_C2
AI_C3
Other Signals
RESET#
ERROR
CFG_CYC
OSC
B3
A2
IN
OUT
OUT
IN
LVTTL
LVTTL
LVTTL
LVTTL
A
Asynchronous Hardware Reset (active LOW)
Pixel Clock Recovery Error
A1
Indicates that the configuration process is active
Reference Oscillator Input (see chapter 3.7)
Loop filter pin of Downlink
A6
CAP1
C11
C12
B1
IN
CAP2
NC
IN
–
A
Loop filter pin of Downlink
Not connected
–
Table 4.4: INDR166B Receiver Signals
Pin
Pin Name
Dir
Type
Description
Power Supply
VCC_CORE C3,E3,G8,G10,J3,J4,J7,J11,L5,L6,L10,M8,M11
IN
IN
POWER
GROUND
CMOS core supply
GND_CORE E4,E11,F4,F11,F12,G4,G6,H6,H10,J10,K8,K11,L3,L8,M9
C4,D3,D4,E2,F2,G7,G9,G11,H3,H4,H7,H8,H11,J8,J12,K5,K6,K9,
VCC_IO
IN
POWER
K10,L9,L12,M3,M4,M7,M12
CMOS digital I/O
supply
D5,E5,E12,F3,F5,F6,G3,G5,G12,H5,H9,H12,J5,J6,J9,K3,K4,K7,
GND_IO
IN
GROUND
K12,L4,L7,L11,M5,M6,M10
VCC_CML
GND_CML
VCC_SX
GND_SX
VCC_IA
F7,F8
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
CMOS chip-to-chip
interface supply
F9,F10
B4
CMOS uplink I/O
supply
B5
E8,E10
Bipolar Chip-to-chip
interface supply
GND_IA
E7,E9
VCC_A0
GND_A0
VCC_A1
GND_A1
A7,A10,C6,C7,C10,D6,D12
A8,A9,B7,B10,C8,C9,D11,E6
D9,D10
Bipolar downlink I/O
supply
Bipolar PLL supply
D7,D8
Table 4.5: INDR166B Receiver Power Supply
Pin Name
Pin
K14
K13
L14
L13
M14
M13
N14
N13
P14
P13
P12
N12
Pin Name
PX_D35
PX_D34
PX_D33
PX_D32
PX_D31
PX_D30
PX_D29
PX_D28
PX_D27
PX_D26
PX_D25
PX_D24
Pin
P11
N11
P10
N10
P9
Pin Name
PX_D23
PX_D22
PX_D21
PX_D20
PX_D19
PX_D18
PX_D17
PX_D16
PX_D15
PX_D14
PX_D13
PX_D12
Pin
P5
N5
P4
N4
P3
N3
P2
P1
N1
N2
M1
M2
Pin Name
PX_D11
PX_D10
PX_D9
PX_D8
PX_D7
PX_D6
PX_D5
PX_D4
PX_D3
PX_D2
PX_D1
PX_D0
Pin
L1
PX_D47
PX_D46
PX_D45
PX_D44
PX_D43
PX_D42
PX_D41
PX_D40
PX_D39
PX_D38
PX_D37
PX_D36
L2
K1
K2
J1
N9
J2
P8
H1
H2
G1
G2
F1
E1
N8
P7
N7
P6
N6
Table 4.6: INDR166B Receiver Pixel Data Pin Numbers
Date: 2005-03-14 Revision: 0.1
Page 29 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
4.3 INDT331B Transmitter Signal Description
Pin Name
Link Interface
TX0+
Pin
Dir
Type
Description
B12
B13
B5
OUT
OUT
OUT
OUT
IN
CML
CML
Serial Data Output (Downlink 0)
Serial Data Output (Downlink 1)
Serial Data Input (Uplink)
TX0–
TX1+
CML
TX1–
B6
CML
RX2+
A10
A9
CML
RX2–
IN
CML
LOCK0
B10
B3
OUT
OUT
OUT
LVTTL
LVTTL
LVTTL
Lock Indicator 0. HIGH when PLL of Downlink 0 is properly locked
Lock Indicator 1. HIGH when PLL of Downlink 1 is properly locked
HIGH when the Uplink is frame synchronous
LOCK1
SYNC2
Pixel Interface
PX_CLK+
PX_CLK–
C2
T18
R18
IN
IN
LVTTL*
LVTTL*
Pixel clock 24 – 161 MHz, diff + or single-ended
Pixel clock 24 – 161 MHz, diff – pull to GND in single ended mode
(see Table
4.9)
PX_D[47:0]
IN
LVTTL*
Configurable parallel pixel data interface
PX_HSYNC
PX_VSYNC
PX_DE
R17
IN
IN
IN
IN
LVTTL*
LVTTL*
LVTTL*
A
Pixel data framing – Horizontal sync pulse (active HIGH)
Pixel data framing – Vertical sync pulse (active HIGH)
Pixel data framing – Data enable (active HIGH)
Configures the input level of the pixel interface
P18
P17
VREF
N18
Sideband Interface
Sideband Data Channel 0 Upstream Synchronous Clock Output. Data is
provided aligned to rising edge.
SB0_CLK
C18
OUT
OUT
LVTTL
LVTTL
SB0_D[3:0]
A16,A17,A
18,B18
If CFG_CYC=0: Sideband Data Channel 0 Upstream Output
If CFG_CYC=1: Configuration vector output
(CFG_SEL[3:0])
Sideband Data Channel 1 Upstream Synchronous Clock Output. Data is
provided aligned to rising edge.
SB1_CLK
SB1_ D[1:0]
SB2_CLK
G18
F18,F17
E17
OUT
OUT
OUT
LVTTL
LVTTL
LVTTL
Sideband Data Channel 1 Upstream Output
Sideband Data Channel 2 Downstream Synchronous Clock Output. Data is
registered at rising edge.
SB2_D[3:0]
C17,D18,
D17,E18
If CFG_CYC=0: Sideband Data Channel 2 Downstream Input
If CFG_CYC=1: Configuration data input
IN
IN
LVTTL
LVTTL
(CFG_D[3:0])
Sideband Data Channel 3 Downstream Asynchronous Clock Input. Data is
registered at rising edge.
SB3_CLKI
J18
Sideband Data Channel 3 Downstream Synchronous Clock Output. Data is
registered at rising edge.
SB3_CLKO
SB3_D[1:0]
SB4_CLKI
H17
G17,H18
N17
OUT
IN
LVTTL
LVTTL
LVTTL
Sideband Data Channel 3 Downstream Input
Sideband Data Channel 4 Downstream Asynchronous Clock Input. Data is
registered at rising edge.
IN
Sideband Data Channel 4 Downstream Synchronous Clock Output. Data is
registered at rising edge.
SB4_CLKO
M18
OUT
IN
LVTTL
LVTTL
SB4_D[1:0]
Audio Interface
AI_C0
K18,L18
Sideband Data Channel 1 Downstream Input
D2
D1
E1
F1
IN
IN
IN
IN
LVTTL
LVTTL
LVTTL
LVTTL
S/P-DIF Audio Channel 0
S/P-DIF Audio Channel 1
S/P-DIF Audio Channel 2
S/P-DIF Audio Channel 3
AI_C1
AI_C2
AI_C3
Other Signals
RESET#
ERROR
CFG_CYC
OSC
A2
B2
IN
OUT
OUT
IN
LVTTL
Asynchronous Hardware Reset. Active LOW
Pixel Buffer Overrun
LVTTL
B1
LVTTL
LVTTL
A
A
A
A
–
Indicates that the configuration process is active
Reference Oscillator Input (see chapter 3.7)
Loop filter pin Downlink 0
A3
CAP1
A15
B15
A8
IN
CAP2
IN
Loop filter pin Downlink 0
CAP3
IN
Loop filter pin Downlink 1
CAP4
B8
C1
IN
Loop filter pin Downlink 1
NC
–
Not connected
Table 4.7: INDT331B Transmitter Signals
* Configurable to LVTTL or Low Voltage Swing via VREF-pin
Date: 2005-03-14 Revision: 0.1
Page 30 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
Pin Name
Pin
Dir
Type
Description
Power Supply
G3,G4,G9,G12,H4,J4,J8,J12,J15,J16,J17,L6,L10,L14,N2,N3,N4,N8,
N12,R6,R10,R14,T6,T10,T14
VCC_CORE
IN
IN
POWER
CMOS core supply
F2,G7,G13,G14,H6,H10,H14,J2,J3,K2,K4,K8,K12,K15,K16,K17,L2,
M6,M10,M14,P4,P8,P12,P15,P16,T3,T4
G2,G5,G8,G10,G11,G15,G16,H2,H3,H7,H8,H11,H12,H15,H16,J7,
J11,K5,K6,K9,K10,K13,K14,L5,L9,L13,M2,M3,M4,M7,M8,M11,M12,
M15,M16,M17,N7,N11,N15,N16,P5,P6,P9,P10,P13,P14,R5,R9,
R13,T5,T9,T13
GND_CORE
GROUND
VCC_IO
GND_IO
IN
POWER
CMOS digital I/O
supply
A1,B16,B17,C16,D9,D16,E2,E3,E9,E15,E16,F3,F8,F9,F10,F15,F16,
G6,H5,H9,H13,J5,J6,J9,J10,J13,J14,K3,K7,K11,L3,L4,L7,L8,L11,
L12,L15,L16,L17,M5,M9,M13,N5,N6,N9,N10,N13,N14,P3,P7,P11,
R3,R4,R7,R8,R11,R12,R15,R16,T2,T7,T8,T11,T12,T15,T16,U2
F4,F5,F11,F12
IN
GROUND
VCC_CML
GND_CML
VCC_SX
GND_SX
VCC_IA
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
CMOS chip-to-chip
interface supply
F6,F7,F13,F14
B9
C9
CMOS uplink I/O
supply
E6,E8,E12,E14
Bipolar Chip-to-chip
interface supply
GND_IA
E5,E7,E11,E13
VCC_A0
GND_A0
VCC_A1
GND_A1
A4,A7,A11,A14,C3,C4,C8,C10,C11,C15,D3,D8,D10,D15
A5,A6,A12,A13,B4,B7,B11,B14,C5,C6,C7,C12,C13,C14,E4,E10
D6,D7,D13,D14
Bipolar downlink I/O
supply
Bipolar PLL supply
D4,D5,D11,D12
Table 4.8: INDT331B Transmitter Power Supply
Pin Name
Pin
T17
U18
U17
V18
V17
V16
U16
V15
U15
V14
U14
V13
Pin Name
PX_D35
PX_D34
PX_D33
PX_D32
PX_D31
PX_D30
PX_D29
PX_D28
PX_D27
PX_D26
PX_D25
PX_D24
Pin
U13
V12
U12
V11
U11
V10
U10
V9
Pin Name
PX_D23
PX_D22
PX_D21
PX_D20
PX_D19
PX_D18
PX_D17
PX_D16
PX_D15
PX_D14
PX_D13
PX_D12
Pin
U7
V6
U6
V5
U5
V4
U4
V3
U3
V2
V1
U1
Pin Name
PX_D11
PX_D10
PX_D9
PX_D8
PX_D7
PX_D6
PX_D5
PX_D4
PX_D3
PX_D2
PX_D1
PX_D0
Pin
T1
R1
R2
P1
P2
N1
M1
L1
PX_D47
PX_D46
PX_D45
PX_D44
PX_D43
PX_D42
PX_D41
PX_D40
PX_D39
PX_D38
PX_D37
PX_D36
U9
K1
J1
V8
U8
H1
G1
V7
Table 4.9: INDT331B Transmitter Pixel Data Pin Numbers
Date: 2005-03-14 Revision: 0.1
Page 31 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
4.4 INDR331B Receiver Signal Description
Pin Name
Link Interface
RX0+
Pin
Dir
Type
Description
B12
B13
B5
IN
IN
CML
CML
Serial Data Input (Downlink 0)
Serial Data Input (Downlink 1)
Serial Data Output (Uplink)
RX0–
RX1+
IN
CML
RX1–
B6
IN
CML
TX2+
A10
A9
OUT
OUT
OUT
OUT
OUT
OUT
IN
CML
TX2–
CML
LOCK0
B10
B3
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Lock Indicator 0. HIGH when PLL of Downlink 0 is properly locked
Lock Indicator 1. HIGH when PLL of Downlink 1 is properly locked
HIGH when the Downlink 0 is frame synchronous
HIGH when the Downlink 1 is frame synchronous
Selects the Downlink equalizer (LOW=OFF; HIGH=ON)
LOCK1
SYNC0
C1
SYNC1
D1
EQ
A2
Pixel Interface
PX_CLK
PX_CLK_IN
PX_CLK_OUT
R18
B2
OUT
IN
LVTTL
LVTTL
LVTTL
Pixel clock 24 – 161 MHz,
Pixel clock 24 – 161 MHz, de-jitter feedback
Pixel clock 24 – 161 MHz, de-jitter feedback
P18
OUT
(see Table
4.12)
N18
PX_D[47:0]
OUT
LVTTL
Configurable parallel pixel data interface
PX_HSYNC
PX_VSYNC
PX_DE
OUT
OUT
OUT
LVTTL
LVTTL
LVTTL
Pixel data framing – Horizontal sync pulse (active HIGH)
Pixel data framing – Vertical sync pulse (active HIGH)
Pixel data framing – Data enable (active HIGH)
N17
P17
Sideband Interface
Sideband Data Channel 0 Upstream Synchronous Clock Output. Data is
registered at rising edge.
SB0_CLK
C18
OUT
IN
LVTTL
LVTTL
LVTTL
SB0_D[3:0]
A16,A17,A
18,B18
If CFG_CYC=0: Sideband Data Channel 0 Upstream Input
If CFG_CYC=1: Configuration data input
(CFG_D[3:0])
Sideband Data Channel 1 Upstream Asynchronous Clock Input. Data is
registered at rising edge.
SB1_CLKI
G17
IN
Sideband Data Channel 1 Upstream Synchronous Clock Output. Data is
registered at rising edge.
SB1_CLKO
SB1_ D[1:0]
SB2_CLK
G18
F18,F17
E17
OUT
IN
LVTTL
LVTTL
LVTTL
Sideband Data Channel 1 Upstream Input
Sideband Data Channel 2 Downstream Synchronous Clock Output. Data is
provided aligned to rising edge.
OUT
SB2_D[3:0]
C17,D18,
D17,E18
If CFG_CYC=0: Sideband Data Channel 2 Downstream Output
If CFG_CYC=1: Configuration vector output
OUT
LVTTL
(CFG_SEL[3:0])
Sideband Data Channel 3 Downstream Synchronous Clock Output. Data is
provided aligned to rising edge.
SB3_CLK
SB3_D[1:0]
SB4_CLK
M18
K18,L18
J18
OUT
OUT
OUT
LVTTL
LVTTL
LVTTL
LVTTL
Sideband Data Channel 3 Downstream Output
Sideband Data Channel 4 Downstream Synchronous Clock Output. Data is
provided aligned to rising edge.
SB4_D[1:0]
Audio Interface
AI_C0
H18,H17 OUT
Sideband Data Channel 4 Downstream Output
E1
F1
G1
H1
OUT
OUT
OUT
OUT
LVTTL
LVTTL
LVTTL
LVTTL
S/P-DIF Audio Channel 0
S/P-DIF Audio Channel 1
S/P-DIF Audio Channel 2
S/P-DIF Audio Channel 3
AI_C1
AI_C2
AI_C3
Other Signals
RESET#
ERROR
CFG_CYC
OSC
A1
B1
IN
OUT
OUT
IN
LVTTL
LVTTL
LVTTL
LVTTL
A
Asynchronous Hardware Reset (active LOW)
Pixel Clock Recovery Error
C2
A3
Indicates that the configuration process is active
Reference Oscillator Input (see chapter 3.7)
Loop filter pin Downlink 0
CAP1
A15
B15
A8
IN
CAP2
IN
A
Loop filter pin Downlink 0
CAP3
IN
A
A
Loop filter pin Downlink 1
CAP4
B8
IN
Loop filter pin Downlink 1
Table 4.10: INDR331B Receiver Signals
Date: 2005-03-14 Revision: 0.1
Page 32 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
Pin Name
Pin
Dir
Type
Description
Power Supply
G4,G9,G12,H3,H4,J3,J4,J8,J12,J15,J16,J17,L6,L10,L14,N3,N4,N8,
N12,R6,R10,R14,T6,T10,T14
VCC_CORE
IN
IN
POWER
CMOS core supply
E3,F15,G7,G13,H6,H10,H14,K3,K4,K8,K12,K15,K16,K17,L3,L4,M6,
M10,M14,P4,P8,P12,P15,P16,R4,R16,T4
G2,G3,G5,G8,G10,G11,G15,G16,H2,H7,H8,H11,H12,H15,H16,J2,
J7,J11,K5,K6,K9,K10,K13,K14,L5,L9,L13,M3,M4,M7,M8,M11,M12,M15,M16
,M17,N2,N7,N11,N15,N16,P5,P6,P9,P10,P13,P14,R5,R9,R13,T5,T9,T13
B16,B17,C16,D2,D9,D16,E2,E9,E15,E16,F2,F3,F8,F9,F10,F16,
G6,G14,H5,H9,H13,J5,J6,J9,J10,J13,J14,K2,K7,K11,L2,L7,L8,L11,
L12,L15,L16,L17,M2,M5,M9,M13,N5,N6,N9,N10,N13,N14,P3,P7,
P11,R3,R7,R8,R11,R12,R15,T2,T3,T7,T8,T11,T12,T15,T16,U2
F4,F5,F11,F12
GND_CORE
GROUND
VCC_IO
GND_IO
IN
IN
POWER
CMOS digital I/O
supply
GROUND
VCC_CML
GND_CML
VCC_SX
GND_SX
VCC_IA
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
POWER
GROUND
CMOS chip-to-chip
interface supply
F6,F7,F13,F14
B9
C9
CMOS uplink I/O
supply
E6,E8,E12,E14
Bipolar Chip-to-chip
interface supply
GND_IA
E5,E7,E11,E13
VCC_A0
GND_A0
VCC_A1
GND_A1
A4,A7,A11,A14,C3,C4,C8,C10,C11,C15,D3,D8,D10,D15
A5,A6,A12,A13,B4,B7,B11,B14,C5,C6,C7,C12,C13,C14,E4,E10
D6,D7,D13,D14
Bipolar downlink I/O
supply
Bipolar PLL supply
D4,D5,D11,D12
Table 4.11: INDR331B Receiver Power Supply
Pin Name
Pin
R17
T18
T17
U18
U17
V18
V17
V16
U16
V15
U15
V14
Pin Name
PX_D35
PX_D34
PX_D33
PX_D32
PX_D31
PX_D30
PX_D29
PX_D28
PX_D27
PX_D26
PX_D25
PX_D24
Pin
U14
V13
U13
V12
U12
V11
U11
V10
U10
V9
Pin Name
PX_D23
PX_D22
PX_D21
PX_D20
PX_D19
PX_D18
PX_D17
PX_D16
PX_D15
PX_D14
PX_D13
PX_D12
Pin
U8
V7
U7
V6
U6
V5
U5
V4
U4
V3
U3
V2
Pin Name
PX_D11
PX_D10
PX_D9
PX_D8
PX_D7
PX_D6
PX_D5
PX_D4
PX_D3
PX_D2
PX_D1
PX_D0
Pin
V1
U1
T1
R1
R2
P1
P2
N1
M1
L1
PX_D47
PX_D46
PX_D45
PX_D44
PX_D43
PX_D42
PX_D41
PX_D40
PX_D39
PX_D38
PX_D37
PX_D36
U9
K1
J1
V8
Table 4.12: INDR331B Receiver Pixel Data Pin Numbers
Date: 2005-03-14 Revision: 0.1
Page 33 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
5 Pin Assignment
5.1 INDT166B Transmitter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CFG_
CYC
GND_
IO
VCC_
A0
GND_
A0
GND_
A0
VCC_
A0
SB0_
D3
SB0_
D1
SB0_
CLK
SB2_
D3
ERROR
RX2-
RX2+
OSC
A
B
C
D
E
F
VCC_
SX
GND_
SX
GND_
A0
GND_
A0
SB0_
D2
SB0_
D0
SB2_
D1
SB2_
D2
NC
SYNC2 RESET#
LOCK0
TX0+
TX0-
VCC_
CORE
VCC_
IO
GND_
IO
VCC_
A0
VCC_
A0
GND_
A0
GND_
A0
VCC_
A0
SB2_
CLK
SB2_
D0
AI_C1 AI_C0
AI_C3 AI_C2
CAP1
CAP2
VCC_
CORE
VCC_
IO
GND_
CORE
VCC_
A0
GND_
A1
GND_
A1
VCC_
A1
VCC_
A1
GND_
A0
VCC_
A0
SB1_
D0
SB1_
D1
VCC_
VCC_
IO
VCC_
CORE
GND_
CORE
GND_
A0
GND_
IA
VCC_
IA
GND_
IA
VCC_
IA
GND_
CORE
GND_
IO
SB3_
D1
SB1_
CLK
PX_D0
IO
GND_
IO
GND_
CORE
GND_
IO
GND_
CORE
VCC_
CML
VCC_
CML
GND_
CML
GND_
CML
GND_
CORE
GND_
IO
SB3_
CLKO
SB3_
D0
PX_D2 PX_D1
PX_D4 PX_D3
PX_D6 PX_D5
PX_D8 PX_D7
PX_D10 PX_D9
PX_D12 PX_D11
PX_D14 PX_D13
GND_
IO
GND_
CORE
GND_
IO
GND_
CORE
VCC_
CORE
VCC_
CORE
VCC_
IO
VCC_
CORE
VCC_
IO
GND_
IO
SB3_
CLKI
VREF
G
H
J
VCC_
CORE
VCC_
IO
GND_
CORE
GND_
CORE
VCC_
IO
VCC_
CORE
GND_
IO
GND_
CORE
VCC_
IO
GND_
CORE
PX_
VSYNC
PX_
DE
VCC_
CORE
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
CORE
VCC_
CORE
VCC_
IO
PX_
HSYNC
PX_
CLK–
GND_
CORE
GND_
IO
VCC_
IO
VCC_
IO
GND_
CORE
GND_
CORE
VCC_
IO
VCC_
IO
GND_
CORE
GND_
IO
PX_
CLK+
PX_D47
K
L
GND_
CORE
GND_
IO
VCC_
CORE
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
CORE
VCC_
IO
PX_D45 PX_D46
PX_D43 PX_D44
VCC_
CORE
VCC_
IO
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
CORE
GND_
IO
VCC_
CORE
VCC_
CORE
M
N
P
PX_D16 PX_D15 PX_D19 PX_D21 PX_D23 PX_D25 PX_D27 PX_D29 PX_D31 PX_D33 PX_D35 PX_D37 PX_D41 PX_D42
PX_D17 PX_D18 PX_D20 PX_D22 PX_D24 PX_D26 PX_D28 PX_D30 PX_D32 PX_D34 PX_D36 PX_D38 PX_D39 PX_D40
Table 5.1: INDT166B GigaSTaR Digital Display Link Transmitter Pin Assignment (Top View)
= Pin A1 Identifier
Date: 2005-03-14 Revision: 0.1
Page 34 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
5.2 INDR166B Receiver
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CFG_
CYC
PX_CLK
_IN
VCC_
A0
GND_
A0
GND_
A0
VCC_
A0
SB0_
D3
SB0_
D1
SB0_
CLK
SB2_
D3
ERROR
TX2-
TX2+
OSC
A
B
C
D
E
F
VCC_
SX
GND_
SX
GND_
A0
GND_
A0
SB0_
D2
SB0_
D0
SB2_
D1
SB2_
D2
NC
SYNC0 RESET#
LOCK0
RX0+
RX0-
VCC_
CORE
VCC_
IO
VCC_
A0
VCC_
A0
GND_
A0
GND_
A0
VCC_
A0
SB2_
CLK
SB2_
D0
AI_C1 AI_C0
AI_C3 AI_C2
EQ
CAP1
CAP2
VCC_
IO
VCC_
IO
GND_
IO
VCC_
A0
GND_
A1
GND_
A1
VCC_
A1
VCC_
A1
GND_
A0
VCC_
A0
SB1_
D0
SB1_
D1
VCC_
VCC_
CORE
GND_
CORE
GND_
IO
GND_
A0
GND_
IA
VCC_
IA
GND_
IA
VCC_
IA
GND_
CORE
GND_
IO
SB1_
CLKI
SB1_
CLKO
PX_D0
IO
VCC_
GND_
IO
GND_
CORE
GND_
IO
GND_
IO
VCC_
CML
VCC_
CML
GND_
CML
GND_
CML
GND_
CORE
GND_
CORE
SB3_
D0
SB3_
D1
PX_D1
IO
GND_
IO
GND_
CORE
GND_
IO
GND_
CORE
VCC_
IO
VCC_
CORE
VCC_
IO
VCC_
CORE
VCC_
IO
GND_
IO
PX_
HSYNC
SB3_
CLK
PX_D3 PX_D2
PX_D5 PX_D4
PX_D7 PX_D6
PX_D9 PX_D8
PX_D11 PX_D10
PX_D13 PX_D12
G
H
J
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
GND_
IO
PX_
VSYNC
PX_CLK
_OUT
VCC_
CORE
VCC_
CORE
GND_
IO
GND_
IO
VCC_
CORE
VCC_
IO
GND_
IO
GND_
CORE
VCC_
CORE
VCC_
IO
PX_DE PX_CLK
PX_D46 PX_D47
PX_D44 PX_D45
PX_D42 PX_D43
GND_
IO
GND_
IO
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
CORE
GND_
IO
K
L
GND_
CORE
GND_
IO
VCC_
CORE
VCC_
CORE
GND_
IO
GND_
CORE
VCC_
IO
VCC_
CORE
GND_
IO
VCC_
IO
VCC_
IO
VCC_
IO
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
CORE
GND_
IO
VCC_
CORE
VCC_
IO
M
N
P
PX_D15 PX_D14 PX_D18 PX_D20 PX_D22 PX_D24 PX_D26 PX_D28 PX_D30 PX_D32 PX_D34 PX_D36 PX_D40 PX_D41
PX_D16 PX_D17 PX_D19 PX_D21 PX_D23 PX_D25 PX_D27 PX_D29 PX_D31 PX_D33 PX_D35 PX_D37 PX_D38 PX_D39
Table 5.2: INDR166B GigaSTaR Digital Display Link Receiver Pin Assignment (Top View)
Date: 2005-03-14 Revision: 0.1
Page 35 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
5.3 INDT331B Transmitter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
VCC_
A0
GND_
A0
GND_
A0
VCC_
A0
VCC_
A0
GND_
A0
GND_
A0
VCC_
A0
SB0_
D3
SB0_
D2
SB0_
D1
RESET#
OSC
CAP3
RX2–
RX2+
CAP1
A
B
C
D
E
F
GND_
IO
CFG_
CYC
GND_
A0
GND_
A0
VCC_
SX
GND_
A0
GND_
A0
GND_
IO
GND_
IO
SB0_
D0
ERROR LOCK1
TX1+
TX1–
CAP4
LOCK0
TX0+
TX0–
CAP2
VCC_
VCC_
A0
GND_
A0
GND_
A0
GND_
A0
VCC_
A0
GND_
SX
VCC_
A0
VCC_
A0
GND_
A0
GND_
A0
GND_
A0
VCC_
A0
GND_
IO
SB2_
D3
SB0_
CLK
NC
SYNC2
A0
VCC_
A0
GND_
A1
GND_
A1
VCC_
A1
VCC_
A1
VCC_
A0
GND_
IO
VCC_
A0
GND_
A1
GND_
A1
VCC_
A1
VCC_
A1
VCC_
A0
GND_
IO
SB2_
D1
SB2_
D2
AI_C1 AI_C0
GND_
GND_
IO
GND_
A0
GND_
IA
VCC_
IA
GND_
IA
VCC_
IA
GND_
IO
GND_
A0
GND_
IA
VCC_
IA
GND_
IA
VCC_
IA
GND_
IO
GND_
IO
SB2_
CLK
SB2_
D0
AI_C2
IO
GND_
AI_C3
GND_
IO
VCC_
CML
VCC_
CML
GND_
CML
GND_
CML
GND_
IO
GND_
IO
GND_
IO
VCC_
CML
VCC_
CML
GND_
CML
GND_
CML
GND_
IO
GND_
IO
SB1_
D0
SB1_
D1
CORE
VCC_
VCC_
CORE
VCC_
CORE
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
CORE
VCC_
IO
VCC_
IO
VCC_
CORE
GND_
CORE
GND_
CORE
VCC_
IO
VCC_
IO
SB3_
D1
SB1_
CLK
PX_D0
IO
G
H
J
VCC_
VCC_
IO
VCC_
CORE
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
SB3_
CLKO
SB3_
D0
PX_D1
IO
GND_
PX_D2
GND_
CORE
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
CORE
VCC_
CORE
VCC_
CORE
SB3_
CLKI
CORE
GND_
PX_D3
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
CORE
GND_
CORE
GND_
CORE
SB4_
D1
K
L
CORE
GND_
PX_D4
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
GND_
IO
SB4_
D0
CORE
VCC_
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
VCC_
IO
SB4_
CLKO
PX_D5
IO
M
N
P
R
T
VCC_
PX_D6
VCC_
CORE
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
IO
SB4_
CLKI
VREF
CORE
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
CORE
GND_
CORE
PX_
VSYNC
PX_D8 PX_D7
PX_D10 PX_D9
PX_DE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
PX_
HSYNC
PX_
CLK–
GND_
PX_D11
GND_
CORE
GND_
CORE
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
PX_
CLK+
PX_D47
IO
GND_
PX_D12
PX_D15 PX_D17 PX_D19 PX_D21 PX_D23 PX_D25 PX_D27 PX_D29 PX_D31 PX_D33 PX_D35 PX_D37 PX_D39 PX_D41 PX_D45 PX_D46
U
V
IO
PX_D13 PX_D14 PX_D16 PX_D18 PX_D20 PX_D22 PX_D24 PX_D26 PX_D28 PX_D30 PX_D32 PX_D34 PX_D36 PX_D38 PX_D40 PX_D42 PX_D43 PX_D44
Table 5.3: INDT331B GigaSTaR Digital Display Link Transmitter Pin Assignment (Top View)
Date: 2005-03-14 Revision: 0.1
Page 36 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
5.4 INDR331B Receiver
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
VCC_
A0
GND_
A0
GND_
A0
VCC_
A0
VCC_
A0
GND_
A0
GND_
A0
VCC_
A0
SB0_
D3
SB0_
D2
SB0_
D1
EQ
OSC
CAP3
TX2–
TX2+
CAP1
A
B
C
D
E
F
RESET#
PX_CLK
_IN
GND_
A0
GND_
A0
VCC_
SX
GND_
A0
GND_
A0
GND_
IO
GND_
IO
SB0_
D0
ERROR
SNYC0
SYNC1
AI_C0
AI_C1
AI_C2
AI_C3
PX_D0
PX_D1
PX_D2
PX_D3
PX_D4
LOCK1
RX1+
RX1–
CAP4
LOCK0
RX0+
RX0–
CAP2
CFG_
CYC
VCC_
A0
VCC_
A0
GND_
A0
GND_
A0
GND_
A0
VCC_
A0
GND_
SX
VCC_
A0
VCC_
A0
GND_
A0
GND_
A0
GND_
A0
VCC_
A0
GND_
IO
SB2_
D3
SB0_
CLK
GND_
IO
VCC_
A0
GND_
A1
GND_
A1
VCC_
A1
VCC_
A1
VCC_
A0
GND_
IO
VCC_
A0
GND_
A1
GND_
A1
VCC_
A1
VCC_
A1
VCC_
A0
GND_
IO
SB2_
D1
SB2_
D2
GND_
IO
GND_
CORE
GND_
A0
GND_
IA
VCC_
IA
GND_
IA
VCC_
IA
GND_
IO
GND_
A0
GND_
IA
VCC_
IA
GND_
IA
VCC_
IA
GND_
IO
GND_
IO
SB2_
CLK
SB2_
D0
GND_
IO
GND_
IO
VCC_
CML
VCC_
CML
GND_
CML
GND_
CML
GND_
IO
GND_
IO
GND_
IO
VCC_
CML
VCC_
CML
GND_
CML
GND_
CML
GND_
CORE
GND_
IO
SB1_
D0
SB1_
D1
VCC_
IO
VCC_
IO
VCC_
CORE
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
CORE
VCC_
IO
VCC_
IO
VCC_
CORE
GND_
CORE
GND_
IO
VCC_
IO
VCC_
IO
SB1_
CLKI
SB1_
CLKO
G
H
J
VCC_
IO
VCC_
CORE
VCC_
CORE
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
SB4_
D0
SB4_
D1
VCC_
IO
VCC_
CORE
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
CORE
VCC_
CORE
VCC_
CORE
SB4_
CLK
GND_
IO
GND_
CORE
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
CORE
GND_
CORE
GND_
CORE
SB3_
D1
K
L
GND_
IO
GND_
CORE
GND_
CORE
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
GND_
IO
SB3_
D0
GND_
IO
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
VCC_
IO
SB3_
CLK
M
N
P
R
T
VCC_
IO
VCC_
CORE
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
IO
PX_
PX_
VSYNC HSYNC
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
IO
GND_
CORE
VCC_
IO
VCC_
IO
GND_
CORE
GND_
CORE
PX_CLK
PX_DE
PX_D6 PX_D5
PX_D8 PX_D7
_OUT
GND_
IO
GND_
CORE
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
CORE
PX_D47 PX_CLK
PX_D45 PX_D46
GND_
GND_
IO
GND_
CORE
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
VCC_
IO
VCC_
CORE
GND_
IO
GND_
IO
PX_D9
IO
GND_
PX_D10
PX_D13 PX_D15 PX_D17 PX_D19 PX_D21 PX_D23 PX_D25 PX_D27 PX_D29 PX_D31 PX_D33 PX_D35 PX_D37 PX_D39 PX_D43 PX_D44
U
V
IO
PX_D11 PX_D12 PX_D14 PX_D16 PX_D18 PX_D20 PX_D22 PX_D24 PX_D26 PX_D28 PX_D30 PX_D32 PX_D34 PX_D36 PX_D38 PX_D40 PX_D41 PX_D42
Table 5.4: INDR331B GigaSTaR Digital Display Link Receiver Pin Assignment (Top View)
Date: 2005-03-14 Revision: 0.1
Page 37 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
6 Package Information
6.1 INDT/R166B
Figure 6.1: Package: BGA 196, 15 x 15 mm, 196 balls, 1 mm ball pitch
Dim
Min
Nom
Max
A
A1
A2
A3
b
–
1.9
0.36
0.46
0.38 REF
1.0 REF
0.44
0.64
D
15 BSC
15 BSC
1.0 BSC
13 BSC
13 BSC
E
e
D1
E1
All dimensions and tolerances in mm!
Figure 6.2: BGA 196 – Dimensions and Tolerances
Date: 2005-03-14 Revision: 0.1
Page 38 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
6.2 INDT/R331B
Figure 6.3: Package: BGA 324, 19 x 19 mm, 324 balls, 1 mm ball pitch
Dim
Min
Nom
Max
A
A1
A2
A3
b
–
2.0
0.6
0.4
0.38 Ref
1.0 Ref
0.55
0.7
D
19 BSC
19 BSC
1.0 BSC
17 BSC
17 BSC
E
e
D1
E1
All dimensions and tolerances in mm!
Figure 6.4: BGA 324 – Dimensions and Tolerances
Date: 2005-03-14 Revision: 0.1
Page 39 of 40
INDT/R166B
INDT/R331B
Preliminary Data Sheet
7 Ordering and Product Availability
Ordering Code Delivery Package
Minimum Packing Quantity
Status
INDT166B
INDR166B
IND166SK
INDT331B
INDR331B
IND331SK
Tray (in sealed dry pack)
Tray (in sealed dry pack)
Sample Kit (5 x Tx, 5 x Rx)
Tray (in sealed dry pack)
Tray (in sealed dry pack)
Sample Kit (2 x Tx, 2 x Rx)
126 units
126 units
10 units
84 units
84 units
4 units
Engineering Samples available by June ‘05
Engineering Samples available by June ‘05
Engineering Samples available by June ‘05
Engineering Samples available by June ‘05
Engineering Samples available by June ‘05
Engineering Samples available by June ‘05
Table 7.1: Product Availability
8 Revision History
The information contained in this data sheet supersedes information published in previous versions.
The following changes were made:
• v 0.1 Preliminary Data Sheet
Inova Semiconductors GmbH
Grafinger Str. 26
D-81675 Munich, Germany
Phone: +49 (0)89 / 45 74 75 - 60
Fax:
+49 (0)89 / 45 74 75 - 88
Email: mailto:info@inova-semiconductors.de
URL: http://www.inova-semiconductors.com
is a registered trademark of Inova Semiconductors GmbH.
All other trademarks or registered trademarks are the property of their respective holders.
This document contains information on new products not yet released to production. Therefore specifications and
information herein are subject to change without notice. Inova Semiconductors GmbH does not assume any liability arising
out of the applications or use of the product described herein; nor does it convey any license under its patents, copyright
rights or any rights of others.
Inova Semiconductors products are not designed, intended or authorized for use as components in systems to support or
sustain life, or for any other application in which the failure of the product could create a situation where personal injury or
death may occur. The information contained in this document is believed to be current and accurate as of the publication
date. Inova Semiconductors GmbH reserves the right to make changes at any time in order to improve reliability, function
or performance to supply the best product possible.
Inova Semiconductors GmbH assumes no obligation to correct any errors contained herein or to advise any user of this
text of any correction if such be made.
© Inova Semiconductors 2005
Date: 2005-03-14 Revision: 0.1
Page 40 of 40
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