IRFW720A [ETC]

TRANSISTOR | MOSFET | N-CHANNEL | 400V V(BR)DSS | 3.3A I(D) | TO-263AB ; 晶体管| MOSFET | N沟道| 400V V( BR ) DSS | 3.3AI (D ) | TO- 263AB\n
IRFW720A
型号: IRFW720A
厂家: ETC    ETC
描述:

TRANSISTOR | MOSFET | N-CHANNEL | 400V V(BR)DSS | 3.3A I(D) | TO-263AB
晶体管| MOSFET | N沟道| 400V V( BR ) DSS | 3.3AI (D ) | TO- 263AB\n

晶体 晶体管 开关 脉冲
文件: 总7页 (文件大小:227K)
中文:  中文翻译
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IRFW/I720A  
FEATURES  
BVDSS = 400 V  
RDS(on) = 1.8  
ID = 3.3 A  
Avalanche Rugged Technology  
Rugged Gate Oxide Technology  
Lower Input Capacitance  
Improved Gate Charge  
Extended Safe Operating Area  
D2-PAK  
I2-PAK  
Lower Leakage Current: 10 A (Max.) @ VDS = 400V  
µ
2
Lower RDS(ON): 1.408 (Typ.)  
1
1
2
3
3
1. Gate 2. Drain 3. Source  
Absolute Maximum Ratings  
Symbol  
Characteristic  
Value  
400  
3.3  
Units  
VDSS  
Drain-to-Source Voltage  
V
Continuous Drain Current (TC=25°C)  
Continuous Drain Current (TC=100°C)  
Drain Current-Pulsed  
ID  
A
2.1  
IDM  
VGS  
EAS  
IAR  
(1)  
13  
A
V
Gate-to-Source Voltage  
30  
±
(2)  
(1)  
(1)  
(3)  
Single Pulsed Avalanche Energy  
Avalanche Current  
249  
3.3  
4.9  
4.0  
3.1  
49  
mJ  
A
EAR  
dv/dt  
Repetitive Avalanche Energy  
Peak Diode Recovery dv/dt  
mJ  
V/ns  
W
*
Total Power Dissipation (TA=25°C)  
Total Power Dissipation (TC=25°C)  
Linear Derating Factor  
PD  
W
0.39  
W/°C  
Operating Junction and  
TJ , TSTG  
- 55 to +150  
300  
Storage Temperature Range  
°C  
Maximum Lead Temp. for Soldering  
Purposes, 1/8 from case for 5-seconds  
TL  
Thermal Resistance  
Symbol  
RθJC  
Characteristic  
Typ.  
Max.  
Units  
Junction-to-Case  
--  
--  
--  
2.57  
40  
RθJA  
*
Junction-to-Ambient  
Junction-to-Ambient  
°C/W  
RθJA  
62.5  
When mounted on the minimum pad size recommended (PCB Mount).  
*
Rev. B  
©1999 Fairchild Semiconductor Corporation  
IRFW/I720A  
Electrical Characteristics (TC=25°C unless otherwise specified)  
Symbol  
BVDSS  
Characteristic  
Min. Typ. Max. Units  
Test Condition  
V
GS=0V,ID=250µA  
V
Drain-Source Breakdown Voltage  
Breakdown Voltage Temp. Coeff.  
Gate Threshold Voltage  
400 --  
--  
BV/TJ  
VGS(th)  
ID=250µA  
See Fig 7  
V/°C  
-- 0.54 --  
VDS=5V,ID=250µA  
VGS=30V  
V
2.0  
--  
--  
4.0  
100  
Gate-Source Leakage , Forward  
Gate-Source Leakage , Reverse  
--  
--  
--  
--  
IGSS  
nA  
VGS=-30V  
-- -100  
V
V
DS=400V  
--  
--  
10  
IDSS  
Drain-to-Source Leakage Current  
µA  
DS=320V,TC=125°C  
100  
Static Drain-Source  
On-State Resistance  
Forward Transconductance  
Input Capacitance  
VGS=10V,ID=1.65A  
VDS=50V,ID=1.65A  
(4)  
(4)  
RDS(on)  
--  
--  
1.8  
gfs  
Ciss  
Coss  
Crss  
td(on)  
tr  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
2.25 --  
385 500  
V
GS=0V,VDS=25V,f =1MHz  
See Fig 5  
Output Capacitance  
Reverse Transfer Capacitance  
Turn-On Delay Time  
Rise Time  
70  
33  
35  
45  
110  
45  
26  
--  
60  
27  
pF  
ns  
12  
VDD=200V,ID=3.3A,  
RG=18Ω  
17  
td(off)  
tf  
Turn-Off Delay Time  
Fall Time  
51  
(4) (5)  
(4) (5)  
See Fig 13  
18  
Qg  
Total Gate Charge  
Gate-Source Charge  
Gate-Drain ( Miller ) Charge  
19  
VDS=320V,VGS=10V,  
ID=3.3A  
Qgs  
Qgd  
nC  
2.7  
11.1  
--  
See Fig 6 & Fig 12  
Source-Drain Diode Ratings and Characteristics  
Symbol  
IS  
Characteristic  
Continuous Source Current  
Pulsed-Source Current  
Diode Forward Voltage  
Reverse Recovery Time  
Reverse Recovery Charge  
Min. Typ. Max. Units  
Test Condition  
Integral reverse pn-diode  
in the MOSFET  
--  
--  
--  
--  
--  
--  
3.3  
13  
1.5  
--  
A
ISM  
(1)  
(4)  
VSD  
trr  
V
--  
TJ=25°C,IS=3.3A,VGS=0V  
TJ=25°C,IF=3.3A  
ns  
µC  
230  
Qrr  
-- 1.16 --  
(4)  
diF/dt=100A/µs  
Notes;  
(1) Repetitive Rating: Pulse Width Limited by Maximum Junction Temperature  
(2) L=40mH, IAS=3.3A, VDD=50V, R =27 , Starting T =25 C  
°
G
J
(3) ISD 3.3A, di/dt 110A/ s, V  
BV , Starting T =25 C  
°
DSS J  
µ
DD  
(4) Pulse Test: Pulse Width = 250 s, Duty Cycle 2%  
µ
(5) Essentially Independent of Operating Temperature  
IRFW/I720A  
Fig 1. Output Characteristics  
Fig 2. Transfer Characteristics  
1
1
VGS  
10  
10  
Top :  
15V  
10 V  
8.0 V  
7.0 V  
6.0 V  
5.5V  
5.0 V  
150oC  
0
Bottom : 4.5V  
10  
0
10  
25oC  
@Notes :  
1. VGS =0 V  
2. VDS =50V  
3. 250 µsPulse Test  
-1  
10  
@ Notes:  
-55 oC  
1. 250µs PulseTest  
2. T =25 oC  
C
-1  
10  
-1  
0
1
2
4
6
8
10  
10  
10  
10  
VGS , Gate-Source Voltage [V]  
VDS , Drain-Source Voltage [V]  
Fig 3. On-Resistance vs. Drain Current  
Fig 4. Source-Drain Diode Forward Voltage  
5
4
3
2
1
0
1
10  
VGS =10V  
0
10  
VGS =20V  
@Notes:  
150oC  
1. VGS =0V  
25oC  
@Note:T =25oC  
2. 250µsPulseTest  
J
-1  
10  
0
3
6
9
12  
0.4  
0.6  
0.8  
1.0  
1.2  
I , Drain Current [A]  
VSD , Source-Drain Voltage [V]  
D
Fig 5. Capacitance vs. Drain-Source Voltage  
Fig 6. Gate Charge vs. Gate-Source Voltage  
600  
400  
200  
C
iss= C + Cgd (C = shorted)  
gs ds  
V
DS =80V  
DS =200V  
DS =320V  
C
oss= C + C  
ds gd  
10  
C
rss= C  
C iss  
gd  
V
V
5
C oss  
@ Notes:  
1. VGS =0 V  
2. f =1 MHz  
C rss  
@Notes :I =3.3A  
D
00  
10  
0
1
0
5
10  
15  
20  
10  
Q , Total Gate Charge [nC]  
V
DS , Drain-Source Voltage [V]  
G
IRFW/I720A  
Fig 7. Breakdown Voltage vs. Temperature  
Fig 8. On-Resistance vs. Temperature  
1.2  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
1.1  
1.0  
0.9  
@ Notes:  
1. VGS =0 V  
@Notes :  
1. VGS =10V  
2. I =250µA  
2. I =1.65 A  
D
D
0.8  
-75 -50 -25  
0
25  
50  
75  
100 125 150 175  
o
-75 -50 -25  
0
25  
50  
75  
100 125 150 175  
o
T , Junction Temperature [C]  
T , Junction Temperature [C]  
J
J
Fig 9. Max. Safe Operating Area  
Fig 10. Max. Drain Current vs. Case Temperature  
4
2
10  
Operation in This Area  
isLimitedby R DS(on)  
1
10µs  
3
2
1
0
10  
100µs  
1 ms  
10ms  
0
DC  
10  
@ Notes:  
-1  
10  
1. T =25oC  
2. T =150oC  
C
J
3. SinglePulse  
-2  
10  
0
1
2
3
25  
50  
75  
100  
125  
150  
10  
10  
10  
10  
o
T , Case Temperature [C]  
VDS , Drain-Source Voltage [V]  
c
Fig 11. Thermal Response  
D=0.5  
0.2  
100  
10-1  
10-2  
@ Notes :  
1. Z (t)=2.57 oC/W Max.  
θ JC  
0.1  
2. Duty Factor, D=t1/t2  
3. TJM-TC=PDM*Zθ JC(t)  
0.05  
0.02  
0.01  
PDM  
single pulse  
t1  
t2  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
101  
t1 , Square Wave Pulse Duration [sec]  
IRFW/I720A  
Fig 12. Gate Charge Test Circuit & Waveform  
Current Regulator  
VGS  
Same Type  
as DUT  
50k  
Qg  
200nF  
12V  
10V  
300nF  
VDS  
Qgs  
Qgd  
VGS  
DUT  
R2  
3mA  
R1  
Charge  
Current Sampling (IG) Current Sampling (ID)  
Resistor Resistor  
Fig 13. Resistive Switching Test Circuit & Waveforms  
RL  
Vout  
Vin  
Vout  
90%  
VDD  
( 0.5 rated VDS  
)
RG  
DUT  
10%  
Vin  
10V  
td(on)  
tr  
td(off)  
tf  
t on  
t off  
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms  
BVDSS  
1
2
2
LL  
ID  
----  
--------------------  
EAS  
=
LL IAS  
BVDSS -- VDD  
VDS  
BVDSS  
IAS  
Vary tp to obtain  
required peak ID  
RG  
ID (t)  
VDD  
C
DUT  
VDS (t)  
VDD  
10V  
t p  
t p  
Time  
IRFW/I720A  
Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms  
+
DUT  
VDS  
--  
I S  
L
Driver  
VGS  
Same Type  
as DUT  
RG  
VDD  
VGS  
dv/dt controlled by RG  
IS controlled by Duty Factor  
D
Gate Pulse Width  
--------------------------  
VGS  
D =  
Gate Pulse Period  
10V  
( Driver )  
IFM , Body Diode Forward Current  
I S  
di/dt  
( DUT )  
IRM  
Body Diode Reverse Current  
Body Diode Recovery dv/dt  
Vf  
VDS  
( DUT )  
VDD  
Body Diode  
Forward Voltage Drop  
TRADEMARKS  
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is  
not intended to be an exhaustive list of all such trademarks.  
ACEx™  
CoolFET™  
ISOPLANAR™  
MICROWIRE™  
POP™  
PowerTrench™  
QS™  
CROSSVOLT™  
E2CMOSTM  
FACT™  
FACT Quiet Series™  
Quiet Series™  
SuperSOT™-3  
SuperSOT™-6  
SuperSOT™-8  
TinyLogic™  
FAST®  
FASTr™  
GTO™  
HiSeC™  
DISCLAIMER  
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER  
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD  
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT  
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT  
RIGHTS, NOR THE RIGHTS OF OTHERS.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.  
As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant into  
the body, or (b) support or sustain life, or (c) whose  
failure to perform when properly used in accordance  
with instructions for use provided in the labeling, can be  
reasonably expected to result in significant injury to the  
user.  
2. A critical component is any component of a life  
support device or system whose failure to perform can  
be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or  
effectiveness.  
PRODUCT STATUS DEFINITIONS  
Definition of Terms  
Datasheet Identification  
Product Status  
Definition  
Advance Information  
Formative or  
In Design  
This datasheet contains the design specifications for  
product development. Specifications may change in  
any manner without notice.  
Preliminary  
First Production  
This datasheet contains preliminary data, and  
supplementary data will be published at a later date.  
Fairchild Semiconductor reserves the right to make  
changes at any time without notice in order to improve  
design.  
No Identification Needed  
Obsolete  
Full Production  
This datasheet contains final specifications. Fairchild  
Semiconductor reserves the right to make changes at  
any time without notice in order to improve design.  
Not In Production  
This datasheet contains specifications on a product  
that has been discontinued by Fairchild semiconductor.  
The datasheet is printed for reference information only.  

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