IS25LD020 [ETC]
512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus Interface;
| 型号： | IS25LD020 |
| 厂家： | 
ETC |
| 描述： | 512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus Interface |
| 文件： | 总40页 (文件大小：912K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS25CD512/010 & IS25LD020
512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory
With 100 MHz Dual-Output SPI Bus Interface
FEATURES
• Low Power Consumption
• Single Power Supply Operation
- Low voltage range: 2.70 V – 3.60 V (512Kbit / 1Mbit)
2.30 V – 3.60 V (2Mbit)
- Typical 10 mA active read current
- Typical 15 mA program/erase current
• Hardware Write Protection
• Memory Organization
- Protect and unprotect the device from write operation by
Write Protect (WP#) Pin
- IS25CD512: 64K x 8 (512 Kbit)
- IS25CD010: 128K x 8 (1 Mbit)
- IS25LD020: 256K x 8 (2 Mbit)
• Software Write Protection
- The Block Protect (BP2, BP1, BP0) bits allow partial or
entire memory to be configured as read-only
• Cost Effective Sector/Block Architecture
- 512Kb : Uniform 4KByte sectors / Two uniform 32KByte
blocks
• High Product Endurance
- 1Mb : Uniform 4KByte sectors / Four uniform 32KByte
- Guaranteed 200,000 program/erase cycles per single
sector
blocks
- 2Mb : Uniform 4KByte sectors / Four uniform 64KByte
blocks
- Minimum 20 years data retention
• Industrial Standard Pin-out and Package
- 8-pin SOIC 150mil
• Low standby current 1uA (Typ)
• Serial Peripheral Interface (SPI) Compatible
- Supports single- or dual-output
- Supports SPI Modes 0 and 3
- 8-pin VVSOP 150mil (2Mb)
- 8-pin USON (2x3 mm) (512Kb)
- 8-pin WSON (5x6 mm)
- Maximum 33 MHz clock rate for normal read
- Maximum 100 MHz clock rate for fast read
- 8-pin TSSOP
- KGD (Call Factory)
- Lead-free (Pb-free) package
- Automotive Temperature Ranges Available
• Page Program (up to 256 Bytes) Operation
- Typical 2 ms per page program
• Security function
• Sector, Block or Chip Erase Operation
- Maximum 10 ms sector, block or chip erase
- Built in Safe Guard function and sector unlock function
to make the flash Robust (Appendix1&2)
GENERAL DESCRIPTION
The IS25CD512/010 and IS25LD020 are 512Kbit/ 1Mbit / 2Mbit Serial Peripheral Interface (SPI) Flash memories, providing
single- or dual-output. The devices are designed to support a 33 MHz clock rate in normal read mode, and 100 MHz in fast
read, the fastest in the industry. The devices use a single low voltage power supply, wide operating voltage ranging to
perform read, erase and program operations. The devices can be programmed in standard EPROM programmers.
The IS25CD512/010 and IS25LD020 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output
(SlO), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. They comply with all recognized command
codes and operations. The dual-output fast read operation provides and effective serial data rate of 200MHz.
The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in one program
operation. These devices are divided into uniform 4 KByte sectors or uniform 32 KByte blocks.(IS25LD020 is uniform 4
KByte sectors or uniform 64 KByte).
The IS25CD512/010 and IS25LD020 are manufactured on pFLASH™’s advanced non-volatile technology. The devices are
offered in a variety of packages for all critical needs. The devices operate at wide temperatures between -40°C to +105°C.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
1
08/12/2013
IS25CD512/010 & IS25LD020
CONNECTION DIAGRAMS
CE#
SO
1
2
8
7
Vcc
8 Vcc
CE#
SO
1
2
7
HOLD#
6 SCK
SIO
HOLD#
3
4
WP#
GND
WP#
GND
3
4
6
5
SCK
SIO
5
8-pin WSON
8-Pin SOIC/VVSOP
CE#
Vcc
1
2
3
4
8
7
6
5
Vcc
CE#
SO
HOLD#
HOLD#
SCK
SO
WP#
GND
WP#
GND
SCK
SIO
8-Pin TSSOP
SIO
8-Pin USON
PIN DESCRIPTIONS
SYMBOL TYPE
DESCRIPTION
Chip Enable: CE# low activates the devices internal circuitries for
CE#
INPUT
device operation. CE# high deselects the devices and switches into
standby mode to reduce the power consumption. When a device is not
selected, data will not be accepted via the serial input pin (SlO), and the
serial output pin (SO) will remain in a high impedance state.
Serial Data Clock
SCK
SIO
SO
INPUT
INPUT/OUTPUT Serial Data Input/Output
OUTPUT
Serial Data Output
GND
Vcc
Ground
Device Power Supply
WP#
INPUT
Write Protect: A hardware program/erase protection for all or part of a
memory array. When the WP# pin is low, memory array write-protection depends on the
setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is high, the devices
are not write-protected.
HOLD#
INPUT
Hold: Pause serial communication by the master device without resetting
the serial sequence.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
2
08/12/2013
IS25CD512/010 & IS25LD020
BLOCK DIAGRAM
SIO
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
3
08/12/2013
IS25CD512/010 & IS25LD020
SPI MODES DESCRIPTION
Multiple IS25CD512/010 and IS25LD020 devices can be
connected on the SPI serial bus and controlled by a SPI
Master, i.e. microcontroller, as shown in Figure 1. The
devices support either of two SPI modes:
Mode 0 (0, 0)
The difference between these two modes is the clock polarity
when the SPI master is in Stand-by mode: the serial clock
remains at “0” (SCK = 0) for Mode 0 and the clock remains at
“1” (SCK = 1) for Mode 3. Please refer to Figure 2. For both
modes, the input data is latched on the rising edge of Serial
Clock (SCK), and the output data is available from the falling
edge of SCK.
Mode 3 (1, 1)
Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SDIO
SPI Interface with
(0,0) or (1,1)
SDI
SCK
SCK
CE#
SO SIO
SCK
SO
SCK
CE#
SIO
SO SIO
SPI Master
(i.e. Microcontroller)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3
CS2
CS1
WP#
CE# WP#
WP#
HOLD#
HOLD#
HOLD#
Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as
Figure 2. SPI Modes Supported
SCK
Mode 0 (0, 0)
SCK
Mode 3 (1, 1)
SIO
Input mode
MSb
SO
MSb
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
4
08/12/2013
IS25CD512/010 & IS25LD020
SYSTEM CONFIGURATION
The IS25CD512/010 and IS25LD020 devices are designed to interface directly with the synchronous Serial Peripheral
Interface (SPI) of the Motorola MC68HCxx series of microcontrollers or any SPI interface-equipped system controllers. The
devices have two superset features that can be enabled through specific software instructions and the Configuration
Register:
Block Size
(Kbytes)
Sector Size
(Kbytes)
Memory Density
Block No.
Sector No.
Address Range
Sector 0(1)
000000h - 000FFFh
001000h - 001FFFh
:
4
4
:
Sector 1
Block 0
32
32
:
Sector 7
007000h - 007FFFh
008000h - 008FFFh
009000h - 009FFFh
000000h - 006FFFh
00F000h - 00FFFFh
010000h - 017FFFh
018000h - 01FFFFh
4
4
4
:
512 Kbit
1 Mbit
Sector 8
Sector 9
Block 1
:
Sector 15
4
"
"
Block 2
Block 3
32
32
"
"
Block
Size
Sector
Size
Memory Density
Block No.
Sector No.
Address Range
(KBytes)
(KBytes)
Sector 0
4
4
:
000000h - 000FFFh
001000h - 001FFFh
:
Sector 1
Block 0
64
64
:
Sector 15
4
4
4
:
00F000h - 00FFFFh
010000h - 010FFFh
011000h - 011FFFh
:
Sector 16
2 Mbit
Sector 17
Block 1
:
Sector 31
4
:
01F000h - 01FFFFh
:
:
:
:
:
Block 3
64
4
030000h – 03FFFFh
Table 1-1. Block/Sector Addresses of IS25CD512/010 and IS25LD020
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
5
08/12/2013
IS25CD512/010 & IS25LD020
REGISTERS (CONTINUED)
STATUS REGISTER
Refer to Tables 5 and 6 for Status Register Format and
Status Register Bit Definitions.
a Write Enable (WREN) instruction. Each write register,
program and erase instruction must be preceded by a WREN
instruction. The WEL bit can be reset by a Write Disable
(WRDI) instruction. It will automatically be the reset after the
completion of a write instruction.
The BP0, BP1, BP2, and SRWD are volatile memory cells
that can be written by a Write Status Register (WRSR)
instruction. The default value of the BP2, BP1, BP0 were set
to “0” and SRWD bits was set to “0” at factory. Once a “0” or BP2, BP1, BP0 bits: The Block Protection (BP2, BP1, BP0)
“1”is written, it will not be changed by device power-up or
power-down, and can only be altered by the next WRSR
instruction. The Status Register can be read by the Read
Status Register (RDSR). Refer to Table 10 for Instruction
Set.
bits are used to define the portion of the memory area to be
protected. Refer to Tables 7, 8 and 9 for the Block Write
Protection bit settings. When a defined combination of BP2,
BP1 and BP0 bits are set, the corresponding memory area is
protected. Any program or erase operation to that area will
be inhibited. Note: a Chip Erase (CHIP_ER) instruction is
The function of Status Register bits are described as follows: executed successfully only if all the Block Protection Bits are
set as “0”s.
WIP bit: The Write In Progress (WIP) bit is read-only, and
can be used to detect the progress or completion of a
program or erase operation. When the WIP bit is “0”, the
device is ready for a write status register, program or erase
operation. When the WIP bit is “1”, the device is busy.
SRWD bit: The Status Register Write Disable (SRWD) bit
operates in conjunction with the Write Protection (WP#)
signal to provide a Hardware Protection Mode. When the
SRWD is set to “0”, the Status Register is not write-protected.
When the SRWD is set to “1” and the WP# is pulled low
(VIL), the volatile bits of Status Register (SRWD, BP2, BP1,
WEL bit: The Write Enable Latch (WEL) bit indicates the
status of the internal write enable latch. When the WEL is “0”, BP0) become read-only, and a WRSR instruction will be
the write enable latch is disabled, and all write operations,
including write status register, page program, sector erase,
ignored. If the SRWD is set to “1” and WP# is pulled high
(VIH), the Status Register can be changed by a WRSR
block and chip erase operations are inhibited. When the WEL instruction.
bit is “1”, write operations are allowed. The WEL bit is set by
Table 5. Status Register Format
Bit 7
SRWD1
0
Bit 6
Bit 5
Bit 4
BP2
0
Bit 3
BP1
0
Bit 2
BP0
0
Bit 1
WEL
0
Bit 0
WIP
0
Reserved
Default (flash bit)
0
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
6
08/12/2013
IS25CD512/010 & IS25LD020
REGISTERS (CONTINUED)
Table 6. Status Register Bit Definition
Read- Non-Volatile
Bit
Name
Definition
/Write
bit
Write In Progress Bit:
Bit 0
WIP
"0" indicates the device is ready
R
No
"1" indicates a write cycle is in progress and the device is busy
Write Enable Latch:
Bit 1
WEL
"0" indicates the device is not write enabled
"1" indicates the device is write enabled (default)
Block Protection Bit: (See Table 7 and Table 8 for details)
"0" indicates the specific blocks are not write-protected (default)
"1" indicates the specific blocks are write-protected
Reserved: Always "0"s
R/W
No
Bit 2
Bit 3
Bit 4
BP0
BP1
BP2
N/A
R/W
N/A
Yes
Bits 5 - 6
Status Register Write Disable: (See Table 9 for details)
Bit 7
SRWD "0" indicates the Status Register is not write-protected (default)
"1" indicates the Status Register is write-protected
R/W
Yes
Table 8. Block Write Protect Bits for IS25CD512/010 and IS25LD020
Status Register Bits Protected Memory Area
BP1
0
BP0
0
IS25CD512
None
IS25CD010
IS25LD020
None
None
0
1
None
Upper quarter (Block 3)
01800h-01FFFFh
Upper quarter (Block 3)
03000h-03FFFFh
1
1
0
1
None
Upper half (Block 2 & 3)
010000h-01FFFFh
Upper half (Block 2 & 3)
020000h-03FFFFh
All Blocks
All Blocks
All Blocks
000000h-00FFFFh
000000h-01FFFFh
000000h-03FFFFh
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
7
08/12/2013
IS25CD512/010 & IS25LD020
REGISTERS (CONTINUED)
PROTECTION MODE
The IS25CD512/010 and IS25LD020 have two types of write- Table 9. Hardware Write Protection on Status
protection mechanisms: hardware and software. These are Register
used to prevent irrelevant operation in a possibly noisy
environment and protect the data integrity.
SRWD
WP#
Low
Low
High
High
Status Register
Writable
0
1
0
1
HARDWARE WRITE-PROTECTION
Protected
Writable
The devices provide two hardware write-protection
features:
Writable
a. When inputting a program, erase or write status register
instruction, the number of clock pulse is checked to
determine whether it is a multiple of eight before the
executing. Any incomplete instruction command sequence
will be ignored.
b. The Write Protection (WP#) pin provides a hardware write
protection method for BP2, BP1, BP0 and SRWD in the
Status Register. Refer to the STATUS REGISTER
description.
c. All write sequences will be ignored when Vcc drop to VWI
(see p.26)
SOFTWARE WRITE PROTECTION
The IS25CD512/010 and IS25LD020 also provides two
software write protection features:
a. Before the execution of any program, erase or write status
register instruction, the Write Enable Latch (WEL) bit must be
enabled by executing a Write Enable (WREN) instruction. If
the WEL bit is not enabled first, the program, erase or write
register instruction will be ignored.
b. The Block Protection (BP2, BP1, BP0) bits allow part or
the whole memory area to be write-protected.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
8
08/12/2013
IS25CD512/010 & IS25LD020
DEVICE OPERATION
The IS25CD512/010 and IS25LD020 utilize an 8-bit
instruction register. Refer to Table 10 Instruction Set for
details of the Instructions and Instruction Codes. All
followed by address bytes, data bytes, or both address bytes
and data bytes, depending on the type of instruction. CE#
must be driven high (VIH) after the last bit of the instruction
instructions, addresses, and data are shifted in with the most sequence has been shifted in.
significant bit (MSB) first on Serial Data Input (SI). The input
data on SI is latched on the rising edge of Serial Clock (SCK) The timing for each instruction is illustrated in the following
after Chip Enable (CE#) is driven low (VIL). Every instruction operational descriptions.
sequence starts with a one-byte instruction code and is
Table 10. Instruction Set
Instruction Name
Hex Code Operation
Command Maximum
Cycle
4 Bytes
1 Byte
Frequency
100 MHz
100 MHz
RDID
JEDEC ID READ
ABh
9Fh
Read Manufacturer and Product ID
Read Manufacturer and Product ID by JEDEC ID
Command
RDMDID
WREN
WRDI
RDSR
WRSR
READ
FAST_READ
FRDO
90h
06h
04h
05h
01h
03h
0Bh
3Bh
02h
Read Manufacturer and Device ID
Write Enable
Write Disable
Read Status Register
Write Status Register
Read Data Bytes from Memory at Normal Read Mode
Read Data Bytes from Memory at Fast Read Mode
Fast Read Dual Output
4 Bytes
1 Byte
1 Byte
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
33 MHz
100 MHz
100 MHz
100 MHz
1 Byte
2 Bytes
4 Bytes
5 Bytes
5 Bytes
4 Bytes +
256B
PAGE_ PROG
Page Program Data Bytes Into Memory
SECTOR_ER
BLOCK_ER
CHIP_ER
D7h/20h
D8h
C7h/60h
Sector Erase
Block Erase
Chip Erase
4 Bytes
4 Bytes
1 Byte
100 MHz
100 MHz
100 MHz
HOLD OPERATION
HOLD# is used in conjunction with CE# to select the
IS25CD512/010 and IS25LD020. When the devices are
selected and a serial sequence is underway, HOLD# can
be used to pause the serial communication with the
master device without resetting the serial sequence. To
pause, HOLD# is brought low while the SCK signal is low.
To resume serial communication, HOLD# is brought high
while the SCK signal is low (SCK may still toggle during
HOLD). Inputs to SlO will be ignored while SO is in the
high impedance state.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
9
08/12/2013
IS25CD512/010 & IS25LD020
DEVICE OPERATION (CONTINUED)
RDID COMMAND (READ PRODUCT IDENTIFICATION)
OPERATION
The Read Product Identification (RDID) instruction is for
reading out the old style of 8-bit Electronic Signature, whose Table 11. Product Identification
values are shown as table of ID Definitions. This is not same
as RDID or JEDEC ID instruction. It’s not recommended to
use for new design. For new design, please use RDID or
JEDEC ID instruction.
Product Identification
Data
First Byte
9Dh
7Fh
Manufacturer ID
The RDES instruction code is followed by three dummy
bytes, each bit being latched-in on SI during the rising
edge of SCK. Then the Device ID is shifted out on SO
with the MSB first, each bit been shifted out during the
falling edge of SCK. The RDES instruction is ended by
CE# goes high. The Device ID outputs repeatedly if
continuously send the additional clock cycles on SCK while
CE# is at low.
Second Byte
Device ID 1
05h
Device ID:
IS25CD512
IS25CD010
IS25LD020
Device ID 2
20h
10h
21h
11h
22h
Figure 3. Read Product Identification Sequence
CE#
7
9
46
0
1
8
38 39
47
54
31
SCK
SI
INSTRUCTION
1010 1011b
3 Dummy Bytes
HIGH IMPEDANCE
SO
Device ID1
Device ID1
Device ID1
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
10
08/12/2013
IS25CD512/010 & IS25LD020
DEVICE OPERATION (CONTINUED)
JEDEC ID READ COMMAND (READ PRODUCT IDENTIFICATION BY JEDEC ID)
OPERATION
The JEDEC ID READ instruction allows the user to read the
manufacturer and product ID of devices. Refer to Table 11
followed by the first Manufacturer ID (9Dh) and the Device ID
(22h, in the case of the IS25LD020), each bit shifted out
Product Identification for pFlash Manufacturer ID and Device during the falling edge of SCK. If CE# stays low after the last
ID. After the JEDEC ID READ command is input, the second bit of the Device ID is shifted out, the Manufacturer ID and
Manufacturer ID (7Fh) is shifted out on SO with the MSB first, Device ID will loop until CE# is pulled high.
Figure 4. Read Product Identification by JEDEC ID READ Sequence
CE#
0
7
8
15 16
23 24
31
SCK
SI
INSTRUCTION
1001 1111b
HIGH IMPEDANCE
SO
Manufacture ID2
Manufacture ID1
Device ID2
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
11
08/12/2013
IS25CD512/010 & IS25LD020
DEVICE OPERATION (CONTINUED)
RDMDID COMMAND (READ DEVICE MANUFACTURER AND DEVICE ID)
OPERATION
The RDMDID instruction allows the user to read the
manufacturer and product ID of devices. Refer to Table 11
the IS25LD020), and is shifted out on SO with the MSB first,
each bit shifted out during the falling edge of SCK. If CE#
Product Identification for pFlash Manufacturer ID and Device stays low after the last bit of the Device ID is shifted out, the
ID. The RDMDID command is input, followed by a 24-bit
address pointing to an ID table. The table contains the first
Manufacturer ID (9Dh) and the Device ID (22h, in the case of
Manufacturer ID and Device ID will loop until CE# is pulled
high.
Figure 5. Read Product Identification by RDMDID READ Sequence
CE#
9
0
2
3
4
5
8
31
A0
1
6
7
10 11 28
29 30
SCK
SIO
...
3 - BYTE ADDRESS
2
1
INSTRUCTION = 1001 0000b
HIGH IMPEDANCE
23
3
...
22
21
SO
CE#
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
32
SCK
SIO
Manufacturer ID1
Device ID1
5
SO
0
2
1
6
7
3
3
4
4
7
6
5
2
1
0
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
12
08/12/2013
IS25CD512/010 & IS25LD020
CE#
48
50 51 52 53
56
49
54 55
SCK
SIO
Manufacturer ID2
SO
3
4
7
6
5
2
1
0
Note :
(1) ADDRESS A0 = 0, will output the 1st manufacture ID (9Dh) first -> device ID1 -> 2nd manufacture ID (7Fh)
ADDRESS A0 = 1, will output the device ID1 -> 1st manufacture ID (9D) -> 2nd manufacture ID (7Fh)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
13
08/12/2013
IS25CD512/010 & IS25LD020
DEVICE OPERATION (CONTINUED)
WRITE ENABLE OPERATION
The Write Enable (WREN) instruction is used to set the Write erase, chip erase, page program and write status register
Enable Latch (WEL) bit. The WEL bit of the
operations. The WEL bit will be reset to the write-protect
state automatically upon completion of a write operation. The
WREN instruction is required before any above operation is
executed.
IS25CD512/010 and IS25LD020 is reset to the write –
protected state after power-up. The WEL bit must be write
enabled before any write operation, including sector, block
Figure 6. Write Enable Sequence
SIO
WRDI COMMAND (WRITE DISABLE) OPERATION
The Write Disable (WRDI) instruction resets the WEL bit and required after the execution of a write instruction, since the
disables all write instructions. The WRDI instruction is not
WEL bit is automatically reset.
Figure 7. Write Disable Sequence
SIO
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Rev. C
14
08/12/2013
IS25CD512/010 & IS25LD020
DEVICE OPERATION (CONTINUED)
RDSR COMMAND (READ STATUS REGISTER) OPERATION
The Read Status Register (RDSR) instruction provides
access to the Status Register. During the execution of a
program, erase or write status register operation, all other
instructions will be ignored except the RDSR instruction,
which can be used to check the progress or completion of an
operation by reading the WIP bit of Status Register.
Figure 8. Read Status Register Sequence
SIO
WRSR COMMAND (WRITE STATUS REGISTER) OPERATION
The Write Status Register (WRSR) instruction allows
the user to enable or disable the block protection and status
register write protection features by writing “0”s or “1” s into
the volatile BP2, BP1, BP0 and SRWD bits.
Figure 9. Write Status Register Sequence
SIO
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
15
08/12/2013
IS25CD512/010 & IS25LD020
DEVICE OPERATION (CONTINUED)
READ COMMAND (READ DATA) OPERATION
The Read Data (READ) instruction is used to read memory
data of a IS25CD512/010 and IS25LD020 under normal
mode running up to 33 MHz.
The first byte data (D7 - D0) addressed is then shifted out on
the SO line, MSb first. A single byte of data, or up to the
whole memory array, can be read out in one READ
The READ instruction code is transmitted via the SlO line,
followed by three address bytes (A23 - A0) of the first
memory location to be read. A total of 24 address bits are
shifted in, but only AMS (most significant address) - A0 are
decoded. The remaining bits (A23 – AMS) are ignored. The
first byte addressed can be at any memory location. Upon
instruction. The address is automatically incremented after
each byte of data is shifted out. The read operation can be
terminated at any time by driving CE# high (VIH) after the
data comes out. When the highest address of the devices is
reached, the address counter will roll over to the 000000h
address, allowing the entire memory to be read in one
completion, any data on the Sl will be ignored. Refer to Table continuous READ instruction.
12 for the related Address Key.
Table 12. Address Key
Address
AN (AMS – A0)
Don't Care Bits
IS25LD020
A17 - A0
IS25CD010
A16 - A0
IS25CD512
A15 - A0
A23 – A18
A23 – A17
A23 – A16
Figure 12. Read Data Sequence
SIO
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Rev. C
16
08/12/2013
IS25CD512/010 & IS25LD020
DEVICE OPERATION (CONTINUED)
FAST_READ COMMAND (FAST READ DATA) OPERATION
The FAST_READ instruction is used to read memory data at
up to a 100 MHz clock.
The first byte addressed can be at any memory location. The
address is automatically incremented after each byte of data
is shifted out. When the highest address is reached, the
address counter will roll over to the 000000h address,
The FAST_READ instruction code is followed by three
address bytes (A23 - A0) and a dummy byte (8 clocks),
transmitted via the SI line, with each bit latched-in during the allowing the entire memory to be read with a single
rising edge of SCK. Then the first data byte addressed is
shifted out on the SO line, with each bit shifted out at a
maximum frequency fCT, during the falling edge of SCK.
FAST_READ instruction. The FAST_READ instruction is
terminated by driving CE# high (VIH).
Figure 13. Fast Read Data Sequence
SIO
SIO
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DEVICE OPERATION (CONTINUED)
FRDO COMMAND (FAST READ DUAL OUTPUT) OPERATION
The FRDO instruction is used to read memory data on two
output pins each at up to a 100 MHz clock.
The first bit (MSb) is output on SO, while simultaneously the
second bit is output on SIO.
The FRDO instruction code is followed by three address
bytes (A23 - A0) and a dummy byte (8 clocks), transmitted
The first byte addressed can be at any memory location. The
address is automatically incremented after each byte of data
via the SI line, with each bit latched-in during the rising edge is shifted out. When the highest address is reached, the
of SCK. Then the first data byte addressed is shifted out on
the SO and SIO lines, with each pair of bits shifted out at a
maximum frequency fCT, during the falling edge of SCK.
address counter will roll over to the 000000h address,
allowing the entire memory to be read with a single FRDO
instruction. FRDO instruction is terminated by driving CE#
high (VIH).
Figure 14. Fast Read Dual-Output Sequence
CE#
9
0
2
3
4
5
8
31
1
6
7
10 11 28
29 30
SCK
SIO
...
3 - BYTE ADDRESS
2
1
INSTRUCTION = 0011 1011b
HIGH IMPEDANCE
23
3
0
...
22
21
SO
CE#
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
32
SCK
SIO
2
2
0
1
6
7
6
6
7
4
4
0
1
DATA OUT 1
DATA OUT 2
HIGH IMPEDANCE
SO
5
3
5
3
7
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DEVICE OPERATION (CONTINUED)
PAGE_PROG COMMAND (PAGE PROGRAM) OPERATION
The Page Program (PAGE_PROG) instruction allows up to
256 bytes data to be programmed into memory in a single
Register via a RDSR instruction. If the WIP bit is “1”, the
program operation is still in progress. If WIP bit is “0”, the
operation. The destination of the memory to be programmed program operation has completed.
must be outside the protected memory area set by the Block
Protection (BP2, BP1, BP0) bits. A PAGE_PROG instruction If more than 256 bytes data are sent to a device, the address
which attempts to program into a page that is write-protected counter rolls over within the same page, the previously
will be ignored. Before the execution of PAGE_PROG
instruction, the Write Enable Latch (WEL) must be enabled
through a Write Enable (WREN) instruction.
latched data are discarded, and the last 256 bytes data are
kept to be programmed into the page. The starting byte can
be anywhere within the page. When the end of the page is
reached, the address will wrap around to the beginning of the
The PAGE_PROG instruction code, three address bytes and same page. If the data to be programmed are less than a full
program data (1 to 256 bytes) are input via the SlO line.
Program operation will start immediately after the CE# is
brought high, otherwise the PAGE_PROG instruction will not
page, the data of all other bytes on the same page will
remain unchanged.
be executed. The internal control logic automatically handles Note: A program operation can alter “1”s into “0”s, but an
the programming voltages and timing. During a program
operation, all instructions will be ignored except the RDSR
instruction. The progress or completion of the program
operation can be determined by reading the WIP bit in Status
erase operation is required to change “0”s back to “1”s. A
byte cannot be reprogrammed without first erasing the whole
sector or block.
Figure 15. Page Program Sequence
SIO
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DEVICE OPERATION (CONTINUED)
ERASE OPERATION
progress or completion of the erase operation can be
determined by reading the WIP bit in the Status Register
using a RDSR instruction. If the WIP bit is “1”, the erase
The memory array of the IS25CD512/010 is organized into
uniform 4 KByte sectors or 32 KByte uniform blocks (a block operation is still in progress. If the WIP bit is “0”, the erase
consists of eight adjacent sectors). IS25LD020 is organized
into uniform 4 KByte sectors or 64 KByte uniform blocks (a
block consists of sixteen adjacent sectors)
operation has been completed.
BLOCK_ER COMMAND (BLOCK ERASE) OPERATION
Before a byte can be reprogrammed, the sector or block that A Block Erase (BLOCK_ER) instruction erases a 64 KByte
contains the byte must be erased (erasing sets bits to “1”). In block of the IS25LD020, and 32 KByte block of the
order to erase the devices, there are three erase instructions IS25CD512C/010C. Before the execution of a BLOCK_ER
available: Sector Erase (SECTOR_ER), Block Erase
(BLOCK_ER) and Chip Erase (CHIP_ER). A sector erase
operation allows any individual sector to be erased without
affecting the data in other sectors. A block erase operation
erases any individual block. A chip erase operation erases
the whole memory array of a device. A sector erase, block
erase or chip erase operation can be executed prior to any
programming operation.
instruction, the Write Enable Latch (WEL) must be set via a
Write Enable (WREN) instruction. The WEL is reset
automatically after the completion of a block erase operation.
The BLOCK_ER instruction code and three address bytes
are input via SI. Erase operation will start immediately after
the CE# is pulled high, otherwise the BLOCK_ER instruction
will not be executed. The internal control logic automatically
handles the erase voltage and timing. Refer to Figure 15 for
SECTOR_ER COMMAND (SECTOR ERASE) OPERATION Block Erase Sequence.
A SECTOR_ER instruction erases a 4 KByte sector Before
the execution of a SECTOR_ER instruction, the Write Enable
Latch (WEL) must be set via a Write Enable (WREN)
instruction. The WEL bit is reset automatically after the
completion of sector an erase operation.
CHIP_ER COMMAND (CHIP ERASE) OPERATION
A Chip Erase (CHIP_ER) instruction erases the entire
memory array of a IS25CD512/010 and IS25LD020. Before
the execution of CHIP_ER instruction, the Write Enable Latch
(WEL) must be set via a Write Enable (WREN) instruction.
A SECTOR_ER instruction is entered, after CE# is pulled low The WEL is reset automatically after completion of a chip
to select the device and stays low during the entire
instruction sequence The SECTOR_ER instruction code, and
three address bytes are input via SI. Erase operation will
start immediately after CE# is pulled high. The internal
control logic automatically handles the erase voltage and
timing. Refer to Figure 14 for Sector Erase Sequence.
erase operation.
The CHIP_ER instruction code is input via the SI. Erase
operation will start immediately after CE# is pulled high,
otherwise the CHIP_ER instruction will not be executed. The
internal control logic automatically handles the erase voltage
and timing. Refer to Figure 16 for Chip Erase Sequence.
During an erase operation, all instruction will be ignored
except the Read Status Register (RDSR) instruction. The
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DEVICE OPERATION (CONTINUED)
Figure 16. Sector Erase Sequence
SIO
Figure 17. Block Erase Sequence
SIO
Figure 18. Chip Erase Sequence
SIO
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ABSOLUTE MAXIMUM RATINGS (1)
Temperature Under Bias
Storage Temperature
-65oC to +125oC
-65oC to +125oC
Standard Package 240oC 3 Seconds
Surface Mount Lead Soldering Temperature
Lead-free Package 260oC 3 Seconds
Input Voltage with Respect to Ground on All Pins (2)
-0.5 V to VCC + 0.5 V
-0.5 V to VCC + 0.5 V
-0.5 V to +6.0 V
All Output Voltage with Respect to Ground
VCC (2)
Notes:
1. Applied conditions greater than those listed in “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only. The functional operation of the device conditions that exceed those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affect
device reliability.
2. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot VCC
by + 2.0 V for a period of time not to exceed 20 ns. Minimum DC voltage on input or I/O pins is
-0.5 V. During voltage transitions, input or I/O pins may undershoot GND by -2.0 V for a period of time not to exceed 20 ns.
DC AND AC OPERATING RANGE
Part Number
IS25CD512/010
IS25LD020
Operating Temperature (Extended Grade)
Operating Temperature (Automotive, A1 Grade)
Operating Temperature (Automotive, A2 Grade)
Vcc Power Supply
-40oC to 105oC
-40oC to 85oC
-40oC to 105oC
2.70 V – 3.60 V
DC CHARACTERISTICS
Applicable over recommended operating range from:
VCC = 2.70 V to 3.60 V (unless otherwise noted).
Symbol
Parameter
Condition
Min
Typ
Max
Units
VCC = 3.60V at 33 MHz, SO =
Open
ICC1
Vcc Active Read Current
10
15
mA
VCC = 3.60V at 33 MHz, SO =
Open
ICC2
Vcc Program/Erase Current
15
30
mA
ISB1
ISB2
ILI
Vcc Standby Current CMOS
Vcc Standby Current TTL
Input Leakage Current
Output Leakage Current
Input Low Voltage
VCC = 3.60V, CE# = VCC
VCC = 3.60V, CE# = VIH to VCC
VIN = 0V to VCC
10
µA
mA
µA
µA
V
3
1
1
ILO
VIN = 0V to VCC, TAC = 0oC to 85oC
VIL
-0.5
0.8
VIH
VOL
VOH
Input HIgh Voltage
0.7VCC
VCC + 0.3
0.45
V
Output Low Voltage
IOL = 2.1 mA
IOH = -100 µA
V
2.30V < VCC
3.60V
<
Output High Voltage
VCC - 0.2
V
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AC CHARACTERISTICS
Applicable over recommended operating range from, VCC = 2.70 V to 3.60 V
CL = 1 TTL Gate and 10 pF (unless otherwise noted).
Symbol
fCT
fC
Parameter
Min
0
Typ
Max
100
33
8
Units
MHz
MHz
ns
Clock Frequency for fast read mode
Clock Frequency for read mode
Input Rise Time
0
tRI
tFI
Input Fall Time
8
ns
tCKH
tCKL
tCEH
tCS
tCH
tDS
tDH
tHS
tHD
tV
SCK High Time
4
4
ns
SCK Low Time
ns
CE# High Time
25
10
5
ns
CE# Setup Time
ns
CE# Hold Time
ns
Data In Setup Time
Data in Hold Time
2
ns
2
ns
Hold Setup Time
15
15
ns
Hold Time
ns
Output Valid
8
ns
tOH
tLZ
Output Hold Time Normal Mode
Hold to Output Low Z
Hold to Output High Z
Output Disable Time
Sector/Block/Chip Erase Time
Page Program Time
VCC Set-up Time
0
ns
200
200
100
10
ns
tHZ
tDIS
tEC
tPP
tVCS
tw
ns
ns
ms
ms
µs
2
5
50
Write Status Register time (flash bit)
10
ms
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AC CHARACTERISTICS (CONTINUED)
SERIAL INPUT/OUTPUT TIMING (1)
SIO
Note: 1. For SPI Mode 0 (0,0)
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AC CHARACTERISTICS (CONTINUED)
HOLD TIMING
PIN CAPACITANCE (f = 1 MHz, T = 25°C )
Typ
Max
6
Units
Conditions
VIN = 0 V
CIN
4
8
pF
pF
COUT
12
VOUT = 0 V
Note: These parameters are characterized but not 100% tested.
OUTPUT TEST LOAD
INPUT TEST WAVEFORMS
AND MEASUREMENT LEVEL
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POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must not be
selected (CE# must follow the voltage applied on Vcc)
until Vcc reaches the correct value:
is not guaranteed if, by this time, Vcc is still below Vcc(min).
No Write Status Register, Program or Erase instructions
should be sent until the later of:
- Vcc(min) at Power-up, and then for a further delay of
tVCE
- tPUW after Vcc passed the VWI threshold
- tVCE after Vcc passed the Vcc(min) level
- Vss at Power-down
Usually a simple pull-up resistor on CE# can be used to
insure safe and proper Power-up and Power-down.
To avoid data corruption and inadvertent write operations
during power up, a Power On Reset (POR) circuit is included.
At Power-up, the device is in the following state:
- The device is in the Standby mode
- The Write Enable Latch (WEL) bit is reset
The logic inside the device is held reset while Vcc is less than At Power-down, when Vcc drops from the operating
the POR threshold value (Vwi) during power up, the device
does not respond to any instruction until a time delay of
voltage, to below the Vwi, all write operations are disabled
and the device does not respond to any write
tPUW has elapsed after the moment that Vcc rised above the instruction.
VWI threshold. However, the correct operation of the device
Vcc
Vcc(max)
All Write Commands are Rejected
Chip Selection Not Allowed
Vcc(min)
Reset State
tVCE
Read Access Allowed
Device fully accessible
V (write inhibit)
tPUW
Time
Symbol Parameter
Min.
Max.
Unit
µs
*1
tVCE
Vcc(min) to CE# Low
10
*1
tPUW
Power-Up time delay to Write instruction
IS25CD512/010
1
1.6
1.9
10
2.1
2.4
ms
*1
VWI
V
IS25LD020
Note:
*1. These parameters are characterized only.
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PROGRAM/ERASE PERFORMANCE
Parameter
Unit Typ Max Remarks
Sector Erase Time
Block Erase Time
Chip Erase Time
ms
ms
ms
10
10
10
5
From writing erase command to erase completion
From writing erase command to erase completion
From writing erase command to erase completion
From writing program command to program completion
Page Programming Time ms
2
Note: These parameters are characterized and are not 100% tested.
RELIABILITY CHARACTERISTICS
Parameter
Min
200,000
20
Unit
Cycles
Years
Volts
Volts
mA
Test Method
Endurance
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard A114
JEDEC Standard A115
JEDEC Standard 78
Data Retention
ESD – Human Body Model
ESD – Machine Model
Latch-Up
2,000
200
100 + ICC1
Note: These parameters are characterized and are not 100% tested.
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PACKAGE TYPE INFORMATION
JN
8-Pin SOIC 150mil Broad Small Outline Integrated Circuit Package (Unit: millimeters)
Note: Package dimensions are shown in mm.
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PACKAGE TYPE INFORMATION (CONTINUED)
JD
8-pin TSSOP Package (Unit: millimeters)
0.127
Pin1
Detail A
2.9
3.1
Detail A
GAGE PLANE
0.65
0.05
0.15
0.25
0.30
00
0.5
0.7
80
Note: Package dimensions are shown in mm.
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PACKAGE TYPE INFORMATION (CONTINUED)
JK
8-pin Ultra-Thin Small Outline No-Lead (WSON) Package (Unit: millimeters)
Note: Package dimensions are shown in mm.
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PACKAGE TYPE INFORMATION (CONTINUED)
JV
8-pin VVSOP Package 150mil (Unit: millimeters)
Note: Package dimensions are shown in mm.
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PACKAGE TYPE INFORMATION (CONTINUED)
JU
8-pin USON Package (Unit: millimeters)
Note: Package dimensions are shown in mm.
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Appendix1: Safe Guard function
Safe Guard function is a security function for customer to protect by sector (4Kbyte).
Every sector has one bit register to decide it will under safe guard protect or not. (“0”means protect and “1” means not
protect by safe guard.) IS25CD512 (sector 0~sector 15), IS25CD010 (sector 0~sector 31) and IS25LD020 (sector 0~sector
63)
*safe guard function priority is higher than status register (BP0/1/2)
Mapping table for safe guard register
Address[9:0]
000h
000h
000h
000h
000h
000h
000h
000h
001h
001h
001h
001h
001h
001h
001h
001h
D7
D6
D5
D4
D3
D2
D1
D0
Sector0
Sector1
Sector2
Sector3
Sector4
Sector5
Sector6
Sector7
Sector8
Sector9
Sector10
Sector11
Sector12
Sector13
Sector14
Sector15
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
Sector56
Sector57
Sector58
Sector59
Sector60
Sector61
Sector62
Sector63
007h
007h
007h
007h
007h
007h
007h
007h
008h
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
1
0
1
1
1
1
1
0
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
0
1
1
0
1
1
1
1
1
0
1
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
Chip Erase disable*
Note:1. Please set the Chip Erase disable to "0" after finished the register setting.
2. Please set the address 009h to "00" after finished the register setting.
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Read Safe Guard register
The READ Safe Guard instruction code is transmitted via the SlO line, followed by three address bytes (A23 - A0) of the first
register location to be read. The first byte data (D7 - D0) addressed is then shifted out on the SO line, MSb first. The address
is automatically incremented after each byte of data is shifted out. The read operation can be terminated at any time by
driving CE# high (VIH) after the data comes out.
CS
1
2
7
8
9
10
23 24 25 26
31 32 33 34
39 40 41 42
47 48
SCK
SI
2Fh
A23-A0
2nd byte
1st byte
SO
D7-D0
D7-D0
Fig a. Timing waveform of Read Safe guard register
Erase Safe Guard register
If we want to erase the safe guard register to let the flash into unprotect status, it needs five continuous instructions. If any
instruction is wrong, the erase command will be ignored. Erase wait time follow product erase timing spec.
Fig b. shows the complete steps for Erase safe guard register.
Program Safe Guard register
If we want to erase the safe guard register to let the flash into unprotect status, it needs five continuous instructions. If any
instruction is wrong, the program command will be ignored. The Program safe guard instruction allows up to 256 bytes data
to be programmed into memory in a single operation. Program wait time follow product program timing spec.
Fig c. shows the complete steps for program safe guard register.
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Sector Protection Mode Erase
CS
1
2
7
8
9 10
31 32
SCK
SI
55h
A23-A0
CS
1
2
7 8
9 10
31 32
SCK
SI
AAh
A23-A0
CS
1
2
7 8
9 10
31 32
SCK
SI
80h
A23-A0
CS
1
2
7
8
9 10
31 32
SCK
SI
AAh
A23-A0
CS
1
2
7 8
SCK
SI
2Bh
Fig b. Erase safe guard register
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CS
1
2
7
8
9 10
31 32
SCK
SI
55h
A23-A0
CS
1
2
7 8
9 10
31 32
SCK
SI
AAh
A23-A0
CS
1
2
7 8
9 10
31 32
SCK
SI
A0h
A23-A0
CS
1
2
7
8
9 10
31 32
SCK
SI
55h
A23-A0
CS
1
2
7
8
9
10
31 32 33 34
39 40 41 42
47 48
SCK
SI
1st byte
2nd byte
23h
A23-A0
D7-D0
D7-D0
Fig c. program safe guard register
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Appendix2: Sector Unlock function
Instruction Name
Hex
Code
26h
Operation
Command
Cycle
4 Bytes
1 Byte
Maximum
Frequency
100 MHz
100 MHz
SECT_UNLOCK
SECT_LOCK
Sector unlock
Sector lock
24h
SEC_UNLOCK COMMAND OPERATION
The Sector unlock command allows the user to select a
specific sector to allow program and erase operations.
This instruction is effective when the blocks are
designated as write-protected through the BP0, BP1 and
BP2 bits in the status register. Only one sector can be
enabled at any time. To enable a different sector, a
previously enabled sector must be disabled by executing
a Sector Lock command. The instruction code is followed
by a 24-bit address specifying the target sector, but A0
through A11 are not decoded. The remaining sectors
within the same block remain in read-only mode.
Figure d. Sector Unlock Sequence
Sector unlock
CS
1
2
7
8
1
2
7
8 9 10
15 16 17 18
23 24 25 26
31 32
SCK
SI
06h
26h
A23-A16
A15-A8
A7-A0
In the sector unlock procedure, [A11:A0] needs equal to “0”, unlock procedure is
completed, otherwise chip will regard it as illegal command.
Note: 1.If the clock number will not match 8 clocks(command)+ 24 clocks (address), it will be ignored.
2.It must be executed write enable (06h) before sector unlock instructions.
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SECT_LOCK COMMAND OPERATION
The Sector Lock command reverses the function of the
Sector Unlock command. The instruction code does not
require an address to be specified, as only one sector can
be enabled at a time. The remaining sectors within the
same block remain in read-only mode.
Figure e. Sector Lock Sequence
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ORDERING INFORMATION:
Frequency
Density
(MHz)
Order Part Number
Package
IS25CD512-JDLE
IS25CD512-JNLE
IS25CD512-JKLE
IS25CD512-JULE
IS25CD512-JDLA*
IS25CD512-JNLA*
IS25CD512-JKLA*
IS25CD512-JULA*
IS25CD512-JWLE
IS25CD010-JDLE
IS25CD010-JNLE
IS25CD010-JKLE
IS25CD010-JDLA*
IS25CD010-JNLA*
IS25CD010-JWLE
IS25LD020-JDLE
IS25LD020-JNLE
IS25LD020-JKLE
IS25LD020-JVLE
IS25LD020-JDLA*
IS25LD020-JNLA*
IS25LD020-JKLA*
IS25LD020-JVLA*
IS25LD020-JWLE
8-pin TSSOP
8-pin SOIC 150mil
8-pin WSON (5x6mm)
8-pin USON (2x3mm)
8-pin TSSOP (Call Factory)
8-pin SOIC 150mil (Call Factory)
8-pin WSON (5x6mm) (Call Factory)
8-pin USON (2x3mm) (Call Factory)
KGD (Call Factory)
8-pin TSSOP
8-pin SOIC 150mil
8-pin WSON (5x6mm) (Call Factory)
8-pin TSSOP (Call Factory)
8-pin SOIC 150mil (Call Factory)
KGD (Call Factory)
8-pin TSSOP
8-pin SOIC 150mil
8-pin WSON (5x6mm)
8-pin VVSOP 150mil
512Kb
100
100
100
1Mb
2Mb
8-pin TSSOP (Call Factory)
8-pin SOIC 150mil (Call Factory)
8-pin WSON (5x6mm) (Call Factory)
8-pin VVSOP 150mil (Call Factory)
KGD (Call Factory)
A* = A1, A2 Automotive Temperature Ranges
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C
40
08/12/2013
相关型号：
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