IS61LV6464-6TQI [ETC]
x64 Fast Synchronous SRAM ; 64快速同步SRAM\n
| 型号： | IS61LV6464-6TQI |
| 厂家： | 
ETC |
| 描述： | x64 Fast Synchronous SRAM
|
| 文件： | 总17页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
IS61LV6464
ISSI
APRIL 2001
64K x 64 SYNCHRONOUS
PIPELINE STATIC RAM
FEATURES
DESCRIPTION
The ISSI IS61LV6464 is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, high-
performance, secondary cache for the Pentium™, 680X0™,
and PowerPC™ microprocessors. It is organized as 65,536
words by 64 bits, fabricated with ISSI's advanced CMOS
technology. The device integrates a 2-bit burst counter, high-
speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
• Fast access time:
– -100 MHz; 6 ns-83 MHz;
7 ns-75 MHz; 8 ns-66 MHz
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
eight bytes wide as controlled by the write control inputs.
• Five chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 128-Pin TQFP 14mm x 20mm
package
Separate byte enables allow individual bytes to be written.
BW1 controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 con-
trols I/O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls
I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49-
I/O56, BW8 controls I/O57-I/O64, conditioned by BWE being
LOW. A LOW on GW input would cause all bytes to be written.
• Single +3.3V power supply
• 2.5V VCCQ (I/O supply)
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated inter-
nally by the IS61LV6464 and controlled by the ADV (burst
address advance) input pin.
These control pins can be connected to GNDQ
or VCCQ to alter their power-up state
Asynchronoussignalsincludeoutputenable(OE),sleepmode
input(ZZ), andburstmodeinput(MODE). AHIGHinputonthe
ZZ pin puts the SRAM in the power-down state. When ZZ is
pulled LOW (or no connect), the SRAM normally operates
after the wake-up period. A LOW input, i.e., GNDQ, on MODE
pin selects LINEAR Burst. A VCCQ (or no connect) on MODE
pin selects INTERLEAVED Burst.
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
1
04/17/01
®
IS61LV6464
ISSI
BLOCK DIAGRAM
MODE
A0
A0'
A1'
Q0
CLK
CLK
BINARY
COUNTER
Q1
CE
ADV
A1
64K x 64
MEMORY
ARRAY
ADSC
ADSP
CLR
16
14
16
D
Q
A15-A0
ADDRESS
REGISTER
CE
CLK
64
64
D
Q
GW
BWE
DQ57-DQ64
BW8
BYTE WRITE
REGISTERS
CLK
D
Q
DQ8-DQ1
BYTE WRITE
REGISTERS
BW1
CLK
CE
CE2
CE2
CE3
CE3
8
64
INPUT
OUTPUT
D
Q
DATA[64:1]
REGISTERS
REGISTERS
ENABLE
OE
REGISTER
CLK
CLK
CE
CLK
D
Q
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
®
IS61LV6464
ISSI
PIN CONFIGURATION
128-Pin TQFP
1
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCCQ
I/O32
I/O31
I/O30
I/O29
I/O28
I/O27
I/O26
I/O25
I/O24
I/O23
I/O22
GNDQ
VCCQ
I/O21
I/O20
I/O19
I/O18
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
GNDQ
VCCQ
I/O11
I/O10
GNDQ
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
I/O40
I/O41
I/O42
I/O43
VCCQ
GNDQ
I/O44
I/O45
I/O46
I/O47
I/O48
I/O49
I/O50
I/O51
I/O52
I/O53
VCCQ
GNDQ
I/O54
I/O55
I/O56
I/O57
I/O58
I/O59
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
9
8
7
6
5
4
3
2
1
30
31
32
33
I/O60
I/O61
I/O62
I/O63
I/O64
VCCQ
34
35
36
37
38
GNDQ
PIN DESCRIPTIONS
A0-A15
CLK
Address Inputs
DQ1-DQ64
Data Input/Output
Sleep Mode
Clock
ZZ
ADSP
ADSC
ADV
Processor Address Status
Controller Address Status
Burst Address Advance
Synchronous Byte Write Enable
Byte Write Enable
MODE
VCC
Burst Sequence Mode
+3.3V Power Supply
Ground
GND
VCCQ
BW1-BW8
BWE
Isolated Output Buffer Supply:
+2.5V
NC
No Connect
GW
Global Write Enable
GNDQ
Isolated Output Buffer Ground
CE, CE2, CE2,
CE3, CE3
Synchronous Chip Enable
OE
Output Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
3
04/17/01
®
IS61LV6464
ISSI
TRUTH TABLE
ADDRESS
USED
OPERATION
CE3 CE2 CE3
CE2
CE ADSP ADSC ADV WRITE OE CLK
I/O
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
None
None
X
L
X
X
L
X
X
X
H
X
X
X
H
X
L
X
X
X
X
H
X
X
X
H
L
H
L
X
L
L
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
L
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H Dout
L-H High-Z
None
X
X
X
L
L
L
None
X
X
X
L
L
L
None
L
L
None
L
H
H
H
H
L
None
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
None
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
None
L
L
External
External
External
External
External
Next
L
X
X
L
L
L
L
L
H
X
L
L
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
Din
L
L
L
L
H
H
H
H
H
H
L
L-H Dout
L-H High-Z
L-H Dout
L-H High-Z
L-H Dout
L-H High-Z
L
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
X
H
X
X
H
H
X
H
H
H
H
H
H
H
H
H
H
H
H
H
Next
L
H
L
Next
L
Next
L
H
X
X
L
Next
L
L-H
L-H
Din
Din
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
L-H Dout
L-H High-Z
L-H Dout
L-H High-Z
H
L
H
X
X
L-H
L-H
Din
Din
L
Notes:
1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW8) and BWE are LOW or GW is LOW.
WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
®
IS61LV6464
ISSI
ASYNCHRONOUS TRUTH TABLE
Operation
ZZ
OE
I/O STATUS
Pipelined Read
Pipelined Read
Write
L
L
L
L
L
H
L
Dout
High-Z
High-Z
Din
Write
H
Deselect
Sleep
L
X
X
High-Z
High-Z
H
WRITE TRUTH TABLE
Operation
GW
BWE
BW8
BW7
BW6
BW5
BW4
BW3
BW2
BW1
Read
H
H
H
L
H
L
L
X
L
L
L
L
L
L
L
L
X
H
L
X
H
L
X
H
L
X
H
L
X
H
L
X
H
L
X
H
L
X
H
L
Read
Write all bytes
Write all bytes
Write Byte 1
Write Byte 2
Write Byte 3
Write Byte 4
Write Byte 5
Write Byte 6
Write Byte 7
Write Byte 8
X
H
H
H
H
H
H
H
L
X
H
H
H
H
H
H
L
X
H
H
H
H
H
L
X
H
H
H
H
L
X
H
H
H
L
X
H
H
L
X
H
L
X
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
5
04/17/01
®
IS61LV6464
ISSI
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address
A1 A0
1st Burst Address
A1 A0
2nd Burst Address
A1 A0
3rd Burst Address
A1 A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
A1’, A0’ = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
°C
°C
W
TBIAS
TSTG
PD
Temperature Under Bias
Storage Temperature
Power Dissipation
–10 to +85
–55 to +150
1.0
IOUT
Output Current (per I/O)
100
mA
V
VIN, VOUT Voltage Relative to GND for I/O Pins
–0.5 to VCCQ + 0.3
–0.5 to 5.5
VIN
Voltage Relative to GND for
for Address and Control Inputs
V
VCC
Voltage on Vcc Supply Relatiive to GND
–0.5 to 4.6
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
thisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextended
periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
orelectricfields;however,precautionsmaybetakentoavoidapplicationofanyvoltagehigher
than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
®
IS61LV6464
ISSI
OPERATING RANGE
Range
Ambient Temperature
VCC
VCCQ
Commercial
0°C to +70°C
3.3V +10%, –5%
2.375V min., 3.465V max.
Industrial
–40°C to +85°C
3.3V +10%, –5%
2.375V min., 3.465V max.
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
Test Conditions
IOH = –1.0 mA
IOL = 1 mA
Min.
2.0
Max.
Unit
V
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
—
0.4
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
—
V
1.7
VCCQ + 0.3
0.8
V
–0.3
V
(2)
GND - VIN - VCCQ
Com.
Ind.
–2
–10
2
10
µA
ILO
Output Leakage Current
GND - VOUT - VCCQ, OE = VIH Com.
–2
2
µA
Ind.
–10
10
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-100
6-
7-
8-
Symbol Parameter
Test Conditions
Typ. Max.
Typ. Max.
Typ. Max.
Typ. Max. Uni
t
ICC
AC Operating
Supply Current
Device Selected,
All Inputs = VIL or VIH
OE = VIH,
Com.
Ind.
210 250
190 200
200 220
160 170
170 190
140 150 mA
160 170 mA
—
—
Cycle Time • tKC min.
ISB1
ISB2
Standby Current
TTL Inputs
Device Deselected,
VCC = Max.,
All Inputs = VIH or VIL
CLK Cycle Time • tKC min.
Com.
Ind.
45 70
45
50
70
75
45
50
70
75
45
50
70
75
mA
mA
—
—
Standby Current
CMOS Inputs
Device Deselected,
VCC = Max.,
Com.
Ind.
2
5
2
5
5
10
2
5
5
10
2
5
5
10
mA
mA
—
—
VIN = VCC • 0.2V, or VIN - 0.2V
CLK Cycle Time • tKC min.
IZZ
Power-Down Mode
Current
ZZ = VCCQ, CLK Running
All Inputs - GND + 0.2V
or • VCC – 0.2V
Com.
Ind.
1
—
5
—
1
2
5
15
1
2
5
15
1
2
5
15
mA
mA
Note:
1. The MODE pin has an internal pullup. ZZ pin has an internal pull-down. This pin may be a No Connect, tied to GND, or tied to
VCCQ.
2. The MODE pin should be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to - GND + 0.2V
or • Vcc – 0.2V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
7
04/17/01
®
IS61LV6464
ISSI
CAPACITANCE(1,2)
Symbol
CIN
Parameter
Conditions
VIN = 0V
Max.
Unit
pF
Input Capacitance
5
7
COUT
Input/Output Capacitance
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter
Unit
0V to 3.0V
0V to 2.5V
1.5 ns
Input Pulse Level for Input Pins
Input Pulse Level for I/O Pins
Input Rise and Fall Times
Input and Output Timing
and Reference Level
1.25V
Output Load
See Figures 1 and 2
AC TEST LOADS
317 Ω
2.5V
ZO = 50Ω
OUTPUT
Output
Buffer
50Ω
30 pF
351 Ω
5 pF
Including
jig and
1.25V
scope
Figure 1
Figure 2
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
®
IS61LV6464
ISSI
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-100
Min. Max.
-6
-7
-8
Min. Max. Unit
Symbol Parameter
Min. Max.
Min. Max.
tKC
tKH
tKL
Cycle Time
10
4
—
—
—
5
12
4.5
4.5
—
—
—
—
6
13
5
—
—
—
7
15
6
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock High Time
Clock Low Time
4
5
6
tKQ
tKQX
Clock Access Time
—
2.5
0
—
3
—
3
(1)
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Disable to Output Invalid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
—
—
5
2.5
0
—
—
5
—
—
5
—
—
6
(1,2)
tKQLZ
0
0
(1,2)
tKQHZ
tOEQ
2
2
2
2
—
0
5
—
5
—
0
5
—
0
5
(1)
tOEQX
—
—
5
0
—
—
5
—
—
5
—
—
6
(1,2)
tOELZ
0
0
0
0
(1,2)
tOEHZ
tAS
2
2
2
2
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
tSS
Address Status Setup Time
Write Setup Time
tWS
tCES
tAVS
tAH
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
tSH
Address Status Hold Time
Write Hold Time
tWH
tCEH
tAVH
Note:
Chip Enable Hold Time
Address Advance Hold Time
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
9
04/17/01
®
IS61LV6464
READ CYCLE TIMING
CLK
ISSI
tKC
tKH
tKL
ADSP is blocked by CE inactive
ADSC initiate read
tSS
tSH
ADSP
ADSC
tSS
tSH
tAVH
tAVS
Suspend Burst
ADV
tAS
tAH
A15-A0
RD1
RD2
RD3
tWS
tWH
GW
BWE
tWS
tWH
BW8-BW1
tCES
tCES
tCES
tCEH
CE Masks ADSP
CE
CE2, CE3
CE2, CE3
tCEH
tCEH
Unselected with CE2, CE3
CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC
tOEHZ
tOEQ
OE
tKQX
tOEQX
tOELZ
High-Z
High-Z
DATAOUT
2a
2b
2c
2d
3a
1a
tKQLZ
tKQHZ
tKQ
DATAIN
Pipelined Read
Burst Read
Single Read
Unselected
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
®
IS61LV6464
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-100
Min. Max.
-6
-7
-8
Min. Max. Unit
Symbol Parameter
Min. Max.
Min. Max.
tKC
Cycle Time
10
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
13
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKH
Clock High Time
4.5
4.5
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
tKL
Clock Low Time
4
5
6
tAS
Address Setup Time
Address Status Setup Time
Write Setup Time
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
2.5
2.5
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
0.5
0.5
tSS
tWS
tDS
Data In Setup Time
Chip Enable Setup Time
Address Advance Setup Time
Address Hold Time
Address Status Hold Time
Data In Hold Time
tCES
tAVS
tAH
tSH
tDH
tWH
tCEH
tAVH
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11
04/17/01
®
IS61LV6464
ISSI
WRITE CYCLE TIMING
t
KC
CLK
t
KH
tKL
ADSP is blocked by CE inactive
ADSC initiate Write
t
SS
tSH
ADSP
ADSC
t
AVH
t
AVS
ADV must be inactive for ADSP Write
ADV
t
AS
tAH
A15-A0
WR1
WR2
WR3
t
t
WS
WS
t
t
WH
WH
GW
BWE
t
WS
t
WH
t
WS
tWH
BW8-BW1
WR1
WR2
CE Masks ADSP
WR3
t
CES
tCEH
CE
CE2, CE3
CE2, CE3
t
t
CES
CES
t
CEH
CEH
Unselected with CE2, CE3
CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC
t
OE
DATAOUT
DATAIN
High-Z
t
DS
tDH
BW8-BW1 only are applied to first cycle of WR2
2a 2b 2c 2d
High-Z
3a
1a
Burst Write
Single Write
Write
Unselected
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
®
IS61LV6464
ISSI
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-100
Min. Max.
-6
-7
-8
Min. Max. Unit
Symbol Parameter
Min. Max.
Min. Max.
tKC
tKH
tKL
Cycle Time
10
4
—
—
—
5
12
4.5
4.5
—
—
—
—
6
13
5
—
—
—
7
15
6
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock High Time
Clock Low Time
4
5
6
tKQ
tKQX
Clock Access Time
—
2.5
0
—
3
—
3
(1)
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Disable to Output Invalid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
—
—
5
2.5
0
—
—
5
—
—
5
—
—
6
(1,2)
tKQLZ
0
0
(1,2)
tKQHZ
tOEQ
2
2
2
2
—
0
5
—
5
—
0
5
—
0
5
(1)
tOEQX
—
—
5
0
—
—
5
—
—
5
—
—
6
(1,2)
tOELZ
0
0
0
0
(1,2)
tOEHZ
tAS
2
2
2
2
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
2.5
2.5
2.5
2.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
tSS
Address Status Setup Time
Write Setup Time
tWS
tCES
tAH
Chip Enable Setup Time
Address Hold Time
tSH
Address Status Hold Time
Write Hold Time
tWH
tCEH
Note:
Chip Enable Hold Time
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
13
04/17/01
®
IS61LV6464
ISSI
READ/WRITE CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE inactive
t
SS
tSH
t
SS
tSH
ADV
t
AS
tAH
A15-A0
RD1
WR1
RD2
RD3
t
t
WS
WS
t
t
WH
GW
BWE
WH
t
WS
tWH
WR1
BW8-BW1
t
CES
tCEH
CE Masks ADSP
CE
CE2, CE3
CE2, CE3
t
t
CES
CES
t
t
CEH
CEH
CE2, CE3 and CE2, CE3 only sampled with ADSP or ADSC
Unselected with CE2, CE3
t
OEHZ
t
OEQ
OE
t
KQX
t
OEQX
t
OELZ
High-Z
High-Z
DATAOUT
2a
2b
2c
2d
1a
t
KQLZ
t
KQHZ
t
KQX
KQHZ
t
KQ
t
1a
DATAIN
t
DS
tDH
Single Write
Burst Read
Single Read
Unselected
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
®
IS61LV6464
ISSI
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-100
-6
-7
-8
Symbol Parameter
Min. Max.
Min. Max.
Min. Max.
Min. Max. Unit
tKC
tKH
tKL
Cycle Time
10
4
—
—
—
5
12
4.5
4.5
—
2.5
0
—
—
—
6
13
5
—
—
—
7
15
6
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
Clock High Time
Clock Low Time
4
5
6
tKQ
tKQX
Clock Access Time
—
2.5
0
—
3
—
3
(3)
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Disable to Output Invalid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
—
—
5
—
—
5
—
—
5
—
—
6
(3,4)
tKQLZ
0
0
(3,4)
tKQHZ
tOEQ
2
2
2
2
—
0
5
—
0
5
—
0
5
—
0
5
(3)
tOEQX
—
—
5
—
—
5
—
—
5
—
—
6
(3,4)
tOELZ
0
0
0
0
(3,4)
tOEHZ
tAS
2
2
2
2
2.5
2.5
2.5
0.5
0.5
0.5
2
—
—
—
—
—
—
—
—
2.5
2.5
2.5
0.5
0.5
0.5
2
—
—
—
—
—
—
—
—
2.5
2.5
2.5
0.5
0.5
0.5
2
—
—
—
—
—
—
—
—
2.5
2.5
2.5
0.5
0.5
0.5
2
—
—
—
—
—
—
—
—
tSS
Address Status Setup Time
Chip Enable Setup Time
Address Hold Time
tCES
tAH
tSH
Address Status Hold Time
Chip Enable Hold Time
ZZ Standby(1)
tCEH
tZZS
tZZREC
ZZ Recovery(2)
2
2
2
2
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state.
3. Guaranteed but not 100% tested. This parameter is periodically sampled.
4. Tested with load in Figure 2.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
15
04/17/01
®
IS61LV6464
ISSI
SNOOZE AND RECOVERY CYCLE TIMING
t
KC
CLK
ADSP
ADSC
t
KH
tKL
t
SS
tSH
ADV
t
AS
tAH
A15-A0
RD1
RD2
GW
BWE
BW8-BW1
t
CES
tCEH
CE
CE2, CE3
CE2, CE3
t
t
CES
CES
t
CEH
CEH
t
t
OEHZ
t
OEQ
OE
t
OEQX
t
OELZ
High-Z
High-Z
DATAOUT
1a
t
KQLZ
t
KQX
KQHZ
t
KQ
t
DATAIN
ZZ
t
ZZS
tZZREC
Snooze with Data Retention
Single Read
Read
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
®
IS61LV6464
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns)
Order Part Number
Package
100
100
IS61LV6464-100TQ
IS61LV6464-100PQ
TQFP
PQFP
83
83
IS61LV6464-6TQ
IS61LV6464-6PQ
TQFP
PQFP
75
75
IS61LV6464-7TQ
IS61LV6464-7PQ
TQFP
PQFP
66
66
IS61LV6464-8TQ
IS61LV6464-8PQ
TQFP
PQFP
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part Number
Package
83
83
IS61LV6464-6TQI
IS61LV6464-6PQI
TQFP
PQFP
75
75
IS61LV6464-7TQI
IS61LV6464-7PQI
TQFP
PQFP
66
66
IS61LV6464-8TQI
IS61LV6464-8PQI
TQFP
PQFP
®
ISSI
IntegratedSiliconSolution,Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
17
04/17/01
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