IS62C5128BL-45HI [ETC]
512K x 8 HIGH-SPEED CMOS STATIC RAM; 512K ×8高速CMOS静态RAM
| 型号： | IS62C5128BL-45HI |
| 厂家： | 
ETC |
| 描述： | 512K x 8 HIGH-SPEED CMOS STATIC RAM |
| 文件： | 总14页 (文件大小：512K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS62C5128BL, IS65C5128BL
512Kꢀxꢀ8ꢀHIGH-SPEEDꢀCMOSꢀSTATICꢀRAM
JULYꢀ2011
FEATURES
•ꢀ High-speedꢀaccessꢀtime:ꢀ45ns
•ꢀ LowꢀActiveꢀPower:ꢀ50ꢀmWꢀ(typical)
DESCRIPTION
TheꢀISSIꢀIS62C5128BLꢀandꢀIS65C5128BLꢀareꢀhigh-speed,ꢀ
4,194,304-bitꢀstaticꢀRAMsꢀorganizedꢀasꢀ524,288ꢀwordsꢀbyꢀ
8ꢀbits.ꢀTheyꢀareꢀfabricatedꢀusingꢀISSI'sꢀhigh-performanceꢀ
CMOSꢀtechnology.ꢀThisꢀhighlyꢀreliableꢀprocessꢀcoupledꢀwithꢀ
innovativeꢀcircuitꢀdesignꢀtechniques,ꢀyieldsꢀaccessꢀtimesꢀasꢀ
fastꢀasꢀ45nsꢀwithꢀlowꢀpowerꢀconsumption.
•ꢀ LowꢀStandbyꢀPower:ꢀ10ꢀmWꢀ(typical)ꢀꢀ
ꢀ
CMOSꢀstandby
•ꢀ TTLꢀcompatibleꢀinterfaceꢀlevels
•ꢀ Singleꢀ5Vꢀ ꢀ10%ꢀpowerꢀsupply
Whenꢀ CEꢀ isꢀ HIGHꢀ (deselected),ꢀ theꢀ deviceꢀ assumesꢀ aꢀ
standbyꢀmodeꢀatꢀwhichꢀtheꢀpowerꢀdissipationꢀcanꢀbeꢀreducedꢀ
downꢀwithꢀCMOSꢀinputꢀlevels.
•ꢀ Fullyꢀstaticꢀoperation:ꢀnoꢀclockꢀorꢀrefreshꢀꢀ
required
•ꢀ Availableꢀinꢀ32-pinꢀsTSOP-I,ꢀ32-pinꢀSOPꢀandꢀ
32-pinꢀTSOP-IIꢀpackages
EasyꢀmemoryꢀexpansionꢀisꢀprovidedꢀbyꢀusingꢀChipꢀEnableꢀ
andꢀOutputꢀEnableꢀinputs,ꢀCEꢀandꢀOE.ꢀTheꢀactiveꢀLOWꢀ
WriteꢀEnableꢀ(WE)ꢀcontrolsꢀbothꢀwritingꢀandꢀreadingꢀofꢀtheꢀ
memory.ꢀAꢀdataꢀbyteꢀallowsꢀUpperꢀByteꢀ(UB)ꢀandꢀLowerꢀ
Byteꢀ(LB)ꢀaccess.
•ꢀ Commercial,ꢀIndustrialꢀandꢀAutomotiveꢀtem-
peratureꢀrangesꢀavailable
•ꢀ Lead-freeꢀavailable
TheꢀIS62C5128BLꢀandꢀIS65C5128BLꢀareꢀpackagedꢀinꢀtheꢀ
JEDECꢀstandardꢀ32-pinꢀsTSOP-I,ꢀ32-pinꢀSOPꢀandꢀ32-pinꢀ
TSOP-IIꢀpackages
FUNCTIONAL BLOCK DIAGRAM
512K X 8
MEMORY ARRAY
A0-A18
DECODER
VDD
GND
I/O
DATA
COLUMN I/O
I/O0-I/O7
CIRCUIT
CE
CONTROL
CIRCUIT
OE
WE
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.comꢀ
1
Rev.ꢀ B
06/28/2011
I/O0-I/O7
Vddꢀ
IS62C5128BL, IS65C5128BLꢀ
PIN CONFIGURATION
32-pinꢀsTSOPꢀ(TYPEꢀI)ꢀ
32-pinꢀSOP
32-pinꢀTSOPꢀ(TYPEꢀII)ꢀ
A17
A16
A14
A12
A7
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
VDD
A11
A9
1
2
A15
A18
WE
A13
A8
2
A10
CE
3
A8
3
4
A13
WE
A18
A15
4
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
5
5
A6
6
6
A5
7
A9
7
A4
8
A11
OE
V
DD
8
A3
9
A17
A16
A14
A12
A7
9
A2
10
11
12
13
14
15
16
A10
CE
10
11
12
13
14
15
16
A1
A0
I/O7
I/O6
I/O5
I/O4
I/O3
I/O0
I/O1
I/O2
GND
A6
A1
A5
A2
A4
A3
PINꢀDESCRIPTIONS
A0-A18ꢀ AddressꢀInputs
CEꢀꢀ
ChipꢀEnableꢀ1ꢀInputꢀ
OEꢀꢀ
OutputꢀEnableꢀInput
WriteꢀEnableꢀInput
Input/Output
Power
WEꢀꢀ
GNDꢀ
Ground
2ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ B
06/28/2011
IS62C5128BL, IS65C5128BLꢀ
TRUTHꢀTABLE
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
WEꢀ
Xꢀ
Hꢀ
Hꢀ
ꢀ
CEꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
ꢀ
OEꢀ
Xꢀ
Hꢀ
Lꢀ
ꢀ
I/OꢀPIN
Modeꢀ
I/O0-I/O7ꢀ VDDꢀCurrentꢀ
NotꢀSelectedꢀ
OutputꢀDisabledꢀ
Readꢀ
High-Zꢀ
High-Zꢀ
doutꢀ
dinꢀ
isb1,ꢀisb2
iCC1,ꢀiCC2ꢀ
iCC1,ꢀiCC2ꢀ
iCC1,ꢀiCC2ꢀ
ꢀ
ꢀ
Writeꢀ
Lꢀ
Xꢀ
ABSOLUTEꢀMAXIMUMꢀRATINGS(1)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Symbolꢀ Parameterꢀ
Valueꢀ
Unit
V
°C
W
mAꢀ
Vtermꢀ
tstgꢀ
Ptꢀ
TerminalꢀVoltageꢀwithꢀRespectꢀtoꢀGNDꢀ
StorageꢀTemperatureꢀ
PowerꢀDissipationꢀ
–0.5ꢀtoꢀ+7.0ꢀ
–65ꢀtoꢀ+150ꢀ
1.5ꢀ
ioutꢀ
DCꢀOutputꢀCurrentꢀ(LOW)ꢀ
20ꢀ
Notes:
1.ꢀꢀStressꢀgreaterꢀthanꢀthoseꢀlistedꢀunderꢀABSOLUTEꢀMAXIMUMꢀRATINGSꢀmayꢀcauseꢀpermanentꢀdam-
ageꢀtoꢀtheꢀdevice.ꢀThisꢀisꢀaꢀstressꢀratingꢀonlyꢀandꢀfunctionalꢀoperationꢀofꢀtheꢀdeviceꢀatꢀtheseꢀorꢀanyꢀ
otherꢀconditionsꢀaboveꢀthoseꢀindicatedꢀinꢀtheꢀoperationalꢀsectionsꢀofꢀthisꢀspecificationꢀisꢀnotꢀimplied.ꢀ
Exposureꢀtoꢀabsoluteꢀmaximumꢀratingꢀconditionsꢀforꢀextendedꢀperiodsꢀmayꢀaffectꢀreliability.ꢀ
CAPACITANCE(1,2)
ꢀ
ꢀ
ꢀ
Symbolꢀ
Cinꢀ
Parameterꢀ
InputꢀCapacitanceꢀ
OutputꢀCapacitanceꢀ
Conditionsꢀ
Vinꢀ=ꢀ0Vꢀ
Max.ꢀ
6ꢀ
8ꢀ
Unit
pF
pF
Coutꢀ
Voutꢀ=ꢀ0Vꢀ
Notes:
1.ꢀꢀTestedꢀinitiallyꢀandꢀafterꢀanyꢀdesignꢀorꢀprocessꢀchangesꢀthatꢀmayꢀaffectꢀtheseꢀparameters.
2.ꢀ Testꢀconditions:ꢀTaꢀ=ꢀ25°C,ꢀfꢀ=ꢀ1ꢀMHz,ꢀVddꢀ=ꢀ5.0V.
DCꢀELECTRICALꢀCHARACTERISTICSꢀ(OverꢀOperatingꢀRange)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Symbolꢀ Parameterꢀ
TestꢀConditionsꢀ
Vddꢀ=ꢀMin.,ꢀiohꢀ=ꢀ–1.0ꢀmAꢀ
ꢀ
Min.ꢀ
2.4ꢀ
—ꢀ
2.2ꢀ
–0.3ꢀ
–1ꢀ
–2ꢀ
–5ꢀ
–1ꢀ
–2ꢀ
–5ꢀ
Max.ꢀ
—ꢀ
0.4ꢀ
Unit
V
V
V
V
Vohꢀ
Volꢀ
Vihꢀ
Vilꢀ
OutputꢀHIGHꢀVoltageꢀ
ꢀ
ꢀ
ꢀ
ꢀ
OutputꢀLOWꢀVoltageꢀ
InputꢀHIGHꢀVoltage(1)ꢀ
InputꢀLOWꢀVoltage(1)ꢀ
Vddꢀ=ꢀMin.,ꢀiolꢀ=ꢀ2.1ꢀmAꢀ
ꢀ
ꢀ
Vddꢀ+ꢀ0.5ꢀ
0.8ꢀ
ꢀ
iliꢀ
InputꢀLeakageꢀ
GNDꢀ≤ꢀVinꢀ≤ꢀVdd
Com.ꢀ
Ind.ꢀ
Auto.ꢀ
Com.ꢀ
Ind.ꢀ
Auto.ꢀ
1ꢀ
2ꢀ
5ꢀ
1ꢀ
2ꢀ
5
µAꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
iloꢀ
OutputꢀLeakageꢀ
GNDꢀ≤ꢀVoutꢀ≤ꢀVddꢀ
OutputsꢀDisabledꢀ
ꢀ
µAꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Note:
1.ꢀꢀVillꢀ(min)ꢀ=ꢀ-2.0VꢀACꢀ(pulseꢀwidthꢀ<10ꢀns).ꢀNotꢀ100%ꢀtested.ꢀ
ꢀ
Vihhꢀ(max)ꢀ=ꢀVddꢀ+ꢀ2.0VꢀACꢀ(pulseꢀwidthꢀ<10ꢀns).ꢀNotꢀ100%ꢀtested.ꢀ
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
3
Rev.ꢀ B
06/28/2011
IS62C5128BL, IS65C5128BLꢀ
OPERATINGꢀRANGE
ꢀ
ꢀ
ꢀ
ꢀ
Rangeꢀ
Commercialꢀ 0°Cꢀtoꢀ+70°Cꢀ
Industrialꢀ -40°Cꢀtoꢀ+85°Cꢀ
Automotiveꢀ -40°Cꢀtoꢀ+125°Cꢀ
AmbientꢀTemperatureꢀ
VDD
Speedꢀ(ns)
5Vꢀ ꢀ10%ꢀ
5Vꢀ ꢀ10%ꢀ
5Vꢀ ꢀ10%ꢀ
45
45
45
POWERꢀSUPPLYꢀCHARACTERISTICS(1)ꢀ(OverꢀOperatingꢀRange)
ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ-45ꢀnsꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ
ꢀ SymbolꢀParameterꢀ
TestꢀConditionsꢀ
ꢀ
Min.ꢀ Max.ꢀ
ꢀ
Unit
ꢀ iCC
ꢀ ꢀ
ꢀ ꢀ
ꢀ
Averageꢀoperatingꢀ
Currentꢀ
ꢀ
CEꢀ=ꢀVil,ꢀVddꢀ=ꢀMax.ꢀ
iꢀout=ꢀ0ꢀmA,ꢀf=ꢀ0ꢀ
ꢀ
Com.ꢀ
Ind.ꢀ
Auto.ꢀ
—ꢀ
—ꢀ
—ꢀ
10ꢀ
10ꢀ
10ꢀ
ꢀ
mA
ꢀ iCC1ꢀ
ꢀ ꢀ
ꢀ ꢀ
V
ddꢀDynamicꢀOperatingꢀꢀVddꢀ=ꢀMax.,ꢀCEꢀ=ꢀVil
ꢀ
ꢀ
Com.ꢀ
Ind.ꢀ
—ꢀ
—ꢀ
—ꢀ
15ꢀ
20ꢀ
25ꢀ
ꢀ
ꢀ
mA
ꢀ
SupplyꢀCurrentꢀ
ꢀ
ꢀ
i
ꢀ
ꢀ
outꢀ=ꢀ0ꢀmA,ꢀꢀfꢀ=ꢀfmax
Auto.ꢀ
ꢀ
ꢀ
ꢀ ꢀ
typ.(2)ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ10
ꢀ isb1ꢀ
ꢀ ꢀ
ꢀ ꢀ
TTLꢀStandbyꢀCurrentꢀ
(TTLꢀInputs)ꢀ
ꢀꢀ
V
V
fꢀ=ꢀ0ꢀ
ddꢀ=ꢀMax.,ꢀꢀ
inꢀ=ꢀVihꢀorꢀVil,ꢀCEꢀ≥ꢀVih,ꢀ
Com.ꢀ
Ind.ꢀ
Auto.ꢀ
—ꢀ
—ꢀ
—ꢀ
1ꢀ
1.5ꢀ
2ꢀ
ꢀ
mAꢀ
mA
ꢀ isb2ꢀ
ꢀ ꢀ
ꢀ ꢀ
CMOSꢀStandbyꢀ
Currentꢀ(CMOSꢀInputs)ꢀ CEꢀ≥ꢀꢀVddꢀ–ꢀ0.2V,ꢀ
ꢀ
ꢀ
Vddꢀ=ꢀMax.,ꢀꢀ
Com.ꢀ
Ind.ꢀ
Auto.ꢀ
typ.ꢀ
—ꢀ
—ꢀ
—ꢀ
10ꢀ
15ꢀ
35ꢀ
ꢀ
Vinꢀ≥ꢀVddꢀ–ꢀ0.2V,ꢀ
ꢀ ꢀ
orꢀVinꢀ≤ꢀVssꢀ+ꢀ0.2V,ꢀꢀfꢀ=ꢀ0ꢀ
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ4ꢀ
Note:
1.ꢀꢀAtꢀfꢀ=ꢀfmax,ꢀaddressꢀandꢀdataꢀinputsꢀareꢀcyclingꢀatꢀtheꢀmaximumꢀfrequency,ꢀfꢀ=ꢀ0ꢀmeansꢀnoꢀinputꢀlinesꢀchange.
2.ꢀꢀTypicalꢀvaluesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀ5V,ꢀTaꢀ=ꢀ25oCꢀandꢀnotꢀ100%ꢀtested.
4ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ B
06/28/2011
IS62C5128BL, IS65C5128BLꢀ
READꢀCYCLEꢀSWITCHINGꢀCHARACTERISTICS(1)ꢀ(OverꢀOperatingꢀRange)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
-45ꢀ
Symbolꢀ
ꢀ trCꢀ
Parameterꢀ
Min.ꢀ Max.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ReadꢀCycleꢀTimeꢀ
AddressꢀAccessꢀTimeꢀ
OutputꢀHoldꢀTimeꢀ
CEꢀAccessꢀTimeꢀ
OEꢀAccessꢀTimeꢀ
OEꢀtoꢀHigh-ZꢀOutputꢀ
OEꢀtoꢀLow-ZꢀOutputꢀ
CEꢀtoꢀHigh-ZꢀOutputꢀ
CEꢀtoꢀLow-ZꢀOutputꢀ
45ꢀ
—ꢀ
3ꢀ
—ꢀ
45ꢀ
—ꢀ
45ꢀ
20ꢀ
15ꢀ
—ꢀ
15ꢀ
—ꢀ
ꢀ taaꢀ
ꢀ tohaꢀ
ꢀ taCeꢀ
—ꢀ
—ꢀ
0ꢀ
ꢀ tdoeꢀ
ꢀ thzoe(2)ꢀ
ꢀ tlzoe(2)ꢀ
ꢀ thzCe(2)ꢀ
ꢀ tlzCe(2)ꢀ
5ꢀ
0ꢀ
5ꢀ
Notes:ꢀ
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ3ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0ꢀtoꢀ
3.0VꢀandꢀoutputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀꢀTransitionꢀisꢀmeasuredꢀ 500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
3.ꢀ Notꢀ100%ꢀtested.
ACꢀTESTꢀCONDITIONS
ꢀ
ꢀ
ꢀ
Parameterꢀ
Unit
0Vꢀtoꢀ3.0V
3ꢀns
InputꢀPulseꢀLevelꢀ
InputꢀRiseꢀandꢀFallꢀTimesꢀ
ꢀ
ꢀ
InputꢀandꢀOutputꢀTimingꢀ
andꢀReferenceꢀLevel
1.5Vꢀ
ꢀ
OutputꢀLoadꢀ
SeeꢀFiguresꢀ1ꢀandꢀ2
ACꢀTESTꢀLOADS
1838 Ω
1838 Ω
5V
5V
OUTPUT
OUTPUT
994 Ω
994 Ω
30 pF
Including
jig and
5 pF
Including
jig and
scope
scope
Figureꢀ1
Figureꢀ2
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
5
Rev.ꢀ B
06/28/2011
IS62C5128BL, IS65C5128BLꢀ
ACꢀWAVEFORMS
READꢀCYCLEꢀNO.ꢀ1(1,2)
t
RC
ADDRESS
t
AA
t
OHA
t
OHA
DATA VALID
DOUT
PREVIOUS DATA VALID
READ1.eps
READꢀCYCLEꢀNO.ꢀ2(1,3)
t
RC
ADDRESS
OE
t
AA
t
OHA
t
HZOE
t
DOE
t
t
LZOE
ACS
CE
t
HZCS
t
LZCS
HIGH-Z
DOUT
DATA VALID
CE_RD2.eps
Notes:ꢀ
1.ꢀ WEꢀisꢀHIGHꢀforꢀaꢀReadꢀCycle.
2.ꢀ Theꢀdeviceꢀisꢀcontinuouslyꢀselected.ꢀOE,ꢀCEꢀ=ꢀVil.
3.ꢀ AddressꢀisꢀvalidꢀpriorꢀtoꢀorꢀcoincidentꢀwithꢀCEꢀLOWꢀtransitions.
6ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ B
06/28/2011
ꢀ ꢀ thdꢀ
IS62C5128BL, IS65C5128BLꢀ
WRITEꢀCYCLEꢀSWITCHINGꢀCHARACTERISTICS(1,3)ꢀ(OverꢀOperatingꢀRange)
ꢀ
-45ꢀ
ꢀ Symbolꢀ Parameterꢀ
Min.ꢀ Max.ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Unit
ns
ꢀ ꢀ twCꢀ
ꢀ ꢀ tsCeꢀ
WriteꢀCycleꢀTimeꢀ
45ꢀ
35ꢀ
35ꢀ
—ꢀ
—ꢀ
—ꢀ
CEꢀtoꢀWriteꢀEndꢀ
ns
ꢀ ꢀ tawꢀ
ꢀ ꢀ ꢀ
AddressꢀSetupꢀTimeꢀꢀ
toꢀWriteꢀEnd
ns
ꢀ ꢀ thaꢀ
AddressꢀHoldꢀfromꢀWriteꢀEndꢀ
AddressꢀSetupꢀTimeꢀ
0ꢀ
0ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
—ꢀ
15ꢀ
—ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ns
ns
ns
ns
ns
ns
ns
ns
ꢀ ꢀ tsaꢀ
ꢀ ꢀ tPwe1ꢀ
ꢀ ꢀ tPwe2ꢀ
ꢀ ꢀ tsdꢀ
WEꢀPulseꢀWidthꢀ(OEꢀ=High)ꢀ
WEꢀPulseꢀWidthꢀ(OE=Low)ꢀ
DataꢀSetupꢀtoꢀWriteꢀEndꢀ
DataꢀHoldꢀfromꢀWriteꢀEndꢀ
35ꢀ
35ꢀ
25ꢀ
0ꢀ
ꢀ ꢀ thzwe(2)ꢀ WEꢀLOWꢀtoꢀHigh-ZꢀOutputꢀ
ꢀ ꢀ tlzwe(2)ꢀ WEꢀHIGHꢀtoꢀLow-ZꢀOutputꢀ
Notes:ꢀ
—ꢀ
5ꢀ
1.ꢀ Testꢀconditionsꢀassumeꢀsignalꢀtransitionꢀtimesꢀofꢀ3ꢀnsꢀorꢀless,ꢀtimingꢀreferenceꢀlevelsꢀofꢀ1.5V,ꢀinputꢀpulseꢀlevelsꢀofꢀ0ꢀtoꢀ3.0Vꢀandꢀ
outputꢀloadingꢀspecifiedꢀinꢀFigureꢀ1.
2.ꢀ TestedꢀwithꢀtheꢀloadꢀinꢀFigureꢀ2.ꢀꢀTransitionꢀisꢀmeasuredꢀ 500ꢀmVꢀfromꢀsteady-stateꢀvoltage.ꢀNotꢀ100%ꢀtested.
3.ꢀ TheꢀinternalꢀwriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀofꢀCEꢀLOW,ꢀandꢀWEꢀLOW.ꢀꢀAllꢀsignalsꢀmustꢀbeꢀinꢀvalidꢀstatesꢀtoꢀinitiateꢀaꢀWrite,ꢀ
butꢀanyꢀoneꢀcanꢀgoꢀinactiveꢀtoꢀterminateꢀtheꢀWrite.ꢀꢀTheꢀDataꢀInputꢀSetupꢀandꢀHoldꢀtimingꢀareꢀreferencedꢀtoꢀtheꢀrisingꢀorꢀfallingꢀ
edgeꢀofꢀtheꢀsignalꢀthatꢀterminatesꢀtheꢀwrite.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
7
Rev.ꢀ B
06/28/2011
IS62C5128BL, IS65C5128BLꢀ
ACꢀWAVEFORMS
WRITEꢀCYCLEꢀNO.ꢀ1ꢀ(WEꢀControlled)(1,2)
t
WC
VALID ADDRESS
SCS
ADDRESS
t
SA
t
t
HA
CE
t
AW
t
tPPWWEE21
WE
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR1.eps
Notes:ꢀ
1.ꢀ TheꢀinternalꢀwriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀofꢀCEꢀLOWꢀandꢀWEꢀLOW.ꢀꢀAllꢀsignalsꢀmustꢀbeꢀinꢀvalidꢀstatesꢀtoꢀinitiateꢀaꢀWrite,ꢀ
butꢀanyꢀoneꢀcanꢀgoꢀinactiveꢀtoꢀterminateꢀtheꢀWrite.ꢀꢀTheꢀDataꢀInputꢀSetupꢀandꢀHoldꢀtimingꢀareꢀreferencedꢀtoꢀtheꢀrisingꢀorꢀfallingꢀ
edgeꢀofꢀtheꢀsignalꢀthatꢀterminatesꢀtheꢀWrite.
2.ꢀ I/OꢀwillꢀassumeꢀtheꢀHigh-ZꢀstateꢀifꢀOEꢀ≥ꢀVih.
8ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ B
06/28/2011
IS62C5128BL, IS65C5128BLꢀ
WRITEꢀCYCLEꢀNO.ꢀ2ꢀ(OEꢀisꢀHIGHꢀDuringꢀWriteꢀCycle)ꢀ(1,2)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
CE
t
AW
t
PWE1
WE
t
SA
t
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR2.eps
WRITEꢀCYCLEꢀNO.ꢀ3ꢀ(OEꢀisꢀLOWꢀDuringꢀWriteꢀCycle)ꢀ(1)
t
WC
ADDRESS
OE
VALID ADDRESS
t
HA
LOW
LOW
CE
t
t
AW
t
PWE2
WE
t
SA
HZWE
t
LZWE
HIGH-Z
DATA UNDEFINED
DOUT
t
SD
t
HD
DATAIN VALID
DIN
CE_WR3.eps
Notes:ꢀ
1.ꢀ TheꢀinternalꢀwriteꢀtimeꢀisꢀdefinedꢀbyꢀtheꢀoverlapꢀofꢀCEꢀLOWꢀandꢀWEꢀLOW.ꢀꢀAllꢀsignalsꢀmustꢀbeꢀinꢀvalidꢀstatesꢀtoꢀinitiateꢀaꢀWrite,ꢀ
butꢀanyꢀoneꢀcanꢀgoꢀinactiveꢀtoꢀterminateꢀtheꢀWrite.ꢀꢀTheꢀDataꢀInputꢀSetupꢀandꢀHoldꢀtimingꢀareꢀreferencedꢀtoꢀtheꢀrisingꢀorꢀfallingꢀ
edgeꢀofꢀtheꢀsignalꢀthatꢀterminatesꢀtheꢀWrite.
2.ꢀ I/OꢀwillꢀassumeꢀtheꢀHigh-ZꢀstateꢀifꢀOEꢀ≥ꢀVih.
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
9
Rev.ꢀ B
06/28/2011
IS62C5128BL, IS65C5128BLꢀ
DATAꢀRETENTIONꢀSWITCHINGꢀCHARACTERISTICS
ꢀ Symbolꢀ Parameterꢀ
TestꢀConditionꢀ
ꢀ
Min.ꢀ
ꢀ
Max.ꢀ Unit
ꢀ ꢀ Vdr ddꢀforꢀDataꢀRetentionꢀ
ꢀ
V
SeeꢀDataꢀRetentionꢀWaveformꢀ
ꢀ
2.0ꢀ
ꢀ
5.5ꢀ
V
ꢀ ꢀ idr
ꢀ ꢀ ꢀ
ꢀ
DataꢀRetentionꢀCurrentꢀ
ꢀ
V
ddꢀ=ꢀ2.0V,ꢀCEꢀ≥ꢀVddꢀ–ꢀ0.2Vꢀ
Com.ꢀ
Ind.ꢀ
—ꢀ
—ꢀ
ꢀ
ꢀ
10ꢀ
15ꢀ
mA
Vinꢀ≥ꢀVddꢀ–ꢀ0.2V,ꢀorꢀVinꢀ≤ꢀVssꢀ+ꢀ0.2Vꢀ
ꢀ ꢀ ꢀ
ꢀ ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Auto.ꢀ
typ.ꢀ(1)ꢀ
—ꢀ
ꢀ
ꢀ
2
35ꢀ
ꢀ
ꢀ ꢀ tsdr
ꢀ
DataꢀRetentionꢀSetupꢀTimeꢀ SeeꢀDataꢀRetentionꢀWaveformꢀ
RecoveryꢀTimeꢀ SeeꢀDataꢀRetentionꢀWaveformꢀ
ꢀ
ꢀ
0ꢀ
ꢀ
ꢀ
—ꢀ
—ꢀ
ns
ns
ꢀ ꢀ trdr
ꢀ
trCꢀ
Note:ꢀ
ꢀ 1.ꢀTypicalꢀValuesꢀareꢀmeasuredꢀatꢀVddꢀ=ꢀ5V,ꢀT
ꢀ=ꢀ25oCꢀandꢀnotꢀ100%ꢀtested.
a
DATAꢀRETENTIONꢀWAVEFORMꢀ(CEꢀControlled)
t
Data Retention Mode
t
RDR
SDR
VDD
4.5V
V
DR
CE ≥ VDD - 0.2V
CE
GND
10ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ B
06/28/2011
IS62C5128BL, IS65C5128BLꢀ
ORDERINGꢀINFORMATION
IndustrialꢀRange:ꢀ–40°Cꢀtoꢀ+85°C
ꢀ Speedꢀ(ns)ꢀ
OrderꢀPartꢀNo.ꢀ
Package
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
45ꢀ
IS62C5128BL-45QIꢀ
IS62C5128BL-45QLIꢀ
IS62C5128BL-45HIꢀ
IS62C5128BL-45HLIꢀ
IS62C5128BL-45TIꢀ
IS62C5128BL-45TLIꢀ
450-milꢀPlasticꢀSOPꢀ ꢀ
450-milꢀPlasticꢀSOP,ꢀLead-freeꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
32-pinꢀSTSOP-Iꢀ
32-pinꢀSTSOP-I,ꢀLead-freeꢀ
32-pinꢀTSOP-IIꢀ
32-pinꢀTSOP-II,ꢀLead-free
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
11
Rev.ꢀ B
06/28/2011
IS62C5128BL, IS65C5128BLꢀ
12ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ B
06/28/2011
IS62C5128BL, IS65C5128BLꢀ
Integrated Silicon Solution, Inc. — www.issi.com ꢀ
13
Rev.ꢀ B
06/28/2011
IS62C5128BL, IS65C5128BLꢀ
14ꢀ
Integrated Silicon Solution, Inc. — www.issi.com
Rev.ꢀ B
06/28/2011
相关型号：
IS62C5128BL-45QLI
Standard SRAM, 512KX8, 45ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, PLASTIC, SOP-32
ISSI
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