ISD2360_技术文档

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ISD2360

Digital ChipCorder with Embedded Flash

3-Channel Audio Playback

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TABLE OF CONTENTS

1

2

3

4

5

6

GENERAL DESCRIPTION .............................................................................................................. 4

FEATURES ...................................................................................................................................... 4

BLOCK DIAGRAM ........................................................................................................................... 6

PINOUT CONFIGURATION ............................................................................................................ 7

PIN DESCRIPTION – QFN32.......................................................................................................... 8

DEVICE OPERATION.................................................................................................................... 10

6.1

AUDIO STORAGE.....................................................................................................................................10

DEVICE CONFIGURATION........................................................................................................................10

GPIO CONFIGURATION...........................................................................................................................10

OSCILLATOR AND SAMPLE RATES ..........................................................................................................11

6.2

6.3

6.4

7

MEMORY FORMAT....................................................................................................................... 11

7.1.1

7.1.2

7.1.3

Voice Prompts................................................................................................................................12

Voice Macros .................................................................................................................................12

User Data.......................................................................................................................................13

MEMORY CONTENTS PROTECTION .........................................................................................................13

7.2

8

SPI INTERFACE ............................................................................................................................ 14

SIGNAL PATH................................................................................................................................ 16

GPIO VOICE MACRO TRIGGERS ............................................................................................ 17

9

10

10.1 ASSIGN PLAYBACK CHANNEL FOR THE GPIO TRIGGER ........................................................................17

10.2 VOICE MACRO EXAMPLES......................................................................................................................17

10.2.1

10.2.2

10.2.3

10.2.4

10.2.5

10.2.6

POI/PU/WAKEUP Voice Macros..................................................................................................17

Example: Cycle through a sequence of messages..........................................................................18

Example: Looping short sounds. Interrupt to stop playback. ........................................................19

Example: Uninterruptable Trigger, smooth audio.........................................................................19

Example: Continuous Play until re-trigger....................................................................................20

Example: Level Hold Trigger. .......................................................................................................21

11

CHANNEL SELECTION AND EXECUTION CONTROL............................................................ 21

11.1 SELECT CHANNEL FOR THE PLYABCK AND MIXING..............................................................................21

11.2 EXECUTION CONTROL ............................................................................................................................21

11.2.1

11.2.2

Conditional Branch and Unconditional Jump ...............................................................................22

Execution Delay / Pause ................................................................................................................22

12

ELECTRICAL CHARACTERISTICS .......................................................................................... 23

12.1 OPERATING CONDITIONS ........................................................................................................................23

12.2 AC PARAMETERS ...................................................................................................................................23

12.2.1

12.2.2

Internal Oscillator .........................................................................................................................23

Speaker Outputs.............................................................................................................................23

12.3 DC PARAMETERS ...................................................................................................................................24

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12.4 SPI TIMING.............................................................................................................................................25

13

APPLICATION DIAGRAM .......................................................................................................... 26

13.1 SPI MODE APPLICATION ........................................................................................................................26

13.2 STANDALONE APPLICATION ...................................................................................................................27

14

PACKAGE SPECIFICATION...................................................................................................... 28

14.1 16 LEAD 300-MIL SOP ..........................................................................................................................29

15

16

ORDERING INFORMATION ...................................................................................................... 30

REVISION HISTORY.................................................................................................................. 31

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1

GENERAL DESCRIPTION

The ISD2360 is a 3-channel digital ChipCorder^®providing single-chip storage and playback of high

quality audio. The device features digital de-compression, comprehensive memory management, flash

storage, integrated audio signal path with up to 3 channel concurrent playback and Class D speaker

driver capable of delivering power of 0.95W. This family utilizes flash memory to provide non-volatile

audio playback with duration up to 64 seconds (based on 8kHz/4bit ADPCM compression) for a single-

chip audio playback solution.

The ISD2360 can be controlled and programmed through an SPI serial interface or operated stand-

alone by triggers applied to the device‟s six GPIO pins.

The ISD2360 requires no external clock sources or components except a speaker to deliver quality

audio prompts or sound effects to enhance user interfaces.

In addition the part can provide non-volatile flash storage in 1Kbyte sectors eliminating the need for

additional serial EEPROM/Flash devices.

Compared to previous ChipCorder series, this device provides higher sampling frequencies, improved

SNR, lower power, fast programming time and integrated program verification.

2

FEATURES



Duration

o

ISD2360 – 64 seconds based on 8kHz/4bit ADPCM in 2Mbit of flash storage (256KB)



Audio Management

o

Store pre-recorded audio (Voice Prompts) using high quality digital compression

Use simple index based command for playback – no address needed.

Execute pre-programmed macro scripts (Voice Macros) designed to control the configuration

of the device and playback Voice Prompts sequences.



Path and playback Control

o

Up to 3 channel audio streaming can be mixed and played back concurrently

Each channel has independent counter which enables user micro-management on VM

execution

o

Mask Jump allows branch execution depending on internal register or external GPIO pin

status



Control

o

Serial SPI interface for microprocessor control and programming.

Stand-alone control where customized Voice Macro scripts are assigned to GPIO trigger

pins.



Sample Rate

o

7 sampling frequencies 4, 5.3, 6.4, 8, 12.8, 16 and 32 kHz are available.

Each Voice Prompt can have optimal sample rate.

Compression Algorithms

o

µ-Law: 6, 7 or 8 bits per sample

Differential µ-Law: 6, 7 or 8 bits per sample

PCM: 8, 10 or 12 bits per sample

Enhanced ADPCM: 2, 3, 4 or 5 bits per sample

Variable-bit-rate optimized compression. This allows best possible compression given a

metric of SNR and background noise levels.



Oscillator

Internal oscillator with internal reference: factory trimmed to ±1% deviation at room

temperature.

o

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

Output

o

PWM: Class D speaker driver to direct drive an 8Ω speaker or buzzer.

Delivers 400mW at 3V supply.

I/Os

o

SPI interface: MISO, MOSI, SCLK, SSB for commands and digital audio data

6 general purpose I/O pins multiplexed with SPI interface.

Flash Storage

o

2Mbit of storage for combined audio/data.

Fast programming time (20µs/byte)

Erase sector size 1Kbyte, sector erase time 2ms.

Integrated memory checksum calculation for fast verification.

Endurance >100K cycles. Retention > 10 years



Operating Voltage: 2.4-5.5V

Package:

o

Green, QFN32

Temperature Options:

Industrial: -40C to 85C



o

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3

BLOCK DIAGRAM

SP+

Digital Signal Path

Digital Filters

Digital Mixing

PWM

Control

Resampling

Volume Control

SP-

MOSI/GPIO(0)

SCLK/GPIO(1)

MISO/GPIO(2)

Memory management and

Command Interpreter Ch1

De-Compression

Internal Flash

INTB/GPIO(3)

SPI Interface

GPIO

Interface

Memory management and

Command Interpreter Ch2

De-Compression

Memory

RDY/BSYB/GPIO(4)

GPIO(5)

Memory management and

Command Interpreter Ch3

De-Compression

SSB

Power

Conditioning

Flash Memory Controller

Figure 3-1 ISD2360 Block Diagram

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4

PINOUT CONFIGURATION

Figure 4-1 ISD2360 32-Lead QFN Pin Configuration.

Figure 4-2 ISD2360 16-Lead SOP Pin Configuration.

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PIN DESCRIPTION – QFN32

Pin Name

I/O

Function

Number

1

2

3

NC

This pin should be left unconnected.

MOSI /

GPIO0

I

Master-Out-Slave-In. Serial input to the ISD2360 from the host.

Can be configured as a general purpose I/O pin.

4

5

VSSD

NC

Digital Ground.

This pin should be left unconnected.

Digital Power for the PWM Driver.

6

NC

7

NC

8

NC

9

NC

10

11

V_CCD_PWM

SPK+

I

O

PWM driver positive output. This SPK+ output, together with SPK- pin,

provide a differential output to drive 8Ω speaker or buzzer. During

power down this pin is in tri-state.

12

13

14

V_SSD_PWM

SPK-

I

Digital Ground for the PWM Driver.

O

PWM driver negative output. This SPK- output, together with SPK+

pin, provides a differential output to drive 8Ω speaker or buzzer.

During power down this pin is tri-state.

15

16

17

18

19

20

21

V_CCD_PWM

I

Digital Power for the PWM Driver.

This pin should be left unconnected.

NC

INTB /

GPIO3

O

Active low interrupt request pin. This pin is an open-drain output.

Can be configured as a general purpose I/O pin.

22

23

RDY/BSYB /

GPIO4

An output pin to report the status of data transfer on the SPI interface.

“High” indicates that ISD2360 is ready to accept new SPI commands

or data. Can be configured as a general purpose I/O pin.

NC

This pin should be left unconnected.

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Pin Name

I/O

Function

Number

24

25

26

27

28

29

NC

This pin should be left unconnected.

Digital Power.

NC

V_CCD

GPIO5

NC

I

I/O

General purpose I/O pin

This pin should be left unconnected.

MISO /

GPIO2

O

Master-In-Slave-Out. Serial output from the ISD2360 to the host. This

pin is in tri-state when SSB=1.

Can be configured as a general purpose I/O pin.

30

31

SCLK / GPI1

SSB

I

Serial Clock input to the ISD2360 from the host.

Can be configured as a general purpose input pin.

Slave Select input to the ISD2360 from the host. When SSB is low

device is selected and responds to commands on the SPI interface.

When asserted, GPIO0/1/2 automatically configure to MOSI/SCLK and

MISO respectively. SSB has an internal pull-up to Vccd.

32

NC

This pin should be left unconnected.

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6

DEVICE OPERATION

Playback of audio stored on the ISD2360 can be accomplished by either sending SPI commands via

the serial interface or triggered by signal edges applied to GPIO pins. The device is programmed via

the SPI interface either in-system or utilizing commercially available gang programmers.

6.1 AUDIO STORAGE

The audio compression and customization of the ISD2360 is rapidly achieved with the supplied

ISD2360VPE or Voice Prompt Editor. This software tool allows the developer to take audio clips in

standard wave file format and re-sample and compress them for download to the ISD2360.

Audio is stored in the ISD2360 as series of Voice Prompts: these units of audio can be of any

length – the compression and sample rate of each Voice Prompt can be individually selected. A

powerful feature of the ISD2360 is presence of a scripting ability Voice Macros. A Voice Macro can

contain commands to play individual Voice Prompts and configure the ISD2360. A Voice Macro can be

associated with a GPIO pin such that it is triggered by a transition on that pin. In this way stand-alone

systems can be developed without the need for micro-controller interaction. Voice Macros can also be

executed via the SPI command interface. Both Voice Prompts and Voice Macros are addressed via a

simple sequential index address, no absolute memory address is required, thus audio source material

or voice macro function can be updated (or changed for multi-language implementation) without the

need to update microcontroller code.

6.2 DEVICE CONFIGURATION

The ISD2360 is configured by writing to a set of configuration registers. This can be accomplished

either by sending configuration via the serial SPI interface or executing Voice Macros containing

configuration commands. Most configuration registers are reset to their default values when the device

is powered down to ensure lowest possible standby current. Exceptions to this are registers that

control the configuration of GPIO pins and Jump registers that contain the Voice Macro index to

execute for GPIO triggers. Configuration registers may be initialized automatically in customizable

Voice Macros that are executed on a power-on reset or power-up condition.

6.3 GPIO CONFIGURATION

The six GPIO pins of the ISD2360 can be configured for a variety of purposes. Each pin can be

configured to trigger a Voice Macro function. Each pin also has an alternate function allowing the pins

to be configured as SPI, interrupt or oscillator reference pins.

PS

Logic

PE

DOUT

OE

DIN

Figure 6-1 GPIO Structure

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The structure of the GPIO pads is shown in Figure 6-1. Configuration registers allow the user to

control pull-up and pull down resistors, enable the pin as an output or set the output value. See

ISD2360 Design Guide for details on the configuration options.

6.4 OSCILLATOR AND SAMPLE RATES

The ISD2360 has an internal oscillator trimmed at manufacturing that requires no external components

to operate. This oscillator provides an internal clock source that operates the ISD2360 at a maximum

audio sample rate

of 32kHz. The sample rates available for audio storage at this maximum

sample rate are shown in Table 6-1. The sample rate is selected during compression using the

ISD2360 Voice Prompt Editor software.

Table 6-1 Available Sample Rates.

SR[2:0]

Ratio to

Sample Rate

(kHz)

0

1

2

3

4

5

6

8

6

4

5.44

6.4

8

5

4

2.5

2

12.8

16

1

32

7

MEMORY FORMAT

The memory of the ISD2360 consists of byte addressable flash memory that is erasable in 1Kbyte

sectors. Erased memory has a value of 0xFF. Writing to the memory allows host to change bits from

erased „1‟ state to programmed „0‟ state.

The memory of the ISD2360 is organized into four distinct regions as shown in Figure 7-1. The four

regions are:

1. Configuration and Index Table: The first region of memory contains configuration data for

the device and the index table that points to the Voice Prompt and Voice Macro data. The

ISD2360VPE creates this section for download to the device.

2. Voice Macros: This section contains the script code of all the projects Voice Macros.

3. Voice Prompts: This section contains the compressed audio data for all Voice Prompts.

4. User Data: An optional section containing memory sectors allocated by the developer for

generic use by the host controller.

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Byte

Sector

Address Address

0

1

2

Configuration and

Index Table

400h

800h

Voice Prompts

C00h

3

6

1800h

Voice Macros

User Data

PMP

1FC00h

20000h

7F

80

Figure 7-1 ISD2360 Memory Organization

7.1.1 Voice Prompts

Voice prompts are pre-recorded audio of any length, from short words, phrases or sound

effects to long passages of music. These Voice Prompts can be played back in any order as

determined by the application. A Voice Prompt consists of two components:

1. An index entry in the Index Table pointing to the pre-recorded audio.

2. Compressed pre-recorded audio data.

A Voice Prompt is addressed using its index number to locate and play the pre-recorded

audio. This address free approach allows users to easily manage the pre-recorded audio

without the need to update the code on the host controller. In addition, the users can store a

multitude of pre-recorded audio without the overhead of maintaining a complicated lookup

table. To assist customers in creating the Voice Prompts, ISD2360 Voice Prompt Editor and

writer are available for development purposes.

7.1.2 Voice Macros

Voice Macros are a script that allows users to customize their own play patterns such as play

Voice Prompts, insert silence, power-down the device and configure the signal path, including

volume control. Voice Macros are executed using a single SPI command and are accessed

using the same index structure as Voice Prompts. This means that a Voice Macro (or Voice

Prompt) can be updated on the ISD2360 without the need to update code on the host micro-

controller since absolute addresses are not needed.

The following locations have been reserved for special Voice Macros:

Index 0: Power-On Initialization (POI)

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Index 1: Power-Up (PU)

Index 2: GPIO-Wakeup (WAKEUP)

These Voice Macros allow the users to customize the ISD2360 power-on, power-up and GPIO

wake-up procedures and are executed automatically when utilized. If these Voice Macros are

not used device will perform default operations on these events.

An example to illustrate the usage of the PU Voice Macro is:



WR_CFG(VOLC, 0x0C)

WR_CFG(REG2, 0x44)

WR_CFG (REG_GPIO_AF1 ,0xFF)

WR_CFG (REG_GPIO_AF0 ,0x10)

FINISH

; Set VOLC to 0x0C

; Set REG2 to 0x44

; Set REG_GPIO_AF1 to 0xFF

; Set REG_GPIO_AF0 to 0x10

; Exit Voice Macro

The above PU Voice Macro will perform the following:



Choose Volume Control for -3dB level.

Configure and power up the signal path to decode compressed audio to speaker driver.

Set up all GPIOs except GPIO4 for Falling edge trigger and set GPIO4 for both falling

and rising edge trigger.

The following is the complete list of the command available for use in Voice Macros:



WR_CFG_REG(reg n) – Set configuration register reg to value n.

PWR_DN – Power down the ISD2360.

PLAY_VP(i) – Play Voice Prompt index i.

PLAY_VP@(Rn) – Indirect Play Voice Prompt of index in register Rn

PLAY_VP_LP(i,cnt) – Loop Play Voice Prompt index i, cnt times.

PLAY_VP_LP@(Rn,cnt) – Indirect Loop Play Voice Prompt index in Rn, cnt times.

EXE_VM(i) – Execute Voice Macro index i.

EXE_VM@(Rn) – Indirect Execute Voice Macro index in register Rn

PLAY_SIL(n) – Play silence for n units. A unit is 32ms at master sampling rate of 32 kHz.

WAIT_INT – Wait until current play command finishes before executing next macro

instruction.



FINISH – Finish the voice macro and exit.

These commands are equivalent to the commands available via the SPI interface and are described in

Section 錯誤! 找不到參照來源。.

7.1.3 User Data

User Data consists of 1KByte multiples of erasable sectors allocated by the user. This can be

used as generic non-volatile storage by the host application. The developer has the freedom

not to allocate or reserve any memory sectors. A software tool, the ISD2360 Voice Prompt

Editor is available to assist customers in allocating such memory.

7.2

MEMORY CONTENTS PROTECTION

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Under certain circumstances, it is desirable to protect portions of the internal memory from

write/erase or interrogation (read). The ISD2360 provides a method to achieve this by setting a

protection memory pointer (PMP) that allows the users to protect memory for an address range from

the beginning of memory to this sector containing the PMP pointer. The type of protection is set by

three bits in the memory header byte.

Memory protection is activated on power-up of the chip. Therefore, each time the user changes the

setting of memory protection, the new setting will not be effective until the chip is reset.

8

SPI INTERFACE

This is a standard four-wire serial interface used for communication between ISD2360 and the host. It

consists of an active low slave-select (SSB), a serial clock (SCLK), a data input (Master Out Slave In -

MOSI), and a data output (Master In Slave Out - MISO). In addition, for some transactions requiring

data flow control, a RDY/BSYB signal (pin) is available.

The ISD2360 supports SPI mode 3: (1) SCLK must be high when SPI bus is inactive, and (2) data is

sampled at SCLK rising edge. A SPI transaction begins on the falling edge of SSB and its waveform is

illustrated below:

SSB

SCLK

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

Z

X

S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0

C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

MISO

MOSI

X

Figure 8-1 SPI Data Transaction.

A transaction begins with sending a command byte (C7-C0) with the most significant bit (MSB – C7)

sent in first. During the byte transmission, the status (S7-S0) of the device is sent out via the MISO

pin. After the byte transmission, depending upon the command sent, one or more bytes of data will be

sent via the MISO pin.

RDY/BSYB pin is used to handshake data into or out of the device. Upon completion of a byte

transmission, RDY/BSYB pin could change its state after the rising edge of the SCLK if the built-in 32-

byte data buffer is either full or empty. At this point, SCLK must remain high until RDY/BSYB pin

returns to high, indicating that the ISD2360 is ready for the next data transmission. See 如下 for

timing diagram.

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T_{R / B}

SSB

SCLK

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

RDY/BSYB

MISO

=1

VG BUF

BSY FUL

CMD

BSY

VG BUF CMD

BSY FUL BSY

Z

X

PD RDY INT FULL

X

PD RDY INT FULL

X

C7 C6 C5 C4 C3 C2 C1 C0

D7 D6 D5 D4 D3 D2 D1 D0

X

MOSI

Figure 8-2 RDY/BSYB Timing for SPI Writing Transactions.

If the SCLK does not remain high, RDY bit of the status register will be set to zero and be reported via

the MISO pin so the host can take the necessary actions (i.e., terminate SPI transmission and re-

transmit the data when the RDY/BSYB pin returns to high).

For commands (i.e., DIG_READ, SPI_PCM_READ) that read data from the ISD2360 device, MISO is

used to read the data; therefore, the host must monitor the status via the RDY/BSYB pin and take the

necessary actions. The INT pin will go low to indicate (1) data overrun/overflow when sending data to

the ISD2360; or (2) invalid data from ISD2360. See Figure 8-3 for the timing diagram.

To avoid RDY/BSYB polling for digital operations the following conditions must be met:



Ensure device is idle (CMD_BSY=0 in status) before operation.

Digital Write: Send 32 bytes of data or less in a digital write transaction or ensure that there is

a 24µs period between each byte sent where SCLK is held high.



Digital Read: Ensure a 2µs period between last address byte of digital read command and first

data byte where SCLK is held high.

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T_{R / B}

SSB

SCLK

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

RDY/BSYB

=1

=0

VG BUF CMD

BSY FUL BSY

VG BUF CMD

BSY FUL BSY

Z

X

PD RDY INT FULL

X

PD RDY INT FULL

X

MISO

C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

X

MOSI

INT

Fi

gure 8-3 SPI Transaction Ignoring RDY/BSYB

9

SIGNAL PATH

The signal path performs filtering, sample rate conversion, volume control and decompression. A

block diagram of the signal path is shown in Figure 9-1. The PWM driver output pins SPK- and SPK+

provide a differential output to drive an 8Ω speaker or buzzer. During power down these pins are in tri-

state.

Pre-compressed audio transfers from memory or SPI interface through the de-compressor block to

PWM driver or SPI out. The audio level is adjustable via VOLC before going out on to the PWM driver

path. The possible path combinations are:

MEMORY → DECOMPRESS → SPKR (Playback to speaker)

MEMORY → DECOMPRESS → SPI_OUT (SPI playback)

SPI_IN → DECOMPRESS → SPKR (SPI decode to speaker)

For example to playback audio to speaker, enable decompression and PWM (write 0x44 to register

0x02) then send a PLAY_VP command to play audio.

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Figure 9-1 ISD2360 Signal Path

10 GPIO VOICE MACRO TRIGGERS

The ISD2360 Voice Macro capability and GPIO flexibility allows the user to configure the device to

operate independently of the SPI interface or host micro-controller.

GPIO triggering utilizes the Jump registers R0 through R6. When a GPIO trigger event occurs the

ISD2360 executes the Voice Macro whose index is stored in the corresponding Jump register: that is

GPIO0 will execute the VM whose index is stored in R0, GPIO1 in R1 etc. The initial values of the R0-

R6 registers can be set up in the POI Voice macro which is executed when a power-on reset condition

is detected. When the ISD2360 responds to a trigger event, if a Voice Macro is currently being

executed, that Voice Macro is first stopped before execution of new Voice Macro.

10.1

ASSIGN PLAYBACK CHANNEL FOR THE GPIO TRIGGER

For each GPIO pins, Register 0x14 and 0x15 can assign the playback channel for that GPIO. So once

triggered, the playback audio streaming will be routed to that channel.

10.2

VOICE MACRO EXAMPLES

Below are some useful examples demonstrating the features Voice trigger macros. The example

project can be found in the ISD2360VPE distribution as the ISD2360example project.

10.2.1 POI/PU/WAKEUP Voice Macros

These special purpose Voice Macros allow the user to configure the ISD2360 for subsequent trigger

events. The POI macro is executed when the chip receives an internal power-on reset condition or the

SPI SW_RESET command is sent.

The POI Voice macro is used to configure the ISD2360 for subsequent trigger events, for example:

a.

b.

c.

d.

e.

f.

CFG(REG2, 0x44)

CFG(VOLC, 0x00)

CFG(R5, 0x03)

CFG(R4, 0x07)

CFG(R3, 0x09)

CFG(R2, 0x0a)

; Configure signal path to playback

; Set Volume to 0dB

; Set Jump register R5 to 0x03, GPIO5 to trigger VM#3

; Set Jump register R4 to 0x07, GPIO4 to trigger VM#7

; Set Jump register R3 to 0x09, GPIO3 to trigger VM#9

; Set Jump register R2 to 0x0a, GPIO2 to trigger VM#A

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g.

h.

i.

CFG(R1, 0x0c)

; Set Jump register R1 to 0x0c, GPIO1 to trigger VM#C

; Set Jump register R0 to 0x0e, GPIO0 to trigger VM#E

; Play Voice Prompt FastBeep

CFG(R0, 0x0e)

PLAY_VP(FastBeep)

j.

CFG(REG_GPIO_AF1, 0xff) ; Set up GPIOs to trigger off falling edges

CFG(REG_GPIO_AF0, 0x00)

k.

l.

PD

; Power Down

This POI macro will initialize the GPIO configuration such that all GPIO triggers are enabled for falling

edges and performs initialization of the jump registers to point to appropriate Voice Macros. It also

configures the play path and plays a beep. At the end of the macro the chip powers down.

The GPIO_WAKEUP is executed whenever the device is triggered from a power down state.

a. CFG(REG2, 0x44)

b. CFG(VOLC, 0x00)

c. CFG(R4, 0x07)

d. CFG(R2, 0x0a)

e. Finish

; Configure signal path to playback

; Set Volume to 0dB

; Set Jump register R4 to 0x07, GPIO4 to trigger VM#7

; Set Jump register R2 to 0x0a, GPIO2 to trigger VM#A

; Exit Voice Macro, stay powered up.

This GPIO_WAKEUP macro sets up the play path as settings in these registers are reset during power

down. It also resets jump registers R4 and R2 to default conditions.

10.2.2 Example: Cycle through a sequence of messages.

In this example a high-to-low transition on GPIO5 will initially trigger VM#3 as defined in the POI

initialization macro. In VM#3 the Voice Prompt “One” is played and jump register R5 set to VM#4.

Thus the next high-to-low transition on GPIO5 will trigger VM#4 and play Voice Prompt “Two”.

Similarly next trigger will play “Three” then “Four” and back to “One”. Notice the difference in VM#4

where a WAIT_INTERRUPT command has been inserted before the setting of the jump register. If the

GPIO5/SW6 button is pushed rapidly, so that play is interrupted, “Two” will continue to be repeated.

Other Voice Macros, because the jump register is changed first, will always progress to the next step

in sequence.



VM#3: R5_Count_One (GPIO5)

a. CFG(R5, 0x04)

b. Play(One)

c. PD

; Configure GPIO5 to play VM#4 on next trigger

; Play voice prompt “One”

; Power Down



VM#4:Two

a. Play(Two)

b. Wait Interrupt

c. CFG(R5, 0x05)

d. PD

; Play voice prompt “Two”

; Wait until Play finishes

; Configure GPIO5 to play VM#5 on next trigger

; Power Down



VM#5: Three

a. CFG(R5, 0x06)

b. Play(Three)

c. PD

; Configure GPIO5 to play VM#6 on next trigger

; Play voice prompt “Three”

; Power Down

VM#6: Four

a. CFG(R5, 0x03)

b. Play(Four)

c. PD

; Configure GPIO5 to play VM# 3 on next trigger

; Play voice prompt “Four “

; Power Down

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10.2.3 Example: Looping short sounds. Interrupt to stop playback.

This example demonstrates how to loop short sound samples and use a trigger interrupt to stop

playback. A trigger on GPIO4 will play a series of Voice Prompts until it is interrupted by another

trigger to stop playback. VM#7 was associated with the GPIO4 trigger in the POI routine. The first

action of this VM is to change the trigger VM to VM#8, thus if GPIO4 is re-triggered while the Voice

Macro is running it will execute the power down voice macro rather than start the play sequence again.

The next command sets the LRMP bit of REG1, under normal operation the compressor ramps signal

level to zero after a sound sample is played to prevent a DC voltage appearing on the output. The

LRMP bit prevents this from happening while a sample is looping allowing continuous audio. To loop a

sound sample, the audio should be edited such that the last sample loops smoothly to the first. To do

this, create the sample in a sound editor at the sample rate desired for storage then find the first

sample that returns to the initial condition and cut back audio to one before this sample. Note that

tones require different lengths to fulfill these conditions at a given sample rate and thus loop numbers

vary to produce the same length of output audio.

At the end of the VM REG1 is reset and the trigger is re-enabled back to VM#7 before powering down.



VM#7: R4_PlayLoop (GPIO4)

a. CFG(R4, 0x08)

; Configure GPIO4 to execute VM# 8 on next trigger.

b. CFG(REG1, 0x20) ; Configure LRMP bit in REG1

c. LOOP_VP(Do,20) ; LOOP “Do” 20 times.

d. LOOP_VP(Re,250) ; LOOP “Re” 250 times.

e. LOOP_VP(Mi,5)

; LOOP “Mi” 5 times.

f. LOOP_VP(Fa,33) ; LOOP “Fa” 33 times.

g. LOOP_VP(So,10) ; LOOP “So” 10 times

h. LOOP_VP(La,10) ; LOOP “La” 10 times

i. LOOP_VP(Si,7)

j. Silence (128 ms)

; LOOP “Si” 7 times.

; Insert 128ms of silence

k. CFG(REG1, 0x00) ; Reset REG1

l. CFG(R4, 0x07)

m. PD

; Configure GPIO4 to execute VM#7 on next trigger.

; Power Down



VM#8: PD_R4

a. CFG(REG1, 0x00)

b. CFG(R4, 0x07)

c. PD

; Configure Register one to its default value 00

; Configure GPIO4 to execute VM#7 on next trigger.

; Power Down

10.2.4 Example: Uninterruptable Trigger, smooth audio.

In this example a single trigger on GPIO3 will sequence through several messages until all messages

are played the playback cannot be interrupted by any other trigger. The example also demonstrates

how to use begin and end segments to create smooth playback. Each “note” consists of concatenating

three voice prompts, for instance “So_begin” “So” and “So_end”. The begin and end prompts ramp

the audio smoothly to avoid sudden transients in sound level. The middle, full amplitude, section is

created by looping a short sample.

At the beginning of the Voice Macro, all triggers are disabled so that Voice Macro cannot be

interrupted from any source. The NRMP bit of REG1 is set so that concatenation of audio occurs

without any ramp down between prompts. At the end of the macro, interrupts are re-enabled and

device is powered down.

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

VM#9: R3_Non-Int_Smooth (GPIO3)

a. CFG(REG_GPIO_AF1, 0x00) ; Disable all triggers.

b. CFG(REG1, 0x04)

c. PLAY_VP(So_begin)

d. LOOP_VP(So,10)

e. PLAY_VP(So_end)

f. PLAY_VP(Fa_begin)

g. LOOP_VP(Fa,33)

h. PLAY_VP(Fa_end)

i. PLAY_VP(Mi_begin)

j. LOOP_VP(Mi,5)

; Set NRMP bit

; Play “So_begin”

; Loop “So” 10 times.

; Play “So_end”

k. PLAY_VP(Mi_end)

l. PLAY_VP(Re_begin)

m. LOOP_VP(Re,250)

n. PLAY_VP(Re_end)

o. PLAY_VP(Do_begin)

p. LOOP_VP(Do,20)

q. PLAY_VP(Do_end)

r. Wait Interrupt

; Wait for audio to finish

; Reset NRMP bit

s. CFG(REG1, 0x00)

t. CFG(REG_GPIO_AF1, 0x3f)

u. PD

; Re-enable interrupts

; Power down device.

10.2.5 Example: Continuous Play until re-trigger.

In this example a single trigger on GPIO2 will sequence through several messages with pause in

between each message. Messages are played in a loop indefinitely until another trigger occurs on

GPIO2 to stop playback.



VM0#A: R2_Loop_VM (GPIO2)

a. CFG(R2, 0x0b)

b. PLAY_VP(One)

c. Silence (256 ms)

d. PLAY_VP(two)

e. Silence (256 ms)

f. PLAY_VP(three)

g. Silence (736 ms)

h. PLAY_VP(four)

i. Silence (256 ms)

j. EXE_VM(0xA)

k. Finish

; Set Trigger to VM#B (PD_R2)

; Play “One”

; pause 256ms

; Play “Two”

; Execute VM#A (repeat)



VM0#B: PD_R2

a. CFG(R2, 0x0a)

b. PD

; Reset Trigger to VM#A

; Power Down.

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10.2.6 Example: Level Hold Trigger.

In this example holding GPIO1 will play several messages. Releasing GPIO1 will stop the playback.

No other triggers will affect operation.



VM#C: R1_Level_Hold (GPIO1)

a. CFG(REG_GPIO_AF0, 0x02) ; Enable rising edge trigger for GPIO2

b. CFG(REG_GPIO_AF1, 0x02) ; Disable all triggers except GPIO2

c. CFG(R1, 0x0d)

d. CFG(REG1, 0x20)

e. LOOP_VP(Re,200)

f. Silence (32 ms)

g. LOOP_VP(Mi,4)

h. Silence (32 ms)

i. LOOP_VP(Fa,20)

j. Silence (32 ms)

k. CFG(REG1, 0x00)

l. PLAY_VP(applause)

m. PD

; Set Trigger to VM#D (PD_R1)



VM#D: PD_R1

a. CFG(REG_GPIO_AF0, 0x00) ; Disable rising edge trigger

b. CFG(REG_GPIO_AF1, 0x3f)

c. CFG(REG1, 0x00)

d. CFG(R1, 0x0c)

e. PD

; Re-enable all triggers.

; Ensure REG1 reset

; Set trigger to VM#C

; Power Down.

11 CHANNEL SELECTION AND EXECUTION CONTROL

11.1

SELECT CHANNEL FOR THE PLYABCK AND MIXING

For any play command such as PLAY_VM or PLAY_VP, etc, the playback occurs in either one

channel or all three channels. In other words, user can either specify one single active channel for next

playback operation, or make the next play operation happen in all three channels. Channel selection

can be achieved by configuring register 0x0C.

To mix two different sound effects from two channels, e.g. channel #0 and channel #1, user can first

configure channel #0 as the active channel by writing 0bxxxxxx00 into register 0x0C, then send a play

command to play the first sound effect; then configure channel #1 as the active channel by writing

0bxxxxxx01 into register 0x0C, then send another play command to play the second sound effect. This

way sound effect mixing can be achieved.

By Default, play operations will always happen in channel #0.

11.2

EXECUTION CONTROL

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The ISD2360 implemented several commands which allow user add fine control in a VM script

execution.

11.2.1 Conditional Branch and Unconditional Jump

The ISD2360 can do mask branch which judges device‟s current pin status and its internal status

register value against the value in mask register, to decide if jump to a memory address (and start

execution from there) or continue executing the next script command inside the current VM. This gives

the possibility of multi-tasking, i.e. let the ISD2360 do something during the play.

The ISD2360 can also do an absolute jump, which jumps to a memory address and start execution

from there.

The new start address should be a valid command entry address; otherwise it will cause unknown

behavior. The scope for the mask jump and absolute jump is global, i.e. the full range of the flash size.

11.2.2 Execution Delay / Pause

The ISD2360 has time counter for each channel. So it allows customer add delay during a VM

execution. This adds the convenience for certain operations such as GPIO driving with time control.

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12 ELECTRICAL CHARACTERISTICS

12.1

OPERATING CONDITIONS

OPERATING CONDITIONS (INDUSTRIAL PACKAGED PARTS)

CONDITIONS

Operating temperature range (Case temperature)

VALUES

-40°C to +85°C

+2.4V to +5.5V

0V

Supply voltage (V_DD) ^[1]

Ground voltage (V_SS) ^[2]

Input voltage (V_DD) ^[1]

Voltage applied to any pins

[1]

0V to 5.5V

(V_SS–0.3V) to (V_DD+0.3V)

NOTES:

V

DD

= V_CCD= V_CCPWM

[2]

V

SS

= V_SSD= V_SSPWM

12.2

AC PARAMETERS

12.2.1 Internal Oscillator

PARAMETER

SYMBOL MIN

TYP

MAX UNITS CONDITIONS

-1%

32kHz

+1%

kHz

Vdd = 3V.

Sample rate with Internal

Oscillator

At room temperature

12.2.2 Speaker Outputs

PARAMETER

SYMBOL

SNR_{MEM_SPK}

P_{OUT_SPK}VCC=5.0

THD %

MIN

TYP^[1]

MAX UNITS CONDITIONS

SNR, Memory to SPK+/SPK-

Output Power

60

dB

W

Load 150Ω ^[2][3]

Load 8Ω ^[2]

0.95

THD, Memory to SPK+/SPK-

<1%

8

Load 8Ω ^[2]

Minimum Load Impedance

R_L(SPK)

4

Ω

Notes:

^[1]Conditions V_cc=3V, T_A=25°C unless otherwise stated.

^[2]Based on 12-bit PCM.

^[3]All measurements are C-message weighted.

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12.3

DC PARAMETERS

PARAMETER

SYMBOL MIN

TYP ^[1]MAX

5.5

UNITS CONDITIONS

Supply Voltage

V_DD

V_IL

2.4

V

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Pull-up Resistance

Pull-down Resistance

INTB Output Low Voltage

Playback Current

Standby Current

V_SS-0.3

0.7xV_DD

V_SS-0.3

0.7xV_DD

0.3xV_DD

V_DD

V_IH

V_OL

0.3xV_DD

V_DD

V

I_OL= 1mA

V_OH

I_OH= -1mA

R_PU

50

10

kΩ

V

R_PD

V_OH1

I_{DD_Playback}

I_SB

0.4

3

mA

µA

No Load ^[2]

V_DD= 3.6V

Force V_DD

<1

10

I_IL

Input Leakage Current

1

Notes:

^[1]Conditions V_DD=3V, T_A=25°C unless otherwise stated

^[2]To calculate total current, add load dissipation into application specific load.

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12.4

SPI TIMING

T_SSBHI

SSB

T_SSBH

T_SSBS

T_SCK

T_RISE

T_FALL

SCLK

T_SCKH

T_SCKL

MOSI

T_MOS

T_MOH

T_MIZD

T_ZMID

MISO

T_MID

T_CRBD

T_RBCD

RDY/BSYB

Figure 12-1 SPI Timing

SYMBOL

DESCRIPTION

MIN

TYP MAX

UNIT

SCLK Cycle Time

T_SCK

T_SCKH

T_SCKL

T_RISE

T_FALL

T_SSBS

T_SSBH

T_SSBHI

T_MOS

T_MOH

T_ZMID

T_MIZD

T_MID

60

25

---

30

30ns

20

15

--

---

--

---

ns

---

ns

SCLK High Pulse Width

SCLK Low Pulse Width

---

Rise Time for All Digital Signals

Fall Time for All Digital Signals

10

---

SSB Falling Edge to 1^stSCLK Falling Edge Setup Time

Last SCLK Rising Edge to SSB Rising Edge Hold Time

SSB High Time between SSB Lows

50us

---

MOSI to SCLK Rising Edge Setup Time

---

SCLK Rising Edge to MOSI Hold Time

---

Delay Time from SSB Falling Edge to MISO Active

Delay Time from SSB Rising Edge to MISO Tri-state

Delay Time from SCLK Falling Edge to MISO

Delay Time: SCLK Rising Edge to RDY/BSYB Falling Edge

Delay Time: RDY/BSYB Rising Edge to SCLK Falling Edge

12

--

---

--

---

--

T_CRBD

T_RBCD

0

--

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13 APPLICATION DIAGRAM

13.1

SPI MODE APPLICATION

The following applications example is for reference only. It makes no representation or warranty that

such applications shall be suitable for the use specified. Each design has to be optimized in its own

system for the best performance on voice quality, current consumption, functionality etc.

V_CCD

26

V_CCD

µF

0.1

4

V_SSD

V_CCD

10

15

V_CCD_PWM

10

µF

0.1

µF

ISD2360

QFN -32

12

11

V_SSD_PWM

SPK+

14

27

SPK

-

29

30

31

3

21

22

MISO / GPIO 2

SCLK / GPI1

SSB

MOSI / GPIO 0

INTB / GPIO 3

RDY /BSYB / GPIO 4

VCCD

SPI Interface

-

GPIO 5



10K

Data flow control

Figure 13-1 ISD2360 Application Diagram Example for programming with a Microcontroller SPI Mode

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13.2

STANDALONE APPLICATION

The following applications example is for reference only. It makes no representation or warranty that

such applications shall be suitable for the use specified. Each design has to be optimized in its own

system for the best performance on voice quality, current consumption, functionality etc.

VCCD

SWI

29

30

26

4

MISO/GPIO2

SCLK /GPIO1

V_CCD

4.7

µF

SW2

V_SSD

V

CCD

10

15

VCCDPWM

_

31

VCCDPWM

ISD2360

QFN-32

SSB

_

µF

10

NC

12

VSSDPWM

_

SW3

SW4

3

MOSI/GPIO0

21

11

14

SPK+

SPK-

INTB/GPIO3

SW5

SW6

22

27

RDY/BSYB/GPIO4

GPIO5/XCLK

Figure 135-2 ISD2360 Application Diagram Stand-Alone Mode

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14 PACKAGE SPECIFICATION

QFN 32L 5X5 MM^2, Thickness 0.8 MM(Max) ,Pitch 0.5 MM (Saw Type)

(GR)EP Size 3.2X3.2MM

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14.1

16 LEAD 300-MIL SOP

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15 ORDERING INFORMATION

I2360 x Y I x

Blank: None

R: Tape and Reel

Temperature

Duration

I: Industrial -40C to 85C

60: 64 Seconds

* Based on 8kHz/4bit ADPCM

Lead-Free

Y: green

Package Type

Y: 32L-QFN

S: 16L-SOP

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16 REVISION HISTORY

Version

0.1

Date

Description

July 01, 2011

Nov 22, 2011

Mar 21, 2022

Initial draft.

0.2

Package update, Application Diagram update

Update package and ordering information

0.3

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Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment

intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation

instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or

sustain life. Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton products could

result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur.

Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully

indemnify Nuvoton for any damages resulting from such improper use or sales.

The contents of this document are provided only as a guide for the applications of Nuvoton products. Nuvoton makes no

representation or warranties with respect to the accuracy or completeness of the contents of this publication and

reserves the right to discontinue or make changes to specifications and product descriptions at any time without notice.

No license, whether express or implied, to any intellectual property or other right of Nuvoton or others is granted by this

publication. Except as set forth in Nuvoton's Standard Terms and Conditions of Sale, Nuvoton assumes no liability

whatsoever and disclaims any express or implied warranty of merchantability, fitness for a particular purpose or

infringement of any Intellectual property.

The contents of this document are provided “AS IS”, and Nuvoton assumes no liability whatsoever and disclaims any

express or implied warranty of merchantability, fitness for a particular purpose or infringement of any Intellectual

property. In no event, shall Nuvoton be liable for any damages whatsoever (including, without limitation, damages for

loss of profits, business interruption, loss of information) arising out of the use of or inability to use the contents of this

documents, even if Nuvoton has been advised of the possibility of such damages.

Application examples and alternative uses of any integrated circuit contained in this publication are for illustration only

and Nuvoton makes no representation or warranty that such applications shall be suitable for the use specified.

The 100-year retention and 100K record cycle projections are based upon accelerated reliability tests, as published in

the Nuvoton Reliability Report, and are neither warranted nor guaranteed by Nuvoton.

This datasheet and any future addendum to this datasheet is(are) the complete and controlling ISD^®ChipCorder^®

product specifications. In the event any inconsistencies exist between the information in this and other product

documentation, or in the event that other product documentation contains information in addition to the information in

this, the information contained herein supersedes and governs such other information in its entirety. This datasheet is

subject to change without notice.

Nuvoton Electronics Corporation. All other trademarks are properties of their respective owners.

Headquarters

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Nuvoton Technology (Shanghai) Ltd.

No. 4, Creation Rd. III

Science-Based Industrial Park, CA 95134, U.S.A.

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Please note that all data and specifications are subject to change without notice.

All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.

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型号：	ISD2360
厂家：	ETC
描述：	Digital ChipCorder with Embedded Flash 3-Channel Audio Playback
文件：	总32页 (文件大小：894K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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